1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - powerpc architecture code
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
13 #include <linux/uaccess.h>
16 #include <asm/machdep.h>
17 #include <asm/firmware.h>
18 #include <asm/ptrace.h>
19 #include <asm/code-patching.h>
25 #define BHRB_MAX_ENTRIES 32
26 #define BHRB_TARGET 0x0000000000000002
27 #define BHRB_PREDICTION 0x0000000000000001
28 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
30 struct cpu_hw_events {
37 struct perf_event *event[MAX_HWEVENTS];
38 u64 events[MAX_HWEVENTS];
39 unsigned int flags[MAX_HWEVENTS];
41 * The order of the MMCR array is:
42 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
43 * - 32-bit, MMCR0, MMCR1, MMCR2
45 unsigned long mmcr[4];
46 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
47 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
48 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
50 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
52 unsigned int txn_flags;
56 u64 bhrb_filter; /* BHRB HW branch filter */
57 unsigned int bhrb_users;
59 struct perf_branch_stack bhrb_stack;
60 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
64 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
66 static struct power_pmu *ppmu;
69 * Normally, to ignore kernel events we set the FCS (freeze counters
70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
71 * hypervisor bit set in the MSR, or if we are running on a processor
72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
73 * then we need to use the FCHV bit to ignore kernel events.
75 static unsigned int freeze_events_kernel = MMCR0_FCS;
78 * 32-bit doesn't have MMCRA but does have an MMCR2,
79 * and a few other names are different.
84 #define MMCR0_PMCjCE MMCR0_PMCnCE
90 #define MMCR0_PMCC_U6 0
92 #define SPRN_MMCRA SPRN_MMCR2
93 #define MMCRA_SAMPLE_ENABLE 0
95 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
99 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { }
100 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
104 static inline void perf_read_regs(struct pt_regs *regs)
108 static inline int perf_intr_is_nmi(struct pt_regs *regs)
113 static inline int siar_valid(struct pt_regs *regs)
118 static bool is_ebb_event(struct perf_event *event) { return false; }
119 static int ebb_event_check(struct perf_event *event) { return 0; }
120 static void ebb_event_add(struct perf_event *event) { }
121 static void ebb_switch_out(unsigned long mmcr0) { }
122 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
124 return cpuhw->mmcr[0];
127 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
128 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
129 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
130 static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {}
131 static void pmao_restore_workaround(bool ebb) { }
132 #endif /* CONFIG_PPC32 */
134 bool is_sier_available(void)
136 if (ppmu->flags & PPMU_HAS_SIER)
142 static bool regs_use_siar(struct pt_regs *regs)
145 * When we take a performance monitor exception the regs are setup
146 * using perf_read_regs() which overloads some fields, in particular
147 * regs->result to tell us whether to use SIAR.
149 * However if the regs are from another exception, eg. a syscall, then
150 * they have not been setup using perf_read_regs() and so regs->result
151 * is something random.
153 return ((TRAP(regs) == 0xf00) && regs->result);
157 * Things that are specific to 64-bit implementations.
161 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
163 unsigned long mmcra = regs->dsisr;
165 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
166 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
168 return 4 * (slot - 1);
175 * The user wants a data address recorded.
176 * If we're not doing instruction sampling, give them the SDAR
177 * (sampled data address). If we are doing instruction sampling, then
178 * only give them the SDAR if it corresponds to the instruction
179 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
180 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
182 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp)
184 unsigned long mmcra = regs->dsisr;
187 if (ppmu->flags & PPMU_HAS_SIER)
188 sdar_valid = regs->dar & SIER_SDAR_VALID;
190 unsigned long sdsync;
192 if (ppmu->flags & PPMU_SIAR_VALID)
193 sdsync = POWER7P_MMCRA_SDAR_VALID;
194 else if (ppmu->flags & PPMU_ALT_SIPR)
195 sdsync = POWER6_MMCRA_SDSYNC;
196 else if (ppmu->flags & PPMU_NO_SIAR)
197 sdsync = MMCRA_SAMPLE_ENABLE;
199 sdsync = MMCRA_SDSYNC;
201 sdar_valid = mmcra & sdsync;
204 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
205 *addrp = mfspr(SPRN_SDAR);
207 if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0)
211 static bool regs_sihv(struct pt_regs *regs)
213 unsigned long sihv = MMCRA_SIHV;
215 if (ppmu->flags & PPMU_HAS_SIER)
216 return !!(regs->dar & SIER_SIHV);
218 if (ppmu->flags & PPMU_ALT_SIPR)
219 sihv = POWER6_MMCRA_SIHV;
221 return !!(regs->dsisr & sihv);
224 static bool regs_sipr(struct pt_regs *regs)
226 unsigned long sipr = MMCRA_SIPR;
228 if (ppmu->flags & PPMU_HAS_SIER)
229 return !!(regs->dar & SIER_SIPR);
231 if (ppmu->flags & PPMU_ALT_SIPR)
232 sipr = POWER6_MMCRA_SIPR;
234 return !!(regs->dsisr & sipr);
237 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
239 if (regs->msr & MSR_PR)
240 return PERF_RECORD_MISC_USER;
241 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
242 return PERF_RECORD_MISC_HYPERVISOR;
243 return PERF_RECORD_MISC_KERNEL;
246 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
248 bool use_siar = regs_use_siar(regs);
251 return perf_flags_from_msr(regs);
254 * If we don't have flags in MMCRA, rather than using
255 * the MSR, we intuit the flags from the address in
256 * SIAR which should give slightly more reliable
259 if (ppmu->flags & PPMU_NO_SIPR) {
260 unsigned long siar = mfspr(SPRN_SIAR);
261 if (is_kernel_addr(siar))
262 return PERF_RECORD_MISC_KERNEL;
263 return PERF_RECORD_MISC_USER;
266 /* PR has priority over HV, so order below is important */
268 return PERF_RECORD_MISC_USER;
270 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
271 return PERF_RECORD_MISC_HYPERVISOR;
273 return PERF_RECORD_MISC_KERNEL;
277 * Overload regs->dsisr to store MMCRA so we only need to read it once
279 * Overload regs->dar to store SIER if we have it.
280 * Overload regs->result to specify whether we should use the MSR (result
281 * is zero) or the SIAR (result is non zero).
283 static inline void perf_read_regs(struct pt_regs *regs)
285 unsigned long mmcra = mfspr(SPRN_MMCRA);
286 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
291 if (ppmu->flags & PPMU_HAS_SIER)
292 regs->dar = mfspr(SPRN_SIER);
295 * If this isn't a PMU exception (eg a software event) the SIAR is
296 * not valid. Use pt_regs.
298 * If it is a marked event use the SIAR.
300 * If the PMU doesn't update the SIAR for non marked events use
303 * If the PMU has HV/PR flags then check to see if they
304 * place the exception in userspace. If so, use pt_regs. In
305 * continuous sampling mode the SIAR and the PMU exception are
306 * not synchronised, so they may be many instructions apart.
307 * This can result in confusing backtraces. We still want
308 * hypervisor samples as well as samples in the kernel with
309 * interrupts off hence the userspace check.
311 if (TRAP(regs) != 0xf00)
313 else if ((ppmu->flags & PPMU_NO_SIAR))
317 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
319 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
324 regs->result = use_siar;
328 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
331 static inline int perf_intr_is_nmi(struct pt_regs *regs)
333 return (regs->softe & IRQS_DISABLED);
337 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
338 * must be sampled only if the SIAR-valid bit is set.
340 * For unmarked instructions and for processors that don't have the SIAR-Valid
341 * bit, assume that SIAR is valid.
343 static inline int siar_valid(struct pt_regs *regs)
345 unsigned long mmcra = regs->dsisr;
346 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
349 if (ppmu->flags & PPMU_HAS_SIER)
350 return regs->dar & SIER_SIAR_VALID;
352 if (ppmu->flags & PPMU_SIAR_VALID)
353 return mmcra & POWER7P_MMCRA_SIAR_VALID;
360 /* Reset all possible BHRB entries */
361 static void power_pmu_bhrb_reset(void)
363 asm volatile(PPC_CLRBHRB);
366 static void power_pmu_bhrb_enable(struct perf_event *event)
368 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
373 /* Clear BHRB if we changed task context to avoid data leaks */
374 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
375 power_pmu_bhrb_reset();
376 cpuhw->bhrb_context = event->ctx;
379 perf_sched_cb_inc(event->ctx->pmu);
382 static void power_pmu_bhrb_disable(struct perf_event *event)
384 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
389 WARN_ON_ONCE(!cpuhw->bhrb_users);
391 perf_sched_cb_dec(event->ctx->pmu);
393 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
394 /* BHRB cannot be turned off when other
395 * events are active on the PMU.
398 /* avoid stale pointer */
399 cpuhw->bhrb_context = NULL;
403 /* Called from ctxsw to prevent one process's branch entries to
404 * mingle with the other process's entries during context switch.
406 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
412 power_pmu_bhrb_reset();
414 /* Calculate the to address for a branch */
415 static __u64 power_pmu_bhrb_to(u64 addr)
420 if (is_kernel_addr(addr)) {
421 if (copy_from_kernel_nofault(&instr, (void *)addr,
425 return branch_target((struct ppc_inst *)&instr);
428 /* Userspace: need copy instruction here then translate it */
429 if (copy_from_user_nofault(&instr, (unsigned int __user *)addr,
433 target = branch_target((struct ppc_inst *)&instr);
434 if ((!target) || (instr & BRANCH_ABSOLUTE))
437 /* Translate relative branch target from kernel to user address */
438 return target - (unsigned long)&instr + addr;
441 /* Processing BHRB entries */
442 static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw)
446 int r_index, u_index, pred;
450 while (r_index < ppmu->bhrb_nr) {
451 /* Assembly read function */
452 val = read_bhrb(r_index++);
454 /* Terminal marker: End of valid BHRB entries */
457 addr = val & BHRB_EA;
458 pred = val & BHRB_PREDICTION;
465 * BHRB rolling buffer could very much contain the kernel
466 * addresses at this point. Check the privileges before
467 * exporting it to userspace (avoid exposure of regions
468 * where we could have speculative execution)
470 if (is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0)
473 /* Branches are read most recent first (ie. mfbhrb 0 is
474 * the most recent branch).
475 * There are two types of valid entries:
476 * 1) a target entry which is the to address of a
477 * computed goto like a blr,bctr,btar. The next
478 * entry read from the bhrb will be branch
479 * corresponding to this target (ie. the actual
480 * blr/bctr/btar instruction).
481 * 2) a from address which is an actual branch. If a
482 * target entry proceeds this, then this is the
483 * matching branch for that target. If this is not
484 * following a target entry, then this is a branch
485 * where the target is given as an immediate field
486 * in the instruction (ie. an i or b form branch).
487 * In this case we need to read the instruction from
488 * memory to determine the target/to address.
491 if (val & BHRB_TARGET) {
492 /* Target branches use two entries
493 * (ie. computed gotos/XL form)
495 cpuhw->bhrb_entries[u_index].to = addr;
496 cpuhw->bhrb_entries[u_index].mispred = pred;
497 cpuhw->bhrb_entries[u_index].predicted = ~pred;
499 /* Get from address in next entry */
500 val = read_bhrb(r_index++);
501 addr = val & BHRB_EA;
502 if (val & BHRB_TARGET) {
503 /* Shouldn't have two targets in a
504 row.. Reset index and try again */
508 cpuhw->bhrb_entries[u_index].from = addr;
510 /* Branches to immediate field
512 cpuhw->bhrb_entries[u_index].from = addr;
513 cpuhw->bhrb_entries[u_index].to =
514 power_pmu_bhrb_to(addr);
515 cpuhw->bhrb_entries[u_index].mispred = pred;
516 cpuhw->bhrb_entries[u_index].predicted = ~pred;
522 cpuhw->bhrb_stack.nr = u_index;
523 cpuhw->bhrb_stack.hw_idx = -1ULL;
527 static bool is_ebb_event(struct perf_event *event)
530 * This could be a per-PMU callback, but we'd rather avoid the cost. We
531 * check that the PMU supports EBB, meaning those that don't can still
532 * use bit 63 of the event code for something else if they wish.
534 return (ppmu->flags & PPMU_ARCH_207S) &&
535 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
538 static int ebb_event_check(struct perf_event *event)
540 struct perf_event *leader = event->group_leader;
542 /* Event and group leader must agree on EBB */
543 if (is_ebb_event(leader) != is_ebb_event(event))
546 if (is_ebb_event(event)) {
547 if (!(event->attach_state & PERF_ATTACH_TASK))
550 if (!leader->attr.pinned || !leader->attr.exclusive)
553 if (event->attr.freq ||
554 event->attr.inherit ||
555 event->attr.sample_type ||
556 event->attr.sample_period ||
557 event->attr.enable_on_exec)
564 static void ebb_event_add(struct perf_event *event)
566 if (!is_ebb_event(event) || current->thread.used_ebb)
570 * IFF this is the first time we've added an EBB event, set
571 * PMXE in the user MMCR0 so we can detect when it's cleared by
572 * userspace. We need this so that we can context switch while
573 * userspace is in the EBB handler (where PMXE is 0).
575 current->thread.used_ebb = 1;
576 current->thread.mmcr0 |= MMCR0_PMXE;
579 static void ebb_switch_out(unsigned long mmcr0)
581 if (!(mmcr0 & MMCR0_EBE))
584 current->thread.siar = mfspr(SPRN_SIAR);
585 current->thread.sier = mfspr(SPRN_SIER);
586 current->thread.sdar = mfspr(SPRN_SDAR);
587 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
588 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
591 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
593 unsigned long mmcr0 = cpuhw->mmcr[0];
598 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
599 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
602 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
603 * with pmao_restore_workaround() because we may add PMAO but we never
606 mmcr0 |= current->thread.mmcr0;
609 * Be careful not to set PMXE if userspace had it cleared. This is also
610 * compatible with pmao_restore_workaround() because it has already
611 * cleared PMXE and we leave PMAO alone.
613 if (!(current->thread.mmcr0 & MMCR0_PMXE))
614 mmcr0 &= ~MMCR0_PMXE;
616 mtspr(SPRN_SIAR, current->thread.siar);
617 mtspr(SPRN_SIER, current->thread.sier);
618 mtspr(SPRN_SDAR, current->thread.sdar);
621 * Merge the kernel & user values of MMCR2. The semantics we implement
622 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
623 * but not clear bits. If a task wants to be able to clear bits, ie.
624 * unfreeze counters, it should not set exclude_xxx in its events and
625 * instead manage the MMCR2 entirely by itself.
627 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
632 static void pmao_restore_workaround(bool ebb)
636 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
640 * On POWER8E there is a hardware defect which affects the PMU context
641 * switch logic, ie. power_pmu_disable/enable().
643 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
644 * by the hardware. Sometime later the actual PMU exception is
647 * If we context switch, or simply disable/enable, the PMU prior to the
648 * exception arriving, the exception will be lost when we clear PMAO.
650 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
651 * set, and this _should_ generate an exception. However because of the
652 * defect no exception is generated when we write PMAO, and we get
653 * stuck with no counters counting but no exception delivered.
655 * The workaround is to detect this case and tweak the hardware to
656 * create another pending PMU exception.
658 * We do that by setting up PMC6 (cycles) for an imminent overflow and
659 * enabling the PMU. That causes a new exception to be generated in the
660 * chip, but we don't take it yet because we have interrupts hard
661 * disabled. We then write back the PMU state as we want it to be seen
662 * by the exception handler. When we reenable interrupts the exception
663 * handler will be called and see the correct state.
665 * The logic is the same for EBB, except that the exception is gated by
666 * us having interrupts hard disabled as well as the fact that we are
667 * not in userspace. The exception is finally delivered when we return
671 /* Only if PMAO is set and PMAO_SYNC is clear */
672 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
675 /* If we're doing EBB, only if BESCR[GE] is set */
676 if (ebb && !(current->thread.bescr & BESCR_GE))
680 * We are already soft-disabled in power_pmu_enable(). We need to hard
681 * disable to actually prevent the PMU exception from firing.
686 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
687 * Using read/write_pmc() in a for loop adds 12 function calls and
688 * almost doubles our code size.
690 pmcs[0] = mfspr(SPRN_PMC1);
691 pmcs[1] = mfspr(SPRN_PMC2);
692 pmcs[2] = mfspr(SPRN_PMC3);
693 pmcs[3] = mfspr(SPRN_PMC4);
694 pmcs[4] = mfspr(SPRN_PMC5);
695 pmcs[5] = mfspr(SPRN_PMC6);
697 /* Ensure all freeze bits are unset */
698 mtspr(SPRN_MMCR2, 0);
700 /* Set up PMC6 to overflow in one cycle */
701 mtspr(SPRN_PMC6, 0x7FFFFFFE);
703 /* Enable exceptions and unfreeze PMC6 */
704 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
706 /* Now we need to refreeze and restore the PMCs */
707 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
709 mtspr(SPRN_PMC1, pmcs[0]);
710 mtspr(SPRN_PMC2, pmcs[1]);
711 mtspr(SPRN_PMC3, pmcs[2]);
712 mtspr(SPRN_PMC4, pmcs[3]);
713 mtspr(SPRN_PMC5, pmcs[4]);
714 mtspr(SPRN_PMC6, pmcs[5]);
717 #endif /* CONFIG_PPC64 */
719 static void perf_event_interrupt(struct pt_regs *regs);
722 * Read one performance monitor counter (PMC).
724 static unsigned long read_pmc(int idx)
730 val = mfspr(SPRN_PMC1);
733 val = mfspr(SPRN_PMC2);
736 val = mfspr(SPRN_PMC3);
739 val = mfspr(SPRN_PMC4);
742 val = mfspr(SPRN_PMC5);
745 val = mfspr(SPRN_PMC6);
749 val = mfspr(SPRN_PMC7);
752 val = mfspr(SPRN_PMC8);
754 #endif /* CONFIG_PPC64 */
756 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
765 static void write_pmc(int idx, unsigned long val)
769 mtspr(SPRN_PMC1, val);
772 mtspr(SPRN_PMC2, val);
775 mtspr(SPRN_PMC3, val);
778 mtspr(SPRN_PMC4, val);
781 mtspr(SPRN_PMC5, val);
784 mtspr(SPRN_PMC6, val);
788 mtspr(SPRN_PMC7, val);
791 mtspr(SPRN_PMC8, val);
793 #endif /* CONFIG_PPC64 */
795 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
799 /* Called from sysrq_handle_showregs() */
800 void perf_event_print_debug(void)
802 unsigned long sdar, sier, flags;
803 u32 pmcs[MAX_HWEVENTS];
807 pr_info("Performance monitor hardware not registered.\n");
811 if (!ppmu->n_counter)
814 local_irq_save(flags);
816 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
817 smp_processor_id(), ppmu->name, ppmu->n_counter);
819 for (i = 0; i < ppmu->n_counter; i++)
820 pmcs[i] = read_pmc(i + 1);
822 for (; i < MAX_HWEVENTS; i++)
823 pmcs[i] = 0xdeadbeef;
825 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
826 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
828 if (ppmu->n_counter > 4)
829 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
830 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
832 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
833 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
837 sdar = mfspr(SPRN_SDAR);
839 if (ppmu->flags & PPMU_HAS_SIER)
840 sier = mfspr(SPRN_SIER);
842 if (ppmu->flags & PPMU_ARCH_207S) {
843 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
844 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
845 pr_info("EBBRR: %016lx BESCR: %016lx\n",
846 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
849 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
850 mfspr(SPRN_SIAR), sdar, sier);
852 local_irq_restore(flags);
856 * Check if a set of events can all go on the PMU at once.
857 * If they can't, this will look at alternative codes for the events
858 * and see if any combination of alternative codes is feasible.
859 * The feasible set is returned in event_id[].
861 static int power_check_constraints(struct cpu_hw_events *cpuhw,
862 u64 event_id[], unsigned int cflags[],
865 unsigned long mask, value, nv;
866 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
867 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
869 unsigned long addf = ppmu->add_fields;
870 unsigned long tadd = ppmu->test_adder;
871 unsigned long grp_mask = ppmu->group_constraint_mask;
872 unsigned long grp_val = ppmu->group_constraint_val;
874 if (n_ev > ppmu->n_counter)
877 /* First see if the events will go on as-is */
878 for (i = 0; i < n_ev; ++i) {
879 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
880 && !ppmu->limited_pmc_event(event_id[i])) {
881 ppmu->get_alternatives(event_id[i], cflags[i],
882 cpuhw->alternatives[i]);
883 event_id[i] = cpuhw->alternatives[i][0];
885 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
886 &cpuhw->avalues[i][0]))
890 for (i = 0; i < n_ev; ++i) {
891 nv = (value | cpuhw->avalues[i][0]) +
892 (value & cpuhw->avalues[i][0] & addf);
894 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0)
897 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0])
902 mask |= cpuhw->amasks[i][0];
905 if ((value & mask & grp_mask) != (mask & grp_val))
908 return 0; /* all OK */
911 /* doesn't work, gather alternatives... */
912 if (!ppmu->get_alternatives)
914 for (i = 0; i < n_ev; ++i) {
916 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
917 cpuhw->alternatives[i]);
918 for (j = 1; j < n_alt[i]; ++j)
919 ppmu->get_constraint(cpuhw->alternatives[i][j],
920 &cpuhw->amasks[i][j],
921 &cpuhw->avalues[i][j]);
924 /* enumerate all possibilities and see if any will work */
927 value = mask = nv = 0;
930 /* we're backtracking, restore context */
936 * See if any alternative k for event_id i,
937 * where k > j, will satisfy the constraints.
939 while (++j < n_alt[i]) {
940 nv = (value | cpuhw->avalues[i][j]) +
941 (value & cpuhw->avalues[i][j] & addf);
942 if ((((nv + tadd) ^ value) & mask) == 0 &&
943 (((nv + tadd) ^ cpuhw->avalues[i][j])
944 & cpuhw->amasks[i][j]) == 0)
949 * No feasible alternative, backtrack
950 * to event_id i-1 and continue enumerating its
951 * alternatives from where we got up to.
957 * Found a feasible alternative for event_id i,
958 * remember where we got up to with this event_id,
959 * go on to the next event_id, and start with
960 * the first alternative for it.
966 mask |= cpuhw->amasks[i][j];
972 /* OK, we have a feasible combination, tell the caller the solution */
973 for (i = 0; i < n_ev; ++i)
974 event_id[i] = cpuhw->alternatives[i][choice[i]];
979 * Check if newly-added events have consistent settings for
980 * exclude_{user,kernel,hv} with each other and any previously
983 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
984 int n_prev, int n_new)
986 int eu = 0, ek = 0, eh = 0;
988 struct perf_event *event;
991 * If the PMU we're on supports per event exclude settings then we
992 * don't need to do any of this logic. NB. This assumes no PMU has both
993 * per event exclude and limited PMCs.
995 if (ppmu->flags & PPMU_ARCH_207S)
1003 for (i = 0; i < n; ++i) {
1004 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1005 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1010 eu = event->attr.exclude_user;
1011 ek = event->attr.exclude_kernel;
1012 eh = event->attr.exclude_hv;
1014 } else if (event->attr.exclude_user != eu ||
1015 event->attr.exclude_kernel != ek ||
1016 event->attr.exclude_hv != eh) {
1022 for (i = 0; i < n; ++i)
1023 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1024 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1029 static u64 check_and_compute_delta(u64 prev, u64 val)
1031 u64 delta = (val - prev) & 0xfffffffful;
1034 * POWER7 can roll back counter values, if the new value is smaller
1035 * than the previous value it will cause the delta and the counter to
1036 * have bogus values unless we rolled a counter over. If a coutner is
1037 * rolled back, it will be smaller, but within 256, which is the maximum
1038 * number of events to rollback at once. If we detect a rollback
1039 * return 0. This can lead to a small lack of precision in the
1042 if (prev > val && (prev - val) < 256)
1048 static void power_pmu_read(struct perf_event *event)
1050 s64 val, delta, prev;
1052 if (event->hw.state & PERF_HES_STOPPED)
1058 if (is_ebb_event(event)) {
1059 val = read_pmc(event->hw.idx);
1060 local64_set(&event->hw.prev_count, val);
1065 * Performance monitor interrupts come even when interrupts
1066 * are soft-disabled, as long as interrupts are hard-enabled.
1067 * Therefore we treat them like NMIs.
1070 prev = local64_read(&event->hw.prev_count);
1072 val = read_pmc(event->hw.idx);
1073 delta = check_and_compute_delta(prev, val);
1076 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1078 local64_add(delta, &event->count);
1081 * A number of places program the PMC with (0x80000000 - period_left).
1082 * We never want period_left to be less than 1 because we will program
1083 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1084 * roll around to 0 before taking an exception. We have seen this
1087 * To fix this, clamp the minimum value of period_left to 1.
1090 prev = local64_read(&event->hw.period_left);
1094 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1098 * On some machines, PMC5 and PMC6 can't be written, don't respect
1099 * the freeze conditions, and don't generate interrupts. This tells
1100 * us if `event' is using such a PMC.
1102 static int is_limited_pmc(int pmcnum)
1104 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1105 && (pmcnum == 5 || pmcnum == 6);
1108 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1109 unsigned long pmc5, unsigned long pmc6)
1111 struct perf_event *event;
1112 u64 val, prev, delta;
1115 for (i = 0; i < cpuhw->n_limited; ++i) {
1116 event = cpuhw->limited_counter[i];
1119 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1120 prev = local64_read(&event->hw.prev_count);
1122 delta = check_and_compute_delta(prev, val);
1124 local64_add(delta, &event->count);
1128 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1129 unsigned long pmc5, unsigned long pmc6)
1131 struct perf_event *event;
1135 for (i = 0; i < cpuhw->n_limited; ++i) {
1136 event = cpuhw->limited_counter[i];
1137 event->hw.idx = cpuhw->limited_hwidx[i];
1138 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1139 prev = local64_read(&event->hw.prev_count);
1140 if (check_and_compute_delta(prev, val))
1141 local64_set(&event->hw.prev_count, val);
1142 perf_event_update_userpage(event);
1147 * Since limited events don't respect the freeze conditions, we
1148 * have to read them immediately after freezing or unfreezing the
1149 * other events. We try to keep the values from the limited
1150 * events as consistent as possible by keeping the delay (in
1151 * cycles and instructions) between freezing/unfreezing and reading
1152 * the limited events as small and consistent as possible.
1153 * Therefore, if any limited events are in use, we read them
1154 * both, and always in the same order, to minimize variability,
1155 * and do it inside the same asm that writes MMCR0.
1157 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1159 unsigned long pmc5, pmc6;
1161 if (!cpuhw->n_limited) {
1162 mtspr(SPRN_MMCR0, mmcr0);
1167 * Write MMCR0, then read PMC5 and PMC6 immediately.
1168 * To ensure we don't get a performance monitor interrupt
1169 * between writing MMCR0 and freezing/thawing the limited
1170 * events, we first write MMCR0 with the event overflow
1171 * interrupt enable bits turned off.
1173 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1174 : "=&r" (pmc5), "=&r" (pmc6)
1175 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1177 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1179 if (mmcr0 & MMCR0_FC)
1180 freeze_limited_counters(cpuhw, pmc5, pmc6);
1182 thaw_limited_counters(cpuhw, pmc5, pmc6);
1185 * Write the full MMCR0 including the event overflow interrupt
1186 * enable bits, if necessary.
1188 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1189 mtspr(SPRN_MMCR0, mmcr0);
1193 * Disable all events to prevent PMU interrupts and to allow
1194 * events to be added or removed.
1196 static void power_pmu_disable(struct pmu *pmu)
1198 struct cpu_hw_events *cpuhw;
1199 unsigned long flags, mmcr0, val;
1203 local_irq_save(flags);
1204 cpuhw = this_cpu_ptr(&cpu_hw_events);
1206 if (!cpuhw->disabled) {
1208 * Check if we ever enabled the PMU on this cpu.
1210 if (!cpuhw->pmcs_enabled) {
1212 cpuhw->pmcs_enabled = 1;
1216 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1218 val = mmcr0 = mfspr(SPRN_MMCR0);
1220 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1224 * The barrier is to make sure the mtspr has been
1225 * executed and the PMU has frozen the events etc.
1228 write_mmcr0(cpuhw, val);
1233 * Disable instruction sampling if it was enabled
1235 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1237 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1242 cpuhw->disabled = 1;
1245 ebb_switch_out(mmcr0);
1249 * These are readable by userspace, may contain kernel
1250 * addresses and are not switched by context switch, so clear
1251 * them now to avoid leaking anything to userspace in general
1252 * including to another process.
1254 if (ppmu->flags & PPMU_ARCH_207S) {
1255 mtspr(SPRN_SDAR, 0);
1256 mtspr(SPRN_SIAR, 0);
1261 local_irq_restore(flags);
1265 * Re-enable all events if disable == 0.
1266 * If we were previously disabled and events were added, then
1267 * put the new config on the PMU.
1269 static void power_pmu_enable(struct pmu *pmu)
1271 struct perf_event *event;
1272 struct cpu_hw_events *cpuhw;
1273 unsigned long flags;
1275 unsigned long val, mmcr0;
1277 unsigned int hwc_index[MAX_HWEVENTS];
1284 local_irq_save(flags);
1286 cpuhw = this_cpu_ptr(&cpu_hw_events);
1287 if (!cpuhw->disabled)
1290 if (cpuhw->n_events == 0) {
1291 ppc_set_pmu_inuse(0);
1295 cpuhw->disabled = 0;
1298 * EBB requires an exclusive group and all events must have the EBB
1299 * flag set, or not set, so we can just check a single event. Also we
1300 * know we have at least one event.
1302 ebb = is_ebb_event(cpuhw->event[0]);
1305 * If we didn't change anything, or only removed events,
1306 * no need to recalculate MMCR* settings and reset the PMCs.
1307 * Just reenable the PMU with the current MMCR* settings
1308 * (possibly updated for removal of events).
1310 if (!cpuhw->n_added) {
1311 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1312 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1317 * Clear all MMCR settings and recompute them for the new set of events.
1319 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1321 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1322 cpuhw->mmcr, cpuhw->event)) {
1323 /* shouldn't ever get here */
1324 printk(KERN_ERR "oops compute_mmcr failed\n");
1328 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1330 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1331 * bits for the first event. We have already checked that all
1332 * events have the same value for these bits as the first event.
1334 event = cpuhw->event[0];
1335 if (event->attr.exclude_user)
1336 cpuhw->mmcr[0] |= MMCR0_FCP;
1337 if (event->attr.exclude_kernel)
1338 cpuhw->mmcr[0] |= freeze_events_kernel;
1339 if (event->attr.exclude_hv)
1340 cpuhw->mmcr[0] |= MMCR0_FCHV;
1344 * Write the new configuration to MMCR* with the freeze
1345 * bit set and set the hardware events to their initial values.
1346 * Then unfreeze the events.
1348 ppc_set_pmu_inuse(1);
1349 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1350 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1351 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1353 if (ppmu->flags & PPMU_ARCH_207S)
1354 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1357 * Read off any pre-existing events that need to move
1360 for (i = 0; i < cpuhw->n_events; ++i) {
1361 event = cpuhw->event[i];
1362 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1363 power_pmu_read(event);
1364 write_pmc(event->hw.idx, 0);
1370 * Initialize the PMCs for all the new and moved events.
1372 cpuhw->n_limited = n_lim = 0;
1373 for (i = 0; i < cpuhw->n_events; ++i) {
1374 event = cpuhw->event[i];
1377 idx = hwc_index[i] + 1;
1378 if (is_limited_pmc(idx)) {
1379 cpuhw->limited_counter[n_lim] = event;
1380 cpuhw->limited_hwidx[n_lim] = idx;
1386 val = local64_read(&event->hw.prev_count);
1389 if (event->hw.sample_period) {
1390 left = local64_read(&event->hw.period_left);
1391 if (left < 0x80000000L)
1392 val = 0x80000000L - left;
1394 local64_set(&event->hw.prev_count, val);
1397 event->hw.idx = idx;
1398 if (event->hw.state & PERF_HES_STOPPED)
1400 write_pmc(idx, val);
1402 perf_event_update_userpage(event);
1404 cpuhw->n_limited = n_lim;
1405 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1408 pmao_restore_workaround(ebb);
1410 mmcr0 = ebb_switch_in(ebb, cpuhw);
1413 if (cpuhw->bhrb_users)
1414 ppmu->config_bhrb(cpuhw->bhrb_filter);
1416 write_mmcr0(cpuhw, mmcr0);
1419 * Enable instruction sampling if necessary
1421 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1423 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1428 local_irq_restore(flags);
1431 static int collect_events(struct perf_event *group, int max_count,
1432 struct perf_event *ctrs[], u64 *events,
1433 unsigned int *flags)
1436 struct perf_event *event;
1438 if (group->pmu->task_ctx_nr == perf_hw_context) {
1442 flags[n] = group->hw.event_base;
1443 events[n++] = group->hw.config;
1445 for_each_sibling_event(event, group) {
1446 if (event->pmu->task_ctx_nr == perf_hw_context &&
1447 event->state != PERF_EVENT_STATE_OFF) {
1451 flags[n] = event->hw.event_base;
1452 events[n++] = event->hw.config;
1459 * Add an event to the PMU.
1460 * If all events are not already frozen, then we disable and
1461 * re-enable the PMU in order to get hw_perf_enable to do the
1462 * actual work of reconfiguring the PMU.
1464 static int power_pmu_add(struct perf_event *event, int ef_flags)
1466 struct cpu_hw_events *cpuhw;
1467 unsigned long flags;
1471 local_irq_save(flags);
1472 perf_pmu_disable(event->pmu);
1475 * Add the event to the list (if there is room)
1476 * and check whether the total set is still feasible.
1478 cpuhw = this_cpu_ptr(&cpu_hw_events);
1479 n0 = cpuhw->n_events;
1480 if (n0 >= ppmu->n_counter)
1482 cpuhw->event[n0] = event;
1483 cpuhw->events[n0] = event->hw.config;
1484 cpuhw->flags[n0] = event->hw.event_base;
1487 * This event may have been disabled/stopped in record_and_restart()
1488 * because we exceeded the ->event_limit. If re-starting the event,
1489 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1490 * notification is re-enabled.
1492 if (!(ef_flags & PERF_EF_START))
1493 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1495 event->hw.state = 0;
1498 * If group events scheduling transaction was started,
1499 * skip the schedulability test here, it will be performed
1500 * at commit time(->commit_txn) as a whole
1502 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1505 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1507 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1509 event->hw.config = cpuhw->events[n0];
1512 ebb_event_add(event);
1519 if (has_branch_stack(event)) {
1520 power_pmu_bhrb_enable(event);
1521 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1522 event->attr.branch_sample_type);
1525 perf_pmu_enable(event->pmu);
1526 local_irq_restore(flags);
1531 * Remove an event from the PMU.
1533 static void power_pmu_del(struct perf_event *event, int ef_flags)
1535 struct cpu_hw_events *cpuhw;
1537 unsigned long flags;
1539 local_irq_save(flags);
1540 perf_pmu_disable(event->pmu);
1542 power_pmu_read(event);
1544 cpuhw = this_cpu_ptr(&cpu_hw_events);
1545 for (i = 0; i < cpuhw->n_events; ++i) {
1546 if (event == cpuhw->event[i]) {
1547 while (++i < cpuhw->n_events) {
1548 cpuhw->event[i-1] = cpuhw->event[i];
1549 cpuhw->events[i-1] = cpuhw->events[i];
1550 cpuhw->flags[i-1] = cpuhw->flags[i];
1553 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1554 if (event->hw.idx) {
1555 write_pmc(event->hw.idx, 0);
1558 perf_event_update_userpage(event);
1562 for (i = 0; i < cpuhw->n_limited; ++i)
1563 if (event == cpuhw->limited_counter[i])
1565 if (i < cpuhw->n_limited) {
1566 while (++i < cpuhw->n_limited) {
1567 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1568 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1572 if (cpuhw->n_events == 0) {
1573 /* disable exceptions if no events are running */
1574 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1577 if (has_branch_stack(event))
1578 power_pmu_bhrb_disable(event);
1580 perf_pmu_enable(event->pmu);
1581 local_irq_restore(flags);
1585 * POWER-PMU does not support disabling individual counters, hence
1586 * program their cycle counter to their max value and ignore the interrupts.
1589 static void power_pmu_start(struct perf_event *event, int ef_flags)
1591 unsigned long flags;
1595 if (!event->hw.idx || !event->hw.sample_period)
1598 if (!(event->hw.state & PERF_HES_STOPPED))
1601 if (ef_flags & PERF_EF_RELOAD)
1602 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1604 local_irq_save(flags);
1605 perf_pmu_disable(event->pmu);
1607 event->hw.state = 0;
1608 left = local64_read(&event->hw.period_left);
1611 if (left < 0x80000000L)
1612 val = 0x80000000L - left;
1614 write_pmc(event->hw.idx, val);
1616 perf_event_update_userpage(event);
1617 perf_pmu_enable(event->pmu);
1618 local_irq_restore(flags);
1621 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1623 unsigned long flags;
1625 if (!event->hw.idx || !event->hw.sample_period)
1628 if (event->hw.state & PERF_HES_STOPPED)
1631 local_irq_save(flags);
1632 perf_pmu_disable(event->pmu);
1634 power_pmu_read(event);
1635 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1636 write_pmc(event->hw.idx, 0);
1638 perf_event_update_userpage(event);
1639 perf_pmu_enable(event->pmu);
1640 local_irq_restore(flags);
1644 * Start group events scheduling transaction
1645 * Set the flag to make pmu::enable() not perform the
1646 * schedulability test, it will be performed at commit time
1648 * We only support PERF_PMU_TXN_ADD transactions. Save the
1649 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1652 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1654 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1656 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1658 cpuhw->txn_flags = txn_flags;
1659 if (txn_flags & ~PERF_PMU_TXN_ADD)
1662 perf_pmu_disable(pmu);
1663 cpuhw->n_txn_start = cpuhw->n_events;
1667 * Stop group events scheduling transaction
1668 * Clear the flag and pmu::enable() will perform the
1669 * schedulability test.
1671 static void power_pmu_cancel_txn(struct pmu *pmu)
1673 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1674 unsigned int txn_flags;
1676 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1678 txn_flags = cpuhw->txn_flags;
1679 cpuhw->txn_flags = 0;
1680 if (txn_flags & ~PERF_PMU_TXN_ADD)
1683 perf_pmu_enable(pmu);
1687 * Commit group events scheduling transaction
1688 * Perform the group schedulability test as a whole
1689 * Return 0 if success
1691 static int power_pmu_commit_txn(struct pmu *pmu)
1693 struct cpu_hw_events *cpuhw;
1699 cpuhw = this_cpu_ptr(&cpu_hw_events);
1700 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1702 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1703 cpuhw->txn_flags = 0;
1707 n = cpuhw->n_events;
1708 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1710 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1714 for (i = cpuhw->n_txn_start; i < n; ++i)
1715 cpuhw->event[i]->hw.config = cpuhw->events[i];
1717 cpuhw->txn_flags = 0;
1718 perf_pmu_enable(pmu);
1723 * Return 1 if we might be able to put event on a limited PMC,
1725 * An event can only go on a limited PMC if it counts something
1726 * that a limited PMC can count, doesn't require interrupts, and
1727 * doesn't exclude any processor mode.
1729 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1733 u64 alt[MAX_EVENT_ALTERNATIVES];
1735 if (event->attr.exclude_user
1736 || event->attr.exclude_kernel
1737 || event->attr.exclude_hv
1738 || event->attr.sample_period)
1741 if (ppmu->limited_pmc_event(ev))
1745 * The requested event_id isn't on a limited PMC already;
1746 * see if any alternative code goes on a limited PMC.
1748 if (!ppmu->get_alternatives)
1751 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1752 n = ppmu->get_alternatives(ev, flags, alt);
1758 * Find an alternative event_id that goes on a normal PMC, if possible,
1759 * and return the event_id code, or 0 if there is no such alternative.
1760 * (Note: event_id code 0 is "don't count" on all machines.)
1762 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1764 u64 alt[MAX_EVENT_ALTERNATIVES];
1767 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1768 n = ppmu->get_alternatives(ev, flags, alt);
1774 /* Number of perf_events counting hardware events */
1775 static atomic_t num_events;
1776 /* Used to avoid races in calling reserve/release_pmc_hardware */
1777 static DEFINE_MUTEX(pmc_reserve_mutex);
1780 * Release the PMU if this is the last perf_event.
1782 static void hw_perf_event_destroy(struct perf_event *event)
1784 if (!atomic_add_unless(&num_events, -1, 1)) {
1785 mutex_lock(&pmc_reserve_mutex);
1786 if (atomic_dec_return(&num_events) == 0)
1787 release_pmc_hardware();
1788 mutex_unlock(&pmc_reserve_mutex);
1793 * Translate a generic cache event_id config to a raw event_id code.
1795 static int hw_perf_cache_event(u64 config, u64 *eventp)
1797 unsigned long type, op, result;
1800 if (!ppmu->cache_events)
1804 type = config & 0xff;
1805 op = (config >> 8) & 0xff;
1806 result = (config >> 16) & 0xff;
1808 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1809 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1810 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1813 ev = (*ppmu->cache_events)[type][op][result];
1822 static bool is_event_blacklisted(u64 ev)
1826 for (i=0; i < ppmu->n_blacklist_ev; i++) {
1827 if (ppmu->blacklist_ev[i] == ev)
1834 static int power_pmu_event_init(struct perf_event *event)
1837 unsigned long flags;
1838 struct perf_event *ctrs[MAX_HWEVENTS];
1839 u64 events[MAX_HWEVENTS];
1840 unsigned int cflags[MAX_HWEVENTS];
1843 struct cpu_hw_events *cpuhw;
1849 if (has_branch_stack(event)) {
1850 /* PMU has BHRB enabled */
1851 if (!(ppmu->flags & PPMU_ARCH_207S))
1855 switch (event->attr.type) {
1856 case PERF_TYPE_HARDWARE:
1857 ev = event->attr.config;
1858 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1861 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1863 ev = ppmu->generic_events[ev];
1865 case PERF_TYPE_HW_CACHE:
1866 err = hw_perf_cache_event(event->attr.config, &ev);
1870 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1874 ev = event->attr.config;
1876 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1883 event->hw.config_base = ev;
1887 * If we are not running on a hypervisor, force the
1888 * exclude_hv bit to 0 so that we don't care what
1889 * the user set it to.
1891 if (!firmware_has_feature(FW_FEATURE_LPAR))
1892 event->attr.exclude_hv = 0;
1895 * If this is a per-task event, then we can use
1896 * PM_RUN_* events interchangeably with their non RUN_*
1897 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1898 * XXX we should check if the task is an idle task.
1901 if (event->attach_state & PERF_ATTACH_TASK)
1902 flags |= PPMU_ONLY_COUNT_RUN;
1905 * If this machine has limited events, check whether this
1906 * event_id could go on a limited event.
1908 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1909 if (can_go_on_limited_pmc(event, ev, flags)) {
1910 flags |= PPMU_LIMITED_PMC_OK;
1911 } else if (ppmu->limited_pmc_event(ev)) {
1913 * The requested event_id is on a limited PMC,
1914 * but we can't use a limited PMC; see if any
1915 * alternative goes on a normal PMC.
1917 ev = normal_pmc_alternative(ev, flags);
1923 /* Extra checks for EBB */
1924 err = ebb_event_check(event);
1929 * If this is in a group, check if it can go on with all the
1930 * other hardware events in the group. We assume the event
1931 * hasn't been linked into its leader's sibling list at this point.
1934 if (event->group_leader != event) {
1935 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1936 ctrs, events, cflags);
1943 if (check_excludes(ctrs, cflags, n, 1))
1946 cpuhw = &get_cpu_var(cpu_hw_events);
1947 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1949 if (has_branch_stack(event)) {
1950 bhrb_filter = ppmu->bhrb_filter_map(
1951 event->attr.branch_sample_type);
1953 if (bhrb_filter == -1) {
1954 put_cpu_var(cpu_hw_events);
1957 cpuhw->bhrb_filter = bhrb_filter;
1960 put_cpu_var(cpu_hw_events);
1964 event->hw.config = events[n];
1965 event->hw.event_base = cflags[n];
1966 event->hw.last_period = event->hw.sample_period;
1967 local64_set(&event->hw.period_left, event->hw.last_period);
1970 * For EBB events we just context switch the PMC value, we don't do any
1971 * of the sample_period logic. We use hw.prev_count for this.
1973 if (is_ebb_event(event))
1974 local64_set(&event->hw.prev_count, 0);
1977 * See if we need to reserve the PMU.
1978 * If no events are currently in use, then we have to take a
1979 * mutex to ensure that we don't race with another task doing
1980 * reserve_pmc_hardware or release_pmc_hardware.
1983 if (!atomic_inc_not_zero(&num_events)) {
1984 mutex_lock(&pmc_reserve_mutex);
1985 if (atomic_read(&num_events) == 0 &&
1986 reserve_pmc_hardware(perf_event_interrupt))
1989 atomic_inc(&num_events);
1990 mutex_unlock(&pmc_reserve_mutex);
1992 event->destroy = hw_perf_event_destroy;
1997 static int power_pmu_event_idx(struct perf_event *event)
1999 return event->hw.idx;
2002 ssize_t power_events_sysfs_show(struct device *dev,
2003 struct device_attribute *attr, char *page)
2005 struct perf_pmu_events_attr *pmu_attr;
2007 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2009 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2012 static struct pmu power_pmu = {
2013 .pmu_enable = power_pmu_enable,
2014 .pmu_disable = power_pmu_disable,
2015 .event_init = power_pmu_event_init,
2016 .add = power_pmu_add,
2017 .del = power_pmu_del,
2018 .start = power_pmu_start,
2019 .stop = power_pmu_stop,
2020 .read = power_pmu_read,
2021 .start_txn = power_pmu_start_txn,
2022 .cancel_txn = power_pmu_cancel_txn,
2023 .commit_txn = power_pmu_commit_txn,
2024 .event_idx = power_pmu_event_idx,
2025 .sched_task = power_pmu_sched_task,
2029 * A counter has overflowed; update its count and record
2030 * things if requested. Note that interrupts are hard-disabled
2031 * here so there is no possibility of being interrupted.
2033 static void record_and_restart(struct perf_event *event, unsigned long val,
2034 struct pt_regs *regs)
2036 u64 period = event->hw.sample_period;
2037 s64 prev, delta, left;
2040 if (event->hw.state & PERF_HES_STOPPED) {
2041 write_pmc(event->hw.idx, 0);
2045 /* we don't have to worry about interrupts here */
2046 prev = local64_read(&event->hw.prev_count);
2047 delta = check_and_compute_delta(prev, val);
2048 local64_add(delta, &event->count);
2051 * See if the total period for this event has expired,
2052 * and update for the next period.
2055 left = local64_read(&event->hw.period_left) - delta;
2063 record = siar_valid(regs);
2064 event->hw.last_period = event->hw.sample_period;
2066 if (left < 0x80000000LL)
2067 val = 0x80000000LL - left;
2070 write_pmc(event->hw.idx, val);
2071 local64_set(&event->hw.prev_count, val);
2072 local64_set(&event->hw.period_left, left);
2073 perf_event_update_userpage(event);
2076 * Finally record data if requested.
2079 struct perf_sample_data data;
2081 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2083 if (event->attr.sample_type &
2084 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
2085 perf_get_data_addr(event, regs, &data.addr);
2087 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2088 struct cpu_hw_events *cpuhw;
2089 cpuhw = this_cpu_ptr(&cpu_hw_events);
2090 power_pmu_bhrb_read(event, cpuhw);
2091 data.br_stack = &cpuhw->bhrb_stack;
2094 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2095 ppmu->get_mem_data_src)
2096 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2098 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT &&
2099 ppmu->get_mem_weight)
2100 ppmu->get_mem_weight(&data.weight);
2102 if (perf_event_overflow(event, &data, regs))
2103 power_pmu_stop(event, 0);
2108 * Called from generic code to get the misc flags (i.e. processor mode)
2111 unsigned long perf_misc_flags(struct pt_regs *regs)
2113 u32 flags = perf_get_misc_flags(regs);
2117 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2118 PERF_RECORD_MISC_KERNEL;
2122 * Called from generic code to get the instruction pointer
2125 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2127 bool use_siar = regs_use_siar(regs);
2129 if (use_siar && siar_valid(regs))
2130 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2132 return 0; // no valid instruction pointer
2137 static bool pmc_overflow_power7(unsigned long val)
2140 * Events on POWER7 can roll back if a speculative event doesn't
2141 * eventually complete. Unfortunately in some rare cases they will
2142 * raise a performance monitor exception. We need to catch this to
2143 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2144 * cycles from overflow.
2146 * We only do this if the first pass fails to find any overflowing
2147 * PMCs because a user might set a period of less than 256 and we
2148 * don't want to mistakenly reset them.
2150 if ((0x80000000 - val) <= 256)
2156 static bool pmc_overflow(unsigned long val)
2165 * Performance monitor interrupt stuff
2167 static void __perf_event_interrupt(struct pt_regs *regs)
2170 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2171 struct perf_event *event;
2172 unsigned long val[8];
2176 if (cpuhw->n_limited)
2177 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2180 perf_read_regs(regs);
2183 * If perf interrupts hit in a local_irq_disable (soft-masked) region,
2184 * we consider them as NMIs. This is required to prevent hash faults on
2185 * user addresses when reading callchains. See the NMI test in
2188 nmi = perf_intr_is_nmi(regs);
2194 /* Read all the PMCs since we'll need them a bunch of times */
2195 for (i = 0; i < ppmu->n_counter; ++i)
2196 val[i] = read_pmc(i + 1);
2198 /* Try to find what caused the IRQ */
2200 for (i = 0; i < ppmu->n_counter; ++i) {
2201 if (!pmc_overflow(val[i]))
2203 if (is_limited_pmc(i + 1))
2204 continue; /* these won't generate IRQs */
2206 * We've found one that's overflowed. For active
2207 * counters we need to log this. For inactive
2208 * counters, we need to reset it anyway
2212 for (j = 0; j < cpuhw->n_events; ++j) {
2213 event = cpuhw->event[j];
2214 if (event->hw.idx == (i + 1)) {
2216 record_and_restart(event, val[i], regs);
2221 /* reset non active counters that have overflowed */
2222 write_pmc(i + 1, 0);
2224 if (!found && pvr_version_is(PVR_POWER7)) {
2225 /* check active counters for special buggy p7 overflow */
2226 for (i = 0; i < cpuhw->n_events; ++i) {
2227 event = cpuhw->event[i];
2228 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2230 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2231 /* event has overflowed in a buggy way*/
2233 record_and_restart(event,
2234 val[event->hw.idx - 1],
2239 if (!found && !nmi && printk_ratelimit())
2240 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2243 * Reset MMCR0 to its normal value. This will set PMXE and
2244 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2245 * and thus allow interrupts to occur again.
2246 * XXX might want to use MSR.PM to keep the events frozen until
2247 * we get back out of this interrupt.
2249 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2257 static void perf_event_interrupt(struct pt_regs *regs)
2259 u64 start_clock = sched_clock();
2261 __perf_event_interrupt(regs);
2262 perf_sample_event_took(sched_clock() - start_clock);
2265 static int power_pmu_prepare_cpu(unsigned int cpu)
2267 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2270 memset(cpuhw, 0, sizeof(*cpuhw));
2271 cpuhw->mmcr[0] = MMCR0_FC;
2276 int register_power_pmu(struct power_pmu *pmu)
2279 return -EBUSY; /* something's already registered */
2282 pr_info("%s performance monitor hardware support registered\n",
2285 power_pmu.attr_groups = ppmu->attr_groups;
2289 * Use FCHV to ignore kernel events if MSR.HV is set.
2291 if (mfmsr() & MSR_HV)
2292 freeze_events_kernel = MMCR0_FCHV;
2293 #endif /* CONFIG_PPC64 */
2295 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2296 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2297 power_pmu_prepare_cpu, NULL);
2302 static int __init init_ppc64_pmu(void)
2304 /* run through all the pmu drivers one at a time */
2305 if (!init_power5_pmu())
2307 else if (!init_power5p_pmu())
2309 else if (!init_power6_pmu())
2311 else if (!init_power7_pmu())
2313 else if (!init_power8_pmu())
2315 else if (!init_power9_pmu())
2317 else if (!init_ppc970_pmu())
2320 return init_generic_compat_pmu();
2322 early_initcall(init_ppc64_pmu);