2 * Low level TLB miss handlers for Book3E
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
23 #include <asm/kvm_asm.h>
24 #include <asm/kvm_booke_hv_asm.h>
26 #ifdef CONFIG_PPC_64K_PAGES
27 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
29 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
31 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
32 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
33 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
35 /**********************************************************************
37 * TLB miss handling for Book3E with a bolted linear mapping *
38 * No virtual page table, no nested TLB misses *
40 **********************************************************************/
43 * Note that, unlike non-bolted handlers, TLB_EXFRAME is not
44 * modified by the TLB miss handlers themselves, since the TLB miss
45 * handler code will not itself cause a recursive TLB miss.
47 * TLB_EXFRAME will be modified when crit/mc/debug exceptions are
50 .macro tlb_prolog_bolted intnum addr
51 mtspr SPRN_SPRG_GEN_SCRATCH,r12
52 mfspr r12,SPRN_SPRG_TLB_EXFRAME
53 std r13,EX_TLB_R13(r12)
54 std r10,EX_TLB_R10(r12)
55 mfspr r13,SPRN_SPRG_PACA
58 std r11,EX_TLB_R11(r12)
59 #ifdef CONFIG_KVM_BOOKE_HV
62 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
64 DO_KVM \intnum, SPRN_SRR1
65 std r16,EX_TLB_R16(r12)
66 mfspr r16,\addr /* get faulting address */
67 std r14,EX_TLB_R14(r12)
69 std r15,EX_TLB_R15(r12)
70 std r10,EX_TLB_CR(r12)
74 .macro tlb_epilog_bolted
76 ld r10,EX_TLB_R10(r12)
77 ld r11,EX_TLB_R11(r12)
78 ld r13,EX_TLB_R13(r12)
80 ld r14,EX_TLB_R14(r12)
81 ld r15,EX_TLB_R15(r12)
82 TLB_MISS_RESTORE_STATS
83 ld r16,EX_TLB_R16(r12)
84 mfspr r12,SPRN_SPRG_GEN_SCRATCH
88 START_EXCEPTION(data_tlb_miss_bolted)
89 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
91 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
93 /* We do the user/kernel test for the PID here along with the RW test
95 /* We pre-test some combination of permissions to avoid double
98 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
99 * ESR_ST is 0x00800000
100 * _PAGE_BAP_SW is 0x00000010
101 * So the shift is >> 19. This tests for supervisor writeability.
102 * If the page happens to be supervisor writeable and not user
103 * writeable, we will take a new fault later, but that should be
104 * a rare enough case.
106 * We also move ESR_ST in _PAGE_DIRTY position
107 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
109 * MAS1 is preset for all we need except for TID that needs to
110 * be cleared for kernel translations
115 srdi r15,r16,60 /* get region */
116 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
117 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
119 rlwinm r10,r11,32-19,27,27
120 rlwimi r10,r11,32-16,19,19
121 cmpwi r15,0 /* user vs kernel check */
122 ori r10,r10,_PAGE_PRESENT
123 oris r11,r10,_PAGE_ACCESSED@h
125 TLB_MISS_STATS_SAVE_INFO_BOLTED
126 bne tlb_miss_kernel_bolted
128 tlb_miss_common_bolted:
130 * This is the guts of the TLB miss handler for bolted-linear.
131 * We are entered with:
133 * r16 = faulting address
134 * r15 = crap (free to use)
135 * r14 = page table base
137 * r11 = PTE permission mask
138 * r10 = crap (free to use)
140 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
143 beq tlb_miss_fault_bolted /* No PGDIR, bail */
145 BEGIN_MMU_FTR_SECTION
146 /* Set the TLB reservation and search for existing entry. Then load
149 PPC_TLBSRX_DOT(0,R16)
150 ldx r14,r14,r15 /* grab pgd entry */
151 beq tlb_miss_done_bolted /* tlb exists already, bail */
153 ldx r14,r14,r15 /* grab pgd entry */
154 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
156 #ifndef CONFIG_PPC_64K_PAGES
157 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
160 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
161 ldx r14,r14,r15 /* grab pud entry */
162 #endif /* CONFIG_PPC_64K_PAGES */
164 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
167 bge tlb_miss_fault_bolted
168 ldx r14,r14,r15 /* Grab pmd entry */
170 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
173 bge tlb_miss_fault_bolted
174 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */
176 /* Check if required permissions are met */
178 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
179 bne- tlb_miss_fault_bolted
181 /* Now we build the MAS:
183 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
184 * MAS 1 : Almost fully setup
185 * - PID already updated by caller if necessary
186 * - TSIZE need change if !base page size, not
187 * yet implemented for now
188 * MAS 2 : Defaults not useful, need to be redone
189 * MAS 3+7 : Needs to be done
191 clrrdi r11,r16,12 /* Clear low crap in EA */
192 clrldi r15,r15,12 /* Clear crap at the top */
193 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
194 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
196 andi. r11,r14,_PAGE_DIRTY
197 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
199 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
201 li r11,MAS3_SW|MAS3_UW
204 mtspr SPRN_MAS7_MAS3,r15
207 tlb_miss_done_bolted:
208 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
212 itlb_miss_kernel_bolted:
213 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
214 oris r11,r11,_PAGE_ACCESSED@h
215 tlb_miss_kernel_bolted:
217 ld r14,PACA_KERNELPGD(r13)
218 cmpldi cr0,r15,8 /* Check for vmalloc region */
219 rlwinm r10,r10,0,16,1 /* Clear TID */
221 beq+ tlb_miss_common_bolted
223 tlb_miss_fault_bolted:
224 /* We need to check if it was an instruction miss */
225 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
226 bne itlb_miss_fault_bolted
227 dtlb_miss_fault_bolted:
228 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
230 b exc_data_storage_book3e
231 itlb_miss_fault_bolted:
232 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
234 b exc_instruction_storage_book3e
236 /* Instruction TLB miss */
237 START_EXCEPTION(instruction_tlb_miss_bolted)
238 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
240 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
241 srdi r15,r16,60 /* get region */
242 TLB_MISS_STATS_SAVE_INFO_BOLTED
243 bne- itlb_miss_fault_bolted
245 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
247 /* We do the user/kernel test for the PID here along with the RW test
250 cmpldi cr0,r15,0 /* Check for user region */
251 oris r11,r11,_PAGE_ACCESSED@h
252 beq tlb_miss_common_bolted
253 b itlb_miss_kernel_bolted
255 #ifdef CONFIG_PPC_FSL_BOOK3E
257 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
259 * Linear mapping is bolted: no virtual page table or nested TLB misses
260 * Indirect entries in TLB1, hardware loads resulting direct entries
262 * No HES or NV hint on TLB1, so we need to do software round-robin
263 * No tlbsrx. so we need a spinlock, and we have to deal
264 * with MAS-damage caused by tlbsx
268 START_EXCEPTION(instruction_tlb_miss_e6500)
269 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
271 ld r11,PACA_TCD_PTR(r13)
272 srdi. r15,r16,60 /* get region */
275 TLB_MISS_STATS_SAVE_INFO_BOLTED
276 bne tlb_miss_kernel_e6500 /* user/kernel test */
278 b tlb_miss_common_e6500
280 START_EXCEPTION(data_tlb_miss_e6500)
281 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
283 ld r11,PACA_TCD_PTR(r13)
284 srdi. r15,r16,60 /* get region */
287 TLB_MISS_STATS_SAVE_INFO_BOLTED
288 bne tlb_miss_kernel_e6500 /* user vs kernel check */
291 * This is the guts of the TLB miss handler for e6500 and derivatives.
292 * We are entered with:
294 * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
295 * r15 = crap (free to use)
296 * r14 = page table base
298 * r11 = tlb_per_core ptr
301 tlb_miss_common_e6500:
303 * Search if we already have an indirect entry for that virtual
304 * address, and if we do, bail out.
306 * MAS6:IND should be already set based on MAS4
309 lhz r10,PACAPACAINDEX(r13)
311 cmpdi cr1,r15,1 /* set cr1.eq = 0 for non-recursive */
317 2: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */
318 beq cr1,3b /* unlock will happen if cr1.eq = 0 */
329 andis. r10,r10,MAS1_VALID@h
330 bne tlb_miss_done_e6500
332 /* Undo MAS-damage from the tlbsx */
334 oris r10,r10,MAS1_VALID@h
338 /* Now, we need to walk the page tables. First check if we are in
341 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
342 bne- tlb_miss_fault_e6500
344 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
347 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
348 ldx r14,r14,r15 /* grab pgd entry */
350 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
353 bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */
354 ldx r14,r14,r15 /* grab pud entry */
356 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
359 bge tlb_miss_fault_e6500
360 ldx r14,r14,r15 /* Grab pmd entry */
364 bge tlb_miss_fault_e6500
366 /* Now we build the MAS for a 2M indirect page:
368 * MAS 0 : ESEL needs to be filled by software round-robin
369 * MAS 1 : Fully set up
370 * - PID already updated by caller if necessary
371 * - TSIZE for now is base ind page size always
372 * - TID already cleared if necessary
373 * MAS 2 : Default not 2M-aligned, need to be redone
374 * MAS 3+7 : Needs to be done
377 ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
378 mtspr SPRN_MAS7_MAS3,r14
380 clrrdi r15,r16,21 /* make EA 2M-aligned */
383 lbz r15,TCD_ESEL_NEXT(r11)
384 lbz r16,TCD_ESEL_MAX(r11)
385 lbz r14,TCD_ESEL_FIRST(r11)
386 rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */
387 addi r15,r15,1 /* increment esel_next */
390 iseleq r15,r14,r15 /* if next == last use first */
391 stb r15,TCD_ESEL_NEXT(r11)
396 .macro tlb_unlock_e6500
397 beq cr1,1f /* no unlock if lock was recursively grabbed */
405 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
409 tlb_miss_kernel_e6500:
411 ld r14,PACA_KERNELPGD(r13)
412 cmpldi cr0,r15,8 /* Check for vmalloc region */
413 rlwinm r10,r10,0,16,1 /* Clear TID */
415 beq+ tlb_miss_common_e6500
417 tlb_miss_fault_e6500:
419 /* We need to check if it was an instruction miss */
421 bne itlb_miss_fault_e6500
422 dtlb_miss_fault_e6500:
423 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
425 b exc_data_storage_book3e
426 itlb_miss_fault_e6500:
427 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
429 b exc_instruction_storage_book3e
430 #endif /* CONFIG_PPC_FSL_BOOK3E */
432 /**********************************************************************
434 * TLB miss handling for Book3E with TLB reservation and HES support *
436 **********************************************************************/
440 START_EXCEPTION(data_tlb_miss)
443 /* Now we handle the fault proper. We only save DEAR in normal
444 * fault case since that's the only interesting values here.
445 * We could probably also optimize by not saving SRR0/1 in the
446 * linear mapping case but I'll leave that for later
449 mfspr r16,SPRN_DEAR /* get faulting address */
450 srdi r15,r16,60 /* get region */
451 cmpldi cr0,r15,0xc /* linear mapping ? */
452 TLB_MISS_STATS_SAVE_INFO
453 beq tlb_load_linear /* yes -> go to linear map load */
455 /* The page tables are mapped virtually linear. At this point, though,
456 * we don't know whether we are trying to fault in a first level
457 * virtual address or a virtual page table address. We can get that
458 * from bit 0x1 of the region ID which we have set for a page table
461 bne- virt_page_table_tlb_miss
463 std r14,EX_TLB_ESR(r12); /* save ESR */
464 std r16,EX_TLB_DEAR(r12); /* save DEAR */
466 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
468 oris r11,r11,_PAGE_ACCESSED@h
470 /* We do the user/kernel test for the PID here along with the RW test
472 cmpldi cr0,r15,0 /* Check for user region */
474 /* We pre-test some combination of permissions to avoid double
477 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
478 * ESR_ST is 0x00800000
479 * _PAGE_BAP_SW is 0x00000010
480 * So the shift is >> 19. This tests for supervisor writeability.
481 * If the page happens to be supervisor writeable and not user
482 * writeable, we will take a new fault later, but that should be
483 * a rare enough case.
485 * We also move ESR_ST in _PAGE_DIRTY position
486 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
488 * MAS1 is preset for all we need except for TID that needs to
489 * be cleared for kernel translations
491 rlwimi r11,r14,32-19,27,27
492 rlwimi r11,r14,32-16,19,19
494 /* XXX replace the RMW cycles with immediate loads + writes */
495 1: mfspr r10,SPRN_MAS1
496 cmpldi cr0,r15,8 /* Check for vmalloc region */
497 rlwinm r10,r10,0,16,1 /* Clear TID */
501 /* We got a crappy address, just fault with whatever DEAR and ESR
504 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
505 TLB_MISS_EPILOG_ERROR
506 b exc_data_storage_book3e
508 /* Instruction TLB miss */
509 START_EXCEPTION(instruction_tlb_miss)
512 /* If we take a recursive fault, the second level handler may need
513 * to know whether we are handling a data or instruction fault in
514 * order to get to the right store fault handler. We provide that
515 * info by writing a crazy value in ESR in our exception frame
517 li r14,-1 /* store to exception frame is done later */
519 /* Now we handle the fault proper. We only save DEAR in the non
520 * linear mapping case since we know the linear mapping case will
521 * not re-enter. We could indeed optimize and also not save SRR0/1
522 * in the linear mapping case but I'll leave that for later
524 * Faulting address is SRR0 which is already in r16
526 srdi r15,r16,60 /* get region */
527 cmpldi cr0,r15,0xc /* linear mapping ? */
528 TLB_MISS_STATS_SAVE_INFO
529 beq tlb_load_linear /* yes -> go to linear map load */
531 /* We do the user/kernel test for the PID here along with the RW test
533 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
534 oris r11,r11,_PAGE_ACCESSED@h
536 cmpldi cr0,r15,0 /* Check for user region */
537 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
540 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
541 oris r11,r11,_PAGE_ACCESSED@h
542 /* XXX replace the RMW cycles with immediate loads + writes */
544 cmpldi cr0,r15,8 /* Check for vmalloc region */
545 rlwinm r10,r10,0,16,1 /* Clear TID */
549 /* We got a crappy address, just fault */
550 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
551 TLB_MISS_EPILOG_ERROR
552 b exc_instruction_storage_book3e
555 * This is the guts of the first-level TLB miss handler for direct
556 * misses. We are entered with:
558 * r16 = faulting address
560 * r14 = crap (free to use)
562 * r12 = TLB exception frame in PACA
563 * r11 = PTE permission mask
564 * r10 = crap (free to use)
567 /* So we first construct the page table address. We do that by
568 * shifting the bottom of the address (not the region ID) by
569 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
570 * or'ing the fourth high bit.
572 * NOTE: For 64K pages, we do things slightly differently in
573 * order to handle the weird page table format used by linux
576 #ifdef CONFIG_PPC_64K_PAGES
577 /* For the top bits, 16 bytes per PTE */
578 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
579 /* Now create the bottom bits as 0 in position 0x8000 and
580 * the rest calculated for 8 bytes per PTE
582 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
583 /* Insert the bottom bits in */
584 rlwimi r14,r15,0,16,31
586 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
592 BEGIN_MMU_FTR_SECTION
593 /* Set the TLB reservation and search for existing entry. Then load
596 PPC_TLBSRX_DOT(0,R16)
598 beq normal_tlb_miss_done
601 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
603 finish_normal_tlb_miss:
604 /* Check if required permissions are met */
606 bne- normal_tlb_miss_access_fault
608 /* Now we build the MAS:
610 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
611 * MAS 1 : Almost fully setup
612 * - PID already updated by caller if necessary
613 * - TSIZE need change if !base page size, not
614 * yet implemented for now
615 * MAS 2 : Defaults not useful, need to be redone
616 * MAS 3+7 : Needs to be done
618 * TODO: mix up code below for better scheduling
620 clrrdi r11,r16,12 /* Clear low crap in EA */
621 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
624 /* Check page size, if not standard, update MAS1 */
625 rldicl r11,r14,64-8,64-8
626 #ifdef CONFIG_PPC_64K_PAGES
627 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
629 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
633 rlwimi r11,r14,31,21,24
634 rlwinm r11,r11,0,21,19
637 /* Move RPN in position */
638 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
639 clrldi r15,r11,12 /* Clear crap at the top */
640 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
641 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
643 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
644 andi. r11,r14,_PAGE_DIRTY
646 li r11,MAS3_SW|MAS3_UW
649 BEGIN_MMU_FTR_SECTION
654 mtspr SPRN_MAS7_MAS3,r15
655 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
659 normal_tlb_miss_done:
660 /* We don't bother with restoring DEAR or ESR since we know we are
661 * level 0 and just going back to userland. They are only needed
662 * if you are going to take an access fault
664 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
665 TLB_MISS_EPILOG_SUCCESS
668 normal_tlb_miss_access_fault:
669 /* We need to check if it was an instruction miss */
670 andi. r10,r11,_PAGE_EXEC
672 ld r14,EX_TLB_DEAR(r12)
673 ld r15,EX_TLB_ESR(r12)
676 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
677 TLB_MISS_EPILOG_ERROR
678 b exc_data_storage_book3e
679 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
680 TLB_MISS_EPILOG_ERROR
681 b exc_instruction_storage_book3e
685 * This is the guts of the second-level TLB miss handler for direct
686 * misses. We are entered with:
688 * r16 = virtual page table faulting address
689 * r15 = region (top 4 bits of address)
690 * r14 = crap (free to use)
692 * r12 = TLB exception frame in PACA
693 * r11 = crap (free to use)
694 * r10 = crap (free to use)
696 * Note that this should only ever be called as a second level handler
697 * with the current scheme when using SW load.
698 * That means we can always get the original fault DEAR at
699 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
701 * It can be re-entered by the linear mapping miss handler. However, to
702 * avoid too much complication, it will restart the whole fault at level
703 * 0 so we don't care too much about clobbers
705 * XXX That code was written back when we couldn't clobber r14. We can now,
706 * so we could probably optimize things a bit
708 virt_page_table_tlb_miss:
709 /* Are we hitting a kernel page table ? */
712 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
713 * and we happen to have the swapper_pg_dir at offset 8 from the user
714 * pgdir in the PACA :-).
718 /* If kernel, we need to clear MAS1 TID */
720 /* XXX replace the RMW cycles with immediate loads + writes */
722 rlwinm r10,r10,0,16,1 /* Clear TID */
725 BEGIN_MMU_FTR_SECTION
726 /* Search if we already have a TLB entry for that virtual address, and
727 * if we do, bail out.
729 PPC_TLBSRX_DOT(0,R16)
730 beq virt_page_table_tlb_miss_done
731 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
733 /* Now, we need to walk the page tables. First check if we are in
736 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
737 bne- virt_page_table_tlb_miss_fault
739 /* Get the PGD pointer */
742 beq- virt_page_table_tlb_miss_fault
744 /* Get to PGD entry */
745 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
749 bge virt_page_table_tlb_miss_fault
751 #ifndef CONFIG_PPC_64K_PAGES
752 /* Get to PUD entry */
753 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
757 bge virt_page_table_tlb_miss_fault
758 #endif /* CONFIG_PPC_64K_PAGES */
760 /* Get to PMD entry */
761 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
765 bge virt_page_table_tlb_miss_fault
767 /* Ok, we're all right, we can now create a kernel translation for
768 * a 4K or 64K page from r16 -> r15.
770 /* Now we build the MAS:
772 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
773 * MAS 1 : Almost fully setup
774 * - PID already updated by caller if necessary
775 * - TSIZE for now is base page size always
776 * MAS 2 : Use defaults
777 * MAS 3+7 : Needs to be done
779 * So we only do MAS 2 and 3 for now...
781 clrldi r11,r15,4 /* remove region ID from RPN */
782 ori r10,r11,1 /* Or-in SR */
784 BEGIN_MMU_FTR_SECTION
789 mtspr SPRN_MAS7_MAS3,r10
790 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
794 BEGIN_MMU_FTR_SECTION
795 virt_page_table_tlb_miss_done:
797 /* We have overriden MAS2:EPN but currently our primary TLB miss
798 * handler will always restore it so that should not be an issue,
799 * if we ever optimize the primary handler to not write MAS2 on
800 * some cases, we'll have to restore MAS2:EPN here based on the
801 * original fault's DEAR. If we do that we have to modify the
802 * ITLB miss handler to also store SRR0 in the exception frame
805 * However, one nasty thing we did is we cleared the reservation
806 * (well, potentially we did). We do a trick here thus if we
807 * are not a level 0 exception (we interrupted the TLB miss) we
808 * offset the return address by -4 in order to replay the tlbsrx
812 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
814 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
816 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
818 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
819 /* Return to caller, normal case */
820 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
821 TLB_MISS_EPILOG_SUCCESS
824 virt_page_table_tlb_miss_fault:
825 /* If we fault here, things are a little bit tricky. We need to call
826 * either data or instruction store fault, and we need to retrieve
827 * the original fault address and ESR (for data).
829 * The thing is, we know that in normal circumstances, this is
830 * always called as a second level tlb miss for SW load or as a first
831 * level TLB miss for HW load, so we should be able to peek at the
832 * relevant information in the first exception frame in the PACA.
834 * However, we do need to double check that, because we may just hit
835 * a stray kernel pointer or a userland attack trying to hit those
836 * areas. If that is the case, we do a data fault. (We can't get here
837 * from an instruction tlb miss anyway).
839 * Note also that when going to a fault, we must unwind the previous
840 * level as well. Since we are doing that, we don't need to clear or
841 * restore the TLB reservation neither.
844 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
845 bne- virt_page_table_tlb_miss_whacko_fault
847 /* We dig the original DEAR and ESR from slot 0 */
848 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
849 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
851 /* We check for the "special" ESR value for instruction faults */
856 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
857 TLB_MISS_EPILOG_ERROR
858 b exc_data_storage_book3e
859 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
860 TLB_MISS_EPILOG_ERROR
861 b exc_instruction_storage_book3e
863 virt_page_table_tlb_miss_whacko_fault:
864 /* The linear fault will restart everything so ESR and DEAR will
865 * not have been clobbered, let's just fault with what we have
867 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
868 TLB_MISS_EPILOG_ERROR
869 b exc_data_storage_book3e
872 /**************************************************************
874 * TLB miss handling for Book3E with hw page table support *
876 **************************************************************/
880 START_EXCEPTION(data_tlb_miss_htw)
883 /* Now we handle the fault proper. We only save DEAR in normal
884 * fault case since that's the only interesting values here.
885 * We could probably also optimize by not saving SRR0/1 in the
886 * linear mapping case but I'll leave that for later
889 mfspr r16,SPRN_DEAR /* get faulting address */
890 srdi r11,r16,60 /* get region */
891 cmpldi cr0,r11,0xc /* linear mapping ? */
892 TLB_MISS_STATS_SAVE_INFO
893 beq tlb_load_linear /* yes -> go to linear map load */
895 /* We do the user/kernel test for the PID here along with the RW test
897 cmpldi cr0,r11,0 /* Check for user region */
898 ld r15,PACAPGD(r13) /* Load user pgdir */
901 /* XXX replace the RMW cycles with immediate loads + writes */
902 1: mfspr r10,SPRN_MAS1
903 cmpldi cr0,r11,8 /* Check for vmalloc region */
904 rlwinm r10,r10,0,16,1 /* Clear TID */
906 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
909 /* We got a crappy address, just fault with whatever DEAR and ESR
912 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
913 TLB_MISS_EPILOG_ERROR
914 b exc_data_storage_book3e
916 /* Instruction TLB miss */
917 START_EXCEPTION(instruction_tlb_miss_htw)
920 /* If we take a recursive fault, the second level handler may need
921 * to know whether we are handling a data or instruction fault in
922 * order to get to the right store fault handler. We provide that
923 * info by keeping a crazy value for ESR in r14
925 li r14,-1 /* store to exception frame is done later */
927 /* Now we handle the fault proper. We only save DEAR in the non
928 * linear mapping case since we know the linear mapping case will
929 * not re-enter. We could indeed optimize and also not save SRR0/1
930 * in the linear mapping case but I'll leave that for later
932 * Faulting address is SRR0 which is already in r16
934 srdi r11,r16,60 /* get region */
935 cmpldi cr0,r11,0xc /* linear mapping ? */
936 TLB_MISS_STATS_SAVE_INFO
937 beq tlb_load_linear /* yes -> go to linear map load */
939 /* We do the user/kernel test for the PID here along with the RW test
941 cmpldi cr0,r11,0 /* Check for user region */
942 ld r15,PACAPGD(r13) /* Load user pgdir */
945 /* XXX replace the RMW cycles with immediate loads + writes */
946 1: mfspr r10,SPRN_MAS1
947 cmpldi cr0,r11,8 /* Check for vmalloc region */
948 rlwinm r10,r10,0,16,1 /* Clear TID */
950 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
953 /* We got a crappy address, just fault */
954 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
955 TLB_MISS_EPILOG_ERROR
956 b exc_instruction_storage_book3e
960 * This is the guts of the second-level TLB miss handler for direct
961 * misses. We are entered with:
963 * r16 = virtual page table faulting address
967 * r12 = TLB exception frame in PACA
968 * r11 = crap (free to use)
969 * r10 = crap (free to use)
971 * It can be re-entered by the linear mapping miss handler. However, to
972 * avoid too much complication, it will save/restore things for us
975 /* Search if we already have a TLB entry for that virtual address, and
976 * if we do, bail out.
978 * MAS1:IND should be already set based on MAS4
980 PPC_TLBSRX_DOT(0,R16)
981 beq htw_tlb_miss_done
983 /* Now, we need to walk the page tables. First check if we are in
986 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
987 bne- htw_tlb_miss_fault
989 /* Get the PGD pointer */
991 beq- htw_tlb_miss_fault
993 /* Get to PGD entry */
994 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
998 bge htw_tlb_miss_fault
1000 #ifndef CONFIG_PPC_64K_PAGES
1001 /* Get to PUD entry */
1002 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
1006 bge htw_tlb_miss_fault
1007 #endif /* CONFIG_PPC_64K_PAGES */
1009 /* Get to PMD entry */
1010 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
1014 bge htw_tlb_miss_fault
1016 /* Ok, we're all right, we can now create an indirect entry for
1017 * a 1M or 256M page.
1019 * The last trick is now that because we use "half" pages for
1020 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
1021 * for an added LSB bit to the RPN. For 64K pages, there is no
1022 * problem as we already use 32K arrays (half PTE pages), but for
1023 * 4K page we need to extract a bit from the virtual address and
1024 * insert it into the "PA52" bit of the RPN.
1026 #ifndef CONFIG_PPC_64K_PAGES
1027 rlwimi r15,r16,32-9,20,20
1029 /* Now we build the MAS:
1031 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
1032 * MAS 1 : Almost fully setup
1033 * - PID already updated by caller if necessary
1034 * - TSIZE for now is base ind page size always
1035 * MAS 2 : Use defaults
1036 * MAS 3+7 : Needs to be done
1038 #ifdef CONFIG_PPC_64K_PAGES
1039 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
1041 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
1044 BEGIN_MMU_FTR_SECTION
1048 MMU_FTR_SECTION_ELSE
1049 mtspr SPRN_MAS7_MAS3,r10
1050 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1055 /* We don't bother with restoring DEAR or ESR since we know we are
1056 * level 0 and just going back to userland. They are only needed
1057 * if you are going to take an access fault
1059 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
1060 TLB_MISS_EPILOG_SUCCESS
1064 /* We need to check if it was an instruction miss. We know this
1065 * though because r14 would contain -1
1071 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
1072 TLB_MISS_EPILOG_ERROR
1073 b exc_data_storage_book3e
1074 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
1075 TLB_MISS_EPILOG_ERROR
1076 b exc_instruction_storage_book3e
1079 * This is the guts of "any" level TLB miss handler for kernel linear
1080 * mapping misses. We are entered with:
1083 * r16 = faulting address
1084 * r15 = crap (free to use)
1085 * r14 = ESR (data) or -1 (instruction)
1087 * r12 = TLB exception frame in PACA
1088 * r11 = crap (free to use)
1089 * r10 = crap (free to use)
1091 * In addition we know that we will not re-enter, so in theory, we could
1092 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
1094 * We also need to be careful about MAS registers here & TLB reservation,
1095 * as we know we'll have clobbered them if we interrupt the main TLB miss
1096 * handlers in which case we probably want to do a full restart at level
1097 * 0 rather than saving / restoring the MAS.
1099 * Note: If we care about performance of that core, we can easily shuffle
1100 * a few things around
1103 /* For now, we assume the linear mapping is contiguous and stops at
1104 * linear_map_top. We also assume the size is a multiple of 1G, thus
1105 * we only use 1G pages for now. That might have to be changed in a
1106 * final implementation, especially when dealing with hypervisors
1109 ld r11,linear_map_top@got(r11)
1113 bge tlb_load_linear_fault
1115 /* MAS1 need whole new setup. */
1116 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
1117 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
1120 /* Already somebody there ? */
1121 PPC_TLBSRX_DOT(0,R16)
1122 beq tlb_load_linear_done
1124 /* Now we build the remaining MAS. MAS0 and 2 should be fine
1125 * with their defaults, which leaves us with MAS 3 and 7. The
1126 * mapping is linear, so we just take the address, clear the
1127 * region bits, and or in the permission bits which are currently
1130 clrrdi r10,r16,30 /* 1G page index */
1131 clrldi r10,r10,4 /* clear region bits */
1132 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
1134 BEGIN_MMU_FTR_SECTION
1138 MMU_FTR_SECTION_ELSE
1139 mtspr SPRN_MAS7_MAS3,r10
1140 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1144 tlb_load_linear_done:
1145 /* We use the "error" epilog for success as we do want to
1146 * restore to the initial faulting context, whatever it was.
1147 * We do that because we can't resume a fault within a TLB
1148 * miss handler, due to MAS and TLB reservation being clobbered.
1150 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
1151 TLB_MISS_EPILOG_ERROR
1154 tlb_load_linear_fault:
1155 /* We keep the DEAR and ESR around, this shouldn't have happened */
1158 TLB_MISS_EPILOG_ERROR_SPECIAL
1159 b exc_data_storage_book3e
1160 1: TLB_MISS_EPILOG_ERROR_SPECIAL
1161 b exc_instruction_storage_book3e
1164 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS