2 * Low-level SLB routines
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
6 * Based on earlier C version:
7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
8 * Copyright (c) 2001 Dave Engebretsen
9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <asm/processor.h>
18 #include <asm/ppc_asm.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cputable.h>
23 #include <asm/pgtable.h>
24 #include <asm/firmware.h>
27 * This macro generates asm code to compute the VSID scramble
28 * function. Used in slb_allocate() and do_stab_bolted. The function
29 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
31 * rt = register containing the proto-VSID and into which the
33 * rx = scratch register (clobbered)
36 * - rt and rx must be different registers
37 * - The answer will end up in the low VSID_BITS bits of rt. The higher
38 * bits may contain other garbage, so you may need to mask the
41 #define ASM_VSID_SCRAMBLE(rt, rx, rf, size) \
42 lis rx,VSID_MULTIPLIER_##size@h; \
43 ori rx,rx,VSID_MULTIPLIER_##size@l; \
44 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
46 * powermac get slb fault before feature fixup, so make 65 bit part \
47 * the default part of feature fixup \
49 BEGIN_MMU_FTR_SECTION \
50 srdi rx,rt,VSID_BITS_65_##size; \
51 clrldi rt,rt,(64-VSID_BITS_65_##size); \
54 srdi rx,rx,VSID_BITS_65_##size; \
56 rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_65_##size)); \
57 MMU_FTR_SECTION_ELSE \
58 srdi rx,rt,VSID_BITS_##size; \
59 clrldi rt,rt,(64-VSID_BITS_##size); \
60 add rt,rt,rx; /* add high and low bits */ \
62 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
64 rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_##size)); \
65 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_68_BIT_VA)
68 /* void slb_allocate_realmode(unsigned long ea);
70 * Create an SLB entry for the given EA (user or kernel).
71 * r3 = faulting address, r13 = PACA
72 * r9, r10, r11 are clobbered by this function
73 * No other registers are examined or changed.
75 _GLOBAL(slb_allocate_realmode)
77 * check for bad kernel/user address
78 * (ea & ~REGION_MASK) >= PGTABLE_RANGE
80 rldicr. r9,r3,4,(63 - H_PGTABLE_EADDR_SIZE - 4)
83 srdi r9,r3,60 /* get region */
84 srdi r10,r3,SID_SHIFT /* get esid */
85 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
87 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
88 blt cr7,0f /* user or kernel? */
90 /* Check if hitting the linear mapping or some other kernel space
94 /* Linear mapping encoding bits, the "li" instruction below will
95 * be patched by the kernel at boot
97 .globl slb_miss_kernel_load_linear
98 slb_miss_kernel_load_linear:
101 * context = (ea >> 60) - (0xc - 1)
104 subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
108 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
109 b .Lslb_finish_load_1T
112 #ifdef CONFIG_SPARSEMEM_VMEMMAP
115 /* Check virtual memmap region. To be patched at kernel boot */
116 .globl slb_miss_kernel_load_vmemmap
117 slb_miss_kernel_load_vmemmap:
121 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
123 /* vmalloc mapping gets the encoding from the PACA as the mapping
124 * can be demoted from 64K -> 4K dynamically on some machines
127 cmpldi r11,(H_VMALLOC_SIZE >> 28) - 1
129 lhz r11,PACAVMALLOCSLLP(r13)
133 .globl slb_miss_kernel_load_io
134 slb_miss_kernel_load_io:
138 * context = (ea >> 60) - (0xc - 1)
141 subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
145 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
146 b .Lslb_finish_load_1T
149 * For userspace addresses, make sure this is region 0.
154 * user space make sure we are within the allowed limit
156 ld r11,PACA_ADDR_LIMIT(r13)
160 /* when using slices, we extract the psize off the slice bitmaps
161 * and then we need to get the sllp encoding off the mmu_psize_defs
164 * XXX This is a bit inefficient especially for the normal case,
165 * so we should try to implement a fast path for the standard page
166 * size using the old sllp value so we avoid the array. We cannot
167 * really do dynamic patching unfortunately as processes might flip
168 * between 4k and 64k standard page size
170 #ifdef CONFIG_PPC_MM_SLICES
173 /* below SLICE_LOW_TOP */
177 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
179 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
180 addi r9,r11,PACAHIGHSLICEPSIZE
181 lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
182 /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
183 rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
189 * r9 is get_paca()->context.low_slices_psize, r11 is index
191 ld r9,PACALOWSLICESPSIZE(r13)
194 sldi r11,r11,2 /* index * 4 */
195 /* Extract the psize and multiply to get an array offset */
198 mulli r9,r9,MMUPSIZEDEFSIZE
200 /* Now get to the array and obtain the sllp
203 ld r11,mmu_psize_defs@got(r11)
205 ld r11,MMUPSIZESLLP(r11)
206 ori r11,r11,SLB_VSID_USER
208 /* paca context sllp already contains the SLB_VSID_USER bits */
209 lhz r11,PACACONTEXTSLLP(r13)
210 #endif /* CONFIG_PPC_MM_SLICES */
212 ld r9,PACACONTEXTID(r13)
215 bge .Lslb_finish_load_1T
216 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
219 8: /* invalid EA - return an error indication */
220 crset 4*cr0+eq /* indicate failure */
224 * Finish loading of an SLB entry and return
226 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
229 rldimi r10,r9,ESID_BITS,0
230 ASM_VSID_SCRAMBLE(r10,r9,r11,256M)
231 /* r3 = EA, r11 = VSID data */
233 * Find a slot, round robin. Previously we tried to find a
234 * free slot first but that took too long. Unfortunately we
235 * dont have any LRU information to help us choose a slot.
238 7: ld r10,PACASTABRR(r13)
240 /* This gets soft patched on boot. */
241 .globl slb_compare_rr_to_size
242 slb_compare_rr_to_size:
246 li r10,SLB_NUM_BOLTED
249 std r10,PACASTABRR(r13)
252 rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
253 oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
255 /* r3 = ESID data, r11 = VSID data */
258 * No need for an isync before or after this slbmte. The exception
259 * we enter with and the rfid we exit with are context synchronizing.
263 /* we're done for kernel addresses */
264 crclr 4*cr0+eq /* set result to "success" */
267 /* Update the slb cache */
268 lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
269 cmpldi r3,SLB_CACHE_ENTRIES
272 /* still room in the slb cache */
273 sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
274 srdi r10,r10,28 /* get the 36 bits of the ESID */
275 add r11,r11,r13 /* r11 = (u32 *)paca + offset */
276 stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
277 addi r3,r3,1 /* offset++ */
279 1: /* offset >= SLB_CACHE_ENTRIES */
280 li r3,SLB_CACHE_ENTRIES+1
282 sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
283 crclr 4*cr0+eq /* set result to "success" */
287 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
289 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
291 .Lslb_finish_load_1T:
292 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
293 rldimi r10,r9,ESID_BITS_1T,0
294 ASM_VSID_SCRAMBLE(r10,r9,r11,1T)
296 * bits above VSID_BITS_1T need to be ignored from r10
297 * also combine VSID and flags
300 li r10,MMU_SEGSIZE_1T
301 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
303 /* r3 = EA, r11 = VSID data */
304 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */
308 _ASM_NOKPROBE_SYMBOL(slb_allocate_realmode)
309 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_linear)
310 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_io)
311 _ASM_NOKPROBE_SYMBOL(slb_compare_rr_to_size)
312 #ifdef CONFIG_SPARSEMEM_VMEMMAP
313 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_vmemmap)