1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Page table handling routines for radix page table.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
8 #define pr_fmt(fmt) "radix-mmu: " fmt
11 #include <linux/kernel.h>
12 #include <linux/sched/mm.h>
13 #include <linux/memblock.h>
14 #include <linux/of_fdt.h>
16 #include <linux/hugetlb.h>
17 #include <linux/string_helpers.h>
18 #include <linux/memory.h>
20 #include <asm/pgalloc.h>
21 #include <asm/mmu_context.h>
23 #include <asm/machdep.h>
25 #include <asm/firmware.h>
26 #include <asm/powernv.h>
27 #include <asm/sections.h>
29 #include <asm/trace.h>
30 #include <asm/uaccess.h>
31 #include <asm/ultravisor.h>
33 #include <trace/events/thp.h>
35 unsigned int mmu_pid_bits;
36 unsigned int mmu_base_pid;
37 unsigned int radix_mem_block_size __ro_after_init;
39 static __ref void *early_alloc_pgtable(unsigned long size, int nid,
40 unsigned long region_start, unsigned long region_end)
42 phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT;
43 phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE;
47 min_addr = region_start;
49 max_addr = region_end;
51 ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid);
54 panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n",
55 __func__, size, size, nid, &min_addr, &max_addr);
61 * When allocating pud or pmd pointers, we allocate a complete page
62 * of PAGE_SIZE rather than PUD_TABLE_SIZE or PMD_TABLE_SIZE. This
63 * is to ensure that the page obtained from the memblock allocator
64 * can be completely used as page table page and can be freed
65 * correctly when the page table entries are removed.
67 static int early_map_kernel_page(unsigned long ea, unsigned long pa,
69 unsigned int map_page_size,
71 unsigned long region_start, unsigned long region_end)
73 unsigned long pfn = pa >> PAGE_SHIFT;
80 pgdp = pgd_offset_k(ea);
81 p4dp = p4d_offset(pgdp, ea);
82 if (p4d_none(*p4dp)) {
83 pudp = early_alloc_pgtable(PAGE_SIZE, nid,
84 region_start, region_end);
85 p4d_populate(&init_mm, p4dp, pudp);
87 pudp = pud_offset(p4dp, ea);
88 if (map_page_size == PUD_SIZE) {
92 if (pud_none(*pudp)) {
93 pmdp = early_alloc_pgtable(PAGE_SIZE, nid, region_start,
95 pud_populate(&init_mm, pudp, pmdp);
97 pmdp = pmd_offset(pudp, ea);
98 if (map_page_size == PMD_SIZE) {
99 ptep = pmdp_ptep(pmdp);
102 if (!pmd_present(*pmdp)) {
103 ptep = early_alloc_pgtable(PAGE_SIZE, nid,
104 region_start, region_end);
105 pmd_populate_kernel(&init_mm, pmdp, ptep);
107 ptep = pte_offset_kernel(pmdp, ea);
110 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
116 * nid, region_start, and region_end are hints to try to place the page
117 * table memory in the same node or region.
119 static int __map_kernel_page(unsigned long ea, unsigned long pa,
121 unsigned int map_page_size,
123 unsigned long region_start, unsigned long region_end)
125 unsigned long pfn = pa >> PAGE_SHIFT;
132 * Make sure task size is correct as per the max adddr
134 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
136 #ifdef CONFIG_PPC_64K_PAGES
137 BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT));
140 if (unlikely(!slab_is_available()))
141 return early_map_kernel_page(ea, pa, flags, map_page_size,
142 nid, region_start, region_end);
145 * Should make page table allocation functions be able to take a
146 * node, so we can place kernel page tables on the right nodes after
149 pgdp = pgd_offset_k(ea);
150 p4dp = p4d_offset(pgdp, ea);
151 pudp = pud_alloc(&init_mm, p4dp, ea);
154 if (map_page_size == PUD_SIZE) {
155 ptep = (pte_t *)pudp;
158 pmdp = pmd_alloc(&init_mm, pudp, ea);
161 if (map_page_size == PMD_SIZE) {
162 ptep = pmdp_ptep(pmdp);
165 ptep = pte_alloc_kernel(pmdp, ea);
170 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
175 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
177 unsigned int map_page_size)
179 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
182 #ifdef CONFIG_STRICT_KERNEL_RWX
183 void radix__change_memory_range(unsigned long start, unsigned long end,
193 start = ALIGN_DOWN(start, PAGE_SIZE);
194 end = PAGE_ALIGN(end); // aligns up
196 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
199 for (idx = start; idx < end; idx += PAGE_SIZE) {
200 pgdp = pgd_offset_k(idx);
201 p4dp = p4d_offset(pgdp, idx);
202 pudp = pud_alloc(&init_mm, p4dp, idx);
205 if (pud_is_leaf(*pudp)) {
206 ptep = (pte_t *)pudp;
209 pmdp = pmd_alloc(&init_mm, pudp, idx);
212 if (pmd_is_leaf(*pmdp)) {
213 ptep = pmdp_ptep(pmdp);
216 ptep = pte_alloc_kernel(pmdp, idx);
220 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
223 radix__flush_tlb_kernel_range(start, end);
226 void radix__mark_rodata_ro(void)
228 unsigned long start, end;
230 start = (unsigned long)_stext;
231 end = (unsigned long)__init_begin;
233 radix__change_memory_range(start, end, _PAGE_WRITE);
236 void radix__mark_initmem_nx(void)
238 unsigned long start = (unsigned long)__init_begin;
239 unsigned long end = (unsigned long)__init_end;
241 radix__change_memory_range(start, end, _PAGE_EXEC);
243 #endif /* CONFIG_STRICT_KERNEL_RWX */
245 static inline void __meminit
246 print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec)
253 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
255 pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf,
256 exec ? " (exec)" : "");
259 static unsigned long next_boundary(unsigned long addr, unsigned long end)
261 #ifdef CONFIG_STRICT_KERNEL_RWX
262 if (addr < __pa_symbol(__init_begin))
263 return __pa_symbol(__init_begin);
268 static int __meminit create_physical_mapping(unsigned long start,
270 unsigned long max_mapping_size,
271 int nid, pgprot_t _prot)
273 unsigned long vaddr, addr, mapping_size = 0;
274 bool prev_exec, exec = false;
278 start = ALIGN(start, PAGE_SIZE);
279 for (addr = start; addr < end; addr += mapping_size) {
280 unsigned long gap, previous_size;
283 gap = next_boundary(addr, end) - addr;
284 if (gap > max_mapping_size)
285 gap = max_mapping_size;
286 previous_size = mapping_size;
289 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
290 mmu_psize_defs[MMU_PAGE_1G].shift) {
291 mapping_size = PUD_SIZE;
293 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
294 mmu_psize_defs[MMU_PAGE_2M].shift) {
295 mapping_size = PMD_SIZE;
298 mapping_size = PAGE_SIZE;
299 psize = mmu_virtual_psize;
302 vaddr = (unsigned long)__va(addr);
304 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
305 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) {
306 prot = PAGE_KERNEL_X;
313 if (mapping_size != previous_size || exec != prev_exec) {
314 print_mapping(start, addr, previous_size, prev_exec);
318 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
322 update_page_count(psize, 1);
325 print_mapping(start, addr, mapping_size, exec);
329 static void __init radix_init_pgtable(void)
331 unsigned long rts_field;
332 struct memblock_region *reg;
334 /* We don't support slb for radix */
338 * Create the linear mapping
340 for_each_memblock(memory, reg) {
342 * The memblock allocator is up at this point, so the
343 * page tables will be allocated within the range. No
344 * need or a node (which we don't have yet).
347 if ((reg->base + reg->size) >= RADIX_VMALLOC_START) {
348 pr_warn("Outside the supported range\n");
352 WARN_ON(create_physical_mapping(reg->base,
353 reg->base + reg->size,
354 radix_mem_block_size,
358 /* Find out how many PID bits are supported */
359 if (!cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG)) {
363 } else if (cpu_has_feature(CPU_FTR_HVMODE)) {
366 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
368 * When KVM is possible, we only use the top half of the
369 * PID space to avoid collisions between host and guest PIDs
370 * which can cause problems due to prefetch when exiting the
373 mmu_base_pid = 1 << (mmu_pid_bits - 1);
378 /* The guest uses the bottom half of the PID space */
385 * Allocate Partition table and process table for the
388 BUG_ON(PRTB_SIZE_SHIFT > 36);
389 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
391 * Fill in the process table.
393 rts_field = radix__get_tree_size();
394 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
397 * The init_mm context is given the first available (non-zero) PID,
398 * which is the "guard PID" and contains no page table. PIDR should
399 * never be set to zero because that duplicates the kernel address
400 * space at the 0x0... offset (quadrant 0)!
402 * An arbitrary PID that may later be allocated by the PID allocator
403 * for userspace processes must not be used either, because that
404 * would cause stale user mappings for that PID on CPUs outside of
405 * the TLB invalidation scheme (because it won't be in mm_cpumask).
407 * So permanently carve out one PID for the purpose of a guard PID.
409 init_mm.context.id = mmu_base_pid;
413 static void __init radix_init_partition_table(void)
415 unsigned long rts_field, dw0, dw1;
417 mmu_partition_table_init();
418 rts_field = radix__get_tree_size();
419 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
420 dw1 = __pa(process_tb) | (PRTB_SIZE_SHIFT - 12) | PATB_GR;
421 mmu_partition_table_set_entry(0, dw0, dw1, false);
423 pr_info("Initializing Radix MMU\n");
426 static int __init get_idx_from_shift(unsigned int shift)
447 static int __init radix_dt_scan_page_sizes(unsigned long node,
448 const char *uname, int depth,
455 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
457 /* We are scanning "cpu" nodes only */
458 if (type == NULL || strcmp(type, "cpu") != 0)
461 /* Find MMU PID size */
462 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
463 if (prop && size == 4)
464 mmu_pid_bits = be32_to_cpup(prop);
466 /* Grab page size encodings */
467 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
471 pr_info("Page sizes from device-tree:\n");
472 for (; size >= 4; size -= 4, ++prop) {
474 struct mmu_psize_def *def;
476 /* top 3 bit is AP encoding */
477 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
478 ap = be32_to_cpu(prop[0]) >> 29;
479 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
481 idx = get_idx_from_shift(shift);
485 def = &mmu_psize_defs[idx];
491 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
495 #ifdef CONFIG_MEMORY_HOTPLUG
496 static int __init probe_memory_block_size(unsigned long node, const char *uname, int
499 unsigned long *mem_block_size = (unsigned long *)data;
506 if (strcmp(uname, "ibm,dynamic-reconfiguration-memory"))
509 prop = of_get_flat_dt_prop(node, "ibm,lmb-size", &len);
510 if (!prop || len < sizeof(__be64))
512 * Nothing in the device tree
514 *mem_block_size = MIN_MEMORY_BLOCK_SIZE;
516 *mem_block_size = be64_to_cpup(prop);
520 static unsigned long radix_memory_block_size(void)
522 unsigned long mem_block_size = MIN_MEMORY_BLOCK_SIZE;
525 * OPAL firmware feature is set by now. Hence we are ok
526 * to test OPAL feature.
528 if (firmware_has_feature(FW_FEATURE_OPAL))
529 mem_block_size = 1UL * 1024 * 1024 * 1024;
531 of_scan_flat_dt(probe_memory_block_size, &mem_block_size);
533 return mem_block_size;
536 #else /* CONFIG_MEMORY_HOTPLUG */
538 static unsigned long radix_memory_block_size(void)
540 return 1UL * 1024 * 1024 * 1024;
543 #endif /* CONFIG_MEMORY_HOTPLUG */
546 void __init radix__early_init_devtree(void)
551 * Try to find the available page sizes in the device-tree
553 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
556 * No page size details found in device tree.
557 * Let's assume we have page 4k and 64k support
559 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
560 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
562 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
563 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
567 * Max mapping size used when mapping pages. We don't use
568 * ppc_md.memory_block_size() here because this get called
569 * early and we don't have machine probe called yet. Also
570 * the pseries implementation only check for ibm,lmb-size.
571 * All hypervisor supporting radix do expose that device
574 radix_mem_block_size = radix_memory_block_size();
578 static void radix_init_amor(void)
581 * In HV mode, we init AMOR (Authority Mask Override Register) so that
582 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
583 * Register), enable key 0 and set it to 1.
585 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
587 mtspr(SPRN_AMOR, (3ul << 62));
590 #ifdef CONFIG_PPC_KUEP
591 void setup_kuep(bool disabled)
593 if (disabled || !early_radix_enabled())
596 if (smp_processor_id() == boot_cpuid) {
597 pr_info("Activating Kernel Userspace Execution Prevention\n");
598 cur_cpu_spec->mmu_features |= MMU_FTR_KUEP;
602 * Radix always uses key0 of the IAMR to determine if an access is
603 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
606 mtspr(SPRN_IAMR, (1ul << 62));
610 #ifdef CONFIG_PPC_KUAP
611 void setup_kuap(bool disabled)
613 if (disabled || !early_radix_enabled())
616 if (smp_processor_id() == boot_cpuid) {
617 pr_info("Activating Kernel Userspace Access Prevention\n");
618 cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP;
621 /* Make sure userspace can't change the AMR */
622 mtspr(SPRN_UAMOR, 0);
625 * Set the default kernel AMR values on all cpus.
627 mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
632 void __init radix__early_init_mmu(void)
636 #ifdef CONFIG_PPC_64K_PAGES
637 /* PAGE_SIZE mappings */
638 mmu_virtual_psize = MMU_PAGE_64K;
640 mmu_virtual_psize = MMU_PAGE_4K;
643 #ifdef CONFIG_SPARSEMEM_VMEMMAP
644 /* vmemmap mapping */
645 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
647 * map vmemmap using 2M if available
649 mmu_vmemmap_psize = MMU_PAGE_2M;
651 mmu_vmemmap_psize = mmu_virtual_psize;
654 * initialize page table size
656 __pte_index_size = RADIX_PTE_INDEX_SIZE;
657 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
658 __pud_index_size = RADIX_PUD_INDEX_SIZE;
659 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
660 __pud_cache_index = RADIX_PUD_INDEX_SIZE;
661 __pte_table_size = RADIX_PTE_TABLE_SIZE;
662 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
663 __pud_table_size = RADIX_PUD_TABLE_SIZE;
664 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
666 __pmd_val_bits = RADIX_PMD_VAL_BITS;
667 __pud_val_bits = RADIX_PUD_VAL_BITS;
668 __pgd_val_bits = RADIX_PGD_VAL_BITS;
670 __kernel_virt_start = RADIX_KERN_VIRT_START;
671 __vmalloc_start = RADIX_VMALLOC_START;
672 __vmalloc_end = RADIX_VMALLOC_END;
673 __kernel_io_start = RADIX_KERN_IO_START;
674 __kernel_io_end = RADIX_KERN_IO_END;
675 vmemmap = (struct page *)RADIX_VMEMMAP_START;
676 ioremap_bot = IOREMAP_BASE;
679 pci_io_base = ISA_IO_BASE;
681 __pte_frag_nr = RADIX_PTE_FRAG_NR;
682 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
683 __pmd_frag_nr = RADIX_PMD_FRAG_NR;
684 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
686 radix_init_pgtable();
688 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
689 lpcr = mfspr(SPRN_LPCR);
690 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
691 radix_init_partition_table();
694 radix_init_pseries();
697 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
699 /* Switch to the guard PID before turning on MMU */
700 radix__switch_mmu_context(NULL, &init_mm);
704 void radix__early_init_mmu_secondary(void)
708 * update partition table control register and UPRT
710 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
711 lpcr = mfspr(SPRN_LPCR);
712 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
714 set_ptcr_when_no_uv(__pa(partition_tb) |
715 (PATB_SIZE_SHIFT - 12));
720 radix__switch_mmu_context(NULL, &init_mm);
724 void radix__mmu_cleanup_all(void)
728 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
729 lpcr = mfspr(SPRN_LPCR);
730 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
731 set_ptcr_when_no_uv(0);
732 powernv_set_nmmu_ptcr(0);
733 radix__flush_tlb_all();
737 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
738 phys_addr_t first_memblock_size)
741 * We don't currently support the first MEMBLOCK not mapping 0
742 * physical on those processors
744 BUG_ON(first_memblock_base != 0);
747 * Radix mode is not limited by RMA / VRMA addressing.
749 ppc64_rma_size = ULONG_MAX;
752 #ifdef CONFIG_MEMORY_HOTPLUG
753 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
758 for (i = 0; i < PTRS_PER_PTE; i++) {
764 pte_free_kernel(&init_mm, pte_start);
768 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
773 for (i = 0; i < PTRS_PER_PMD; i++) {
779 pmd_free(&init_mm, pmd_start);
783 static void free_pud_table(pud_t *pud_start, p4d_t *p4d)
788 for (i = 0; i < PTRS_PER_PUD; i++) {
794 pud_free(&init_mm, pud_start);
798 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
804 pte = pte_start + pte_index(addr);
805 for (; addr < end; addr = next, pte++) {
806 next = (addr + PAGE_SIZE) & PAGE_MASK;
810 if (!pte_present(*pte))
813 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
815 * The vmemmap_free() and remove_section_mapping()
816 * codepaths call us with aligned addresses.
818 WARN_ONCE(1, "%s: unaligned range\n", __func__);
822 pte_clear(&init_mm, addr, pte);
826 static void __meminit remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
833 pmd = pmd_start + pmd_index(addr);
834 for (; addr < end; addr = next, pmd++) {
835 next = pmd_addr_end(addr, end);
837 if (!pmd_present(*pmd))
840 if (pmd_is_leaf(*pmd)) {
841 if (!IS_ALIGNED(addr, PMD_SIZE) ||
842 !IS_ALIGNED(next, PMD_SIZE)) {
843 WARN_ONCE(1, "%s: unaligned range\n", __func__);
846 pte_clear(&init_mm, addr, (pte_t *)pmd);
850 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
851 remove_pte_table(pte_base, addr, next);
852 free_pte_table(pte_base, pmd);
856 static void __meminit remove_pud_table(pud_t *pud_start, unsigned long addr,
863 pud = pud_start + pud_index(addr);
864 for (; addr < end; addr = next, pud++) {
865 next = pud_addr_end(addr, end);
867 if (!pud_present(*pud))
870 if (pud_is_leaf(*pud)) {
871 if (!IS_ALIGNED(addr, PUD_SIZE) ||
872 !IS_ALIGNED(next, PUD_SIZE)) {
873 WARN_ONCE(1, "%s: unaligned range\n", __func__);
876 pte_clear(&init_mm, addr, (pte_t *)pud);
880 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
881 remove_pmd_table(pmd_base, addr, next);
882 free_pmd_table(pmd_base, pud);
886 static void __meminit remove_pagetable(unsigned long start, unsigned long end)
888 unsigned long addr, next;
893 spin_lock(&init_mm.page_table_lock);
895 for (addr = start; addr < end; addr = next) {
896 next = pgd_addr_end(addr, end);
898 pgd = pgd_offset_k(addr);
899 p4d = p4d_offset(pgd, addr);
900 if (!p4d_present(*p4d))
903 if (p4d_is_leaf(*p4d)) {
904 if (!IS_ALIGNED(addr, P4D_SIZE) ||
905 !IS_ALIGNED(next, P4D_SIZE)) {
906 WARN_ONCE(1, "%s: unaligned range\n", __func__);
910 pte_clear(&init_mm, addr, (pte_t *)pgd);
914 pud_base = (pud_t *)p4d_page_vaddr(*p4d);
915 remove_pud_table(pud_base, addr, next);
916 free_pud_table(pud_base, p4d);
919 spin_unlock(&init_mm.page_table_lock);
920 radix__flush_tlb_kernel_range(start, end);
923 int __meminit radix__create_section_mapping(unsigned long start,
924 unsigned long end, int nid,
927 if (end >= RADIX_VMALLOC_START) {
928 pr_warn("Outside the supported range\n");
932 return create_physical_mapping(__pa(start), __pa(end),
933 radix_mem_block_size, nid, prot);
936 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
938 remove_pagetable(start, end);
941 #endif /* CONFIG_MEMORY_HOTPLUG */
943 #ifdef CONFIG_SPARSEMEM_VMEMMAP
944 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
945 pgprot_t flags, unsigned int map_page_size,
948 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
951 int __meminit radix__vmemmap_create_mapping(unsigned long start,
952 unsigned long page_size,
955 /* Create a PTE encoding */
956 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
957 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
960 if ((start + page_size) >= RADIX_VMEMMAP_END) {
961 pr_warn("Outside the supported range\n");
965 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
971 #ifdef CONFIG_MEMORY_HOTPLUG
972 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
974 remove_pagetable(start, start + page_size);
979 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
981 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
982 pmd_t *pmdp, unsigned long clr,
987 #ifdef CONFIG_DEBUG_VM
988 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
989 assert_spin_locked(pmd_lockptr(mm, pmdp));
992 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
993 trace_hugepage_update(addr, old, clr, set);
998 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
1004 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
1005 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
1006 VM_BUG_ON(pmd_devmap(*pmdp));
1008 * khugepaged calls this for normal pmd
1014 * pmdp collapse_flush need to ensure that there are no parallel gup
1015 * walk after this call. This is needed so that we can have stable
1016 * page ref count when collapsing a page. We don't allow a collapse page
1017 * if we have gup taken on the page. We can ensure that by sending IPI
1018 * because gup walk happens with IRQ disabled.
1020 serialize_against_pte_lookup(vma->vm_mm);
1022 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
1028 * For us pgtable_t is pte_t *. Inorder to save the deposisted
1029 * page table, we consider the allocated page table as a list
1030 * head. On withdraw we need to make sure we zero out the used
1031 * list_head memory area.
1033 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1036 struct list_head *lh = (struct list_head *) pgtable;
1038 assert_spin_locked(pmd_lockptr(mm, pmdp));
1041 if (!pmd_huge_pte(mm, pmdp))
1044 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
1045 pmd_huge_pte(mm, pmdp) = pgtable;
1048 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
1052 struct list_head *lh;
1054 assert_spin_locked(pmd_lockptr(mm, pmdp));
1057 pgtable = pmd_huge_pte(mm, pmdp);
1058 lh = (struct list_head *) pgtable;
1060 pmd_huge_pte(mm, pmdp) = NULL;
1062 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
1065 ptep = (pte_t *) pgtable;
1072 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
1073 unsigned long addr, pmd_t *pmdp)
1078 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
1079 old_pmd = __pmd(old);
1083 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1085 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
1086 pte_t entry, unsigned long address, int psize)
1088 struct mm_struct *mm = vma->vm_mm;
1089 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
1090 _PAGE_RW | _PAGE_EXEC);
1092 unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1094 * To avoid NMMU hang while relaxing access, we need mark
1095 * the pte invalid in between.
1097 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1098 unsigned long old_pte, new_pte;
1100 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1104 new_pte = old_pte | set;
1105 radix__flush_tlb_page_psize(mm, address, psize);
1106 __radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1108 __radix_pte_update(ptep, 0, set);
1110 * Book3S does not require a TLB flush when relaxing access
1111 * restrictions when the address space is not attached to a
1112 * NMMU, because the core MMU will reload the pte after taking
1113 * an access fault, which is defined by the architectue.
1116 /* See ptesync comment in radix__set_pte_at */
1119 void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
1120 unsigned long addr, pte_t *ptep,
1121 pte_t old_pte, pte_t pte)
1123 struct mm_struct *mm = vma->vm_mm;
1126 * To avoid NMMU hang while relaxing access we need to flush the tlb before
1127 * we set the new value. We need to do this only for radix, because hash
1128 * translation does flush when updating the linux pte.
1130 if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
1131 (atomic_read(&mm->context.copros) > 0))
1132 radix__flush_tlb_page(vma, addr);
1134 set_pte_at(mm, addr, ptep, pte);
1137 int __init arch_ioremap_pud_supported(void)
1139 /* HPT does not cope with large pages in the vmalloc area */
1140 return radix_enabled();
1143 int __init arch_ioremap_pmd_supported(void)
1145 return radix_enabled();
1148 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
1153 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1155 pte_t *ptep = (pte_t *)pud;
1156 pte_t new_pud = pfn_pte(__phys_to_pfn(addr), prot);
1158 if (!radix_enabled())
1161 set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pud);
1166 int pud_clear_huge(pud_t *pud)
1168 if (pud_huge(*pud)) {
1176 int pud_free_pmd_page(pud_t *pud, unsigned long addr)
1181 pmd = (pmd_t *)pud_page_vaddr(*pud);
1184 flush_tlb_kernel_range(addr, addr + PUD_SIZE);
1186 for (i = 0; i < PTRS_PER_PMD; i++) {
1187 if (!pmd_none(pmd[i])) {
1189 pte = (pte_t *)pmd_page_vaddr(pmd[i]);
1191 pte_free_kernel(&init_mm, pte);
1195 pmd_free(&init_mm, pmd);
1200 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1202 pte_t *ptep = (pte_t *)pmd;
1203 pte_t new_pmd = pfn_pte(__phys_to_pfn(addr), prot);
1205 if (!radix_enabled())
1208 set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pmd);
1213 int pmd_clear_huge(pmd_t *pmd)
1215 if (pmd_huge(*pmd)) {
1223 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
1227 pte = (pte_t *)pmd_page_vaddr(*pmd);
1230 flush_tlb_kernel_range(addr, addr + PMD_SIZE);
1232 pte_free_kernel(&init_mm, pte);
1237 int __init arch_ioremap_p4d_supported(void)