1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
38 #include <linux/pgtable.h>
40 #include <asm/debugfs.h>
41 #include <asm/processor.h>
43 #include <asm/mmu_context.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/ultravisor.h>
67 #include <mm/mmu_decl.h>
73 #define DBG(fmt...) udbg_printf(fmt)
79 #define DBG_LOW(fmt...) udbg_printf(fmt)
81 #define DBG_LOW(fmt...)
89 * Note: pte --> Linux PTE
90 * HPTE --> PowerPC Hashed Page Table Entry
93 * htab_initialize is called with the MMU off (of course), but
94 * the kernel has been copied down to zero so it can directly
95 * reference global data. At this point it is very difficult
96 * to print debug info.
100 static unsigned long _SDR1;
101 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
102 EXPORT_SYMBOL_GPL(mmu_psize_defs);
104 u8 hpte_page_sizes[1 << LP_BITS];
105 EXPORT_SYMBOL_GPL(hpte_page_sizes);
107 struct hash_pte *htab_address;
108 unsigned long htab_size_bytes;
109 unsigned long htab_hash_mask;
110 EXPORT_SYMBOL_GPL(htab_hash_mask);
111 int mmu_linear_psize = MMU_PAGE_4K;
112 EXPORT_SYMBOL_GPL(mmu_linear_psize);
113 int mmu_virtual_psize = MMU_PAGE_4K;
114 int mmu_vmalloc_psize = MMU_PAGE_4K;
115 #ifdef CONFIG_SPARSEMEM_VMEMMAP
116 int mmu_vmemmap_psize = MMU_PAGE_4K;
118 int mmu_io_psize = MMU_PAGE_4K;
119 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
120 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
121 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
122 u16 mmu_slb_size = 64;
123 EXPORT_SYMBOL_GPL(mmu_slb_size);
124 #ifdef CONFIG_PPC_64K_PAGES
125 int mmu_ci_restrictions;
127 #ifdef CONFIG_DEBUG_PAGEALLOC
128 static u8 *linear_map_hash_slots;
129 static unsigned long linear_map_hash_count;
130 static DEFINE_SPINLOCK(linear_map_hash_lock);
131 #endif /* CONFIG_DEBUG_PAGEALLOC */
132 struct mmu_hash_ops mmu_hash_ops;
133 EXPORT_SYMBOL(mmu_hash_ops);
136 * These are definitions of page sizes arrays to be used when none
137 * is provided by the firmware.
141 * Fallback (4k pages only)
143 static struct mmu_psize_def mmu_psize_defaults[] = {
147 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
154 * POWER4, GPUL, POWER5
156 * Support for 16Mb large pages
158 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
162 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
169 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
170 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
177 * 'R' and 'C' update notes:
178 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
179 * create writeable HPTEs without C set, because the hcall H_PROTECT
180 * that we use in that case will not update C
181 * - The above is however not a problem, because we also don't do that
182 * fancy "no flush" variant of eviction and we use H_REMOVE which will
183 * do the right thing and thus we don't have the race I described earlier
185 * - Under bare metal, we do have the race, so we need R and C set
186 * - We make sure R is always set and never lost
187 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
189 unsigned long htab_convert_pte_flags(unsigned long pteflags)
191 unsigned long rflags = 0;
193 /* _PAGE_EXEC -> NOEXEC */
194 if ((pteflags & _PAGE_EXEC) == 0)
198 * Linux uses slb key 0 for kernel and 1 for user.
199 * kernel RW areas are mapped with PPP=0b000
200 * User area is mapped with PPP=0b010 for read/write
201 * or PPP=0b011 for read-only (including writeable but clean pages).
203 if (pteflags & _PAGE_PRIVILEGED) {
205 * Kernel read only mapped with ppp bits 0b110
207 if (!(pteflags & _PAGE_WRITE)) {
208 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
209 rflags |= (HPTE_R_PP0 | 0x2);
214 if (pteflags & _PAGE_RWX)
216 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
220 * We can't allow hardware to update hpte bits. Hence always
221 * set 'R' bit and set 'C' if it is a write fault
225 if (pteflags & _PAGE_DIRTY)
231 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
234 rflags |= (HPTE_R_I | HPTE_R_G);
235 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
236 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
239 * Add memory coherence if cache inhibited is not set
243 rflags |= pte_to_hpte_pkey_bits(pteflags);
247 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
248 unsigned long pstart, unsigned long prot,
249 int psize, int ssize)
251 unsigned long vaddr, paddr;
252 unsigned int step, shift;
255 shift = mmu_psize_defs[psize].shift;
258 prot = htab_convert_pte_flags(prot);
260 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
261 vstart, vend, pstart, prot, psize, ssize);
263 for (vaddr = vstart, paddr = pstart; vaddr < vend;
264 vaddr += step, paddr += step) {
265 unsigned long hash, hpteg;
266 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
267 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
268 unsigned long tprot = prot;
269 bool secondary_hash = false;
272 * If we hit a bad address return error.
276 /* Make kernel text executable */
277 if (overlaps_kernel_text(vaddr, vaddr + step))
281 * If relocatable, check if it overlaps interrupt vectors that
282 * are copied down to real 0. For relocatable kernel
283 * (e.g. kdump case) we copy interrupt vectors down to real
284 * address 0. Mark that region as executable. This is
285 * because on p8 system with relocation on exception feature
286 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
287 * in order to execute the interrupt handlers in virtual
288 * mode the vector region need to be marked as executable.
290 if ((PHYSICAL_START > MEMORY_START) &&
291 overlaps_interrupt_vector_text(vaddr, vaddr + step))
294 hash = hpt_hash(vpn, shift, ssize);
295 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
297 BUG_ON(!mmu_hash_ops.hpte_insert);
299 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
300 HPTE_V_BOLTED, psize, psize,
304 * Try to to keep bolted entries in primary.
305 * Remove non bolted entries and try insert again
307 ret = mmu_hash_ops.hpte_remove(hpteg);
309 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
310 HPTE_V_BOLTED, psize, psize,
312 if (ret == -1 && !secondary_hash) {
313 secondary_hash = true;
314 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
323 #ifdef CONFIG_DEBUG_PAGEALLOC
324 if (debug_pagealloc_enabled() &&
325 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
326 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
327 #endif /* CONFIG_DEBUG_PAGEALLOC */
329 return ret < 0 ? ret : 0;
332 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
333 int psize, int ssize)
336 unsigned int step, shift;
340 shift = mmu_psize_defs[psize].shift;
343 if (!mmu_hash_ops.hpte_removebolted)
346 for (vaddr = vstart; vaddr < vend; vaddr += step) {
347 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
359 static bool disable_1tb_segments = false;
361 static int __init parse_disable_1tb_segments(char *p)
363 disable_1tb_segments = true;
366 early_param("disable_1tb_segments", parse_disable_1tb_segments);
368 static int __init htab_dt_scan_seg_sizes(unsigned long node,
369 const char *uname, int depth,
372 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
376 /* We are scanning "cpu" nodes only */
377 if (type == NULL || strcmp(type, "cpu") != 0)
380 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
383 for (; size >= 4; size -= 4, ++prop) {
384 if (be32_to_cpu(prop[0]) == 40) {
385 DBG("1T segment support detected\n");
387 if (disable_1tb_segments) {
388 DBG("1T segments disabled by command line\n");
392 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
396 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
400 static int __init get_idx_from_shift(unsigned int shift)
424 static int __init htab_dt_scan_page_sizes(unsigned long node,
425 const char *uname, int depth,
428 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
432 /* We are scanning "cpu" nodes only */
433 if (type == NULL || strcmp(type, "cpu") != 0)
436 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
440 pr_info("Page sizes from device-tree:\n");
442 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
444 unsigned int base_shift = be32_to_cpu(prop[0]);
445 unsigned int slbenc = be32_to_cpu(prop[1]);
446 unsigned int lpnum = be32_to_cpu(prop[2]);
447 struct mmu_psize_def *def;
450 size -= 3; prop += 3;
451 base_idx = get_idx_from_shift(base_shift);
453 /* skip the pte encoding also */
454 prop += lpnum * 2; size -= lpnum * 2;
457 def = &mmu_psize_defs[base_idx];
458 if (base_idx == MMU_PAGE_16M)
459 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
461 def->shift = base_shift;
462 if (base_shift <= 23)
465 def->avpnm = (1 << (base_shift - 23)) - 1;
468 * We don't know for sure what's up with tlbiel, so
469 * for now we only set it for 4K and 64K pages
471 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
476 while (size > 0 && lpnum) {
477 unsigned int shift = be32_to_cpu(prop[0]);
478 int penc = be32_to_cpu(prop[1]);
480 prop += 2; size -= 2;
483 idx = get_idx_from_shift(shift);
488 pr_err("Invalid penc for base_shift=%d "
489 "shift=%d\n", base_shift, shift);
491 def->penc[idx] = penc;
492 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
493 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
494 base_shift, shift, def->sllp,
495 def->avpnm, def->tlbiel, def->penc[idx]);
502 #ifdef CONFIG_HUGETLB_PAGE
504 * Scan for 16G memory blocks that have been set aside for huge pages
505 * and reserve those blocks for 16G huge pages.
507 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
508 const char *uname, int depth,
510 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
511 const __be64 *addr_prop;
512 const __be32 *page_count_prop;
513 unsigned int expected_pages;
514 long unsigned int phys_addr;
515 long unsigned int block_size;
517 /* We are scanning "memory" nodes only */
518 if (type == NULL || strcmp(type, "memory") != 0)
522 * This property is the log base 2 of the number of virtual pages that
523 * will represent this memory block.
525 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
526 if (page_count_prop == NULL)
528 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
529 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
530 if (addr_prop == NULL)
532 phys_addr = be64_to_cpu(addr_prop[0]);
533 block_size = be64_to_cpu(addr_prop[1]);
534 if (block_size != (16 * GB))
536 printk(KERN_INFO "Huge page(16GB) memory: "
537 "addr = 0x%lX size = 0x%lX pages = %d\n",
538 phys_addr, block_size, expected_pages);
539 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
540 memblock_reserve(phys_addr, block_size * expected_pages);
541 pseries_add_gpage(phys_addr, block_size, expected_pages);
545 #endif /* CONFIG_HUGETLB_PAGE */
547 static void mmu_psize_set_default_penc(void)
550 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
551 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
552 mmu_psize_defs[bpsize].penc[apsize] = -1;
555 #ifdef CONFIG_PPC_64K_PAGES
557 static bool might_have_hea(void)
560 * The HEA ethernet adapter requires awareness of the
561 * GX bus. Without that awareness we can easily assume
562 * we will never see an HEA ethernet device.
564 #ifdef CONFIG_IBMEBUS
565 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
566 firmware_has_feature(FW_FEATURE_SPLPAR);
572 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
574 static void __init htab_scan_page_sizes(void)
578 /* se the invalid penc to -1 */
579 mmu_psize_set_default_penc();
581 /* Default to 4K pages only */
582 memcpy(mmu_psize_defs, mmu_psize_defaults,
583 sizeof(mmu_psize_defaults));
586 * Try to find the available page sizes in the device-tree
588 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
589 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
591 * Nothing in the device-tree, but the CPU supports 16M pages,
592 * so let's fallback on a known size list for 16M capable CPUs.
594 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
595 sizeof(mmu_psize_defaults_gp));
598 #ifdef CONFIG_HUGETLB_PAGE
599 if (!hugetlb_disabled) {
600 /* Reserve 16G huge page memory sections for huge pages */
601 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
603 #endif /* CONFIG_HUGETLB_PAGE */
607 * Fill in the hpte_page_sizes[] array.
608 * We go through the mmu_psize_defs[] array looking for all the
609 * supported base/actual page size combinations. Each combination
610 * has a unique pagesize encoding (penc) value in the low bits of
611 * the LP field of the HPTE. For actual page sizes less than 1MB,
612 * some of the upper LP bits are used for RPN bits, meaning that
613 * we need to fill in several entries in hpte_page_sizes[].
615 * In diagrammatic form, with r = RPN bits and z = page size bits:
616 * PTE LP actual page size
623 * The zzzz bits are implementation-specific but are chosen so that
624 * no encoding for a larger page size uses the same value in its
625 * low-order N bits as the encoding for the 2^(12+N) byte page size
628 static void init_hpte_page_sizes(void)
631 long int shift, penc;
633 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
634 if (!mmu_psize_defs[bp].shift)
635 continue; /* not a supported page size */
636 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
637 penc = mmu_psize_defs[bp].penc[ap];
638 if (penc == -1 || !mmu_psize_defs[ap].shift)
640 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
642 continue; /* should never happen */
644 * For page sizes less than 1MB, this loop
645 * replicates the entry for all possible values
648 while (penc < (1 << LP_BITS)) {
649 hpte_page_sizes[penc] = (ap << 4) | bp;
656 static void __init htab_init_page_sizes(void)
659 init_hpte_page_sizes();
661 if (!debug_pagealloc_enabled()) {
663 * Pick a size for the linear mapping. Currently, we only
664 * support 16M, 1M and 4K which is the default
666 if (IS_ENABLED(STRICT_KERNEL_RWX) &&
667 (unsigned long)_stext % 0x1000000) {
668 if (mmu_psize_defs[MMU_PAGE_16M].shift)
669 pr_warn("Kernel not 16M aligned, "
670 "disabling 16M linear map alignment");
674 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
675 mmu_linear_psize = MMU_PAGE_16M;
676 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
677 mmu_linear_psize = MMU_PAGE_1M;
680 #ifdef CONFIG_PPC_64K_PAGES
682 * Pick a size for the ordinary pages. Default is 4K, we support
683 * 64K for user mappings and vmalloc if supported by the processor.
684 * We only use 64k for ioremap if the processor
685 * (and firmware) support cache-inhibited large pages.
686 * If not, we use 4k and set mmu_ci_restrictions so that
687 * hash_page knows to switch processes that use cache-inhibited
688 * mappings to 4k pages.
690 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
691 mmu_virtual_psize = MMU_PAGE_64K;
692 mmu_vmalloc_psize = MMU_PAGE_64K;
693 if (mmu_linear_psize == MMU_PAGE_4K)
694 mmu_linear_psize = MMU_PAGE_64K;
695 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
697 * When running on pSeries using 64k pages for ioremap
698 * would stop us accessing the HEA ethernet. So if we
699 * have the chance of ever seeing one, stay at 4k.
701 if (!might_have_hea())
702 mmu_io_psize = MMU_PAGE_64K;
704 mmu_ci_restrictions = 1;
706 #endif /* CONFIG_PPC_64K_PAGES */
708 #ifdef CONFIG_SPARSEMEM_VMEMMAP
710 * We try to use 16M pages for vmemmap if that is supported
711 * and we have at least 1G of RAM at boot
713 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
714 memblock_phys_mem_size() >= 0x40000000)
715 mmu_vmemmap_psize = MMU_PAGE_16M;
717 mmu_vmemmap_psize = mmu_virtual_psize;
718 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
720 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
721 "virtual = %d, io = %d"
722 #ifdef CONFIG_SPARSEMEM_VMEMMAP
726 mmu_psize_defs[mmu_linear_psize].shift,
727 mmu_psize_defs[mmu_virtual_psize].shift,
728 mmu_psize_defs[mmu_io_psize].shift
729 #ifdef CONFIG_SPARSEMEM_VMEMMAP
730 ,mmu_psize_defs[mmu_vmemmap_psize].shift
735 static int __init htab_dt_scan_pftsize(unsigned long node,
736 const char *uname, int depth,
739 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
742 /* We are scanning "cpu" nodes only */
743 if (type == NULL || strcmp(type, "cpu") != 0)
746 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
748 /* pft_size[0] is the NUMA CEC cookie */
749 ppc64_pft_size = be32_to_cpu(prop[1]);
755 unsigned htab_shift_for_mem_size(unsigned long mem_size)
757 unsigned memshift = __ilog2(mem_size);
758 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
761 /* round mem_size up to next power of 2 */
762 if ((1UL << memshift) < mem_size)
765 /* aim for 2 pages / pteg */
766 pteg_shift = memshift - (pshift + 1);
769 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
770 * size permitted by the architecture.
772 return max(pteg_shift + 7, 18U);
775 static unsigned long __init htab_get_table_size(void)
778 * If hash size isn't already provided by the platform, we try to
779 * retrieve it from the device-tree. If it's not there neither, we
780 * calculate it now based on the total RAM size
782 if (ppc64_pft_size == 0)
783 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
785 return 1UL << ppc64_pft_size;
787 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
790 #ifdef CONFIG_MEMORY_HOTPLUG
791 int resize_hpt_for_hotplug(unsigned long new_mem_size)
793 unsigned target_hpt_shift;
795 if (!mmu_hash_ops.resize_hpt)
798 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
801 * To avoid lots of HPT resizes if memory size is fluctuating
802 * across a boundary, we deliberately have some hysterisis
803 * here: we immediately increase the HPT size if the target
804 * shift exceeds the current shift, but we won't attempt to
805 * reduce unless the target shift is at least 2 below the
808 if (target_hpt_shift > ppc64_pft_size ||
809 target_hpt_shift < ppc64_pft_size - 1)
810 return mmu_hash_ops.resize_hpt(target_hpt_shift);
815 int hash__create_section_mapping(unsigned long start, unsigned long end,
816 int nid, pgprot_t prot)
820 if (end >= H_VMALLOC_START) {
821 pr_warn("Outside the supported range\n");
825 rc = htab_bolt_mapping(start, end, __pa(start),
826 pgprot_val(prot), mmu_linear_psize,
830 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
832 BUG_ON(rc2 && (rc2 != -ENOENT));
837 int hash__remove_section_mapping(unsigned long start, unsigned long end)
839 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
844 #endif /* CONFIG_MEMORY_HOTPLUG */
846 static void __init hash_init_partition_table(phys_addr_t hash_table,
847 unsigned long htab_size)
849 mmu_partition_table_init();
852 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
853 * For now, UPRT is 0 and we have no segment table.
855 htab_size = __ilog2(htab_size) - 18;
856 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
857 pr_info("Partition table %p\n", partition_tb);
860 static void __init htab_initialize(void)
863 unsigned long pteg_count;
865 unsigned long base = 0, size = 0;
866 struct memblock_region *reg;
868 DBG(" -> htab_initialize()\n");
870 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
871 mmu_kernel_ssize = MMU_SEGSIZE_1T;
872 mmu_highuser_ssize = MMU_SEGSIZE_1T;
873 printk(KERN_INFO "Using 1TB segments\n");
876 if (stress_slb_enabled)
877 static_branch_enable(&stress_slb_key);
880 * Calculate the required size of the htab. We want the number of
881 * PTEGs to equal one half the number of real pages.
883 htab_size_bytes = htab_get_table_size();
884 pteg_count = htab_size_bytes >> 7;
886 htab_hash_mask = pteg_count - 1;
888 if (firmware_has_feature(FW_FEATURE_LPAR) ||
889 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
890 /* Using a hypervisor which owns the htab */
893 #ifdef CONFIG_FA_DUMP
895 * If firmware assisted dump is active firmware preserves
896 * the contents of htab along with entire partition memory.
897 * Clear the htab if firmware assisted dump is active so
898 * that we dont end up using old mappings.
900 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
901 mmu_hash_ops.hpte_clear_all();
904 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
906 #ifdef CONFIG_PPC_CELL
908 * Cell may require the hash table down low when using the
909 * Axon IOMMU in order to fit the dynamic region over it, see
910 * comments in cell/iommu.c
912 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
914 pr_info("Hash table forced below 2G for Axon IOMMU\n");
916 #endif /* CONFIG_PPC_CELL */
918 table = memblock_phys_alloc_range(htab_size_bytes,
922 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
923 &htab_size_bytes, &limit);
925 DBG("Hash table allocated at %lx, size: %lx\n", table,
928 htab_address = __va(table);
930 /* htab absolute addr + encoded htabsize */
931 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
933 /* Initialize the HPT with no entries */
934 memset((void *)table, 0, htab_size_bytes);
936 if (!cpu_has_feature(CPU_FTR_ARCH_300))
938 mtspr(SPRN_SDR1, _SDR1);
940 hash_init_partition_table(table, htab_size_bytes);
943 prot = pgprot_val(PAGE_KERNEL);
945 #ifdef CONFIG_DEBUG_PAGEALLOC
946 if (debug_pagealloc_enabled()) {
947 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
948 linear_map_hash_slots = memblock_alloc_try_nid(
949 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
950 ppc64_rma_size, NUMA_NO_NODE);
951 if (!linear_map_hash_slots)
952 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
953 __func__, linear_map_hash_count, &ppc64_rma_size);
955 #endif /* CONFIG_DEBUG_PAGEALLOC */
957 /* create bolted the linear mapping in the hash table */
958 for_each_memblock(memory, reg) {
959 base = (unsigned long)__va(reg->base);
962 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
965 if ((base + size) >= H_VMALLOC_START) {
966 pr_warn("Outside the supported range\n");
970 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
971 prot, mmu_linear_psize, mmu_kernel_ssize));
973 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
976 * If we have a memory_limit and we've allocated TCEs then we need to
977 * explicitly map the TCE area at the top of RAM. We also cope with the
978 * case that the TCEs start below memory_limit.
979 * tce_alloc_start/end are 16MB aligned so the mapping should work
980 * for either 4K or 16MB pages.
982 if (tce_alloc_start) {
983 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
984 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
986 if (base + size >= tce_alloc_start)
987 tce_alloc_start = base + size + 1;
989 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
990 __pa(tce_alloc_start), prot,
991 mmu_linear_psize, mmu_kernel_ssize));
995 DBG(" <- htab_initialize()\n");
1000 void __init hash__early_init_devtree(void)
1002 /* Initialize segment sizes */
1003 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
1005 /* Initialize page sizes */
1006 htab_scan_page_sizes();
1009 static struct hash_mm_context init_hash_mm_context;
1010 void __init hash__early_init_mmu(void)
1012 #ifndef CONFIG_PPC_64K_PAGES
1014 * We have code in __hash_page_4K() and elsewhere, which assumes it can
1016 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1018 * Where the slot number is between 0-15, and values of 8-15 indicate
1019 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
1020 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1021 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1022 * with a BUILD_BUG_ON().
1024 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1025 #endif /* CONFIG_PPC_64K_PAGES */
1027 htab_init_page_sizes();
1030 * initialize page table size
1032 __pte_frag_nr = H_PTE_FRAG_NR;
1033 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1034 __pmd_frag_nr = H_PMD_FRAG_NR;
1035 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1037 __pte_index_size = H_PTE_INDEX_SIZE;
1038 __pmd_index_size = H_PMD_INDEX_SIZE;
1039 __pud_index_size = H_PUD_INDEX_SIZE;
1040 __pgd_index_size = H_PGD_INDEX_SIZE;
1041 __pud_cache_index = H_PUD_CACHE_INDEX;
1042 __pte_table_size = H_PTE_TABLE_SIZE;
1043 __pmd_table_size = H_PMD_TABLE_SIZE;
1044 __pud_table_size = H_PUD_TABLE_SIZE;
1045 __pgd_table_size = H_PGD_TABLE_SIZE;
1047 * 4k use hugepd format, so for hash set then to
1050 __pmd_val_bits = HASH_PMD_VAL_BITS;
1051 __pud_val_bits = HASH_PUD_VAL_BITS;
1052 __pgd_val_bits = HASH_PGD_VAL_BITS;
1054 __kernel_virt_start = H_KERN_VIRT_START;
1055 __vmalloc_start = H_VMALLOC_START;
1056 __vmalloc_end = H_VMALLOC_END;
1057 __kernel_io_start = H_KERN_IO_START;
1058 __kernel_io_end = H_KERN_IO_END;
1059 vmemmap = (struct page *)H_VMEMMAP_START;
1060 ioremap_bot = IOREMAP_BASE;
1063 pci_io_base = ISA_IO_BASE;
1066 /* Select appropriate backend */
1067 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1068 ps3_early_mm_init();
1069 else if (firmware_has_feature(FW_FEATURE_LPAR))
1070 hpte_init_pseries();
1071 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1074 if (!mmu_hash_ops.hpte_insert)
1075 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1078 * Initialize the MMU Hash table and create the linear mapping
1079 * of memory. Has to be done before SLB initialization as this is
1080 * currently where the page size encoding is obtained.
1084 init_mm.context.hash_context = &init_hash_mm_context;
1085 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1087 pr_info("Initializing hash mmu with SLB\n");
1088 /* Initialize SLB management */
1091 if (cpu_has_feature(CPU_FTR_ARCH_206)
1092 && cpu_has_feature(CPU_FTR_HVMODE))
1097 void hash__early_init_mmu_secondary(void)
1099 /* Initialize hash table for that CPU */
1100 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1102 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1103 mtspr(SPRN_SDR1, _SDR1);
1105 set_ptcr_when_no_uv(__pa(partition_tb) |
1106 (PATB_SIZE_SHIFT - 12));
1108 /* Initialize SLB */
1111 if (cpu_has_feature(CPU_FTR_ARCH_206)
1112 && cpu_has_feature(CPU_FTR_HVMODE))
1115 #endif /* CONFIG_SMP */
1118 * Called by asm hashtable.S for doing lazy icache flush
1120 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1124 if (!pfn_valid(pte_pfn(pte)))
1127 page = pte_page(pte);
1130 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1131 if (trap == 0x400) {
1132 flush_dcache_icache_page(page);
1133 set_bit(PG_arch_1, &page->flags);
1140 #ifdef CONFIG_PPC_MM_SLICES
1141 static unsigned int get_paca_psize(unsigned long addr)
1143 unsigned char *psizes;
1144 unsigned long index, mask_index;
1146 if (addr < SLICE_LOW_TOP) {
1147 psizes = get_paca()->mm_ctx_low_slices_psize;
1148 index = GET_LOW_SLICE_INDEX(addr);
1150 psizes = get_paca()->mm_ctx_high_slices_psize;
1151 index = GET_HIGH_SLICE_INDEX(addr);
1153 mask_index = index & 0x1;
1154 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1158 unsigned int get_paca_psize(unsigned long addr)
1160 return get_paca()->mm_ctx_user_psize;
1165 * Demote a segment to using 4k pages.
1166 * For now this makes the whole process use 4k pages.
1168 #ifdef CONFIG_PPC_64K_PAGES
1169 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1171 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1173 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1174 copro_flush_all_slbs(mm);
1175 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1177 copy_mm_to_paca(mm);
1178 slb_flush_and_restore_bolted();
1181 #endif /* CONFIG_PPC_64K_PAGES */
1183 #ifdef CONFIG_PPC_SUBPAGE_PROT
1185 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1186 * Userspace sets the subpage permissions using the subpage_prot system call.
1188 * Result is 0: full permissions, _PAGE_RW: read-only,
1189 * _PAGE_RWX: no access.
1191 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1193 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1200 if (ea >= spt->maxaddr)
1202 if (ea < 0x100000000UL) {
1203 /* addresses below 4GB use spt->low_prot */
1204 sbpm = spt->low_prot;
1206 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1210 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1213 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1215 /* extract 2-bit bitfield for this 4k subpage */
1216 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1219 * 0 -> full premission
1222 * We return the flag that need to be cleared.
1224 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1228 #else /* CONFIG_PPC_SUBPAGE_PROT */
1229 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1235 void hash_failure_debug(unsigned long ea, unsigned long access,
1236 unsigned long vsid, unsigned long trap,
1237 int ssize, int psize, int lpsize, unsigned long pte)
1239 if (!printk_ratelimit())
1241 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1242 ea, access, current->comm);
1243 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1244 trap, vsid, ssize, psize, lpsize, pte);
1247 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1248 int psize, bool user_region)
1251 if (psize != get_paca_psize(ea)) {
1252 copy_mm_to_paca(mm);
1253 slb_flush_and_restore_bolted();
1255 } else if (get_paca()->vmalloc_sllp !=
1256 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1257 get_paca()->vmalloc_sllp =
1258 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1259 slb_vmalloc_update();
1266 * 1 - normal page fault
1267 * -1 - critical hash insertion error
1268 * -2 - access not permitted by subpage protection mechanism
1270 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1271 unsigned long access, unsigned long trap,
1272 unsigned long flags)
1275 enum ctx_state prev_state = exception_enter();
1280 int rc, user_region = 0;
1283 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1285 trace_hash_fault(ea, access, trap);
1287 /* Get region & vsid */
1288 switch (get_region_id(ea)) {
1289 case USER_REGION_ID:
1292 DBG_LOW(" user region with no mm !\n");
1296 psize = get_slice_psize(mm, ea);
1297 ssize = user_segment_size(ea);
1298 vsid = get_user_vsid(&mm->context, ea, ssize);
1300 case VMALLOC_REGION_ID:
1301 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1302 psize = mmu_vmalloc_psize;
1303 ssize = mmu_kernel_ssize;
1307 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1308 psize = mmu_io_psize;
1309 ssize = mmu_kernel_ssize;
1314 * Send the problem up to do_page_fault()
1319 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1323 DBG_LOW("Bad address!\n");
1329 if (pgdir == NULL) {
1334 /* Check CPU locality */
1335 if (user_region && mm_is_thread_local(mm))
1336 flags |= HPTE_LOCAL_UPDATE;
1338 #ifndef CONFIG_PPC_64K_PAGES
1340 * If we use 4K pages and our psize is not 4K, then we might
1341 * be hitting a special driver mapping, and need to align the
1342 * address before we fetch the PTE.
1344 * It could also be a hugepage mapping, in which case this is
1345 * not necessary, but it's not harmful, either.
1347 if (psize != MMU_PAGE_4K)
1348 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1349 #endif /* CONFIG_PPC_64K_PAGES */
1351 /* Get PTE and page size from page tables */
1352 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1353 if (ptep == NULL || !pte_present(*ptep)) {
1354 DBG_LOW(" no PTE !\n");
1360 * Add _PAGE_PRESENT to the required access perm. If there are parallel
1361 * updates to the pte that can possibly clear _PAGE_PTE, catch that too.
1363 * We can safely use the return pte address in rest of the function
1364 * because we do set H_PAGE_BUSY which prevents further updates to pte
1365 * from generic code.
1367 access |= _PAGE_PRESENT | _PAGE_PTE;
1370 * Pre-check access permissions (will be re-checked atomically
1371 * in __hash_page_XX but this pre-check is a fast path
1373 if (!check_pte_access(access, pte_val(*ptep))) {
1374 DBG_LOW(" no access !\n");
1381 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1382 trap, flags, ssize, psize);
1383 #ifdef CONFIG_HUGETLB_PAGE
1385 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1386 flags, ssize, hugeshift, psize);
1390 * if we have hugeshift, and is not transhuge with
1391 * hugetlb disabled, something is really wrong.
1397 if (current->mm == mm)
1398 check_paca_psize(ea, mm, psize, user_region);
1403 #ifndef CONFIG_PPC_64K_PAGES
1404 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1406 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1407 pte_val(*(ptep + PTRS_PER_PTE)));
1409 /* Do actual hashing */
1410 #ifdef CONFIG_PPC_64K_PAGES
1411 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1412 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1413 demote_segment_4k(mm, ea);
1414 psize = MMU_PAGE_4K;
1418 * If this PTE is non-cacheable and we have restrictions on
1419 * using non cacheable large pages, then we switch to 4k
1421 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1423 demote_segment_4k(mm, ea);
1424 psize = MMU_PAGE_4K;
1425 } else if (ea < VMALLOC_END) {
1427 * some driver did a non-cacheable mapping
1428 * in vmalloc space, so switch vmalloc
1431 printk(KERN_ALERT "Reducing vmalloc segment "
1432 "to 4kB pages because of "
1433 "non-cacheable mapping\n");
1434 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1435 copro_flush_all_slbs(mm);
1439 #endif /* CONFIG_PPC_64K_PAGES */
1441 if (current->mm == mm)
1442 check_paca_psize(ea, mm, psize, user_region);
1444 #ifdef CONFIG_PPC_64K_PAGES
1445 if (psize == MMU_PAGE_64K)
1446 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1449 #endif /* CONFIG_PPC_64K_PAGES */
1451 int spp = subpage_protection(mm, ea);
1455 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1460 * Dump some info in case of hash insertion failure, they should
1461 * never happen so it is really useful to know if/when they do
1464 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1465 psize, pte_val(*ptep));
1466 #ifndef CONFIG_PPC_64K_PAGES
1467 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1469 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1470 pte_val(*(ptep + PTRS_PER_PTE)));
1472 DBG_LOW(" -> rc=%d\n", rc);
1475 exception_exit(prev_state);
1478 EXPORT_SYMBOL_GPL(hash_page_mm);
1480 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1481 unsigned long dsisr)
1483 unsigned long flags = 0;
1484 struct mm_struct *mm = current->mm;
1486 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1487 (get_region_id(ea) == IO_REGION_ID))
1490 if (dsisr & DSISR_NOHPTE)
1491 flags |= HPTE_NOHPTE_UPDATE;
1493 return hash_page_mm(mm, ea, access, trap, flags);
1495 EXPORT_SYMBOL_GPL(hash_page);
1497 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1500 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1501 unsigned long flags = 0;
1502 struct mm_struct *mm = current->mm;
1503 unsigned int region_id = get_region_id(ea);
1505 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1508 if (dsisr & DSISR_NOHPTE)
1509 flags |= HPTE_NOHPTE_UPDATE;
1511 if (dsisr & DSISR_ISSTORE)
1512 access |= _PAGE_WRITE;
1514 * We set _PAGE_PRIVILEGED only when
1515 * kernel mode access kernel space.
1517 * _PAGE_PRIVILEGED is NOT set
1518 * 1) when kernel mode access user space
1519 * 2) user space access kernel space.
1521 access |= _PAGE_PRIVILEGED;
1522 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1523 access &= ~_PAGE_PRIVILEGED;
1526 access |= _PAGE_EXEC;
1528 return hash_page_mm(mm, ea, access, trap, flags);
1531 #ifdef CONFIG_PPC_MM_SLICES
1532 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1534 int psize = get_slice_psize(mm, ea);
1536 /* We only prefault standard pages for now */
1537 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1541 * Don't prefault if subpage protection is enabled for the EA.
1543 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1549 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1555 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea,
1556 bool is_exec, unsigned long trap)
1560 int rc, ssize, update_flags = 0;
1561 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1562 unsigned long flags;
1564 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1566 if (!should_hash_preload(mm, ea))
1569 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1570 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1572 /* Get Linux PTE if available */
1578 ssize = user_segment_size(ea);
1579 vsid = get_user_vsid(&mm->context, ea, ssize);
1583 #ifdef CONFIG_PPC_64K_PAGES
1584 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1585 * a 64K kernel), then we don't preload, hash_page() will take
1586 * care of it once we actually try to access the page.
1587 * That way we don't have to duplicate all of the logic for segment
1588 * page size demotion here
1589 * Called with PTL held, hence can be sure the value won't change in
1592 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1594 #endif /* CONFIG_PPC_64K_PAGES */
1597 * __hash_page_* must run with interrupts off, as it sets the
1598 * H_PAGE_BUSY bit. It's possible for perf interrupts to hit at any
1599 * time and may take a hash fault reading the user stack, see
1600 * read_user_stack_slow() in the powerpc/perf code.
1602 * If that takes a hash fault on the same page as we lock here, it
1603 * will bail out when seeing H_PAGE_BUSY set, and retry the access
1604 * leading to an infinite loop.
1606 * Disabling interrupts here does not prevent perf interrupts, but it
1607 * will prevent them taking hash faults (see the NMI test in
1608 * do_hash_page), then read_user_stack's copy_from_user_nofault will
1609 * fail and perf will fall back to read_user_stack_slow(), which
1610 * walks the Linux page tables.
1612 * Interrupts must also be off for the duration of the
1613 * mm_is_thread_local test and update, to prevent preempt running the
1614 * mm on another CPU (XXX: this may be racy vs kthread_use_mm).
1616 local_irq_save(flags);
1618 /* Is that local to this CPU ? */
1619 if (mm_is_thread_local(mm))
1620 update_flags |= HPTE_LOCAL_UPDATE;
1623 #ifdef CONFIG_PPC_64K_PAGES
1624 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1625 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1626 update_flags, ssize);
1628 #endif /* CONFIG_PPC_64K_PAGES */
1629 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1630 ssize, subpage_protection(mm, ea));
1632 /* Dump some info in case of hash insertion failure, they should
1633 * never happen so it is really useful to know if/when they do
1636 hash_failure_debug(ea, access, vsid, trap, ssize,
1637 mm_ctx_user_psize(&mm->context),
1638 mm_ctx_user_psize(&mm->context),
1641 local_irq_restore(flags);
1645 * This is called at the end of handling a user page fault, when the
1646 * fault has been handled by updating a PTE in the linux page tables.
1647 * We use it to preload an HPTE into the hash table corresponding to
1648 * the updated linux PTE.
1650 * This must always be called with the pte lock held.
1652 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1656 * We don't need to worry about _PAGE_PRESENT here because we are
1657 * called with either mm->page_table_lock held or ptl lock held
1662 if (radix_enabled())
1665 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1666 if (!pte_young(*ptep) || address >= TASK_SIZE)
1670 * We try to figure out if we are coming from an instruction
1671 * access fault and pass that down to __hash_page so we avoid
1672 * double-faulting on execution of fresh text. We have to test
1673 * for regs NULL since init will get here first thing at boot.
1675 * We also avoid filling the hash if not coming from a fault.
1678 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1690 hash_preload(vma->vm_mm, ptep, address, is_exec, trap);
1693 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1694 static inline void tm_flush_hash_page(int local)
1697 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1698 * page back to a block device w/PIO could pick up transactional data
1699 * (bad!) so we force an abort here. Before the sync the page will be
1700 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1701 * kernel uses a page from userspace without unmapping it first, it may
1702 * see the speculated version.
1704 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1705 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1707 tm_abort(TM_CAUSE_TLBI);
1711 static inline void tm_flush_hash_page(int local)
1717 * Return the global hash slot, corresponding to the given PTE, which contains
1720 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1721 int ssize, real_pte_t rpte, unsigned int subpg_index)
1723 unsigned long hash, gslot, hidx;
1725 hash = hpt_hash(vpn, shift, ssize);
1726 hidx = __rpte_to_hidx(rpte, subpg_index);
1727 if (hidx & _PTEIDX_SECONDARY)
1729 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1730 gslot += hidx & _PTEIDX_GROUP_IX;
1735 * WARNING: This is called from hash_low_64.S, if you change this prototype,
1736 * do not forget to update the assembly call site !
1738 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1739 unsigned long flags)
1741 unsigned long index, shift, gslot;
1742 int local = flags & HPTE_LOCAL_UPDATE;
1744 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1745 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1746 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1747 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1749 * We use same base page size and actual psize, because we don't
1750 * use these functions for hugepage
1752 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1754 } pte_iterate_hashed_end();
1756 tm_flush_hash_page(local);
1759 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1760 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1761 pmd_t *pmdp, unsigned int psize, int ssize,
1762 unsigned long flags)
1764 int i, max_hpte_count, valid;
1765 unsigned long s_addr;
1766 unsigned char *hpte_slot_array;
1767 unsigned long hidx, shift, vpn, hash, slot;
1768 int local = flags & HPTE_LOCAL_UPDATE;
1770 s_addr = addr & HPAGE_PMD_MASK;
1771 hpte_slot_array = get_hpte_slot_array(pmdp);
1773 * IF we try to do a HUGE PTE update after a withdraw is done.
1774 * we will find the below NULL. This happens when we do
1777 if (!hpte_slot_array)
1780 if (mmu_hash_ops.hugepage_invalidate) {
1781 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1782 psize, ssize, local);
1786 * No bluk hpte removal support, invalidate each entry
1788 shift = mmu_psize_defs[psize].shift;
1789 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1790 for (i = 0; i < max_hpte_count; i++) {
1792 * 8 bits per each hpte entries
1793 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1795 valid = hpte_valid(hpte_slot_array, i);
1798 hidx = hpte_hash_index(hpte_slot_array, i);
1801 addr = s_addr + (i * (1ul << shift));
1802 vpn = hpt_vpn(addr, vsid, ssize);
1803 hash = hpt_hash(vpn, shift, ssize);
1804 if (hidx & _PTEIDX_SECONDARY)
1807 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1808 slot += hidx & _PTEIDX_GROUP_IX;
1809 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1810 MMU_PAGE_16M, ssize, local);
1813 tm_flush_hash_page(local);
1815 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1817 void flush_hash_range(unsigned long number, int local)
1819 if (mmu_hash_ops.flush_hash_range)
1820 mmu_hash_ops.flush_hash_range(number, local);
1823 struct ppc64_tlb_batch *batch =
1824 this_cpu_ptr(&ppc64_tlb_batch);
1826 for (i = 0; i < number; i++)
1827 flush_hash_page(batch->vpn[i], batch->pte[i],
1828 batch->psize, batch->ssize, local);
1833 * low_hash_fault is called when we the low level hash code failed
1834 * to instert a PTE due to an hypervisor error
1836 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1838 enum ctx_state prev_state = exception_enter();
1840 if (user_mode(regs)) {
1841 #ifdef CONFIG_PPC_SUBPAGE_PROT
1843 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1846 _exception(SIGBUS, regs, BUS_ADRERR, address);
1848 bad_page_fault(regs, address, SIGBUS);
1850 exception_exit(prev_state);
1853 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1854 unsigned long pa, unsigned long rflags,
1855 unsigned long vflags, int psize, int ssize)
1857 unsigned long hpte_group;
1861 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1863 /* Insert into the hash table, primary slot */
1864 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1865 psize, psize, ssize);
1867 /* Primary is full, try the secondary */
1868 if (unlikely(slot == -1)) {
1869 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1870 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1871 vflags | HPTE_V_SECONDARY,
1872 psize, psize, ssize);
1875 hpte_group = (hash & htab_hash_mask) *
1878 mmu_hash_ops.hpte_remove(hpte_group);
1886 #ifdef CONFIG_DEBUG_PAGEALLOC
1887 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1890 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1891 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1892 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1895 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1897 /* Don't create HPTE entries for bad address */
1901 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1903 mmu_linear_psize, mmu_kernel_ssize);
1906 spin_lock(&linear_map_hash_lock);
1907 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1908 linear_map_hash_slots[lmi] = ret | 0x80;
1909 spin_unlock(&linear_map_hash_lock);
1912 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1914 unsigned long hash, hidx, slot;
1915 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1916 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1918 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1919 spin_lock(&linear_map_hash_lock);
1920 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1921 hidx = linear_map_hash_slots[lmi] & 0x7f;
1922 linear_map_hash_slots[lmi] = 0;
1923 spin_unlock(&linear_map_hash_lock);
1924 if (hidx & _PTEIDX_SECONDARY)
1926 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1927 slot += hidx & _PTEIDX_GROUP_IX;
1928 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1930 mmu_kernel_ssize, 0);
1933 void __kernel_map_pages(struct page *page, int numpages, int enable)
1935 unsigned long flags, vaddr, lmi;
1938 local_irq_save(flags);
1939 for (i = 0; i < numpages; i++, page++) {
1940 vaddr = (unsigned long)page_address(page);
1941 lmi = __pa(vaddr) >> PAGE_SHIFT;
1942 if (lmi >= linear_map_hash_count)
1945 kernel_map_linear_page(vaddr, lmi);
1947 kernel_unmap_linear_page(vaddr, lmi);
1949 local_irq_restore(flags);
1951 #endif /* CONFIG_DEBUG_PAGEALLOC */
1953 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1954 phys_addr_t first_memblock_size)
1957 * We don't currently support the first MEMBLOCK not mapping 0
1958 * physical on those processors
1960 BUG_ON(first_memblock_base != 0);
1963 * On virtualized systems the first entry is our RMA region aka VRMA,
1964 * non-virtualized 64-bit hash MMU systems don't have a limitation
1965 * on real mode access.
1967 * For guests on platforms before POWER9, we clamp the it limit to 1G
1968 * to avoid some funky things such as RTAS bugs etc...
1970 * On POWER9 we limit to 1TB in case the host erroneously told us that
1971 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1972 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1973 * for virtual real mode addressing and so it doesn't make sense to
1974 * have an area larger than 1TB as it can't be addressed.
1976 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1977 ppc64_rma_size = first_memblock_size;
1978 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1979 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1981 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1982 1UL << SID_SHIFT_1T);
1984 /* Finally limit subsequent allocations */
1985 memblock_set_current_limit(ppc64_rma_size);
1987 ppc64_rma_size = ULONG_MAX;
1991 #ifdef CONFIG_DEBUG_FS
1993 static int hpt_order_get(void *data, u64 *val)
1995 *val = ppc64_pft_size;
1999 static int hpt_order_set(void *data, u64 val)
2003 if (!mmu_hash_ops.resize_hpt)
2007 ret = mmu_hash_ops.resize_hpt(val);
2013 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2015 static int __init hash64_debugfs(void)
2017 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL,
2021 machine_device_initcall(pseries, hash64_debugfs);
2022 #endif /* CONFIG_DEBUG_FS */
2024 void __init print_system_hash_info(void)
2026 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2029 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);