1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
38 #include <linux/pgtable.h>
40 #include <asm/debugfs.h>
41 #include <asm/processor.h>
43 #include <asm/mmu_context.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/ultravisor.h>
67 #include <mm/mmu_decl.h>
73 #define DBG(fmt...) udbg_printf(fmt)
79 #define DBG_LOW(fmt...) udbg_printf(fmt)
81 #define DBG_LOW(fmt...)
89 * Note: pte --> Linux PTE
90 * HPTE --> PowerPC Hashed Page Table Entry
93 * htab_initialize is called with the MMU off (of course), but
94 * the kernel has been copied down to zero so it can directly
95 * reference global data. At this point it is very difficult
96 * to print debug info.
100 static unsigned long _SDR1;
101 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
102 EXPORT_SYMBOL_GPL(mmu_psize_defs);
104 u8 hpte_page_sizes[1 << LP_BITS];
105 EXPORT_SYMBOL_GPL(hpte_page_sizes);
107 struct hash_pte *htab_address;
108 unsigned long htab_size_bytes;
109 unsigned long htab_hash_mask;
110 EXPORT_SYMBOL_GPL(htab_hash_mask);
111 int mmu_linear_psize = MMU_PAGE_4K;
112 EXPORT_SYMBOL_GPL(mmu_linear_psize);
113 int mmu_virtual_psize = MMU_PAGE_4K;
114 int mmu_vmalloc_psize = MMU_PAGE_4K;
115 EXPORT_SYMBOL_GPL(mmu_vmalloc_psize);
116 #ifdef CONFIG_SPARSEMEM_VMEMMAP
117 int mmu_vmemmap_psize = MMU_PAGE_4K;
119 int mmu_io_psize = MMU_PAGE_4K;
120 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
121 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
122 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
123 u16 mmu_slb_size = 64;
124 EXPORT_SYMBOL_GPL(mmu_slb_size);
125 #ifdef CONFIG_PPC_64K_PAGES
126 int mmu_ci_restrictions;
128 #ifdef CONFIG_DEBUG_PAGEALLOC
129 static u8 *linear_map_hash_slots;
130 static unsigned long linear_map_hash_count;
131 static DEFINE_SPINLOCK(linear_map_hash_lock);
132 #endif /* CONFIG_DEBUG_PAGEALLOC */
133 struct mmu_hash_ops mmu_hash_ops;
134 EXPORT_SYMBOL(mmu_hash_ops);
137 * These are definitions of page sizes arrays to be used when none
138 * is provided by the firmware.
142 * Fallback (4k pages only)
144 static struct mmu_psize_def mmu_psize_defaults[] = {
148 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
155 * POWER4, GPUL, POWER5
157 * Support for 16Mb large pages
159 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
163 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
170 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
171 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
178 * 'R' and 'C' update notes:
179 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
180 * create writeable HPTEs without C set, because the hcall H_PROTECT
181 * that we use in that case will not update C
182 * - The above is however not a problem, because we also don't do that
183 * fancy "no flush" variant of eviction and we use H_REMOVE which will
184 * do the right thing and thus we don't have the race I described earlier
186 * - Under bare metal, we do have the race, so we need R and C set
187 * - We make sure R is always set and never lost
188 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
190 unsigned long htab_convert_pte_flags(unsigned long pteflags, unsigned long flags)
192 unsigned long rflags = 0;
194 /* _PAGE_EXEC -> NOEXEC */
195 if ((pteflags & _PAGE_EXEC) == 0)
199 * Linux uses slb key 0 for kernel and 1 for user.
200 * kernel RW areas are mapped with PPP=0b000
201 * User area is mapped with PPP=0b010 for read/write
202 * or PPP=0b011 for read-only (including writeable but clean pages).
204 if (pteflags & _PAGE_PRIVILEGED) {
206 * Kernel read only mapped with ppp bits 0b110
208 if (!(pteflags & _PAGE_WRITE)) {
209 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
210 rflags |= (HPTE_R_PP0 | 0x2);
215 if (pteflags & _PAGE_RWX)
217 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
221 * We can't allow hardware to update hpte bits. Hence always
222 * set 'R' bit and set 'C' if it is a write fault
226 if (pteflags & _PAGE_DIRTY)
232 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
234 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
235 rflags |= (HPTE_R_I | HPTE_R_G);
236 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
237 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
240 * Add memory coherence if cache inhibited is not set
244 rflags |= pte_to_hpte_pkey_bits(pteflags, flags);
248 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
249 unsigned long pstart, unsigned long prot,
250 int psize, int ssize)
252 unsigned long vaddr, paddr;
253 unsigned int step, shift;
256 shift = mmu_psize_defs[psize].shift;
259 prot = htab_convert_pte_flags(prot, HPTE_USE_KERNEL_KEY);
261 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
262 vstart, vend, pstart, prot, psize, ssize);
264 /* Carefully map only the possible range */
265 vaddr = ALIGN(vstart, step);
266 paddr = ALIGN(pstart, step);
267 vend = ALIGN_DOWN(vend, step);
269 for (; vaddr < vend; vaddr += step, paddr += step) {
270 unsigned long hash, hpteg;
271 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
272 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
273 unsigned long tprot = prot;
274 bool secondary_hash = false;
277 * If we hit a bad address return error.
281 /* Make kernel text executable */
282 if (overlaps_kernel_text(vaddr, vaddr + step))
286 * If relocatable, check if it overlaps interrupt vectors that
287 * are copied down to real 0. For relocatable kernel
288 * (e.g. kdump case) we copy interrupt vectors down to real
289 * address 0. Mark that region as executable. This is
290 * because on p8 system with relocation on exception feature
291 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
292 * in order to execute the interrupt handlers in virtual
293 * mode the vector region need to be marked as executable.
295 if ((PHYSICAL_START > MEMORY_START) &&
296 overlaps_interrupt_vector_text(vaddr, vaddr + step))
299 hash = hpt_hash(vpn, shift, ssize);
300 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
302 BUG_ON(!mmu_hash_ops.hpte_insert);
304 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
305 HPTE_V_BOLTED, psize, psize,
309 * Try to to keep bolted entries in primary.
310 * Remove non bolted entries and try insert again
312 ret = mmu_hash_ops.hpte_remove(hpteg);
314 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
315 HPTE_V_BOLTED, psize, psize,
317 if (ret == -1 && !secondary_hash) {
318 secondary_hash = true;
319 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
328 #ifdef CONFIG_DEBUG_PAGEALLOC
329 if (debug_pagealloc_enabled() &&
330 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
331 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
332 #endif /* CONFIG_DEBUG_PAGEALLOC */
334 return ret < 0 ? ret : 0;
337 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
338 int psize, int ssize)
341 unsigned int step, shift;
345 shift = mmu_psize_defs[psize].shift;
348 if (!mmu_hash_ops.hpte_removebolted)
351 /* Unmap the full range specificied */
352 vaddr = ALIGN_DOWN(vstart, step);
353 for (;vaddr < vend; vaddr += step) {
354 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
366 static bool disable_1tb_segments = false;
368 static int __init parse_disable_1tb_segments(char *p)
370 disable_1tb_segments = true;
373 early_param("disable_1tb_segments", parse_disable_1tb_segments);
375 static int __init htab_dt_scan_seg_sizes(unsigned long node,
376 const char *uname, int depth,
379 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
383 /* We are scanning "cpu" nodes only */
384 if (type == NULL || strcmp(type, "cpu") != 0)
387 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
390 for (; size >= 4; size -= 4, ++prop) {
391 if (be32_to_cpu(prop[0]) == 40) {
392 DBG("1T segment support detected\n");
394 if (disable_1tb_segments) {
395 DBG("1T segments disabled by command line\n");
399 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
403 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
407 static int __init get_idx_from_shift(unsigned int shift)
431 static int __init htab_dt_scan_page_sizes(unsigned long node,
432 const char *uname, int depth,
435 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
439 /* We are scanning "cpu" nodes only */
440 if (type == NULL || strcmp(type, "cpu") != 0)
443 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
447 pr_info("Page sizes from device-tree:\n");
449 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
451 unsigned int base_shift = be32_to_cpu(prop[0]);
452 unsigned int slbenc = be32_to_cpu(prop[1]);
453 unsigned int lpnum = be32_to_cpu(prop[2]);
454 struct mmu_psize_def *def;
457 size -= 3; prop += 3;
458 base_idx = get_idx_from_shift(base_shift);
460 /* skip the pte encoding also */
461 prop += lpnum * 2; size -= lpnum * 2;
464 def = &mmu_psize_defs[base_idx];
465 if (base_idx == MMU_PAGE_16M)
466 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
468 def->shift = base_shift;
469 if (base_shift <= 23)
472 def->avpnm = (1 << (base_shift - 23)) - 1;
475 * We don't know for sure what's up with tlbiel, so
476 * for now we only set it for 4K and 64K pages
478 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
483 while (size > 0 && lpnum) {
484 unsigned int shift = be32_to_cpu(prop[0]);
485 int penc = be32_to_cpu(prop[1]);
487 prop += 2; size -= 2;
490 idx = get_idx_from_shift(shift);
495 pr_err("Invalid penc for base_shift=%d "
496 "shift=%d\n", base_shift, shift);
498 def->penc[idx] = penc;
499 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
500 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
501 base_shift, shift, def->sllp,
502 def->avpnm, def->tlbiel, def->penc[idx]);
509 #ifdef CONFIG_HUGETLB_PAGE
511 * Scan for 16G memory blocks that have been set aside for huge pages
512 * and reserve those blocks for 16G huge pages.
514 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
515 const char *uname, int depth,
517 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
518 const __be64 *addr_prop;
519 const __be32 *page_count_prop;
520 unsigned int expected_pages;
521 long unsigned int phys_addr;
522 long unsigned int block_size;
524 /* We are scanning "memory" nodes only */
525 if (type == NULL || strcmp(type, "memory") != 0)
529 * This property is the log base 2 of the number of virtual pages that
530 * will represent this memory block.
532 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
533 if (page_count_prop == NULL)
535 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
536 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
537 if (addr_prop == NULL)
539 phys_addr = be64_to_cpu(addr_prop[0]);
540 block_size = be64_to_cpu(addr_prop[1]);
541 if (block_size != (16 * GB))
543 printk(KERN_INFO "Huge page(16GB) memory: "
544 "addr = 0x%lX size = 0x%lX pages = %d\n",
545 phys_addr, block_size, expected_pages);
546 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
547 memblock_reserve(phys_addr, block_size * expected_pages);
548 pseries_add_gpage(phys_addr, block_size, expected_pages);
552 #endif /* CONFIG_HUGETLB_PAGE */
554 static void mmu_psize_set_default_penc(void)
557 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
558 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
559 mmu_psize_defs[bpsize].penc[apsize] = -1;
562 #ifdef CONFIG_PPC_64K_PAGES
564 static bool might_have_hea(void)
567 * The HEA ethernet adapter requires awareness of the
568 * GX bus. Without that awareness we can easily assume
569 * we will never see an HEA ethernet device.
571 #ifdef CONFIG_IBMEBUS
572 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
573 firmware_has_feature(FW_FEATURE_SPLPAR);
579 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
581 static void __init htab_scan_page_sizes(void)
585 /* se the invalid penc to -1 */
586 mmu_psize_set_default_penc();
588 /* Default to 4K pages only */
589 memcpy(mmu_psize_defs, mmu_psize_defaults,
590 sizeof(mmu_psize_defaults));
593 * Try to find the available page sizes in the device-tree
595 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
596 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
598 * Nothing in the device-tree, but the CPU supports 16M pages,
599 * so let's fallback on a known size list for 16M capable CPUs.
601 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
602 sizeof(mmu_psize_defaults_gp));
605 #ifdef CONFIG_HUGETLB_PAGE
606 if (!hugetlb_disabled && !early_radix_enabled() ) {
607 /* Reserve 16G huge page memory sections for huge pages */
608 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
610 #endif /* CONFIG_HUGETLB_PAGE */
614 * Fill in the hpte_page_sizes[] array.
615 * We go through the mmu_psize_defs[] array looking for all the
616 * supported base/actual page size combinations. Each combination
617 * has a unique pagesize encoding (penc) value in the low bits of
618 * the LP field of the HPTE. For actual page sizes less than 1MB,
619 * some of the upper LP bits are used for RPN bits, meaning that
620 * we need to fill in several entries in hpte_page_sizes[].
622 * In diagrammatic form, with r = RPN bits and z = page size bits:
623 * PTE LP actual page size
630 * The zzzz bits are implementation-specific but are chosen so that
631 * no encoding for a larger page size uses the same value in its
632 * low-order N bits as the encoding for the 2^(12+N) byte page size
635 static void init_hpte_page_sizes(void)
638 long int shift, penc;
640 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
641 if (!mmu_psize_defs[bp].shift)
642 continue; /* not a supported page size */
643 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
644 penc = mmu_psize_defs[bp].penc[ap];
645 if (penc == -1 || !mmu_psize_defs[ap].shift)
647 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
649 continue; /* should never happen */
651 * For page sizes less than 1MB, this loop
652 * replicates the entry for all possible values
655 while (penc < (1 << LP_BITS)) {
656 hpte_page_sizes[penc] = (ap << 4) | bp;
663 static void __init htab_init_page_sizes(void)
666 init_hpte_page_sizes();
668 if (!debug_pagealloc_enabled()) {
670 * Pick a size for the linear mapping. Currently, we only
671 * support 16M, 1M and 4K which is the default
673 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) &&
674 (unsigned long)_stext % 0x1000000) {
675 if (mmu_psize_defs[MMU_PAGE_16M].shift)
676 pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n");
680 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
681 mmu_linear_psize = MMU_PAGE_16M;
682 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
683 mmu_linear_psize = MMU_PAGE_1M;
686 #ifdef CONFIG_PPC_64K_PAGES
688 * Pick a size for the ordinary pages. Default is 4K, we support
689 * 64K for user mappings and vmalloc if supported by the processor.
690 * We only use 64k for ioremap if the processor
691 * (and firmware) support cache-inhibited large pages.
692 * If not, we use 4k and set mmu_ci_restrictions so that
693 * hash_page knows to switch processes that use cache-inhibited
694 * mappings to 4k pages.
696 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
697 mmu_virtual_psize = MMU_PAGE_64K;
698 mmu_vmalloc_psize = MMU_PAGE_64K;
699 if (mmu_linear_psize == MMU_PAGE_4K)
700 mmu_linear_psize = MMU_PAGE_64K;
701 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
703 * When running on pSeries using 64k pages for ioremap
704 * would stop us accessing the HEA ethernet. So if we
705 * have the chance of ever seeing one, stay at 4k.
707 if (!might_have_hea())
708 mmu_io_psize = MMU_PAGE_64K;
710 mmu_ci_restrictions = 1;
712 #endif /* CONFIG_PPC_64K_PAGES */
714 #ifdef CONFIG_SPARSEMEM_VMEMMAP
716 * We try to use 16M pages for vmemmap if that is supported
717 * and we have at least 1G of RAM at boot
719 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
720 memblock_phys_mem_size() >= 0x40000000)
721 mmu_vmemmap_psize = MMU_PAGE_16M;
723 mmu_vmemmap_psize = mmu_virtual_psize;
724 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
726 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
727 "virtual = %d, io = %d"
728 #ifdef CONFIG_SPARSEMEM_VMEMMAP
732 mmu_psize_defs[mmu_linear_psize].shift,
733 mmu_psize_defs[mmu_virtual_psize].shift,
734 mmu_psize_defs[mmu_io_psize].shift
735 #ifdef CONFIG_SPARSEMEM_VMEMMAP
736 ,mmu_psize_defs[mmu_vmemmap_psize].shift
741 static int __init htab_dt_scan_pftsize(unsigned long node,
742 const char *uname, int depth,
745 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
748 /* We are scanning "cpu" nodes only */
749 if (type == NULL || strcmp(type, "cpu") != 0)
752 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
754 /* pft_size[0] is the NUMA CEC cookie */
755 ppc64_pft_size = be32_to_cpu(prop[1]);
761 unsigned htab_shift_for_mem_size(unsigned long mem_size)
763 unsigned memshift = __ilog2(mem_size);
764 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
767 /* round mem_size up to next power of 2 */
768 if ((1UL << memshift) < mem_size)
771 /* aim for 2 pages / pteg */
772 pteg_shift = memshift - (pshift + 1);
775 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
776 * size permitted by the architecture.
778 return max(pteg_shift + 7, 18U);
781 static unsigned long __init htab_get_table_size(void)
784 * If hash size isn't already provided by the platform, we try to
785 * retrieve it from the device-tree. If it's not there neither, we
786 * calculate it now based on the total RAM size
788 if (ppc64_pft_size == 0)
789 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
791 return 1UL << ppc64_pft_size;
793 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
796 #ifdef CONFIG_MEMORY_HOTPLUG
797 static int resize_hpt_for_hotplug(unsigned long new_mem_size)
799 unsigned target_hpt_shift;
801 if (!mmu_hash_ops.resize_hpt)
804 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
807 * To avoid lots of HPT resizes if memory size is fluctuating
808 * across a boundary, we deliberately have some hysterisis
809 * here: we immediately increase the HPT size if the target
810 * shift exceeds the current shift, but we won't attempt to
811 * reduce unless the target shift is at least 2 below the
814 if (target_hpt_shift > ppc64_pft_size ||
815 target_hpt_shift < ppc64_pft_size - 1)
816 return mmu_hash_ops.resize_hpt(target_hpt_shift);
821 int hash__create_section_mapping(unsigned long start, unsigned long end,
822 int nid, pgprot_t prot)
826 if (end >= H_VMALLOC_START) {
827 pr_warn("Outside the supported range\n");
831 resize_hpt_for_hotplug(memblock_phys_mem_size());
833 rc = htab_bolt_mapping(start, end, __pa(start),
834 pgprot_val(prot), mmu_linear_psize,
838 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
840 BUG_ON(rc2 && (rc2 != -ENOENT));
845 int hash__remove_section_mapping(unsigned long start, unsigned long end)
847 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
850 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC)
851 pr_warn("Hash collision while resizing HPT\n");
855 #endif /* CONFIG_MEMORY_HOTPLUG */
857 static void __init hash_init_partition_table(phys_addr_t hash_table,
858 unsigned long htab_size)
860 mmu_partition_table_init();
863 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
864 * For now, UPRT is 0 and we have no segment table.
866 htab_size = __ilog2(htab_size) - 18;
867 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
868 pr_info("Partition table %p\n", partition_tb);
871 static void __init htab_initialize(void)
874 unsigned long pteg_count;
876 phys_addr_t base = 0, size = 0, end;
879 DBG(" -> htab_initialize()\n");
881 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
882 mmu_kernel_ssize = MMU_SEGSIZE_1T;
883 mmu_highuser_ssize = MMU_SEGSIZE_1T;
884 printk(KERN_INFO "Using 1TB segments\n");
887 if (stress_slb_enabled)
888 static_branch_enable(&stress_slb_key);
891 * Calculate the required size of the htab. We want the number of
892 * PTEGs to equal one half the number of real pages.
894 htab_size_bytes = htab_get_table_size();
895 pteg_count = htab_size_bytes >> 7;
897 htab_hash_mask = pteg_count - 1;
899 if (firmware_has_feature(FW_FEATURE_LPAR) ||
900 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
901 /* Using a hypervisor which owns the htab */
904 #ifdef CONFIG_FA_DUMP
906 * If firmware assisted dump is active firmware preserves
907 * the contents of htab along with entire partition memory.
908 * Clear the htab if firmware assisted dump is active so
909 * that we dont end up using old mappings.
911 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
912 mmu_hash_ops.hpte_clear_all();
915 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
917 #ifdef CONFIG_PPC_CELL
919 * Cell may require the hash table down low when using the
920 * Axon IOMMU in order to fit the dynamic region over it, see
921 * comments in cell/iommu.c
923 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
925 pr_info("Hash table forced below 2G for Axon IOMMU\n");
927 #endif /* CONFIG_PPC_CELL */
929 table = memblock_phys_alloc_range(htab_size_bytes,
933 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
934 &htab_size_bytes, &limit);
936 DBG("Hash table allocated at %lx, size: %lx\n", table,
939 htab_address = __va(table);
941 /* htab absolute addr + encoded htabsize */
942 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
944 /* Initialize the HPT with no entries */
945 memset((void *)table, 0, htab_size_bytes);
947 if (!cpu_has_feature(CPU_FTR_ARCH_300))
949 mtspr(SPRN_SDR1, _SDR1);
951 hash_init_partition_table(table, htab_size_bytes);
954 prot = pgprot_val(PAGE_KERNEL);
956 #ifdef CONFIG_DEBUG_PAGEALLOC
957 if (debug_pagealloc_enabled()) {
958 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
959 linear_map_hash_slots = memblock_alloc_try_nid(
960 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
961 ppc64_rma_size, NUMA_NO_NODE);
962 if (!linear_map_hash_slots)
963 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
964 __func__, linear_map_hash_count, &ppc64_rma_size);
966 #endif /* CONFIG_DEBUG_PAGEALLOC */
968 /* create bolted the linear mapping in the hash table */
969 for_each_mem_range(i, &base, &end) {
971 base = (unsigned long)__va(base);
973 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
976 if ((base + size) >= H_VMALLOC_START) {
977 pr_warn("Outside the supported range\n");
981 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
982 prot, mmu_linear_psize, mmu_kernel_ssize));
984 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
987 * If we have a memory_limit and we've allocated TCEs then we need to
988 * explicitly map the TCE area at the top of RAM. We also cope with the
989 * case that the TCEs start below memory_limit.
990 * tce_alloc_start/end are 16MB aligned so the mapping should work
991 * for either 4K or 16MB pages.
993 if (tce_alloc_start) {
994 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
995 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
997 if (base + size >= tce_alloc_start)
998 tce_alloc_start = base + size + 1;
1000 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
1001 __pa(tce_alloc_start), prot,
1002 mmu_linear_psize, mmu_kernel_ssize));
1006 DBG(" <- htab_initialize()\n");
1011 void __init hash__early_init_devtree(void)
1013 /* Initialize segment sizes */
1014 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
1016 /* Initialize page sizes */
1017 htab_scan_page_sizes();
1020 static struct hash_mm_context init_hash_mm_context;
1021 void __init hash__early_init_mmu(void)
1023 #ifndef CONFIG_PPC_64K_PAGES
1025 * We have code in __hash_page_4K() and elsewhere, which assumes it can
1027 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1029 * Where the slot number is between 0-15, and values of 8-15 indicate
1030 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
1031 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1032 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1033 * with a BUILD_BUG_ON().
1035 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1036 #endif /* CONFIG_PPC_64K_PAGES */
1038 htab_init_page_sizes();
1041 * initialize page table size
1043 __pte_frag_nr = H_PTE_FRAG_NR;
1044 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1045 __pmd_frag_nr = H_PMD_FRAG_NR;
1046 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1048 __pte_index_size = H_PTE_INDEX_SIZE;
1049 __pmd_index_size = H_PMD_INDEX_SIZE;
1050 __pud_index_size = H_PUD_INDEX_SIZE;
1051 __pgd_index_size = H_PGD_INDEX_SIZE;
1052 __pud_cache_index = H_PUD_CACHE_INDEX;
1053 __pte_table_size = H_PTE_TABLE_SIZE;
1054 __pmd_table_size = H_PMD_TABLE_SIZE;
1055 __pud_table_size = H_PUD_TABLE_SIZE;
1056 __pgd_table_size = H_PGD_TABLE_SIZE;
1058 * 4k use hugepd format, so for hash set then to
1061 __pmd_val_bits = HASH_PMD_VAL_BITS;
1062 __pud_val_bits = HASH_PUD_VAL_BITS;
1063 __pgd_val_bits = HASH_PGD_VAL_BITS;
1065 __kernel_virt_start = H_KERN_VIRT_START;
1066 __vmalloc_start = H_VMALLOC_START;
1067 __vmalloc_end = H_VMALLOC_END;
1068 __kernel_io_start = H_KERN_IO_START;
1069 __kernel_io_end = H_KERN_IO_END;
1070 vmemmap = (struct page *)H_VMEMMAP_START;
1071 ioremap_bot = IOREMAP_BASE;
1074 pci_io_base = ISA_IO_BASE;
1077 /* Select appropriate backend */
1078 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1079 ps3_early_mm_init();
1080 else if (firmware_has_feature(FW_FEATURE_LPAR))
1081 hpte_init_pseries();
1082 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1085 if (!mmu_hash_ops.hpte_insert)
1086 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1089 * Initialize the MMU Hash table and create the linear mapping
1090 * of memory. Has to be done before SLB initialization as this is
1091 * currently where the page size encoding is obtained.
1095 init_mm.context.hash_context = &init_hash_mm_context;
1096 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1098 pr_info("Initializing hash mmu with SLB\n");
1099 /* Initialize SLB management */
1102 if (cpu_has_feature(CPU_FTR_ARCH_206)
1103 && cpu_has_feature(CPU_FTR_HVMODE))
1108 void hash__early_init_mmu_secondary(void)
1110 /* Initialize hash table for that CPU */
1111 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1113 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1114 mtspr(SPRN_SDR1, _SDR1);
1116 set_ptcr_when_no_uv(__pa(partition_tb) |
1117 (PATB_SIZE_SHIFT - 12));
1119 /* Initialize SLB */
1122 if (cpu_has_feature(CPU_FTR_ARCH_206)
1123 && cpu_has_feature(CPU_FTR_HVMODE))
1126 #ifdef CONFIG_PPC_MEM_KEYS
1127 if (mmu_has_feature(MMU_FTR_PKEY))
1128 mtspr(SPRN_UAMOR, default_uamor);
1131 #endif /* CONFIG_SMP */
1134 * Called by asm hashtable.S for doing lazy icache flush
1136 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1140 if (!pfn_valid(pte_pfn(pte)))
1143 page = pte_page(pte);
1146 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1147 if (trap == 0x400) {
1148 flush_dcache_icache_page(page);
1149 set_bit(PG_arch_1, &page->flags);
1156 #ifdef CONFIG_PPC_MM_SLICES
1157 static unsigned int get_paca_psize(unsigned long addr)
1159 unsigned char *psizes;
1160 unsigned long index, mask_index;
1162 if (addr < SLICE_LOW_TOP) {
1163 psizes = get_paca()->mm_ctx_low_slices_psize;
1164 index = GET_LOW_SLICE_INDEX(addr);
1166 psizes = get_paca()->mm_ctx_high_slices_psize;
1167 index = GET_HIGH_SLICE_INDEX(addr);
1169 mask_index = index & 0x1;
1170 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1174 unsigned int get_paca_psize(unsigned long addr)
1176 return get_paca()->mm_ctx_user_psize;
1181 * Demote a segment to using 4k pages.
1182 * For now this makes the whole process use 4k pages.
1184 #ifdef CONFIG_PPC_64K_PAGES
1185 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1187 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1189 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1190 copro_flush_all_slbs(mm);
1191 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1193 copy_mm_to_paca(mm);
1194 slb_flush_and_restore_bolted();
1197 #endif /* CONFIG_PPC_64K_PAGES */
1199 #ifdef CONFIG_PPC_SUBPAGE_PROT
1201 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1202 * Userspace sets the subpage permissions using the subpage_prot system call.
1204 * Result is 0: full permissions, _PAGE_RW: read-only,
1205 * _PAGE_RWX: no access.
1207 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1209 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1216 if (ea >= spt->maxaddr)
1218 if (ea < 0x100000000UL) {
1219 /* addresses below 4GB use spt->low_prot */
1220 sbpm = spt->low_prot;
1222 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1226 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1229 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1231 /* extract 2-bit bitfield for this 4k subpage */
1232 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1235 * 0 -> full premission
1238 * We return the flag that need to be cleared.
1240 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1244 #else /* CONFIG_PPC_SUBPAGE_PROT */
1245 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1251 void hash_failure_debug(unsigned long ea, unsigned long access,
1252 unsigned long vsid, unsigned long trap,
1253 int ssize, int psize, int lpsize, unsigned long pte)
1255 if (!printk_ratelimit())
1257 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1258 ea, access, current->comm);
1259 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1260 trap, vsid, ssize, psize, lpsize, pte);
1263 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1264 int psize, bool user_region)
1267 if (psize != get_paca_psize(ea)) {
1268 copy_mm_to_paca(mm);
1269 slb_flush_and_restore_bolted();
1271 } else if (get_paca()->vmalloc_sllp !=
1272 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1273 get_paca()->vmalloc_sllp =
1274 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1275 slb_vmalloc_update();
1282 * 1 - normal page fault
1283 * -1 - critical hash insertion error
1284 * -2 - access not permitted by subpage protection mechanism
1286 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1287 unsigned long access, unsigned long trap,
1288 unsigned long flags)
1291 enum ctx_state prev_state = exception_enter();
1296 int rc, user_region = 0;
1299 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1301 trace_hash_fault(ea, access, trap);
1303 /* Get region & vsid */
1304 switch (get_region_id(ea)) {
1305 case USER_REGION_ID:
1308 DBG_LOW(" user region with no mm !\n");
1312 psize = get_slice_psize(mm, ea);
1313 ssize = user_segment_size(ea);
1314 vsid = get_user_vsid(&mm->context, ea, ssize);
1316 case VMALLOC_REGION_ID:
1317 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1318 psize = mmu_vmalloc_psize;
1319 ssize = mmu_kernel_ssize;
1320 flags |= HPTE_USE_KERNEL_KEY;
1324 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1325 psize = mmu_io_psize;
1326 ssize = mmu_kernel_ssize;
1327 flags |= HPTE_USE_KERNEL_KEY;
1332 * Send the problem up to do_page_fault()
1337 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1341 DBG_LOW("Bad address!\n");
1347 if (pgdir == NULL) {
1352 /* Check CPU locality */
1353 if (user_region && mm_is_thread_local(mm))
1354 flags |= HPTE_LOCAL_UPDATE;
1356 #ifndef CONFIG_PPC_64K_PAGES
1358 * If we use 4K pages and our psize is not 4K, then we might
1359 * be hitting a special driver mapping, and need to align the
1360 * address before we fetch the PTE.
1362 * It could also be a hugepage mapping, in which case this is
1363 * not necessary, but it's not harmful, either.
1365 if (psize != MMU_PAGE_4K)
1366 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1367 #endif /* CONFIG_PPC_64K_PAGES */
1369 /* Get PTE and page size from page tables */
1370 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1371 if (ptep == NULL || !pte_present(*ptep)) {
1372 DBG_LOW(" no PTE !\n");
1378 * Add _PAGE_PRESENT to the required access perm. If there are parallel
1379 * updates to the pte that can possibly clear _PAGE_PTE, catch that too.
1381 * We can safely use the return pte address in rest of the function
1382 * because we do set H_PAGE_BUSY which prevents further updates to pte
1383 * from generic code.
1385 access |= _PAGE_PRESENT | _PAGE_PTE;
1388 * Pre-check access permissions (will be re-checked atomically
1389 * in __hash_page_XX but this pre-check is a fast path
1391 if (!check_pte_access(access, pte_val(*ptep))) {
1392 DBG_LOW(" no access !\n");
1399 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1400 trap, flags, ssize, psize);
1401 #ifdef CONFIG_HUGETLB_PAGE
1403 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1404 flags, ssize, hugeshift, psize);
1408 * if we have hugeshift, and is not transhuge with
1409 * hugetlb disabled, something is really wrong.
1415 if (current->mm == mm)
1416 check_paca_psize(ea, mm, psize, user_region);
1421 #ifndef CONFIG_PPC_64K_PAGES
1422 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1424 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1425 pte_val(*(ptep + PTRS_PER_PTE)));
1427 /* Do actual hashing */
1428 #ifdef CONFIG_PPC_64K_PAGES
1429 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1430 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1431 demote_segment_4k(mm, ea);
1432 psize = MMU_PAGE_4K;
1436 * If this PTE is non-cacheable and we have restrictions on
1437 * using non cacheable large pages, then we switch to 4k
1439 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1441 demote_segment_4k(mm, ea);
1442 psize = MMU_PAGE_4K;
1443 } else if (ea < VMALLOC_END) {
1445 * some driver did a non-cacheable mapping
1446 * in vmalloc space, so switch vmalloc
1449 printk(KERN_ALERT "Reducing vmalloc segment "
1450 "to 4kB pages because of "
1451 "non-cacheable mapping\n");
1452 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1453 copro_flush_all_slbs(mm);
1457 #endif /* CONFIG_PPC_64K_PAGES */
1459 if (current->mm == mm)
1460 check_paca_psize(ea, mm, psize, user_region);
1462 #ifdef CONFIG_PPC_64K_PAGES
1463 if (psize == MMU_PAGE_64K)
1464 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1467 #endif /* CONFIG_PPC_64K_PAGES */
1469 int spp = subpage_protection(mm, ea);
1473 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1478 * Dump some info in case of hash insertion failure, they should
1479 * never happen so it is really useful to know if/when they do
1482 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1483 psize, pte_val(*ptep));
1484 #ifndef CONFIG_PPC_64K_PAGES
1485 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1487 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1488 pte_val(*(ptep + PTRS_PER_PTE)));
1490 DBG_LOW(" -> rc=%d\n", rc);
1493 exception_exit(prev_state);
1496 EXPORT_SYMBOL_GPL(hash_page_mm);
1498 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1499 unsigned long dsisr)
1501 unsigned long flags = 0;
1502 struct mm_struct *mm = current->mm;
1504 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1505 (get_region_id(ea) == IO_REGION_ID))
1508 if (dsisr & DSISR_NOHPTE)
1509 flags |= HPTE_NOHPTE_UPDATE;
1511 return hash_page_mm(mm, ea, access, trap, flags);
1513 EXPORT_SYMBOL_GPL(hash_page);
1515 int do_hash_fault(struct pt_regs *regs, unsigned long ea, unsigned long dsisr)
1517 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1518 unsigned long flags = 0;
1519 struct mm_struct *mm;
1520 unsigned int region_id;
1523 if (unlikely(dsisr & (DSISR_BAD_FAULT_64S | DSISR_KEYFAULT)))
1527 * If we are in an "NMI" (e.g., an interrupt when soft-disabled), then
1528 * don't call hash_page, just fail the fault. This is required to
1529 * prevent re-entrancy problems in the hash code, namely perf
1530 * interrupts hitting while something holds H_PAGE_BUSY, and taking a
1531 * hash fault. See the comment in hash_preload().
1533 * We come here as a result of a DSI at a point where we don't want
1534 * to call hash_page, such as when we are accessing memory (possibly
1535 * user memory) inside a PMU interrupt that occurred while interrupts
1536 * were soft-disabled. We want to invoke the exception handler for
1537 * the access, or panic if there isn't a handler.
1539 if (unlikely(in_nmi())) {
1540 bad_page_fault(regs, ea, SIGSEGV);
1544 region_id = get_region_id(ea);
1545 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1550 if (dsisr & DSISR_NOHPTE)
1551 flags |= HPTE_NOHPTE_UPDATE;
1553 if (dsisr & DSISR_ISSTORE)
1554 access |= _PAGE_WRITE;
1556 * We set _PAGE_PRIVILEGED only when
1557 * kernel mode access kernel space.
1559 * _PAGE_PRIVILEGED is NOT set
1560 * 1) when kernel mode access user space
1561 * 2) user space access kernel space.
1563 access |= _PAGE_PRIVILEGED;
1564 if (user_mode(regs) || (region_id == USER_REGION_ID))
1565 access &= ~_PAGE_PRIVILEGED;
1567 if (regs->trap == 0x400)
1568 access |= _PAGE_EXEC;
1570 err = hash_page_mm(mm, ea, access, regs->trap, flags);
1571 if (unlikely(err < 0)) {
1572 // failed to instert a hash PTE due to an hypervisor error
1573 if (user_mode(regs)) {
1574 if (IS_ENABLED(CONFIG_PPC_SUBPAGE_PROT) && err == -2)
1575 _exception(SIGSEGV, regs, SEGV_ACCERR, ea);
1577 _exception(SIGBUS, regs, BUS_ADRERR, ea);
1579 bad_page_fault(regs, ea, SIGBUS);
1585 err = do_page_fault(regs, ea, dsisr);
1591 #ifdef CONFIG_PPC_MM_SLICES
1592 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1594 int psize = get_slice_psize(mm, ea);
1596 /* We only prefault standard pages for now */
1597 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1601 * Don't prefault if subpage protection is enabled for the EA.
1603 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1609 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1615 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea,
1616 bool is_exec, unsigned long trap)
1620 int rc, ssize, update_flags = 0;
1621 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1622 unsigned long flags;
1624 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1626 if (!should_hash_preload(mm, ea))
1629 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1630 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1632 /* Get Linux PTE if available */
1638 ssize = user_segment_size(ea);
1639 vsid = get_user_vsid(&mm->context, ea, ssize);
1643 #ifdef CONFIG_PPC_64K_PAGES
1644 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1645 * a 64K kernel), then we don't preload, hash_page() will take
1646 * care of it once we actually try to access the page.
1647 * That way we don't have to duplicate all of the logic for segment
1648 * page size demotion here
1649 * Called with PTL held, hence can be sure the value won't change in
1652 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1654 #endif /* CONFIG_PPC_64K_PAGES */
1657 * __hash_page_* must run with interrupts off, as it sets the
1658 * H_PAGE_BUSY bit. It's possible for perf interrupts to hit at any
1659 * time and may take a hash fault reading the user stack, see
1660 * read_user_stack_slow() in the powerpc/perf code.
1662 * If that takes a hash fault on the same page as we lock here, it
1663 * will bail out when seeing H_PAGE_BUSY set, and retry the access
1664 * leading to an infinite loop.
1666 * Disabling interrupts here does not prevent perf interrupts, but it
1667 * will prevent them taking hash faults (see the NMI test in
1668 * do_hash_page), then read_user_stack's copy_from_user_nofault will
1669 * fail and perf will fall back to read_user_stack_slow(), which
1670 * walks the Linux page tables.
1672 * Interrupts must also be off for the duration of the
1673 * mm_is_thread_local test and update, to prevent preempt running the
1674 * mm on another CPU (XXX: this may be racy vs kthread_use_mm).
1676 local_irq_save(flags);
1678 /* Is that local to this CPU ? */
1679 if (mm_is_thread_local(mm))
1680 update_flags |= HPTE_LOCAL_UPDATE;
1683 #ifdef CONFIG_PPC_64K_PAGES
1684 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1685 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1686 update_flags, ssize);
1688 #endif /* CONFIG_PPC_64K_PAGES */
1689 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1690 ssize, subpage_protection(mm, ea));
1692 /* Dump some info in case of hash insertion failure, they should
1693 * never happen so it is really useful to know if/when they do
1696 hash_failure_debug(ea, access, vsid, trap, ssize,
1697 mm_ctx_user_psize(&mm->context),
1698 mm_ctx_user_psize(&mm->context),
1701 local_irq_restore(flags);
1705 * This is called at the end of handling a user page fault, when the
1706 * fault has been handled by updating a PTE in the linux page tables.
1707 * We use it to preload an HPTE into the hash table corresponding to
1708 * the updated linux PTE.
1710 * This must always be called with the pte lock held.
1712 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1716 * We don't need to worry about _PAGE_PRESENT here because we are
1717 * called with either mm->page_table_lock held or ptl lock held
1722 if (radix_enabled())
1725 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1726 if (!pte_young(*ptep) || address >= TASK_SIZE)
1730 * We try to figure out if we are coming from an instruction
1731 * access fault and pass that down to __hash_page so we avoid
1732 * double-faulting on execution of fresh text. We have to test
1733 * for regs NULL since init will get here first thing at boot.
1735 * We also avoid filling the hash if not coming from a fault.
1738 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1750 hash_preload(vma->vm_mm, ptep, address, is_exec, trap);
1753 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1754 static inline void tm_flush_hash_page(int local)
1757 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1758 * page back to a block device w/PIO could pick up transactional data
1759 * (bad!) so we force an abort here. Before the sync the page will be
1760 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1761 * kernel uses a page from userspace without unmapping it first, it may
1762 * see the speculated version.
1764 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1765 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1767 tm_abort(TM_CAUSE_TLBI);
1771 static inline void tm_flush_hash_page(int local)
1777 * Return the global hash slot, corresponding to the given PTE, which contains
1780 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1781 int ssize, real_pte_t rpte, unsigned int subpg_index)
1783 unsigned long hash, gslot, hidx;
1785 hash = hpt_hash(vpn, shift, ssize);
1786 hidx = __rpte_to_hidx(rpte, subpg_index);
1787 if (hidx & _PTEIDX_SECONDARY)
1789 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1790 gslot += hidx & _PTEIDX_GROUP_IX;
1794 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1795 unsigned long flags)
1797 unsigned long index, shift, gslot;
1798 int local = flags & HPTE_LOCAL_UPDATE;
1800 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1801 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1802 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1803 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1805 * We use same base page size and actual psize, because we don't
1806 * use these functions for hugepage
1808 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1810 } pte_iterate_hashed_end();
1812 tm_flush_hash_page(local);
1815 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1816 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1817 pmd_t *pmdp, unsigned int psize, int ssize,
1818 unsigned long flags)
1820 int i, max_hpte_count, valid;
1821 unsigned long s_addr;
1822 unsigned char *hpte_slot_array;
1823 unsigned long hidx, shift, vpn, hash, slot;
1824 int local = flags & HPTE_LOCAL_UPDATE;
1826 s_addr = addr & HPAGE_PMD_MASK;
1827 hpte_slot_array = get_hpte_slot_array(pmdp);
1829 * IF we try to do a HUGE PTE update after a withdraw is done.
1830 * we will find the below NULL. This happens when we do
1833 if (!hpte_slot_array)
1836 if (mmu_hash_ops.hugepage_invalidate) {
1837 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1838 psize, ssize, local);
1842 * No bluk hpte removal support, invalidate each entry
1844 shift = mmu_psize_defs[psize].shift;
1845 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1846 for (i = 0; i < max_hpte_count; i++) {
1848 * 8 bits per each hpte entries
1849 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1851 valid = hpte_valid(hpte_slot_array, i);
1854 hidx = hpte_hash_index(hpte_slot_array, i);
1857 addr = s_addr + (i * (1ul << shift));
1858 vpn = hpt_vpn(addr, vsid, ssize);
1859 hash = hpt_hash(vpn, shift, ssize);
1860 if (hidx & _PTEIDX_SECONDARY)
1863 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1864 slot += hidx & _PTEIDX_GROUP_IX;
1865 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1866 MMU_PAGE_16M, ssize, local);
1869 tm_flush_hash_page(local);
1871 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1873 void flush_hash_range(unsigned long number, int local)
1875 if (mmu_hash_ops.flush_hash_range)
1876 mmu_hash_ops.flush_hash_range(number, local);
1879 struct ppc64_tlb_batch *batch =
1880 this_cpu_ptr(&ppc64_tlb_batch);
1882 for (i = 0; i < number; i++)
1883 flush_hash_page(batch->vpn[i], batch->pte[i],
1884 batch->psize, batch->ssize, local);
1888 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1889 unsigned long pa, unsigned long rflags,
1890 unsigned long vflags, int psize, int ssize)
1892 unsigned long hpte_group;
1896 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1898 /* Insert into the hash table, primary slot */
1899 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1900 psize, psize, ssize);
1902 /* Primary is full, try the secondary */
1903 if (unlikely(slot == -1)) {
1904 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1905 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1906 vflags | HPTE_V_SECONDARY,
1907 psize, psize, ssize);
1910 hpte_group = (hash & htab_hash_mask) *
1913 mmu_hash_ops.hpte_remove(hpte_group);
1921 #ifdef CONFIG_DEBUG_PAGEALLOC
1922 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1925 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1926 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1927 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL), HPTE_USE_KERNEL_KEY);
1930 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1932 /* Don't create HPTE entries for bad address */
1936 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1938 mmu_linear_psize, mmu_kernel_ssize);
1941 spin_lock(&linear_map_hash_lock);
1942 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1943 linear_map_hash_slots[lmi] = ret | 0x80;
1944 spin_unlock(&linear_map_hash_lock);
1947 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1949 unsigned long hash, hidx, slot;
1950 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1951 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1953 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1954 spin_lock(&linear_map_hash_lock);
1955 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1956 hidx = linear_map_hash_slots[lmi] & 0x7f;
1957 linear_map_hash_slots[lmi] = 0;
1958 spin_unlock(&linear_map_hash_lock);
1959 if (hidx & _PTEIDX_SECONDARY)
1961 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1962 slot += hidx & _PTEIDX_GROUP_IX;
1963 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1965 mmu_kernel_ssize, 0);
1968 void __kernel_map_pages(struct page *page, int numpages, int enable)
1970 unsigned long flags, vaddr, lmi;
1973 local_irq_save(flags);
1974 for (i = 0; i < numpages; i++, page++) {
1975 vaddr = (unsigned long)page_address(page);
1976 lmi = __pa(vaddr) >> PAGE_SHIFT;
1977 if (lmi >= linear_map_hash_count)
1980 kernel_map_linear_page(vaddr, lmi);
1982 kernel_unmap_linear_page(vaddr, lmi);
1984 local_irq_restore(flags);
1986 #endif /* CONFIG_DEBUG_PAGEALLOC */
1988 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1989 phys_addr_t first_memblock_size)
1992 * We don't currently support the first MEMBLOCK not mapping 0
1993 * physical on those processors
1995 BUG_ON(first_memblock_base != 0);
1998 * On virtualized systems the first entry is our RMA region aka VRMA,
1999 * non-virtualized 64-bit hash MMU systems don't have a limitation
2000 * on real mode access.
2002 * For guests on platforms before POWER9, we clamp the it limit to 1G
2003 * to avoid some funky things such as RTAS bugs etc...
2005 * On POWER9 we limit to 1TB in case the host erroneously told us that
2006 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
2007 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
2008 * for virtual real mode addressing and so it doesn't make sense to
2009 * have an area larger than 1TB as it can't be addressed.
2011 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
2012 ppc64_rma_size = first_memblock_size;
2013 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
2014 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
2016 ppc64_rma_size = min_t(u64, ppc64_rma_size,
2017 1UL << SID_SHIFT_1T);
2019 /* Finally limit subsequent allocations */
2020 memblock_set_current_limit(ppc64_rma_size);
2022 ppc64_rma_size = ULONG_MAX;
2026 #ifdef CONFIG_DEBUG_FS
2028 static int hpt_order_get(void *data, u64 *val)
2030 *val = ppc64_pft_size;
2034 static int hpt_order_set(void *data, u64 val)
2038 if (!mmu_hash_ops.resize_hpt)
2042 ret = mmu_hash_ops.resize_hpt(val);
2048 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2050 static int __init hash64_debugfs(void)
2052 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL,
2056 machine_device_initcall(pseries, hash64_debugfs);
2057 #endif /* CONFIG_DEBUG_FS */
2059 void __init print_system_hash_info(void)
2061 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2064 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);