1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * native hashtable management.
5 * SMP scalability work:
6 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
11 #include <linux/spinlock.h>
12 #include <linux/bitops.h>
14 #include <linux/processor.h>
15 #include <linux/threads.h>
16 #include <linux/smp.h>
17 #include <linux/pgtable.h>
19 #include <asm/machdep.h>
21 #include <asm/mmu_context.h>
22 #include <asm/trace.h>
24 #include <asm/cputable.h>
26 #include <asm/kexec.h>
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
30 #include <misc/cxl-base.h>
33 #define DBG_LOW(fmt...) udbg_printf(fmt)
35 #define DBG_LOW(fmt...)
39 #define HPTE_LOCK_BIT 3
41 #define HPTE_LOCK_BIT (56+3)
44 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
46 static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is)
50 rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
52 asm volatile("tlbiel %0" : : "r" (rb));
56 * tlbiel instruction for hash, set invalidation
57 * i.e., r=1 and is=01 or is=10 or is=11
59 static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is,
61 unsigned int ric, unsigned int prs)
65 unsigned int r = 0; /* hash format */
67 rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
68 rs = ((unsigned long)pid << PPC_BITLSHIFT(31));
70 asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)
71 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)
76 static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is)
80 asm volatile("ptesync": : :"memory");
82 for (set = 0; set < num_sets; set++)
83 tlbiel_hash_set_isa206(set, is);
85 ppc_after_tlbiel_barrier();
88 static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
92 asm volatile("ptesync": : :"memory");
95 * Flush the partition table cache if this is HV mode.
97 if (early_cpu_has_feature(CPU_FTR_HVMODE))
98 tlbiel_hash_set_isa300(0, is, 0, 2, 0);
101 * Now invalidate the process table cache. UPRT=0 HPT modes (what
102 * current hardware implements) do not use the process table, but
103 * add the flushes anyway.
105 * From ISA v3.0B p. 1078:
106 * The following forms are invalid.
107 * * PRS=1, R=0, and RIC!=2 (The only process-scoped
108 * HPT caching is of the Process Table.)
110 tlbiel_hash_set_isa300(0, is, 0, 2, 1);
113 * Then flush the sets of the TLB proper. Hash mode uses
114 * partition scoped TLB translations, which may be flushed
117 for (set = 0; set < num_sets; set++)
118 tlbiel_hash_set_isa300(set, is, 0, 0, 0);
120 ppc_after_tlbiel_barrier();
122 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");
125 void hash__tlbiel_all(unsigned int action)
130 case TLB_INVAL_SCOPE_GLOBAL:
133 case TLB_INVAL_SCOPE_LPID:
140 if (early_cpu_has_feature(CPU_FTR_ARCH_300))
141 tlbiel_all_isa300(POWER9_TLB_SETS_HASH, is);
142 else if (early_cpu_has_feature(CPU_FTR_ARCH_207S))
143 tlbiel_all_isa206(POWER8_TLB_SETS, is);
144 else if (early_cpu_has_feature(CPU_FTR_ARCH_206))
145 tlbiel_all_isa206(POWER7_TLB_SETS, is);
147 WARN(1, "%s called on pre-POWER7 CPU\n", __func__);
150 static inline unsigned long ___tlbie(unsigned long vpn, int psize,
151 int apsize, int ssize)
158 * We need 14 to 65 bits of va for a tlibe of 4K page
159 * With vpn we ignore the lower VPN_SHIFT bits already.
160 * And top two bits are already ignored because we can
161 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
164 va = vpn << VPN_SHIFT;
166 * clear top 16 bits of 64bit va, non SLS segment
167 * Older versions of the architecture (2.02 and earler) require the
168 * masking of the top 16 bits.
170 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
171 va &= ~(0xffffULL << 48);
175 /* clear out bits after (52) [0....52.....63] */
176 va &= ~((1ul << (64 - 52)) - 1);
178 sllp = get_sllp_encoding(apsize);
180 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
181 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
185 /* We need 14 to 14 + i bits of va */
186 penc = mmu_psize_defs[psize].penc[apsize];
187 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
192 * We don't need all the bits, but rest of the bits
193 * must be ignored by the processor.
194 * vpn cover upto 65 bits of va. (0...65) and we need
197 va |= (vpn & 0xfe); /* AVAL */
199 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
200 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
207 static inline void fixup_tlbie_vpn(unsigned long vpn, int psize,
208 int apsize, int ssize)
210 if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
211 /* Radix flush for a hash guest */
213 unsigned long rb,rs,prs,r,ric;
215 rb = PPC_BIT(52); /* IS = 2 */
216 rs = 0; /* lpid = 0 */
217 prs = 0; /* partition scoped */
218 r = 1; /* radix format */
219 ric = 0; /* RIC_FLSUH_TLB */
222 * Need the extra ptesync to make sure we don't
225 asm volatile("ptesync": : :"memory");
226 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
227 : : "r"(rb), "i"(r), "i"(prs),
228 "i"(ric), "r"(rs) : "memory");
232 if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
233 /* Need the extra ptesync to ensure we don't reorder tlbie*/
234 asm volatile("ptesync": : :"memory");
235 ___tlbie(vpn, psize, apsize, ssize);
239 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
243 rb = ___tlbie(vpn, psize, apsize, ssize);
244 trace_tlbie(0, 0, rb, 0, 0, 0, 0);
247 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
253 /* VPN_SHIFT can be atmost 12 */
254 va = vpn << VPN_SHIFT;
256 * clear top 16 bits of 64 bit va, non SLS segment
257 * Older versions of the architecture (2.02 and earler) require the
258 * masking of the top 16 bits.
260 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
261 va &= ~(0xffffULL << 48);
265 /* clear out bits after(52) [0....52.....63] */
266 va &= ~((1ul << (64 - 52)) - 1);
268 sllp = get_sllp_encoding(apsize);
270 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,0", %1)
271 : : "r" (va), "i" (CPU_FTR_ARCH_206)
275 /* We need 14 to 14 + i bits of va */
276 penc = mmu_psize_defs[psize].penc[apsize];
277 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
282 * We don't need all the bits, but rest of the bits
283 * must be ignored by the processor.
284 * vpn cover upto 65 bits of va. (0...65) and we need
289 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,1", %1)
290 : : "r" (va), "i" (CPU_FTR_ARCH_206)
294 trace_tlbie(0, 1, va, 0, 0, 0, 0);
298 static inline void tlbie(unsigned long vpn, int psize, int apsize,
299 int ssize, int local)
301 unsigned int use_local;
302 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
304 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
307 use_local = mmu_psize_defs[psize].tlbiel;
308 if (lock_tlbie && !use_local)
309 raw_spin_lock(&native_tlbie_lock);
310 asm volatile("ptesync": : :"memory");
312 __tlbiel(vpn, psize, apsize, ssize);
313 ppc_after_tlbiel_barrier();
315 __tlbie(vpn, psize, apsize, ssize);
316 fixup_tlbie_vpn(vpn, psize, apsize, ssize);
317 asm volatile("eieio; tlbsync; ptesync": : :"memory");
319 if (lock_tlbie && !use_local)
320 raw_spin_unlock(&native_tlbie_lock);
323 static inline void native_lock_hpte(struct hash_pte *hptep)
325 unsigned long *word = (unsigned long *)&hptep->v;
328 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
331 while(test_bit(HPTE_LOCK_BIT, word))
337 static inline void native_unlock_hpte(struct hash_pte *hptep)
339 unsigned long *word = (unsigned long *)&hptep->v;
341 clear_bit_unlock(HPTE_LOCK_BIT, word);
344 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
345 unsigned long pa, unsigned long rflags,
346 unsigned long vflags, int psize, int apsize, int ssize)
348 struct hash_pte *hptep = htab_address + hpte_group;
349 unsigned long hpte_v, hpte_r;
352 if (!(vflags & HPTE_V_BOLTED)) {
353 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
354 " rflags=%lx, vflags=%lx, psize=%d)\n",
355 hpte_group, vpn, pa, rflags, vflags, psize);
358 for (i = 0; i < HPTES_PER_GROUP; i++) {
359 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
360 /* retry with lock held */
361 native_lock_hpte(hptep);
362 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
364 native_unlock_hpte(hptep);
370 if (i == HPTES_PER_GROUP)
373 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
374 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
376 if (!(vflags & HPTE_V_BOLTED)) {
377 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
381 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
382 hpte_r = hpte_old_to_new_r(hpte_v, hpte_r);
383 hpte_v = hpte_old_to_new_v(hpte_v);
386 hptep->r = cpu_to_be64(hpte_r);
387 /* Guarantee the second dword is visible before the valid bit */
390 * Now set the first dword including the valid bit
391 * NOTE: this also unlocks the hpte
393 hptep->v = cpu_to_be64(hpte_v);
395 __asm__ __volatile__ ("ptesync" : : : "memory");
397 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
400 static long native_hpte_remove(unsigned long hpte_group)
402 struct hash_pte *hptep;
405 unsigned long hpte_v;
407 DBG_LOW(" remove(group=%lx)\n", hpte_group);
409 /* pick a random entry to start at */
410 slot_offset = mftb() & 0x7;
412 for (i = 0; i < HPTES_PER_GROUP; i++) {
413 hptep = htab_address + hpte_group + slot_offset;
414 hpte_v = be64_to_cpu(hptep->v);
416 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
417 /* retry with lock held */
418 native_lock_hpte(hptep);
419 hpte_v = be64_to_cpu(hptep->v);
420 if ((hpte_v & HPTE_V_VALID)
421 && !(hpte_v & HPTE_V_BOLTED))
423 native_unlock_hpte(hptep);
430 if (i == HPTES_PER_GROUP)
433 /* Invalidate the hpte. NOTE: this also unlocks it */
439 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
440 unsigned long vpn, int bpsize,
441 int apsize, int ssize, unsigned long flags)
443 struct hash_pte *hptep = htab_address + slot;
444 unsigned long hpte_v, want_v;
445 int ret = 0, local = 0;
447 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
449 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
450 vpn, want_v & HPTE_V_AVPN, slot, newpp);
452 hpte_v = hpte_get_old_v(hptep);
454 * We need to invalidate the TLB always because hpte_remove doesn't do
455 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
456 * random entry from it. When we do that we don't invalidate the TLB
457 * (hpte_remove) because we assume the old translation is still
458 * technically "valid".
460 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
461 DBG_LOW(" -> miss\n");
464 native_lock_hpte(hptep);
465 /* recheck with locks held */
466 hpte_v = hpte_get_old_v(hptep);
467 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
468 !(hpte_v & HPTE_V_VALID))) {
471 DBG_LOW(" -> hit\n");
472 /* Update the HPTE */
473 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
474 ~(HPTE_R_PPP | HPTE_R_N)) |
475 (newpp & (HPTE_R_PPP | HPTE_R_N |
478 native_unlock_hpte(hptep);
481 if (flags & HPTE_LOCAL_UPDATE)
484 * Ensure it is out of the tlb too if it is not a nohpte fault
486 if (!(flags & HPTE_NOHPTE_UPDATE))
487 tlbie(vpn, bpsize, apsize, ssize, local);
492 static long __native_hpte_find(unsigned long want_v, unsigned long slot)
494 struct hash_pte *hptep;
495 unsigned long hpte_v;
498 for (i = 0; i < HPTES_PER_GROUP; i++) {
500 hptep = htab_address + slot;
501 hpte_v = hpte_get_old_v(hptep);
502 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
511 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
513 unsigned long hpte_group;
514 unsigned long want_v;
518 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
519 want_v = hpte_encode_avpn(vpn, psize, ssize);
522 * We try to keep bolted entries always in primary hash
523 * But in some case we can find them in secondary too.
525 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
526 slot = __native_hpte_find(want_v, hpte_group);
528 /* Try in secondary */
529 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
530 slot = __native_hpte_find(want_v, hpte_group);
539 * Update the page protection bits. Intended to be used to create
540 * guard pages for kernel data structures on pages which are bolted
541 * in the HPT. Assumes pages being operated on will not be stolen.
543 * No need to lock here because we should be the only user.
545 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
546 int psize, int ssize)
551 struct hash_pte *hptep;
553 vsid = get_kernel_vsid(ea, ssize);
554 vpn = hpt_vpn(ea, vsid, ssize);
556 slot = native_hpte_find(vpn, psize, ssize);
558 panic("could not find page to bolt\n");
559 hptep = htab_address + slot;
561 /* Update the HPTE */
562 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
563 ~(HPTE_R_PPP | HPTE_R_N)) |
564 (newpp & (HPTE_R_PPP | HPTE_R_N)));
566 * Ensure it is out of the tlb too. Bolted entries base and
567 * actual page size will be same.
569 tlbie(vpn, psize, psize, ssize, 0);
573 * Remove a bolted kernel entry. Memory hotplug uses this.
575 * No need to lock here because we should be the only user.
577 static int native_hpte_removebolted(unsigned long ea, int psize, int ssize)
582 struct hash_pte *hptep;
584 vsid = get_kernel_vsid(ea, ssize);
585 vpn = hpt_vpn(ea, vsid, ssize);
587 slot = native_hpte_find(vpn, psize, ssize);
591 hptep = htab_address + slot;
593 VM_WARN_ON(!(be64_to_cpu(hptep->v) & HPTE_V_BOLTED));
595 /* Invalidate the hpte */
598 /* Invalidate the TLB */
599 tlbie(vpn, psize, psize, ssize, 0);
604 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
605 int bpsize, int apsize, int ssize, int local)
607 struct hash_pte *hptep = htab_address + slot;
608 unsigned long hpte_v;
609 unsigned long want_v;
612 local_irq_save(flags);
614 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
616 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
617 hpte_v = hpte_get_old_v(hptep);
619 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
620 native_lock_hpte(hptep);
621 /* recheck with locks held */
622 hpte_v = hpte_get_old_v(hptep);
624 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
625 /* Invalidate the hpte. NOTE: this also unlocks it */
628 native_unlock_hpte(hptep);
631 * We need to invalidate the TLB always because hpte_remove doesn't do
632 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
633 * random entry from it. When we do that we don't invalidate the TLB
634 * (hpte_remove) because we assume the old translation is still
635 * technically "valid".
637 tlbie(vpn, bpsize, apsize, ssize, local);
639 local_irq_restore(flags);
642 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
643 static void native_hugepage_invalidate(unsigned long vsid,
645 unsigned char *hpte_slot_array,
646 int psize, int ssize, int local)
649 struct hash_pte *hptep;
650 int actual_psize = MMU_PAGE_16M;
651 unsigned int max_hpte_count, valid;
652 unsigned long flags, s_addr = addr;
653 unsigned long hpte_v, want_v, shift;
654 unsigned long hidx, vpn = 0, hash, slot;
656 shift = mmu_psize_defs[psize].shift;
657 max_hpte_count = 1U << (PMD_SHIFT - shift);
659 local_irq_save(flags);
660 for (i = 0; i < max_hpte_count; i++) {
661 valid = hpte_valid(hpte_slot_array, i);
664 hidx = hpte_hash_index(hpte_slot_array, i);
667 addr = s_addr + (i * (1ul << shift));
668 vpn = hpt_vpn(addr, vsid, ssize);
669 hash = hpt_hash(vpn, shift, ssize);
670 if (hidx & _PTEIDX_SECONDARY)
673 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
674 slot += hidx & _PTEIDX_GROUP_IX;
676 hptep = htab_address + slot;
677 want_v = hpte_encode_avpn(vpn, psize, ssize);
678 hpte_v = hpte_get_old_v(hptep);
680 /* Even if we miss, we need to invalidate the TLB */
681 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
682 /* recheck with locks held */
683 native_lock_hpte(hptep);
684 hpte_v = hpte_get_old_v(hptep);
686 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
688 * Invalidate the hpte. NOTE: this also unlocks it
693 native_unlock_hpte(hptep);
696 * We need to do tlb invalidate for all the address, tlbie
697 * instruction compares entry_VA in tlb with the VA specified
700 tlbie(vpn, psize, actual_psize, ssize, local);
702 local_irq_restore(flags);
705 static void native_hugepage_invalidate(unsigned long vsid,
707 unsigned char *hpte_slot_array,
708 int psize, int ssize, int local)
710 WARN(1, "%s called without THP support\n", __func__);
714 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
715 int *psize, int *apsize, int *ssize, unsigned long *vpn)
717 unsigned long avpn, pteg, vpi;
718 unsigned long hpte_v = be64_to_cpu(hpte->v);
719 unsigned long hpte_r = be64_to_cpu(hpte->r);
720 unsigned long vsid, seg_off;
721 int size, a_size, shift;
722 /* Look at the 8 bit LP value */
723 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
725 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
726 hpte_v = hpte_new_to_old_v(hpte_v, hpte_r);
727 hpte_r = hpte_new_to_old_r(hpte_r);
729 if (!(hpte_v & HPTE_V_LARGE)) {
731 a_size = MMU_PAGE_4K;
733 size = hpte_page_sizes[lp] & 0xf;
734 a_size = hpte_page_sizes[lp] >> 4;
736 /* This works for all page sizes, and for 256M and 1T segments */
737 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
738 shift = mmu_psize_defs[size].shift;
740 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
741 pteg = slot / HPTES_PER_GROUP;
742 if (hpte_v & HPTE_V_SECONDARY)
746 case MMU_SEGSIZE_256M:
747 /* We only have 28 - 23 bits of seg_off in avpn */
748 seg_off = (avpn & 0x1f) << 23;
750 /* We can find more bits from the pteg value */
752 vpi = (vsid ^ pteg) & htab_hash_mask;
753 seg_off |= vpi << shift;
755 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
758 /* We only have 40 - 23 bits of seg_off in avpn */
759 seg_off = (avpn & 0x1ffff) << 23;
762 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
763 seg_off |= vpi << shift;
765 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
775 * clear all mappings on kexec. All cpus are in real mode (or they will
776 * be when they isi), and we are the only one left. We rely on our kernel
777 * mapping being 0xC0's and the hardware ignoring those two real bits.
779 * This must be called with interrupts disabled.
781 * Taking the native_tlbie_lock is unsafe here due to the possibility of
782 * lockdep being on. On pre POWER5 hardware, not taking the lock could
783 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
784 * gets called during boot before secondary CPUs have come up and during
785 * crashdump and all bets are off anyway.
787 * TODO: add batching support when enabled. remember, no dynamic memory here,
788 * although there is the control page available...
790 static notrace void native_hpte_clear(void)
792 unsigned long vpn = 0;
793 unsigned long slot, slots;
794 struct hash_pte *hptep = htab_address;
795 unsigned long hpte_v;
796 unsigned long pteg_count;
797 int psize, apsize, ssize;
799 pteg_count = htab_hash_mask + 1;
801 slots = pteg_count * HPTES_PER_GROUP;
803 for (slot = 0; slot < slots; slot++, hptep++) {
805 * we could lock the pte here, but we are the only cpu
806 * running, right? and for crash dump, we probably
807 * don't want to wait for a maybe bad cpu.
809 hpte_v = be64_to_cpu(hptep->v);
812 * Call __tlbie() here rather than tlbie() since we can't take the
815 if (hpte_v & HPTE_V_VALID) {
816 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
818 ___tlbie(vpn, psize, apsize, ssize);
822 asm volatile("eieio; tlbsync; ptesync":::"memory");
826 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
827 * the lock all the time
829 static void native_flush_hash_range(unsigned long number, int local)
831 unsigned long vpn = 0;
832 unsigned long hash, index, hidx, shift, slot;
833 struct hash_pte *hptep;
834 unsigned long hpte_v;
835 unsigned long want_v;
838 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
839 unsigned long psize = batch->psize;
840 int ssize = batch->ssize;
842 unsigned int use_local;
844 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
845 mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();
847 local_irq_save(flags);
849 for (i = 0; i < number; i++) {
853 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
854 hash = hpt_hash(vpn, shift, ssize);
855 hidx = __rpte_to_hidx(pte, index);
856 if (hidx & _PTEIDX_SECONDARY)
858 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
859 slot += hidx & _PTEIDX_GROUP_IX;
860 hptep = htab_address + slot;
861 want_v = hpte_encode_avpn(vpn, psize, ssize);
862 hpte_v = hpte_get_old_v(hptep);
864 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
866 /* lock and try again */
867 native_lock_hpte(hptep);
868 hpte_v = hpte_get_old_v(hptep);
870 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
871 native_unlock_hpte(hptep);
875 } pte_iterate_hashed_end();
879 asm volatile("ptesync":::"memory");
880 for (i = 0; i < number; i++) {
884 pte_iterate_hashed_subpages(pte, psize,
886 __tlbiel(vpn, psize, psize, ssize);
887 } pte_iterate_hashed_end();
889 ppc_after_tlbiel_barrier();
891 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
894 raw_spin_lock(&native_tlbie_lock);
896 asm volatile("ptesync":::"memory");
897 for (i = 0; i < number; i++) {
901 pte_iterate_hashed_subpages(pte, psize,
903 __tlbie(vpn, psize, psize, ssize);
904 } pte_iterate_hashed_end();
907 * Just do one more with the last used values.
909 fixup_tlbie_vpn(vpn, psize, psize, ssize);
910 asm volatile("eieio; tlbsync; ptesync":::"memory");
913 raw_spin_unlock(&native_tlbie_lock);
916 local_irq_restore(flags);
919 void __init hpte_init_native(void)
921 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
922 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
923 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
924 mmu_hash_ops.hpte_removebolted = native_hpte_removebolted;
925 mmu_hash_ops.hpte_insert = native_hpte_insert;
926 mmu_hash_ops.hpte_remove = native_hpte_remove;
927 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
928 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
929 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;