1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * This file contains low-level assembler routines for managing
13 * the PowerPC MMU hash table. (PPC 8xx processors don't use a
14 * hash table, so this file is not used on them.)
19 #include <asm/pgtable.h>
20 #include <asm/cputable.h>
21 #include <asm/ppc_asm.h>
22 #include <asm/thread_info.h>
23 #include <asm/asm-offsets.h>
24 #include <asm/export.h>
25 #include <asm/feature-fixups.h>
26 #include <asm/code-patching-asm.h>
33 #endif /* CONFIG_SMP */
36 * Load a PTE into the hash table, if possible.
37 * The address is in r4, and r3 contains an access flag:
38 * _PAGE_RW (0x002) if a write.
39 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
40 * SPRG_THREAD contains the physical address of the current task's thread.
42 * Returns to the caller if the access is illegal or there is no
43 * mapping for the address. Otherwise it places an appropriate PTE
44 * in the hash table and returns from the exception.
45 * Uses r0, r3 - r6, r8, r10, ctr, lr.
50 lis r8, (mmu_hash_lock - PAGE_OFFSET)@h
51 ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l
64 /* Get PTE (linux-style) and check access */
65 lis r0,KERNELBASE@h /* check if kernel address */
67 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
68 mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */
69 blt+ 112f /* assume user more likely */
70 lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
71 addi r5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
72 rlwimi r3,r9,32-14,31,31 /* MSR_PR -> _PAGE_USER */
74 #ifndef CONFIG_PTE_64BIT
75 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
76 lwz r8,0(r5) /* get pmd entry */
77 rlwinm. r8,r8,0,0,19 /* extract address of pte page */
79 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
80 lwzx r8,r8,r5 /* Get L1 entry */
81 rlwinm. r8,r8,0,0,20 /* extract pt base address */
84 beq- hash_page_out /* return if no mapping */
86 /* XXX it seems like the 601 will give a machine fault on the
87 rfi if its alignment is wrong (bottom 4 bits of address are
88 8 or 0xc) and we have had a not-taken conditional branch
89 to the address following the rfi. */
92 #ifndef CONFIG_PTE_64BIT
93 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
95 rlwimi r8,r4,23,20,28 /* compute pte address */
97 rlwinm r0,r3,6,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
98 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
101 * Update the linux PTE atomically. We do the lwarx up-front
102 * because almost always, there won't be a permission violation
103 * and there won't already be an HPTE, and thus we will have
104 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
106 * If PTE_64BIT is set, the low word is the flags word; use that
107 * word for locking since it contains all the interesting bits.
109 #if (PTE_FLAGS_OFFSET != 0)
110 addi r8,r8,PTE_FLAGS_OFFSET
113 lwarx r6,0,r8 /* get linux-style pte, flag word */
114 andc. r5,r3,r6 /* check access & ~permission */
116 bne- hash_page_out /* return if access not permitted */
120 or r5,r0,r6 /* set accessed/dirty bits */
121 #ifdef CONFIG_PTE_64BIT
123 subf r10,r6,r8 /* create false data dependency */
124 subi r10,r10,PTE_FLAGS_OFFSET
125 lwzx r10,r6,r10 /* Get upper PTE word */
127 lwz r10,-PTE_FLAGS_OFFSET(r8)
128 #endif /* CONFIG_SMP */
129 #endif /* CONFIG_PTE_64BIT */
130 stwcx. r5,0,r8 /* attempt to update PTE */
131 bne- retry /* retry if someone got there first */
133 mfsrin r3,r4 /* get segment reg for segment */
134 #ifndef CONFIG_VMAP_STACK
138 bl create_hpte /* add the hash table entry */
142 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
144 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
147 #ifdef CONFIG_VMAP_STACK
148 b fast_hash_page_return
150 /* Return from the exception */
155 b fast_exception_return
161 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
163 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
165 #endif /* CONFIG_SMP */
168 * Add an entry for a particular page to the hash table.
170 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
172 * We assume any necessary modifications to the pte (e.g. setting
173 * the accessed bit) have already been done and that there is actually
174 * a hash table in use (i.e. we're not on a 603).
176 _GLOBAL(add_hash_page)
180 /* Convert context and va to VSID */
181 mulli r3,r3,897*16 /* multiply context by context skew */
182 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
183 mulli r0,r0,0x111 /* multiply by ESID skew */
184 add r3,r3,r0 /* note create_hpte trims to 24 bits */
187 lwz r8,TASK_CPU(r2) /* to go in mmu_hash_lock */
189 #endif /* CONFIG_SMP */
192 * We disable interrupts here, even on UP, because we don't
193 * want to race with hash_page, and because we want the
194 * _PAGE_HASHPTE bit to be a reliable indication of whether
195 * the HPTE exists (or at least whether one did once).
196 * We also turn off the MMU for data accesses so that we
197 * we can't take a hash table miss (assuming the code is
198 * covered by a BAT). -- paulus
202 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */
203 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
209 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
210 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
211 10: lwarx r0,0,r6 /* take the mmu_hash_lock */
224 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
225 * If _PAGE_HASHPTE was already set, we don't replace the existing
226 * HPTE, so we just unlock and return.
229 #ifndef CONFIG_PTE_64BIT
230 rlwimi r8,r4,22,20,29
232 rlwimi r8,r4,23,20,28
233 addi r8,r8,PTE_FLAGS_OFFSET
236 andi. r0,r6,_PAGE_HASHPTE
237 bne 9f /* if HASHPTE already set, done */
238 #ifdef CONFIG_PTE_64BIT
240 subf r10,r6,r8 /* create false data dependency */
241 subi r10,r10,PTE_FLAGS_OFFSET
242 lwzx r10,r6,r10 /* Get upper PTE word */
244 lwz r10,-PTE_FLAGS_OFFSET(r8)
245 #endif /* CONFIG_SMP */
246 #endif /* CONFIG_PTE_64BIT */
247 ori r5,r6,_PAGE_HASHPTE
255 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
256 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
259 stw r0,0(r6) /* clear mmu_hash_lock */
262 /* reenable interrupts and DR */
272 * This routine adds a hardware PTE to the hash table.
273 * It is designed to be called with the MMU either on or off.
274 * r3 contains the VSID, r4 contains the virtual address,
275 * r5 contains the linux PTE, r6 contains the old value of the
276 * linux PTE (before setting _PAGE_HASHPTE). r10 contains the
277 * upper half of the PTE if CONFIG_PTE_64BIT.
278 * On SMP, the caller should have the mmu_hash_lock held.
279 * We assume that the caller has (or will) set the _PAGE_HASHPTE
280 * bit in the linux PTE in memory. The value passed in r6 should
281 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
282 * this routine will skip the search for an existing HPTE.
283 * This procedure modifies r0, r3 - r6, r8, cr0.
286 * For speed, 4 of the instructions get patched once the size and
287 * physical address of the hash table are known. These definitions
288 * of Hash_base and Hash_bits below are just an example.
290 Hash_base = 0xc0180000
291 Hash_bits = 12 /* e.g. 256kB hash table */
292 Hash_msk = (((1 << Hash_bits) - 1) * 64)
294 /* defines for the PTE format for 32-bit PPCs */
297 #define LG_PTEG_SIZE 6
303 #define PTE_V 0x80000000
304 #define TST_V(r) rlwinm. r,r,0,0,0
305 #define SET_V(r) oris r,r,PTE_V@h
306 #define CLR_V(r,t) rlwinm r,r,0,1,31
308 #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
309 #define HASH_RIGHT 31-LG_PTEG_SIZE
312 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
313 rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */
314 and r8,r5,r0 /* writable if _RW & _DIRTY */
315 rlwimi r5,r5,1,30,30 /* _PAGE_USER -> PP msb */
316 ori r8,r8,0xe04 /* clear out reserved bits */
317 andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */
319 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
320 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
321 #ifdef CONFIG_PTE_64BIT
322 /* Put the XPN bits into the PTE */
323 rlwimi r8,r10,8,20,22
324 rlwimi r8,r10,2,29,29
327 /* Construct the high word of the PPC-style PTE (r5) */
328 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
329 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
330 SET_V(r5) /* set V (valid) bit */
332 patch_site 0f, patch__hash_page_A0
333 patch_site 1f, patch__hash_page_A1
334 patch_site 2f, patch__hash_page_A2
335 /* Get the address of the primary PTE group in the hash table (r3) */
336 0: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
337 1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
338 2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
339 xor r3,r3,r0 /* make primary hash */
340 li r0,8 /* PTEs/group */
343 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
344 * if it is clear, meaning that the HPTE isn't there already...
346 andi. r6,r6,_PAGE_HASHPTE
347 beq+ 10f /* no PTE: go look for an empty slot */
350 lis r4, (htab_hash_searches - PAGE_OFFSET)@ha
351 lwz r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
352 addi r6,r6,1 /* count how many searches we do */
353 stw r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
355 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
357 addi r4,r3,-HPTE_SIZE
358 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
360 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
363 patch_site 0f, patch__hash_page_B
364 /* Search the secondary PTEG for a matching PTE */
365 ori r5,r5,PTE_H /* set H (secondary hash) bit */
366 0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
367 xori r4,r4,(-PTEG_SIZE & 0xffff)
368 addi r4,r4,-HPTE_SIZE
370 2: LDPTEu r6,HPTE_SIZE(r4)
374 xori r5,r5,PTE_H /* clear H bit again */
376 /* Search the primary PTEG for an empty slot */
378 addi r4,r3,-HPTE_SIZE /* search primary PTEG */
379 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
380 TST_V(r6) /* test valid bit */
381 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
384 /* update counter of times that the primary PTEG is full */
385 lis r4, (primary_pteg_full - PAGE_OFFSET)@ha
386 lwz r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
388 stw r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
390 patch_site 0f, patch__hash_page_C
391 /* Search the secondary PTEG for an empty slot */
392 ori r5,r5,PTE_H /* set H (secondary hash) bit */
393 0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
394 xori r4,r4,(-PTEG_SIZE & 0xffff)
395 addi r4,r4,-HPTE_SIZE
397 2: LDPTEu r6,HPTE_SIZE(r4)
401 xori r5,r5,PTE_H /* clear H bit again */
404 * Choose an arbitrary slot in the primary PTEG to overwrite.
405 * Since both the primary and secondary PTEGs are full, and we
406 * have no information that the PTEs in the primary PTEG are
407 * more important or useful than those in the secondary PTEG,
408 * and we know there is a definite (although small) speed
409 * advantage to putting the PTE in the primary PTEG, we always
410 * put the PTE in the primary PTEG.
412 * In addition, we skip any slot that is mapping kernel text in
413 * order to avoid a deadlock when not using BAT mappings if
414 * trying to hash in the kernel hash code itself after it has
415 * already taken the hash table lock. This works in conjunction
416 * with pre-faulting of the kernel text.
418 * If the hash table bucket is full of kernel text entries, we'll
419 * lockup here but that shouldn't happen
422 1: lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */
423 lwz r6, (next_slot - PAGE_OFFSET)@l(r4)
424 addi r6,r6,HPTE_SIZE /* search for candidate */
425 andi. r6,r6,7*HPTE_SIZE
426 stw r6,next_slot@l(r4)
428 LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */
431 ori r6,r6,etext@l /* get etext */
433 cmpl cr0,r0,r6 /* compare and try again */
437 /* Store PTE in PTEG */
441 STPTE r8,HPTE_SIZE/2(r4)
443 #else /* CONFIG_SMP */
445 * Between the tlbie above and updating the hash table entry below,
446 * another CPU could read the hash table entry and put it in its TLB.
448 * 1. using an empty slot
449 * 2. updating an earlier entry to change permissions (i.e. enable write)
450 * 3. taking over the PTE for an unrelated address
452 * In each case it doesn't really matter if the other CPUs have the old
453 * PTE in their TLB. So we don't need to bother with another tlbie here,
454 * which is convenient as we've overwritten the register that had the
455 * address. :-) The tlbie above is mainly to make sure that this CPU comes
456 * and gets the new PTE from the hash table.
458 * We do however have to make sure that the PTE is never in an invalid
459 * state with the V bit set.
463 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
467 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
470 STPTE r5,0(r4) /* finally set V bit in PTE */
471 #endif /* CONFIG_SMP */
473 sync /* make sure pte updates get to memory */
487 * Flush the entry for a particular page from the hash table.
489 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
492 * We assume that there is a hash table in use (Hash != 0).
494 _GLOBAL(flush_hash_pages)
496 * We disable interrupts here, even on UP, because we want
497 * the _PAGE_HASHPTE bit to be a reliable indication of
498 * whether the HPTE exists (or at least whether one did once).
499 * We also turn off the MMU for data accesses so that we
500 * we can't take a hash table miss (assuming the code is
501 * covered by a BAT). -- paulus
505 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
506 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
511 /* First find a PTE in the range that has _PAGE_HASHPTE set */
512 #ifndef CONFIG_PTE_64BIT
513 rlwimi r5,r4,22,20,29
515 rlwimi r5,r4,23,20,28
517 1: lwz r0,PTE_FLAGS_OFFSET(r5)
519 andi. r0,r0,_PAGE_HASHPTE
527 /* Convert context and va to VSID */
528 2: mulli r3,r3,897*16 /* multiply context by context skew */
529 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
530 mulli r0,r0,0x111 /* multiply by ESID skew */
531 add r3,r3,r0 /* note code below trims to 24 bits */
533 /* Construct the high word of the PPC-style PTE (r11) */
534 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
535 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
536 SET_V(r11) /* set V (valid) bit */
539 lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha
540 addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l
557 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
558 * already clear, we're done (for this pte). If not,
559 * clear it (atomically) and proceed. -- paulus.
561 #if (PTE_FLAGS_OFFSET != 0)
562 addi r5,r5,PTE_FLAGS_OFFSET
564 33: lwarx r8,0,r5 /* fetch the pte flags word */
565 andi. r0,r8,_PAGE_HASHPTE
566 beq 8f /* done if HASHPTE is already clear */
567 rlwinm r8,r8,0,~_PAGE_HASHPTE /* clear HASHPTE bit */
568 stwcx. r8,0,r5 /* update the pte */
571 patch_site 0f, patch__flush_hash_A0
572 patch_site 1f, patch__flush_hash_A1
573 patch_site 2f, patch__flush_hash_A2
574 /* Get the address of the primary PTE group in the hash table (r3) */
575 0: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
576 1: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
577 2: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
578 xor r8,r0,r8 /* make primary hash */
580 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
581 li r0,8 /* PTEs/group */
583 addi r12,r8,-HPTE_SIZE
584 1: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */
586 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
589 patch_site 0f, patch__flush_hash_B
590 /* Search the secondary PTEG for a matching PTE */
591 ori r11,r11,PTE_H /* set H (secondary hash) bit */
592 li r0,8 /* PTEs/group */
593 0: xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
594 xori r12,r12,(-PTEG_SIZE & 0xffff)
595 addi r12,r12,-HPTE_SIZE
597 2: LDPTEu r0,HPTE_SIZE(r12)
600 xori r11,r11,PTE_H /* clear H again */
601 bne- 4f /* should rarely fail to find it */
604 STPTE r0,0(r12) /* invalidate entry */
606 tlbie r4 /* in hw tlb too */
609 8: ble cr1,9f /* if all ptes checked */
613 lwz r0,0(r5) /* check next pte */
615 andi. r0,r0,_PAGE_HASHPTE
623 stw r0,0(r9) /* clear mmu_hash_lock */
630 EXPORT_SYMBOL(flush_hash_pages)
633 * Flush an entry from the TLB
641 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
642 rlwinm r0,r0,0,28,26 /* clear DR */
646 lis r9,mmu_hash_lock@h
647 ori r9,r9,mmu_hash_lock@l
659 stw r0,0(r9) /* clear mmu_hash_lock */
663 #else /* CONFIG_SMP */
666 #endif /* CONFIG_SMP */
670 * Flush the entire TLB. 603/603e only
673 #if defined(CONFIG_SMP)
678 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
679 rlwinm r0,r0,0,28,26 /* clear DR */
683 lis r9,mmu_hash_lock@h
684 ori r9,r9,mmu_hash_lock@l
691 #endif /* CONFIG_SMP */
703 stw r0,0(r9) /* clear mmu_hash_lock */
707 #endif /* CONFIG_SMP */