1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
16 #include <asm/disassemble.h>
18 extern char system_call_common[];
19 extern char system_call_vectored_emulate[];
22 /* Bits in SRR1 that are copied from MSR */
23 #define MSR_MASK 0xffffffff87c0ffffUL
25 #define MSR_MASK 0x87c0ffff
29 #define XER_SO 0x80000000U
30 #define XER_OV 0x40000000U
31 #define XER_CA 0x20000000U
32 #define XER_OV32 0x00080000U
33 #define XER_CA32 0x00040000U
36 #define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe))
41 * Functions in ldstfp.S
43 extern void get_fpr(int rn, double *p);
44 extern void put_fpr(int rn, const double *p);
45 extern void get_vr(int rn, __vector128 *p);
46 extern void put_vr(int rn, __vector128 *p);
47 extern void load_vsrn(int vsr, const void *p);
48 extern void store_vsrn(int vsr, void *p);
49 extern void conv_sp_to_dp(const float *sp, double *dp);
50 extern void conv_dp_to_sp(const double *dp, float *sp);
57 extern int do_lq(unsigned long ea, unsigned long *regs);
58 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
59 extern int do_lqarx(unsigned long ea, unsigned long *regs);
60 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
64 #ifdef __LITTLE_ENDIAN__
73 * Emulate the truncation of 64 bit values in 32-bit mode.
75 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
79 if ((msr & MSR_64BIT) == 0)
86 * Determine whether a conditional branch instruction would branch.
88 static nokprobe_inline int branch_taken(unsigned int instr,
89 const struct pt_regs *regs,
90 struct instruction_op *op)
92 unsigned int bo = (instr >> 21) & 0x1f;
96 /* decrement counter */
98 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
101 if ((bo & 0x10) == 0) {
102 /* check bit from CR */
103 bi = (instr >> 16) & 0x1f;
104 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
110 static nokprobe_inline long address_ok(struct pt_regs *regs,
111 unsigned long ea, int nb)
113 if (!user_mode(regs))
115 if (__access_ok(ea, nb))
117 if (__access_ok(ea, 1))
118 /* Access overlaps the end of the user region */
119 regs->dar = TASK_SIZE_MAX - 1;
126 * Calculate effective address for a D-form instruction
128 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
129 const struct pt_regs *regs)
134 ra = (instr >> 16) & 0x1f;
135 ea = (signed short) instr; /* sign-extend */
144 * Calculate effective address for a DS-form instruction
146 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
147 const struct pt_regs *regs)
152 ra = (instr >> 16) & 0x1f;
153 ea = (signed short) (instr & ~3); /* sign-extend */
161 * Calculate effective address for a DQ-form instruction
163 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
164 const struct pt_regs *regs)
169 ra = (instr >> 16) & 0x1f;
170 ea = (signed short) (instr & ~0xf); /* sign-extend */
176 #endif /* __powerpc64 */
179 * Calculate effective address for an X-form instruction
181 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
182 const struct pt_regs *regs)
187 ra = (instr >> 16) & 0x1f;
188 rb = (instr >> 11) & 0x1f;
197 * Calculate effective address for a MLS:D-form / 8LS:D-form
198 * prefixed instruction
200 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
202 const struct pt_regs *regs)
206 unsigned long ea, d0, d1, d;
208 prefix_r = GET_PREFIX_R(instr);
209 ra = GET_PREFIX_RA(suffix);
211 d0 = instr & 0x3ffff;
212 d1 = suffix & 0xffff;
216 * sign extend a 34 bit number
218 dd = (unsigned int)(d >> 2);
220 ea = (ea << 2) | (d & 0x3);
224 else if (!prefix_r && !ra)
225 ; /* Leave ea as is */
230 * (prefix_r && ra) is an invalid form. Should already be
231 * checked for by caller!
238 * Return the largest power of 2, not greater than sizeof(unsigned long),
239 * such that x is a multiple of it.
241 static nokprobe_inline unsigned long max_align(unsigned long x)
243 x |= sizeof(unsigned long);
244 return x & -x; /* isolates rightmost bit */
247 static nokprobe_inline unsigned long byterev_2(unsigned long x)
249 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
252 static nokprobe_inline unsigned long byterev_4(unsigned long x)
254 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
255 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
259 static nokprobe_inline unsigned long byterev_8(unsigned long x)
261 return (byterev_4(x) << 32) | byterev_4(x >> 32);
265 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
269 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
272 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
276 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
279 unsigned long *up = (unsigned long *)ptr;
281 tmp = byterev_8(up[0]);
282 up[0] = byterev_8(up[1]);
287 unsigned long *up = (unsigned long *)ptr;
290 tmp = byterev_8(up[0]);
291 up[0] = byterev_8(up[3]);
293 tmp = byterev_8(up[2]);
294 up[2] = byterev_8(up[1]);
305 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
306 unsigned long ea, int nb,
307 struct pt_regs *regs)
314 err = __get_user(x, (unsigned char __user *) ea);
317 err = __get_user(x, (unsigned short __user *) ea);
320 err = __get_user(x, (unsigned int __user *) ea);
324 err = __get_user(x, (unsigned long __user *) ea);
336 * Copy from userspace to a buffer, using the largest possible
337 * aligned accesses, up to sizeof(long).
339 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
340 struct pt_regs *regs)
345 for (; nb > 0; nb -= c) {
351 err = __get_user(*dest, (unsigned char __user *) ea);
354 err = __get_user(*(u16 *)dest,
355 (unsigned short __user *) ea);
358 err = __get_user(*(u32 *)dest,
359 (unsigned int __user *) ea);
363 err = __get_user(*(unsigned long *)dest,
364 (unsigned long __user *) ea);
378 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
379 unsigned long ea, int nb,
380 struct pt_regs *regs)
384 u8 b[sizeof(unsigned long)];
390 i = IS_BE ? sizeof(unsigned long) - nb : 0;
391 err = copy_mem_in(&u.b[i], ea, nb, regs);
398 * Read memory at address ea for nb bytes, return 0 for success
399 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
400 * If nb < sizeof(long), the result is right-justified on BE systems.
402 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
403 struct pt_regs *regs)
405 if (!address_ok(regs, ea, nb))
407 if ((ea & (nb - 1)) == 0)
408 return read_mem_aligned(dest, ea, nb, regs);
409 return read_mem_unaligned(dest, ea, nb, regs);
411 NOKPROBE_SYMBOL(read_mem);
413 static nokprobe_inline int write_mem_aligned(unsigned long val,
414 unsigned long ea, int nb,
415 struct pt_regs *regs)
421 err = __put_user(val, (unsigned char __user *) ea);
424 err = __put_user(val, (unsigned short __user *) ea);
427 err = __put_user(val, (unsigned int __user *) ea);
431 err = __put_user(val, (unsigned long __user *) ea);
441 * Copy from a buffer to userspace, using the largest possible
442 * aligned accesses, up to sizeof(long).
444 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
445 struct pt_regs *regs)
450 for (; nb > 0; nb -= c) {
456 err = __put_user(*dest, (unsigned char __user *) ea);
459 err = __put_user(*(u16 *)dest,
460 (unsigned short __user *) ea);
463 err = __put_user(*(u32 *)dest,
464 (unsigned int __user *) ea);
468 err = __put_user(*(unsigned long *)dest,
469 (unsigned long __user *) ea);
483 static nokprobe_inline int write_mem_unaligned(unsigned long val,
484 unsigned long ea, int nb,
485 struct pt_regs *regs)
489 u8 b[sizeof(unsigned long)];
494 i = IS_BE ? sizeof(unsigned long) - nb : 0;
495 return copy_mem_out(&u.b[i], ea, nb, regs);
499 * Write memory at address ea for nb bytes, return 0 for success
500 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
502 static int write_mem(unsigned long val, unsigned long ea, int nb,
503 struct pt_regs *regs)
505 if (!address_ok(regs, ea, nb))
507 if ((ea & (nb - 1)) == 0)
508 return write_mem_aligned(val, ea, nb, regs);
509 return write_mem_unaligned(val, ea, nb, regs);
511 NOKPROBE_SYMBOL(write_mem);
513 #ifdef CONFIG_PPC_FPU
515 * These access either the real FP register or the image in the
516 * thread_struct, depending on regs->msr & MSR_FP.
518 static int do_fp_load(struct instruction_op *op, unsigned long ea,
519 struct pt_regs *regs, bool cross_endian)
528 u8 b[2 * sizeof(double)];
531 nb = GETSIZE(op->type);
532 if (!address_ok(regs, ea, nb))
535 err = copy_mem_in(u.b, ea, nb, regs);
538 if (unlikely(cross_endian)) {
539 do_byte_reverse(u.b, min(nb, 8));
541 do_byte_reverse(&u.b[8], 8);
545 if (op->type & FPCONV)
546 conv_sp_to_dp(&u.f, &u.d[0]);
547 else if (op->type & SIGNEXT)
552 if (regs->msr & MSR_FP)
553 put_fpr(rn, &u.d[0]);
555 current->thread.TS_FPR(rn) = u.l[0];
559 if (regs->msr & MSR_FP)
560 put_fpr(rn, &u.d[1]);
562 current->thread.TS_FPR(rn) = u.l[1];
567 NOKPROBE_SYMBOL(do_fp_load);
569 static int do_fp_store(struct instruction_op *op, unsigned long ea,
570 struct pt_regs *regs, bool cross_endian)
578 u8 b[2 * sizeof(double)];
581 nb = GETSIZE(op->type);
582 if (!address_ok(regs, ea, nb))
586 if (regs->msr & MSR_FP)
587 get_fpr(rn, &u.d[0]);
589 u.l[0] = current->thread.TS_FPR(rn);
591 if (op->type & FPCONV)
592 conv_dp_to_sp(&u.d[0], &u.f);
598 if (regs->msr & MSR_FP)
599 get_fpr(rn, &u.d[1]);
601 u.l[1] = current->thread.TS_FPR(rn);
604 if (unlikely(cross_endian)) {
605 do_byte_reverse(u.b, min(nb, 8));
607 do_byte_reverse(&u.b[8], 8);
609 return copy_mem_out(u.b, ea, nb, regs);
611 NOKPROBE_SYMBOL(do_fp_store);
614 #ifdef CONFIG_ALTIVEC
615 /* For Altivec/VMX, no need to worry about alignment */
616 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
617 int size, struct pt_regs *regs,
623 u8 b[sizeof(__vector128)];
626 if (!address_ok(regs, ea & ~0xfUL, 16))
628 /* align to multiple of size */
630 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
633 if (unlikely(cross_endian))
634 do_byte_reverse(&u.b[ea & 0xf], size);
636 if (regs->msr & MSR_VEC)
639 current->thread.vr_state.vr[rn] = u.v;
644 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
645 int size, struct pt_regs *regs,
650 u8 b[sizeof(__vector128)];
653 if (!address_ok(regs, ea & ~0xfUL, 16))
655 /* align to multiple of size */
659 if (regs->msr & MSR_VEC)
662 u.v = current->thread.vr_state.vr[rn];
664 if (unlikely(cross_endian))
665 do_byte_reverse(&u.b[ea & 0xf], size);
666 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
668 #endif /* CONFIG_ALTIVEC */
671 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
672 int reg, bool cross_endian)
676 if (!address_ok(regs, ea, 16))
678 /* if aligned, should be atomic */
679 if ((ea & 0xf) == 0) {
680 err = do_lq(ea, ®s->gpr[reg]);
682 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
684 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
686 if (!err && unlikely(cross_endian))
687 do_byte_reverse(®s->gpr[reg], 16);
691 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
692 int reg, bool cross_endian)
695 unsigned long vals[2];
697 if (!address_ok(regs, ea, 16))
699 vals[0] = regs->gpr[reg];
700 vals[1] = regs->gpr[reg + 1];
701 if (unlikely(cross_endian))
702 do_byte_reverse(vals, 16);
704 /* if aligned, should be atomic */
706 return do_stq(ea, vals[0], vals[1]);
708 err = write_mem(vals[IS_LE], ea, 8, regs);
710 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
713 #endif /* __powerpc64 */
716 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
717 const void *mem, bool rev)
721 const unsigned int *wp;
722 const unsigned short *hp;
723 const unsigned char *bp;
725 size = GETSIZE(op->type);
726 reg->d[0] = reg->d[1] = 0;
728 switch (op->element_size) {
732 /* whole vector; lxv[x] or lxvl[l] */
735 memcpy(reg, mem, size);
736 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
739 do_byte_reverse(reg, size);
742 /* scalar loads, lxvd2x, lxvdsx */
743 read_size = (size >= 8) ? 8 : size;
744 i = IS_LE ? 8 : 8 - read_size;
745 memcpy(®->b[i], mem, read_size);
747 do_byte_reverse(®->b[i], 8);
749 if (op->type & SIGNEXT) {
750 /* size == 4 is the only case here */
751 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
752 } else if (op->vsx_flags & VSX_FPCONV) {
754 conv_sp_to_dp(®->fp[1 + IS_LE],
760 unsigned long v = *(unsigned long *)(mem + 8);
761 reg->d[IS_BE] = !rev ? v : byterev_8(v);
762 } else if (op->vsx_flags & VSX_SPLAT)
763 reg->d[IS_BE] = reg->d[IS_LE];
769 for (j = 0; j < size / 4; ++j) {
770 i = IS_LE ? 3 - j : j;
771 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
773 if (op->vsx_flags & VSX_SPLAT) {
774 u32 val = reg->w[IS_LE ? 3 : 0];
776 i = IS_LE ? 3 - j : j;
784 for (j = 0; j < size / 2; ++j) {
785 i = IS_LE ? 7 - j : j;
786 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
792 for (j = 0; j < size; ++j) {
793 i = IS_LE ? 15 - j : j;
799 EXPORT_SYMBOL_GPL(emulate_vsx_load);
800 NOKPROBE_SYMBOL(emulate_vsx_load);
802 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
805 int size, write_size;
812 size = GETSIZE(op->type);
814 switch (op->element_size) {
820 /* reverse 32 bytes */
821 union vsx_reg buf32[2];
822 buf32[0].d[0] = byterev_8(reg[1].d[1]);
823 buf32[0].d[1] = byterev_8(reg[1].d[0]);
824 buf32[1].d[0] = byterev_8(reg[0].d[1]);
825 buf32[1].d[1] = byterev_8(reg[0].d[0]);
826 memcpy(mem, buf32, size);
828 memcpy(mem, reg, size);
832 /* stxv, stxvx, stxvl, stxvll */
835 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
838 /* reverse 16 bytes */
839 buf.d[0] = byterev_8(reg->d[1]);
840 buf.d[1] = byterev_8(reg->d[0]);
843 memcpy(mem, reg, size);
846 /* scalar stores, stxvd2x */
847 write_size = (size >= 8) ? 8 : size;
848 i = IS_LE ? 8 : 8 - write_size;
849 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
850 buf.d[0] = buf.d[1] = 0;
852 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
856 memcpy(mem, ®->b[i], write_size);
858 memcpy(mem + 8, ®->d[IS_BE], 8);
860 do_byte_reverse(mem, write_size);
862 do_byte_reverse(mem + 8, 8);
868 for (j = 0; j < size / 4; ++j) {
869 i = IS_LE ? 3 - j : j;
870 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
876 for (j = 0; j < size / 2; ++j) {
877 i = IS_LE ? 7 - j : j;
878 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
884 for (j = 0; j < size; ++j) {
885 i = IS_LE ? 15 - j : j;
891 EXPORT_SYMBOL_GPL(emulate_vsx_store);
892 NOKPROBE_SYMBOL(emulate_vsx_store);
894 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
895 unsigned long ea, struct pt_regs *regs,
899 int i, j, nr_vsx_regs;
901 union vsx_reg buf[2];
902 int size = GETSIZE(op->type);
904 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
907 nr_vsx_regs = size / sizeof(__vector128);
908 emulate_vsx_load(op, buf, mem, cross_endian);
911 /* FP regs + extensions */
912 if (regs->msr & MSR_FP) {
913 for (i = 0; i < nr_vsx_regs; i++) {
914 j = IS_LE ? nr_vsx_regs - i - 1 : i;
915 load_vsrn(reg + i, &buf[j].v);
918 for (i = 0; i < nr_vsx_regs; i++) {
919 j = IS_LE ? nr_vsx_regs - i - 1 : i;
920 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
921 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
925 if (regs->msr & MSR_VEC) {
926 for (i = 0; i < nr_vsx_regs; i++) {
927 j = IS_LE ? nr_vsx_regs - i - 1 : i;
928 load_vsrn(reg + i, &buf[j].v);
931 for (i = 0; i < nr_vsx_regs; i++) {
932 j = IS_LE ? nr_vsx_regs - i - 1 : i;
933 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
941 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
942 unsigned long ea, struct pt_regs *regs,
946 int i, j, nr_vsx_regs;
948 union vsx_reg buf[2];
949 int size = GETSIZE(op->type);
951 if (!address_ok(regs, ea, size))
954 nr_vsx_regs = size / sizeof(__vector128);
957 /* FP regs + extensions */
958 if (regs->msr & MSR_FP) {
959 for (i = 0; i < nr_vsx_regs; i++) {
960 j = IS_LE ? nr_vsx_regs - i - 1 : i;
961 store_vsrn(reg + i, &buf[j].v);
964 for (i = 0; i < nr_vsx_regs; i++) {
965 j = IS_LE ? nr_vsx_regs - i - 1 : i;
966 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
967 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
971 if (regs->msr & MSR_VEC) {
972 for (i = 0; i < nr_vsx_regs; i++) {
973 j = IS_LE ? nr_vsx_regs - i - 1 : i;
974 store_vsrn(reg + i, &buf[j].v);
977 for (i = 0; i < nr_vsx_regs; i++) {
978 j = IS_LE ? nr_vsx_regs - i - 1 : i;
979 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
984 emulate_vsx_store(op, buf, mem, cross_endian);
985 return copy_mem_out(mem, ea, size, regs);
987 #endif /* CONFIG_VSX */
989 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
992 unsigned long i, size;
995 size = ppc64_caches.l1d.block_size;
996 if (!(regs->msr & MSR_64BIT))
999 size = L1_CACHE_BYTES;
1002 if (!address_ok(regs, ea, size))
1004 for (i = 0; i < size; i += sizeof(long)) {
1005 err = __put_user(0, (unsigned long __user *) (ea + i));
1013 NOKPROBE_SYMBOL(emulate_dcbz);
1015 #define __put_user_asmx(x, addr, err, op, cr) \
1016 __asm__ __volatile__( \
1017 "1: " op " %2,0,%3\n" \
1020 ".section .fixup,\"ax\"\n" \
1025 : "=r" (err), "=r" (cr) \
1026 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1028 #define __get_user_asmx(x, addr, err, op) \
1029 __asm__ __volatile__( \
1030 "1: "op" %1,0,%2\n" \
1032 ".section .fixup,\"ax\"\n" \
1037 : "=r" (err), "=r" (x) \
1038 : "r" (addr), "i" (-EFAULT), "0" (err))
1040 #define __cacheop_user_asmx(addr, err, op) \
1041 __asm__ __volatile__( \
1044 ".section .fixup,\"ax\"\n" \
1050 : "r" (addr), "i" (-EFAULT), "0" (err))
1052 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1053 struct instruction_op *op)
1058 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1059 #ifdef __powerpc64__
1060 if (!(regs->msr & MSR_64BIT))
1064 op->ccval |= 0x80000000;
1066 op->ccval |= 0x40000000;
1068 op->ccval |= 0x20000000;
1071 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1073 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1075 op->xerval |= XER_CA32;
1077 op->xerval &= ~XER_CA32;
1081 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1082 struct instruction_op *op, int rd,
1083 unsigned long val1, unsigned long val2,
1084 unsigned long carry_in)
1086 unsigned long val = val1 + val2;
1090 op->type = COMPUTE + SETREG + SETXER;
1093 #ifdef __powerpc64__
1094 if (!(regs->msr & MSR_64BIT)) {
1095 val = (unsigned int) val;
1096 val1 = (unsigned int) val1;
1099 op->xerval = regs->xer;
1100 if (val < val1 || (carry_in && val == val1))
1101 op->xerval |= XER_CA;
1103 op->xerval &= ~XER_CA;
1105 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1106 (carry_in && (unsigned int)val == (unsigned int)val1));
1109 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1110 struct instruction_op *op,
1111 long v1, long v2, int crfld)
1113 unsigned int crval, shift;
1115 op->type = COMPUTE + SETCC;
1116 crval = (regs->xer >> 31) & 1; /* get SO bit */
1123 shift = (7 - crfld) * 4;
1124 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1127 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1128 struct instruction_op *op,
1130 unsigned long v2, int crfld)
1132 unsigned int crval, shift;
1134 op->type = COMPUTE + SETCC;
1135 crval = (regs->xer >> 31) & 1; /* get SO bit */
1142 shift = (7 - crfld) * 4;
1143 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1146 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1147 struct instruction_op *op,
1148 unsigned long v1, unsigned long v2)
1150 unsigned long long out_val, mask;
1154 for (i = 0; i < 8; i++) {
1155 mask = 0xffUL << (i * 8);
1156 if ((v1 & mask) == (v2 & mask))
1163 * The size parameter is used to adjust the equivalent popcnt instruction.
1164 * popcntb = 8, popcntw = 32, popcntd = 64
1166 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1167 struct instruction_op *op,
1168 unsigned long v1, int size)
1170 unsigned long long out = v1;
1172 out -= (out >> 1) & 0x5555555555555555ULL;
1173 out = (0x3333333333333333ULL & out) +
1174 (0x3333333333333333ULL & (out >> 2));
1175 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1177 if (size == 8) { /* popcntb */
1183 if (size == 32) { /* popcntw */
1184 op->val = out & 0x0000003f0000003fULL;
1188 out = (out + (out >> 32)) & 0x7f;
1189 op->val = out; /* popcntd */
1193 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1194 struct instruction_op *op,
1195 unsigned long v1, unsigned long v2)
1197 unsigned char perm, idx;
1201 for (i = 0; i < 8; i++) {
1202 idx = (v1 >> (i * 8)) & 0xff;
1204 if (v2 & PPC_BIT(idx))
1209 #endif /* CONFIG_PPC64 */
1211 * The size parameter adjusts the equivalent prty instruction.
1212 * prtyw = 32, prtyd = 64
1214 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1215 struct instruction_op *op,
1216 unsigned long v, int size)
1218 unsigned long long res = v ^ (v >> 8);
1221 if (size == 32) { /* prtyw */
1222 op->val = res & 0x0000000100000001ULL;
1227 op->val = res & 1; /*prtyd */
1230 static nokprobe_inline int trap_compare(long v1, long v2)
1240 if ((unsigned long)v1 < (unsigned long)v2)
1242 else if ((unsigned long)v1 > (unsigned long)v2)
1248 * Elements of 32-bit rotate and mask instructions.
1250 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1251 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1252 #ifdef __powerpc64__
1253 #define MASK64_L(mb) (~0UL >> (mb))
1254 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1255 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1256 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1258 #define DATA32(x) (x)
1260 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1263 * Decode an instruction, and return information about it in *op
1264 * without changing *regs.
1265 * Integer arithmetic and logical instructions, branches, and barrier
1266 * instructions can be emulated just using the information in *op.
1268 * Return value is 1 if the instruction can be emulated just by
1269 * updating *regs with the information in *op, -1 if we need the
1270 * GPRs but *regs doesn't contain the full register set, or 0
1273 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1274 struct ppc_inst instr)
1277 unsigned int suffixopcode, prefixtype, prefix_r;
1279 unsigned int opcode, ra, rb, rc, rd, spr, u;
1280 unsigned long int imm;
1281 unsigned long int val, val2;
1282 unsigned int mb, me, sh;
1283 unsigned int word, suffix;
1286 word = ppc_inst_val(instr);
1287 suffix = ppc_inst_suffix(instr);
1291 opcode = ppc_inst_primary_opcode(instr);
1295 imm = (signed short)(word & 0xfffc);
1296 if ((word & 2) == 0)
1298 op->val = truncate_if_32bit(regs->msr, imm);
1301 if (branch_taken(word, regs, op))
1302 op->type |= BRTAKEN;
1306 if ((word & 0xfe2) == 2)
1308 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1309 (word & 0xfe3) == 1)
1310 op->type = SYSCALL_VECTORED_0;
1316 op->type = BRANCH | BRTAKEN;
1317 imm = word & 0x03fffffc;
1318 if (imm & 0x02000000)
1320 if ((word & 2) == 0)
1322 op->val = truncate_if_32bit(regs->msr, imm);
1327 switch ((word >> 1) & 0x3ff) {
1329 op->type = COMPUTE + SETCC;
1330 rd = 7 - ((word >> 23) & 0x7);
1331 ra = 7 - ((word >> 18) & 0x7);
1334 val = (regs->ccr >> ra) & 0xf;
1335 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1339 case 528: /* bcctr */
1341 imm = (word & 0x400)? regs->ctr: regs->link;
1342 op->val = truncate_if_32bit(regs->msr, imm);
1345 if (branch_taken(word, regs, op))
1346 op->type |= BRTAKEN;
1349 case 18: /* rfid, scary */
1350 if (regs->msr & MSR_PR)
1355 case 150: /* isync */
1356 op->type = BARRIER | BARRIER_ISYNC;
1359 case 33: /* crnor */
1360 case 129: /* crandc */
1361 case 193: /* crxor */
1362 case 225: /* crnand */
1363 case 257: /* crand */
1364 case 289: /* creqv */
1365 case 417: /* crorc */
1366 case 449: /* cror */
1367 op->type = COMPUTE + SETCC;
1368 ra = (word >> 16) & 0x1f;
1369 rb = (word >> 11) & 0x1f;
1370 rd = (word >> 21) & 0x1f;
1371 ra = (regs->ccr >> (31 - ra)) & 1;
1372 rb = (regs->ccr >> (31 - rb)) & 1;
1373 val = (word >> (6 + ra * 2 + rb)) & 1;
1374 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1380 switch ((word >> 1) & 0x3ff) {
1381 case 598: /* sync */
1382 op->type = BARRIER + BARRIER_SYNC;
1383 #ifdef __powerpc64__
1384 switch ((word >> 21) & 3) {
1385 case 1: /* lwsync */
1386 op->type = BARRIER + BARRIER_LWSYNC;
1388 case 2: /* ptesync */
1389 op->type = BARRIER + BARRIER_PTESYNC;
1395 case 854: /* eieio */
1396 op->type = BARRIER + BARRIER_EIEIO;
1402 /* Following cases refer to regs->gpr[], so we need all regs */
1403 if (!FULL_REGS(regs))
1406 rd = (word >> 21) & 0x1f;
1407 ra = (word >> 16) & 0x1f;
1408 rb = (word >> 11) & 0x1f;
1409 rc = (word >> 6) & 0x1f;
1412 #ifdef __powerpc64__
1414 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1417 prefix_r = GET_PREFIX_R(word);
1418 ra = GET_PREFIX_RA(suffix);
1419 rd = (suffix >> 21) & 0x1f;
1421 op->val = regs->gpr[rd];
1422 suffixopcode = get_op(suffix);
1423 prefixtype = (word >> 24) & 0x3;
1424 switch (prefixtype) {
1428 switch (suffixopcode) {
1429 case 14: /* paddi */
1430 op->type = COMPUTE | PREFIXED;
1431 op->val = mlsd_8lsd_ea(word, suffix, regs);
1437 if (rd & trap_compare(regs->gpr[ra], (short) word))
1442 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1446 #ifdef __powerpc64__
1448 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1451 switch (word & 0x3f) {
1452 case 48: /* maddhd */
1453 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1454 "=r" (op->val) : "r" (regs->gpr[ra]),
1455 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1458 case 49: /* maddhdu */
1459 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1460 "=r" (op->val) : "r" (regs->gpr[ra]),
1461 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1464 case 51: /* maddld */
1465 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1466 "=r" (op->val) : "r" (regs->gpr[ra]),
1467 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1472 * There are other instructions from ISA 3.0 with the same
1473 * primary opcode which do not have emulation support yet.
1479 op->val = regs->gpr[ra] * (short) word;
1482 case 8: /* subfic */
1484 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1487 case 10: /* cmpli */
1488 imm = (unsigned short) word;
1489 val = regs->gpr[ra];
1490 #ifdef __powerpc64__
1492 val = (unsigned int) val;
1494 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1499 val = regs->gpr[ra];
1500 #ifdef __powerpc64__
1504 do_cmp_signed(regs, op, val, imm, rd >> 2);
1507 case 12: /* addic */
1509 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1512 case 13: /* addic. */
1514 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1521 imm += regs->gpr[ra];
1525 case 15: /* addis */
1526 imm = ((short) word) << 16;
1528 imm += regs->gpr[ra];
1533 if (((word >> 1) & 0x1f) == 2) {
1535 imm = (short) (word & 0xffc1); /* d0 + d2 fields */
1536 imm |= (word >> 15) & 0x3e; /* d1 field */
1537 op->val = regs->nip + (imm << 16) + 4;
1543 case 20: /* rlwimi */
1544 mb = (word >> 6) & 0x1f;
1545 me = (word >> 1) & 0x1f;
1546 val = DATA32(regs->gpr[rd]);
1547 imm = MASK32(mb, me);
1548 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1551 case 21: /* rlwinm */
1552 mb = (word >> 6) & 0x1f;
1553 me = (word >> 1) & 0x1f;
1554 val = DATA32(regs->gpr[rd]);
1555 op->val = ROTATE(val, rb) & MASK32(mb, me);
1558 case 23: /* rlwnm */
1559 mb = (word >> 6) & 0x1f;
1560 me = (word >> 1) & 0x1f;
1561 rb = regs->gpr[rb] & 0x1f;
1562 val = DATA32(regs->gpr[rd]);
1563 op->val = ROTATE(val, rb) & MASK32(mb, me);
1567 op->val = regs->gpr[rd] | (unsigned short) word;
1568 goto logical_done_nocc;
1571 imm = (unsigned short) word;
1572 op->val = regs->gpr[rd] | (imm << 16);
1573 goto logical_done_nocc;
1576 op->val = regs->gpr[rd] ^ (unsigned short) word;
1577 goto logical_done_nocc;
1579 case 27: /* xoris */
1580 imm = (unsigned short) word;
1581 op->val = regs->gpr[rd] ^ (imm << 16);
1582 goto logical_done_nocc;
1584 case 28: /* andi. */
1585 op->val = regs->gpr[rd] & (unsigned short) word;
1587 goto logical_done_nocc;
1589 case 29: /* andis. */
1590 imm = (unsigned short) word;
1591 op->val = regs->gpr[rd] & (imm << 16);
1593 goto logical_done_nocc;
1595 #ifdef __powerpc64__
1597 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1598 val = regs->gpr[rd];
1599 if ((word & 0x10) == 0) {
1600 sh = rb | ((word & 2) << 4);
1601 val = ROTATE(val, sh);
1602 switch ((word >> 2) & 3) {
1603 case 0: /* rldicl */
1604 val &= MASK64_L(mb);
1606 case 1: /* rldicr */
1607 val &= MASK64_R(mb);
1610 val &= MASK64(mb, 63 - sh);
1612 case 3: /* rldimi */
1613 imm = MASK64(mb, 63 - sh);
1614 val = (regs->gpr[ra] & ~imm) |
1620 sh = regs->gpr[rb] & 0x3f;
1621 val = ROTATE(val, sh);
1622 switch ((word >> 1) & 7) {
1624 op->val = val & MASK64_L(mb);
1627 op->val = val & MASK64_R(mb);
1632 op->type = UNKNOWN; /* illegal instruction */
1636 /* isel occupies 32 minor opcodes */
1637 if (((word >> 1) & 0x1f) == 15) {
1638 mb = (word >> 6) & 0x1f; /* bc field */
1639 val = (regs->ccr >> (31 - mb)) & 1;
1640 val2 = (ra) ? regs->gpr[ra] : 0;
1642 op->val = (val) ? val2 : regs->gpr[rb];
1646 switch ((word >> 1) & 0x3ff) {
1649 (rd & trap_compare((int)regs->gpr[ra],
1650 (int)regs->gpr[rb])))
1653 #ifdef __powerpc64__
1655 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1659 case 83: /* mfmsr */
1660 if (regs->msr & MSR_PR)
1665 case 146: /* mtmsr */
1666 if (regs->msr & MSR_PR)
1670 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1673 case 178: /* mtmsrd */
1674 if (regs->msr & MSR_PR)
1678 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1679 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1680 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1687 if ((word >> 20) & 1) {
1689 for (sh = 0; sh < 8; ++sh) {
1690 if (word & (0x80000 >> sh))
1695 op->val = regs->ccr & imm;
1698 case 144: /* mtcrf */
1699 op->type = COMPUTE + SETCC;
1701 val = regs->gpr[rd];
1702 op->ccval = regs->ccr;
1703 for (sh = 0; sh < 8; ++sh) {
1704 if (word & (0x80000 >> sh))
1705 op->ccval = (op->ccval & ~imm) |
1711 case 339: /* mfspr */
1712 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1716 if (spr == SPRN_XER || spr == SPRN_LR ||
1721 case 467: /* mtspr */
1722 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1724 op->val = regs->gpr[rd];
1726 if (spr == SPRN_XER || spr == SPRN_LR ||
1732 * Compare instructions
1735 val = regs->gpr[ra];
1736 val2 = regs->gpr[rb];
1737 #ifdef __powerpc64__
1738 if ((rd & 1) == 0) {
1739 /* word (32-bit) compare */
1744 do_cmp_signed(regs, op, val, val2, rd >> 2);
1748 val = regs->gpr[ra];
1749 val2 = regs->gpr[rb];
1750 #ifdef __powerpc64__
1751 if ((rd & 1) == 0) {
1752 /* word (32-bit) compare */
1753 val = (unsigned int) val;
1754 val2 = (unsigned int) val2;
1757 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1760 case 508: /* cmpb */
1761 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1762 goto logical_done_nocc;
1765 * Arithmetic instructions
1768 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1771 #ifdef __powerpc64__
1772 case 9: /* mulhdu */
1773 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1774 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1778 add_with_carry(regs, op, rd, regs->gpr[ra],
1782 case 11: /* mulhwu */
1783 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1784 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1788 op->val = regs->gpr[rb] - regs->gpr[ra];
1790 #ifdef __powerpc64__
1791 case 73: /* mulhd */
1792 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1793 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1796 case 75: /* mulhw */
1797 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1798 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1802 op->val = -regs->gpr[ra];
1805 case 136: /* subfe */
1806 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1807 regs->gpr[rb], regs->xer & XER_CA);
1810 case 138: /* adde */
1811 add_with_carry(regs, op, rd, regs->gpr[ra],
1812 regs->gpr[rb], regs->xer & XER_CA);
1815 case 200: /* subfze */
1816 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1817 regs->xer & XER_CA);
1820 case 202: /* addze */
1821 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1822 regs->xer & XER_CA);
1825 case 232: /* subfme */
1826 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1827 regs->xer & XER_CA);
1829 #ifdef __powerpc64__
1830 case 233: /* mulld */
1831 op->val = regs->gpr[ra] * regs->gpr[rb];
1834 case 234: /* addme */
1835 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1836 regs->xer & XER_CA);
1839 case 235: /* mullw */
1840 op->val = (long)(int) regs->gpr[ra] *
1841 (int) regs->gpr[rb];
1844 #ifdef __powerpc64__
1845 case 265: /* modud */
1846 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1848 op->val = regs->gpr[ra] % regs->gpr[rb];
1852 op->val = regs->gpr[ra] + regs->gpr[rb];
1855 case 267: /* moduw */
1856 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1858 op->val = (unsigned int) regs->gpr[ra] %
1859 (unsigned int) regs->gpr[rb];
1861 #ifdef __powerpc64__
1862 case 457: /* divdu */
1863 op->val = regs->gpr[ra] / regs->gpr[rb];
1866 case 459: /* divwu */
1867 op->val = (unsigned int) regs->gpr[ra] /
1868 (unsigned int) regs->gpr[rb];
1870 #ifdef __powerpc64__
1871 case 489: /* divd */
1872 op->val = (long int) regs->gpr[ra] /
1873 (long int) regs->gpr[rb];
1876 case 491: /* divw */
1877 op->val = (int) regs->gpr[ra] /
1878 (int) regs->gpr[rb];
1880 #ifdef __powerpc64__
1881 case 425: /* divde[.] */
1882 asm volatile(PPC_DIVDE(%0, %1, %2) :
1883 "=r" (op->val) : "r" (regs->gpr[ra]),
1884 "r" (regs->gpr[rb]));
1886 case 393: /* divdeu[.] */
1887 asm volatile(PPC_DIVDEU(%0, %1, %2) :
1888 "=r" (op->val) : "r" (regs->gpr[ra]),
1889 "r" (regs->gpr[rb]));
1892 case 755: /* darn */
1893 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1897 /* 32-bit conditioned */
1898 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1902 /* 64-bit conditioned */
1903 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1908 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1913 #ifdef __powerpc64__
1914 case 777: /* modsd */
1915 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1917 op->val = (long int) regs->gpr[ra] %
1918 (long int) regs->gpr[rb];
1921 case 779: /* modsw */
1922 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1924 op->val = (int) regs->gpr[ra] %
1925 (int) regs->gpr[rb];
1930 * Logical instructions
1932 case 26: /* cntlzw */
1933 val = (unsigned int) regs->gpr[rd];
1934 op->val = ( val ? __builtin_clz(val) : 32 );
1936 #ifdef __powerpc64__
1937 case 58: /* cntlzd */
1938 val = regs->gpr[rd];
1939 op->val = ( val ? __builtin_clzl(val) : 64 );
1943 op->val = regs->gpr[rd] & regs->gpr[rb];
1947 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1950 case 122: /* popcntb */
1951 do_popcnt(regs, op, regs->gpr[rd], 8);
1952 goto logical_done_nocc;
1955 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1958 case 154: /* prtyw */
1959 do_prty(regs, op, regs->gpr[rd], 32);
1960 goto logical_done_nocc;
1962 case 186: /* prtyd */
1963 do_prty(regs, op, regs->gpr[rd], 64);
1964 goto logical_done_nocc;
1966 case 252: /* bpermd */
1967 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1968 goto logical_done_nocc;
1971 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1975 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1978 case 378: /* popcntw */
1979 do_popcnt(regs, op, regs->gpr[rd], 32);
1980 goto logical_done_nocc;
1983 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1987 op->val = regs->gpr[rd] | regs->gpr[rb];
1990 case 476: /* nand */
1991 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1994 case 506: /* popcntd */
1995 do_popcnt(regs, op, regs->gpr[rd], 64);
1996 goto logical_done_nocc;
1998 case 538: /* cnttzw */
1999 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2001 val = (unsigned int) regs->gpr[rd];
2002 op->val = (val ? __builtin_ctz(val) : 32);
2004 #ifdef __powerpc64__
2005 case 570: /* cnttzd */
2006 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2008 val = regs->gpr[rd];
2009 op->val = (val ? __builtin_ctzl(val) : 64);
2012 case 922: /* extsh */
2013 op->val = (signed short) regs->gpr[rd];
2016 case 954: /* extsb */
2017 op->val = (signed char) regs->gpr[rd];
2019 #ifdef __powerpc64__
2020 case 986: /* extsw */
2021 op->val = (signed int) regs->gpr[rd];
2026 * Shift instructions
2029 sh = regs->gpr[rb] & 0x3f;
2031 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2037 sh = regs->gpr[rb] & 0x3f;
2039 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2044 case 792: /* sraw */
2045 op->type = COMPUTE + SETREG + SETXER;
2046 sh = regs->gpr[rb] & 0x3f;
2047 ival = (signed int) regs->gpr[rd];
2048 op->val = ival >> (sh < 32 ? sh : 31);
2049 op->xerval = regs->xer;
2050 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2051 op->xerval |= XER_CA;
2053 op->xerval &= ~XER_CA;
2054 set_ca32(op, op->xerval & XER_CA);
2057 case 824: /* srawi */
2058 op->type = COMPUTE + SETREG + SETXER;
2060 ival = (signed int) regs->gpr[rd];
2061 op->val = ival >> sh;
2062 op->xerval = regs->xer;
2063 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2064 op->xerval |= XER_CA;
2066 op->xerval &= ~XER_CA;
2067 set_ca32(op, op->xerval & XER_CA);
2070 #ifdef __powerpc64__
2072 sh = regs->gpr[rb] & 0x7f;
2074 op->val = regs->gpr[rd] << sh;
2080 sh = regs->gpr[rb] & 0x7f;
2082 op->val = regs->gpr[rd] >> sh;
2087 case 794: /* srad */
2088 op->type = COMPUTE + SETREG + SETXER;
2089 sh = regs->gpr[rb] & 0x7f;
2090 ival = (signed long int) regs->gpr[rd];
2091 op->val = ival >> (sh < 64 ? sh : 63);
2092 op->xerval = regs->xer;
2093 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2094 op->xerval |= XER_CA;
2096 op->xerval &= ~XER_CA;
2097 set_ca32(op, op->xerval & XER_CA);
2100 case 826: /* sradi with sh_5 = 0 */
2101 case 827: /* sradi with sh_5 = 1 */
2102 op->type = COMPUTE + SETREG + SETXER;
2103 sh = rb | ((word & 2) << 4);
2104 ival = (signed long int) regs->gpr[rd];
2105 op->val = ival >> sh;
2106 op->xerval = regs->xer;
2107 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2108 op->xerval |= XER_CA;
2110 op->xerval &= ~XER_CA;
2111 set_ca32(op, op->xerval & XER_CA);
2114 case 890: /* extswsli with sh_5 = 0 */
2115 case 891: /* extswsli with sh_5 = 1 */
2116 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2118 op->type = COMPUTE + SETREG;
2119 sh = rb | ((word & 2) << 4);
2120 val = (signed int) regs->gpr[rd];
2122 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2127 #endif /* __powerpc64__ */
2130 * Cache instructions
2132 case 54: /* dcbst */
2133 op->type = MKOP(CACHEOP, DCBST, 0);
2134 op->ea = xform_ea(word, regs);
2138 op->type = MKOP(CACHEOP, DCBF, 0);
2139 op->ea = xform_ea(word, regs);
2142 case 246: /* dcbtst */
2143 op->type = MKOP(CACHEOP, DCBTST, 0);
2144 op->ea = xform_ea(word, regs);
2148 case 278: /* dcbt */
2149 op->type = MKOP(CACHEOP, DCBTST, 0);
2150 op->ea = xform_ea(word, regs);
2154 case 982: /* icbi */
2155 op->type = MKOP(CACHEOP, ICBI, 0);
2156 op->ea = xform_ea(word, regs);
2159 case 1014: /* dcbz */
2160 op->type = MKOP(CACHEOP, DCBZ, 0);
2161 op->ea = xform_ea(word, regs);
2171 op->update_reg = ra;
2173 op->val = regs->gpr[rd];
2174 u = (word >> 20) & UPDATE;
2180 op->ea = xform_ea(word, regs);
2181 switch ((word >> 1) & 0x3ff) {
2182 case 20: /* lwarx */
2183 op->type = MKOP(LARX, 0, 4);
2186 case 150: /* stwcx. */
2187 op->type = MKOP(STCX, 0, 4);
2190 #ifdef __powerpc64__
2191 case 84: /* ldarx */
2192 op->type = MKOP(LARX, 0, 8);
2195 case 214: /* stdcx. */
2196 op->type = MKOP(STCX, 0, 8);
2199 case 52: /* lbarx */
2200 op->type = MKOP(LARX, 0, 1);
2203 case 694: /* stbcx. */
2204 op->type = MKOP(STCX, 0, 1);
2207 case 116: /* lharx */
2208 op->type = MKOP(LARX, 0, 2);
2211 case 726: /* sthcx. */
2212 op->type = MKOP(STCX, 0, 2);
2215 case 276: /* lqarx */
2216 if (!((rd & 1) || rd == ra || rd == rb))
2217 op->type = MKOP(LARX, 0, 16);
2220 case 182: /* stqcx. */
2222 op->type = MKOP(STCX, 0, 16);
2227 case 55: /* lwzux */
2228 op->type = MKOP(LOAD, u, 4);
2232 case 119: /* lbzux */
2233 op->type = MKOP(LOAD, u, 1);
2236 #ifdef CONFIG_ALTIVEC
2238 * Note: for the load/store vector element instructions,
2239 * bits of the EA say which field of the VMX register to use.
2242 op->type = MKOP(LOAD_VMX, 0, 1);
2243 op->element_size = 1;
2246 case 39: /* lvehx */
2247 op->type = MKOP(LOAD_VMX, 0, 2);
2248 op->element_size = 2;
2251 case 71: /* lvewx */
2252 op->type = MKOP(LOAD_VMX, 0, 4);
2253 op->element_size = 4;
2257 case 359: /* lvxl */
2258 op->type = MKOP(LOAD_VMX, 0, 16);
2259 op->element_size = 16;
2262 case 135: /* stvebx */
2263 op->type = MKOP(STORE_VMX, 0, 1);
2264 op->element_size = 1;
2267 case 167: /* stvehx */
2268 op->type = MKOP(STORE_VMX, 0, 2);
2269 op->element_size = 2;
2272 case 199: /* stvewx */
2273 op->type = MKOP(STORE_VMX, 0, 4);
2274 op->element_size = 4;
2277 case 231: /* stvx */
2278 case 487: /* stvxl */
2279 op->type = MKOP(STORE_VMX, 0, 16);
2281 #endif /* CONFIG_ALTIVEC */
2283 #ifdef __powerpc64__
2286 op->type = MKOP(LOAD, u, 8);
2289 case 149: /* stdx */
2290 case 181: /* stdux */
2291 op->type = MKOP(STORE, u, 8);
2295 case 151: /* stwx */
2296 case 183: /* stwux */
2297 op->type = MKOP(STORE, u, 4);
2300 case 215: /* stbx */
2301 case 247: /* stbux */
2302 op->type = MKOP(STORE, u, 1);
2305 case 279: /* lhzx */
2306 case 311: /* lhzux */
2307 op->type = MKOP(LOAD, u, 2);
2310 #ifdef __powerpc64__
2311 case 341: /* lwax */
2312 case 373: /* lwaux */
2313 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2317 case 343: /* lhax */
2318 case 375: /* lhaux */
2319 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2322 case 407: /* sthx */
2323 case 439: /* sthux */
2324 op->type = MKOP(STORE, u, 2);
2327 #ifdef __powerpc64__
2328 case 532: /* ldbrx */
2329 op->type = MKOP(LOAD, BYTEREV, 8);
2333 case 533: /* lswx */
2334 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2337 case 534: /* lwbrx */
2338 op->type = MKOP(LOAD, BYTEREV, 4);
2341 case 597: /* lswi */
2343 rb = 32; /* # bytes to load */
2344 op->type = MKOP(LOAD_MULTI, 0, rb);
2345 op->ea = ra ? regs->gpr[ra] : 0;
2348 #ifdef CONFIG_PPC_FPU
2349 case 535: /* lfsx */
2350 case 567: /* lfsux */
2351 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2354 case 599: /* lfdx */
2355 case 631: /* lfdux */
2356 op->type = MKOP(LOAD_FP, u, 8);
2359 case 663: /* stfsx */
2360 case 695: /* stfsux */
2361 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2364 case 727: /* stfdx */
2365 case 759: /* stfdux */
2366 op->type = MKOP(STORE_FP, u, 8);
2369 #ifdef __powerpc64__
2370 case 791: /* lfdpx */
2371 op->type = MKOP(LOAD_FP, 0, 16);
2374 case 855: /* lfiwax */
2375 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2378 case 887: /* lfiwzx */
2379 op->type = MKOP(LOAD_FP, 0, 4);
2382 case 919: /* stfdpx */
2383 op->type = MKOP(STORE_FP, 0, 16);
2386 case 983: /* stfiwx */
2387 op->type = MKOP(STORE_FP, 0, 4);
2389 #endif /* __powerpc64 */
2390 #endif /* CONFIG_PPC_FPU */
2392 #ifdef __powerpc64__
2393 case 660: /* stdbrx */
2394 op->type = MKOP(STORE, BYTEREV, 8);
2395 op->val = byterev_8(regs->gpr[rd]);
2399 case 661: /* stswx */
2400 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2403 case 662: /* stwbrx */
2404 op->type = MKOP(STORE, BYTEREV, 4);
2405 op->val = byterev_4(regs->gpr[rd]);
2408 case 725: /* stswi */
2410 rb = 32; /* # bytes to store */
2411 op->type = MKOP(STORE_MULTI, 0, rb);
2412 op->ea = ra ? regs->gpr[ra] : 0;
2415 case 790: /* lhbrx */
2416 op->type = MKOP(LOAD, BYTEREV, 2);
2419 case 918: /* sthbrx */
2420 op->type = MKOP(STORE, BYTEREV, 2);
2421 op->val = byterev_2(regs->gpr[rd]);
2425 case 12: /* lxsiwzx */
2426 op->reg = rd | ((word & 1) << 5);
2427 op->type = MKOP(LOAD_VSX, 0, 4);
2428 op->element_size = 8;
2431 case 76: /* lxsiwax */
2432 op->reg = rd | ((word & 1) << 5);
2433 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2434 op->element_size = 8;
2437 case 140: /* stxsiwx */
2438 op->reg = rd | ((word & 1) << 5);
2439 op->type = MKOP(STORE_VSX, 0, 4);
2440 op->element_size = 8;
2443 case 268: /* lxvx */
2444 op->reg = rd | ((word & 1) << 5);
2445 op->type = MKOP(LOAD_VSX, 0, 16);
2446 op->element_size = 16;
2447 op->vsx_flags = VSX_CHECK_VEC;
2450 case 269: /* lxvl */
2451 case 301: { /* lxvll */
2453 op->reg = rd | ((word & 1) << 5);
2454 op->ea = ra ? regs->gpr[ra] : 0;
2455 nb = regs->gpr[rb] & 0xff;
2458 op->type = MKOP(LOAD_VSX, 0, nb);
2459 op->element_size = 16;
2460 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2464 case 332: /* lxvdsx */
2465 op->reg = rd | ((word & 1) << 5);
2466 op->type = MKOP(LOAD_VSX, 0, 8);
2467 op->element_size = 8;
2468 op->vsx_flags = VSX_SPLAT;
2471 case 333: /* lxvpx */
2472 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2474 op->reg = VSX_REGISTER_XTP(rd);
2475 op->type = MKOP(LOAD_VSX, 0, 32);
2476 op->element_size = 32;
2479 case 364: /* lxvwsx */
2480 op->reg = rd | ((word & 1) << 5);
2481 op->type = MKOP(LOAD_VSX, 0, 4);
2482 op->element_size = 4;
2483 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2486 case 396: /* stxvx */
2487 op->reg = rd | ((word & 1) << 5);
2488 op->type = MKOP(STORE_VSX, 0, 16);
2489 op->element_size = 16;
2490 op->vsx_flags = VSX_CHECK_VEC;
2493 case 397: /* stxvl */
2494 case 429: { /* stxvll */
2496 op->reg = rd | ((word & 1) << 5);
2497 op->ea = ra ? regs->gpr[ra] : 0;
2498 nb = regs->gpr[rb] & 0xff;
2501 op->type = MKOP(STORE_VSX, 0, nb);
2502 op->element_size = 16;
2503 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2507 case 461: /* stxvpx */
2508 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2510 op->reg = VSX_REGISTER_XTP(rd);
2511 op->type = MKOP(STORE_VSX, 0, 32);
2512 op->element_size = 32;
2514 case 524: /* lxsspx */
2515 op->reg = rd | ((word & 1) << 5);
2516 op->type = MKOP(LOAD_VSX, 0, 4);
2517 op->element_size = 8;
2518 op->vsx_flags = VSX_FPCONV;
2521 case 588: /* lxsdx */
2522 op->reg = rd | ((word & 1) << 5);
2523 op->type = MKOP(LOAD_VSX, 0, 8);
2524 op->element_size = 8;
2527 case 652: /* stxsspx */
2528 op->reg = rd | ((word & 1) << 5);
2529 op->type = MKOP(STORE_VSX, 0, 4);
2530 op->element_size = 8;
2531 op->vsx_flags = VSX_FPCONV;
2534 case 716: /* stxsdx */
2535 op->reg = rd | ((word & 1) << 5);
2536 op->type = MKOP(STORE_VSX, 0, 8);
2537 op->element_size = 8;
2540 case 780: /* lxvw4x */
2541 op->reg = rd | ((word & 1) << 5);
2542 op->type = MKOP(LOAD_VSX, 0, 16);
2543 op->element_size = 4;
2546 case 781: /* lxsibzx */
2547 op->reg = rd | ((word & 1) << 5);
2548 op->type = MKOP(LOAD_VSX, 0, 1);
2549 op->element_size = 8;
2550 op->vsx_flags = VSX_CHECK_VEC;
2553 case 812: /* lxvh8x */
2554 op->reg = rd | ((word & 1) << 5);
2555 op->type = MKOP(LOAD_VSX, 0, 16);
2556 op->element_size = 2;
2557 op->vsx_flags = VSX_CHECK_VEC;
2560 case 813: /* lxsihzx */
2561 op->reg = rd | ((word & 1) << 5);
2562 op->type = MKOP(LOAD_VSX, 0, 2);
2563 op->element_size = 8;
2564 op->vsx_flags = VSX_CHECK_VEC;
2567 case 844: /* lxvd2x */
2568 op->reg = rd | ((word & 1) << 5);
2569 op->type = MKOP(LOAD_VSX, 0, 16);
2570 op->element_size = 8;
2573 case 876: /* lxvb16x */
2574 op->reg = rd | ((word & 1) << 5);
2575 op->type = MKOP(LOAD_VSX, 0, 16);
2576 op->element_size = 1;
2577 op->vsx_flags = VSX_CHECK_VEC;
2580 case 908: /* stxvw4x */
2581 op->reg = rd | ((word & 1) << 5);
2582 op->type = MKOP(STORE_VSX, 0, 16);
2583 op->element_size = 4;
2586 case 909: /* stxsibx */
2587 op->reg = rd | ((word & 1) << 5);
2588 op->type = MKOP(STORE_VSX, 0, 1);
2589 op->element_size = 8;
2590 op->vsx_flags = VSX_CHECK_VEC;
2593 case 940: /* stxvh8x */
2594 op->reg = rd | ((word & 1) << 5);
2595 op->type = MKOP(STORE_VSX, 0, 16);
2596 op->element_size = 2;
2597 op->vsx_flags = VSX_CHECK_VEC;
2600 case 941: /* stxsihx */
2601 op->reg = rd | ((word & 1) << 5);
2602 op->type = MKOP(STORE_VSX, 0, 2);
2603 op->element_size = 8;
2604 op->vsx_flags = VSX_CHECK_VEC;
2607 case 972: /* stxvd2x */
2608 op->reg = rd | ((word & 1) << 5);
2609 op->type = MKOP(STORE_VSX, 0, 16);
2610 op->element_size = 8;
2613 case 1004: /* stxvb16x */
2614 op->reg = rd | ((word & 1) << 5);
2615 op->type = MKOP(STORE_VSX, 0, 16);
2616 op->element_size = 1;
2617 op->vsx_flags = VSX_CHECK_VEC;
2620 #endif /* CONFIG_VSX */
2626 op->type = MKOP(LOAD, u, 4);
2627 op->ea = dform_ea(word, regs);
2632 op->type = MKOP(LOAD, u, 1);
2633 op->ea = dform_ea(word, regs);
2638 op->type = MKOP(STORE, u, 4);
2639 op->ea = dform_ea(word, regs);
2644 op->type = MKOP(STORE, u, 1);
2645 op->ea = dform_ea(word, regs);
2650 op->type = MKOP(LOAD, u, 2);
2651 op->ea = dform_ea(word, regs);
2656 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2657 op->ea = dform_ea(word, regs);
2662 op->type = MKOP(STORE, u, 2);
2663 op->ea = dform_ea(word, regs);
2668 break; /* invalid form, ra in range to load */
2669 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2670 op->ea = dform_ea(word, regs);
2674 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2675 op->ea = dform_ea(word, regs);
2678 #ifdef CONFIG_PPC_FPU
2681 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2682 op->ea = dform_ea(word, regs);
2687 op->type = MKOP(LOAD_FP, u, 8);
2688 op->ea = dform_ea(word, regs);
2692 case 53: /* stfsu */
2693 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2694 op->ea = dform_ea(word, regs);
2698 case 55: /* stfdu */
2699 op->type = MKOP(STORE_FP, u, 8);
2700 op->ea = dform_ea(word, regs);
2704 #ifdef __powerpc64__
2706 if (!((rd & 1) || (rd == ra)))
2707 op->type = MKOP(LOAD, 0, 16);
2708 op->ea = dqform_ea(word, regs);
2713 case 57: /* lfdp, lxsd, lxssp */
2714 op->ea = dsform_ea(word, regs);
2718 break; /* reg must be even */
2719 op->type = MKOP(LOAD_FP, 0, 16);
2723 op->type = MKOP(LOAD_VSX, 0, 8);
2724 op->element_size = 8;
2725 op->vsx_flags = VSX_CHECK_VEC;
2729 op->type = MKOP(LOAD_VSX, 0, 4);
2730 op->element_size = 8;
2731 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2735 #endif /* CONFIG_VSX */
2737 #ifdef __powerpc64__
2738 case 58: /* ld[u], lwa */
2739 op->ea = dsform_ea(word, regs);
2742 op->type = MKOP(LOAD, 0, 8);
2745 op->type = MKOP(LOAD, UPDATE, 8);
2748 op->type = MKOP(LOAD, SIGNEXT, 4);
2756 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2758 op->ea = dqform_ea(word, regs);
2759 op->reg = VSX_REGISTER_XTP(rd);
2760 op->element_size = 32;
2761 switch (word & 0xf) {
2763 op->type = MKOP(LOAD_VSX, 0, 32);
2766 op->type = MKOP(STORE_VSX, 0, 32);
2771 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2773 case 0: /* stfdp with LSB of DS field = 0 */
2774 case 4: /* stfdp with LSB of DS field = 1 */
2775 op->ea = dsform_ea(word, regs);
2776 op->type = MKOP(STORE_FP, 0, 16);
2780 op->ea = dqform_ea(word, regs);
2783 op->type = MKOP(LOAD_VSX, 0, 16);
2784 op->element_size = 16;
2785 op->vsx_flags = VSX_CHECK_VEC;
2788 case 2: /* stxsd with LSB of DS field = 0 */
2789 case 6: /* stxsd with LSB of DS field = 1 */
2790 op->ea = dsform_ea(word, regs);
2792 op->type = MKOP(STORE_VSX, 0, 8);
2793 op->element_size = 8;
2794 op->vsx_flags = VSX_CHECK_VEC;
2797 case 3: /* stxssp with LSB of DS field = 0 */
2798 case 7: /* stxssp with LSB of DS field = 1 */
2799 op->ea = dsform_ea(word, regs);
2801 op->type = MKOP(STORE_VSX, 0, 4);
2802 op->element_size = 8;
2803 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2807 op->ea = dqform_ea(word, regs);
2810 op->type = MKOP(STORE_VSX, 0, 16);
2811 op->element_size = 16;
2812 op->vsx_flags = VSX_CHECK_VEC;
2816 #endif /* CONFIG_VSX */
2818 #ifdef __powerpc64__
2819 case 62: /* std[u] */
2820 op->ea = dsform_ea(word, regs);
2823 op->type = MKOP(STORE, 0, 8);
2826 op->type = MKOP(STORE, UPDATE, 8);
2830 op->type = MKOP(STORE, 0, 16);
2834 case 1: /* Prefixed instructions */
2835 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2838 prefix_r = GET_PREFIX_R(word);
2839 ra = GET_PREFIX_RA(suffix);
2840 op->update_reg = ra;
2841 rd = (suffix >> 21) & 0x1f;
2843 op->val = regs->gpr[rd];
2845 suffixopcode = get_op(suffix);
2846 prefixtype = (word >> 24) & 0x3;
2847 switch (prefixtype) {
2848 case 0: /* Type 00 Eight-Byte Load/Store */
2851 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2852 switch (suffixopcode) {
2854 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2857 case 42: /* plxsd */
2859 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2860 op->element_size = 8;
2861 op->vsx_flags = VSX_CHECK_VEC;
2863 case 43: /* plxssp */
2865 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2866 op->element_size = 8;
2867 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2869 case 46: /* pstxsd */
2871 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2872 op->element_size = 8;
2873 op->vsx_flags = VSX_CHECK_VEC;
2875 case 47: /* pstxssp */
2877 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2878 op->element_size = 8;
2879 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2881 case 51: /* plxv1 */
2884 case 50: /* plxv0 */
2885 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2886 op->element_size = 16;
2887 op->vsx_flags = VSX_CHECK_VEC;
2889 case 55: /* pstxv1 */
2892 case 54: /* pstxv0 */
2893 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2894 op->element_size = 16;
2895 op->vsx_flags = VSX_CHECK_VEC;
2897 #endif /* CONFIG_VSX */
2899 op->type = MKOP(LOAD, PREFIXED, 16);
2902 op->type = MKOP(LOAD, PREFIXED, 8);
2905 case 58: /* plxvp */
2906 op->reg = VSX_REGISTER_XTP(rd);
2907 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
2908 op->element_size = 32;
2910 #endif /* CONFIG_VSX */
2912 op->type = MKOP(STORE, PREFIXED, 16);
2915 op->type = MKOP(STORE, PREFIXED, 8);
2918 case 62: /* pstxvp */
2919 op->reg = VSX_REGISTER_XTP(rd);
2920 op->type = MKOP(STORE_VSX, PREFIXED, 32);
2921 op->element_size = 32;
2923 #endif /* CONFIG_VSX */
2926 case 1: /* Type 01 Eight-Byte Register-to-Register */
2928 case 2: /* Type 10 Modified Load/Store */
2931 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2932 switch (suffixopcode) {
2934 op->type = MKOP(LOAD, PREFIXED, 4);
2937 op->type = MKOP(LOAD, PREFIXED, 1);
2940 op->type = MKOP(STORE, PREFIXED, 4);
2943 op->type = MKOP(STORE, PREFIXED, 1);
2946 op->type = MKOP(LOAD, PREFIXED, 2);
2949 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2952 op->type = MKOP(STORE, PREFIXED, 2);
2955 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2958 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2960 case 52: /* pstfs */
2961 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2963 case 54: /* pstfd */
2964 op->type = MKOP(STORE_FP, PREFIXED, 8);
2968 case 3: /* Type 11 Modified Register-to-Register */
2971 #endif /* __powerpc64__ */
2976 if ((GETTYPE(op->type) == LOAD_VSX ||
2977 GETTYPE(op->type) == STORE_VSX) &&
2978 !cpu_has_feature(CPU_FTR_VSX)) {
2981 #endif /* CONFIG_VSX */
3002 op->type = INTERRUPT | 0x700;
3003 op->val = SRR1_PROGPRIV;
3007 op->type = INTERRUPT | 0x700;
3008 op->val = SRR1_PROGTRAP;
3011 EXPORT_SYMBOL_GPL(analyse_instr);
3012 NOKPROBE_SYMBOL(analyse_instr);
3015 * For PPC32 we always use stwu with r1 to change the stack pointer.
3016 * So this emulated store may corrupt the exception frame, now we
3017 * have to provide the exception frame trampoline, which is pushed
3018 * below the kprobed function stack. So we only update gpr[1] but
3019 * don't emulate the real store operation. We will do real store
3020 * operation safely in exception return code by checking this flag.
3022 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3026 * Check if we will touch kernel stack overflow
3028 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
3029 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
3032 #endif /* CONFIG_PPC32 */
3034 * Check if we already set since that means we'll
3035 * lose the previous value.
3037 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3038 set_thread_flag(TIF_EMULATE_STACK_STORE);
3042 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3046 *valp = (signed short) *valp;
3049 *valp = (signed int) *valp;
3054 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3058 *valp = byterev_2(*valp);
3061 *valp = byterev_4(*valp);
3063 #ifdef __powerpc64__
3065 *valp = byterev_8(*valp);
3072 * Emulate an instruction that can be executed just by updating
3075 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3077 unsigned long next_pc;
3079 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3080 switch (GETTYPE(op->type)) {
3082 if (op->type & SETREG)
3083 regs->gpr[op->reg] = op->val;
3084 if (op->type & SETCC)
3085 regs->ccr = op->ccval;
3086 if (op->type & SETXER)
3087 regs->xer = op->xerval;
3091 if (op->type & SETLK)
3092 regs->link = next_pc;
3093 if (op->type & BRTAKEN)
3095 if (op->type & DECCTR)
3100 switch (op->type & BARRIER_MASK) {
3110 case BARRIER_LWSYNC:
3111 asm volatile("lwsync" : : : "memory");
3113 case BARRIER_PTESYNC:
3114 asm volatile("ptesync" : : : "memory");
3122 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3125 regs->gpr[op->reg] = regs->link;
3128 regs->gpr[op->reg] = regs->ctr;
3138 regs->xer = op->val & 0xffffffffUL;
3141 regs->link = op->val;
3144 regs->ctr = op->val;
3154 regs->nip = next_pc;
3156 NOKPROBE_SYMBOL(emulate_update_regs);
3159 * Emulate a previously-analysed load or store instruction.
3160 * Return values are:
3161 * 0 = instruction emulated successfully
3162 * -EFAULT = address out of range or access faulted (regs->dar
3163 * contains the faulting address)
3164 * -EACCES = misaligned access, instruction requires alignment
3165 * -EINVAL = unknown operation in *op
3167 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3169 int err, size, type;
3177 size = GETSIZE(op->type);
3178 type = GETTYPE(op->type);
3179 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3180 ea = truncate_if_32bit(regs->msr, op->ea);
3184 if (ea & (size - 1))
3185 return -EACCES; /* can't handle misaligned */
3186 if (!address_ok(regs, ea, size))
3191 #ifdef __powerpc64__
3193 __get_user_asmx(val, ea, err, "lbarx");
3196 __get_user_asmx(val, ea, err, "lharx");
3200 __get_user_asmx(val, ea, err, "lwarx");
3202 #ifdef __powerpc64__
3204 __get_user_asmx(val, ea, err, "ldarx");
3207 err = do_lqarx(ea, ®s->gpr[op->reg]);
3218 regs->gpr[op->reg] = val;
3222 if (ea & (size - 1))
3223 return -EACCES; /* can't handle misaligned */
3224 if (!address_ok(regs, ea, size))
3228 #ifdef __powerpc64__
3230 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3233 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3237 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3239 #ifdef __powerpc64__
3241 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3244 err = do_stqcx(ea, regs->gpr[op->reg],
3245 regs->gpr[op->reg + 1], &cr);
3252 regs->ccr = (regs->ccr & 0x0fffffff) |
3254 ((regs->xer >> 3) & 0x10000000);
3260 #ifdef __powerpc64__
3262 err = emulate_lq(regs, ea, op->reg, cross_endian);
3266 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3268 if (op->type & SIGNEXT)
3269 do_signext(®s->gpr[op->reg], size);
3270 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3271 do_byterev(®s->gpr[op->reg], size);
3275 #ifdef CONFIG_PPC_FPU
3278 * If the instruction is in userspace, we can emulate it even
3279 * if the VMX state is not live, because we have the state
3280 * stored in the thread_struct. If the instruction is in
3281 * the kernel, we must not touch the state in the thread_struct.
3283 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3285 err = do_fp_load(op, ea, regs, cross_endian);
3288 #ifdef CONFIG_ALTIVEC
3290 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3292 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3297 unsigned long msrbit = MSR_VSX;
3300 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3301 * when the target of the instruction is a vector register.
3303 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3305 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3307 err = do_vsx_load(op, ea, regs, cross_endian);
3312 if (!address_ok(regs, ea, size))
3315 for (i = 0; i < size; i += 4) {
3316 unsigned int v32 = 0;
3321 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3324 if (unlikely(cross_endian))
3325 v32 = byterev_4(v32);
3326 regs->gpr[rd] = v32;
3328 /* reg number wraps from 31 to 0 for lsw[ix] */
3329 rd = (rd + 1) & 0x1f;
3334 #ifdef __powerpc64__
3336 err = emulate_stq(regs, ea, op->reg, cross_endian);
3340 if ((op->type & UPDATE) && size == sizeof(long) &&
3341 op->reg == 1 && op->update_reg == 1 &&
3342 !(regs->msr & MSR_PR) &&
3343 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3344 err = handle_stack_update(ea, regs);
3347 if (unlikely(cross_endian))
3348 do_byterev(&op->val, size);
3349 err = write_mem(op->val, ea, size, regs);
3352 #ifdef CONFIG_PPC_FPU
3354 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3356 err = do_fp_store(op, ea, regs, cross_endian);
3359 #ifdef CONFIG_ALTIVEC
3361 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3363 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3368 unsigned long msrbit = MSR_VSX;
3371 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3372 * when the target of the instruction is a vector register.
3374 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3376 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3378 err = do_vsx_store(op, ea, regs, cross_endian);
3383 if (!address_ok(regs, ea, size))
3386 for (i = 0; i < size; i += 4) {
3387 unsigned int v32 = regs->gpr[rd];
3392 if (unlikely(cross_endian))
3393 v32 = byterev_4(v32);
3394 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3398 /* reg number wraps from 31 to 0 for stsw[ix] */
3399 rd = (rd + 1) & 0x1f;
3410 if (op->type & UPDATE)
3411 regs->gpr[op->update_reg] = op->ea;
3415 NOKPROBE_SYMBOL(emulate_loadstore);
3418 * Emulate instructions that cause a transfer of control,
3419 * loads and stores, and a few other instructions.
3420 * Returns 1 if the step was emulated, 0 if not,
3421 * or -1 if the instruction is one that should not be stepped,
3422 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3424 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3426 struct instruction_op op;
3431 r = analyse_instr(&op, regs, instr);
3435 emulate_update_regs(regs, &op);
3440 type = GETTYPE(op.type);
3442 if (OP_IS_LOAD_STORE(type)) {
3443 err = emulate_loadstore(regs, &op);
3451 ea = truncate_if_32bit(regs->msr, op.ea);
3452 if (!address_ok(regs, ea, 8))
3454 switch (op.type & CACHEOP_MASK) {
3456 __cacheop_user_asmx(ea, err, "dcbst");
3459 __cacheop_user_asmx(ea, err, "dcbf");
3463 prefetchw((void *) ea);
3467 prefetch((void *) ea);
3470 __cacheop_user_asmx(ea, err, "icbi");
3473 err = emulate_dcbz(ea, regs);
3483 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3487 val = regs->gpr[op.reg];
3488 if ((val & MSR_RI) == 0)
3489 /* can't step mtmsr[d] that would clear MSR_RI */
3491 /* here op.val is the mask of bits to change */
3492 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3496 case SYSCALL: /* sc */
3498 * N.B. this uses knowledge about how the syscall
3499 * entry code works. If that is changed, this will
3500 * need to be changed also.
3502 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3503 cpu_has_feature(CPU_FTR_REAL_LE) &&
3504 regs->gpr[0] == 0x1ebe) {
3505 regs->msr ^= MSR_LE;
3508 regs->gpr[9] = regs->gpr[13];
3509 regs->gpr[10] = MSR_KERNEL;
3510 regs->gpr[11] = regs->nip + 4;
3511 regs->gpr[12] = regs->msr & MSR_MASK;
3512 regs->gpr[13] = (unsigned long) get_paca();
3513 regs->nip = (unsigned long) &system_call_common;
3514 regs->msr = MSR_KERNEL;
3517 #ifdef CONFIG_PPC_BOOK3S_64
3518 case SYSCALL_VECTORED_0: /* scv 0 */
3519 regs->gpr[9] = regs->gpr[13];
3520 regs->gpr[10] = MSR_KERNEL;
3521 regs->gpr[11] = regs->nip + 4;
3522 regs->gpr[12] = regs->msr & MSR_MASK;
3523 regs->gpr[13] = (unsigned long) get_paca();
3524 regs->nip = (unsigned long) &system_call_vectored_emulate;
3525 regs->msr = MSR_KERNEL;
3536 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3539 NOKPROBE_SYMBOL(emulate_step);