arch/powerpc/lib/sstep.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Single-step support.
   4  *
   5  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/kprobes.h>
   9 #include <linux/ptrace.h>
  10 #include <linux/prefetch.h>
  11 #include <asm/sstep.h>
  12 #include <asm/processor.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/cpu_has_feature.h>
  15 #include <asm/cputable.h>
  16 #include <asm/disassemble.h>
  17
  18 extern char system_call_common[];
  19 extern char system_call_vectored_emulate[];
  20
  21 #ifdef CONFIG_PPC64
  22 /* Bits in SRR1 that are copied from MSR */
  23 #define MSR_MASK        0xffffffff87c0ffffUL
  24 #else
  25 #define MSR_MASK        0x87c0ffff
  26 #endif
  27
  28 /* Bits in XER */
  29 #define XER_SO          0x80000000U
  30 #define XER_OV          0x40000000U
  31 #define XER_CA          0x20000000U
  32 #define XER_OV32        0x00080000U
  33 #define XER_CA32        0x00040000U
  34
  35 #ifdef CONFIG_VSX
  36 #define VSX_REGISTER_XTP(rd)   ((((rd) & 1) << 5) | ((rd) & 0xfe))
  37 #endif
  38
  39 #ifdef CONFIG_PPC_FPU
  40 /*
  41  * Functions in ldstfp.S
  42  */
  43 extern void get_fpr(int rn, double *p);
  44 extern void put_fpr(int rn, const double *p);
  45 extern void get_vr(int rn, __vector128 *p);
  46 extern void put_vr(int rn, __vector128 *p);
  47 extern void load_vsrn(int vsr, const void *p);
  48 extern void store_vsrn(int vsr, void *p);
  49 extern void conv_sp_to_dp(const float *sp, double *dp);
  50 extern void conv_dp_to_sp(const double *dp, float *sp);
  51 #endif
  52
  53 #ifdef __powerpc64__
  54 /*
  55  * Functions in quad.S
  56  */
  57 extern int do_lq(unsigned long ea, unsigned long *regs);
  58 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  59 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  60 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  61                     unsigned int *crp);
  62 #endif
  63
  64 #ifdef __LITTLE_ENDIAN__
  65 #define IS_LE   1
  66 #define IS_BE   0
  67 #else
  68 #define IS_LE   0
  69 #define IS_BE   1
  70 #endif
  71
  72 /*
  73  * Emulate the truncation of 64 bit values in 32-bit mode.
  74  */
  75 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  76                                                         unsigned long val)
  77 {
  78 #ifdef __powerpc64__
  79         if ((msr & MSR_64BIT) == 0)
  80                 val &= 0xffffffffUL;
  81 #endif
  82         return val;
  83 }
  84
  85 /*
  86  * Determine whether a conditional branch instruction would branch.
  87  */
  88 static nokprobe_inline int branch_taken(unsigned int instr,
  89                                         const struct pt_regs *regs,
  90                                         struct instruction_op *op)
  91 {
  92         unsigned int bo = (instr >> 21) & 0x1f;
  93         unsigned int bi;
  94
  95         if ((bo & 4) == 0) {
  96                 /* decrement counter */
  97                 op->type |= DECCTR;
  98                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  99                         return 0;
 100         }
 101         if ((bo & 0x10) == 0) {
 102                 /* check bit from CR */
 103                 bi = (instr >> 16) & 0x1f;
 104                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 105                         return 0;
 106         }
 107         return 1;
 108 }
 109
 110 static nokprobe_inline long address_ok(struct pt_regs *regs,
 111                                        unsigned long ea, int nb)
 112 {
 113         if (!user_mode(regs))
 114                 return 1;
 115         if (__access_ok(ea, nb))
 116                 return 1;
 117         if (__access_ok(ea, 1))
 118                 /* Access overlaps the end of the user region */
 119                 regs->dar = TASK_SIZE_MAX - 1;
 120         else
 121                 regs->dar = ea;
 122         return 0;
 123 }
 124
 125 /*
 126  * Calculate effective address for a D-form instruction
 127  */
 128 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 129                                               const struct pt_regs *regs)
 130 {
 131         int ra;
 132         unsigned long ea;
 133
 134         ra = (instr >> 16) & 0x1f;
 135         ea = (signed short) instr;              /* sign-extend */
 136         if (ra)
 137                 ea += regs->gpr[ra];
 138
 139         return ea;
 140 }
 141
 142 #ifdef __powerpc64__
 143 /*
 144  * Calculate effective address for a DS-form instruction
 145  */
 146 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 147                                                const struct pt_regs *regs)
 148 {
 149         int ra;
 150         unsigned long ea;
 151
 152         ra = (instr >> 16) & 0x1f;
 153         ea = (signed short) (instr & ~3);       /* sign-extend */
 154         if (ra)
 155                 ea += regs->gpr[ra];
 156
 157         return ea;
 158 }
 159
 160 /*
 161  * Calculate effective address for a DQ-form instruction
 162  */
 163 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 164                                                const struct pt_regs *regs)
 165 {
 166         int ra;
 167         unsigned long ea;
 168
 169         ra = (instr >> 16) & 0x1f;
 170         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 171         if (ra)
 172                 ea += regs->gpr[ra];
 173
 174         return ea;
 175 }
 176 #endif /* __powerpc64 */
 177
 178 /*
 179  * Calculate effective address for an X-form instruction
 180  */
 181 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 182                                               const struct pt_regs *regs)
 183 {
 184         int ra, rb;
 185         unsigned long ea;
 186
 187         ra = (instr >> 16) & 0x1f;
 188         rb = (instr >> 11) & 0x1f;
 189         ea = regs->gpr[rb];
 190         if (ra)
 191                 ea += regs->gpr[ra];
 192
 193         return ea;
 194 }
 195
 196 /*
 197  * Calculate effective address for a MLS:D-form / 8LS:D-form
 198  * prefixed instruction
 199  */
 200 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
 201                                                   unsigned int suffix,
 202                                                   const struct pt_regs *regs)
 203 {
 204         int ra, prefix_r;
 205         unsigned int  dd;
 206         unsigned long ea, d0, d1, d;
 207
 208         prefix_r = GET_PREFIX_R(instr);
 209         ra = GET_PREFIX_RA(suffix);
 210
 211         d0 = instr & 0x3ffff;
 212         d1 = suffix & 0xffff;
 213         d = (d0 << 16) | d1;
 214
 215         /*
 216          * sign extend a 34 bit number
 217          */
 218         dd = (unsigned int)(d >> 2);
 219         ea = (signed int)dd;
 220         ea = (ea << 2) | (d & 0x3);
 221
 222         if (!prefix_r && ra)
 223                 ea += regs->gpr[ra];
 224         else if (!prefix_r && !ra)
 225                 ; /* Leave ea as is */
 226         else if (prefix_r)
 227                 ea += regs->nip;
 228
 229         /*
 230          * (prefix_r && ra) is an invalid form. Should already be
 231          * checked for by caller!
 232          */
 233
 234         return ea;
 235 }
 236
 237 /*
 238  * Return the largest power of 2, not greater than sizeof(unsigned long),
 239  * such that x is a multiple of it.
 240  */
 241 static nokprobe_inline unsigned long max_align(unsigned long x)
 242 {
 243         x |= sizeof(unsigned long);
 244         return x & -x;          /* isolates rightmost bit */
 245 }
 246
 247 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 248 {
 249         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 250 }
 251
 252 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 253 {
 254         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 255                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 256 }
 257
 258 #ifdef __powerpc64__
 259 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 260 {
 261         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 262 }
 263 #endif
 264
 265 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 266 {
 267         switch (nb) {
 268         case 2:
 269                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 270                 break;
 271         case 4:
 272                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 273                 break;
 274 #ifdef __powerpc64__
 275         case 8:
 276                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 277                 break;
 278         case 16: {
 279                 unsigned long *up = (unsigned long *)ptr;
 280                 unsigned long tmp;
 281                 tmp = byterev_8(up[0]);
 282                 up[0] = byterev_8(up[1]);
 283                 up[1] = tmp;
 284                 break;
 285         }
 286         case 32: {
 287                 unsigned long *up = (unsigned long *)ptr;
 288                 unsigned long tmp;
 289
 290                 tmp = byterev_8(up[0]);
 291                 up[0] = byterev_8(up[3]);
 292                 up[3] = tmp;
 293                 tmp = byterev_8(up[2]);
 294                 up[2] = byterev_8(up[1]);
 295                 up[1] = tmp;
 296                 break;
 297         }
 298
 299 #endif
 300         default:
 301                 WARN_ON_ONCE(1);
 302         }
 303 }
 304
 305 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 306                                             unsigned long ea, int nb,
 307                                             struct pt_regs *regs)
 308 {
 309         int err = 0;
 310         unsigned long x = 0;
 311
 312         switch (nb) {
 313         case 1:
 314                 err = __get_user(x, (unsigned char __user *) ea);
 315                 break;
 316         case 2:
 317                 err = __get_user(x, (unsigned short __user *) ea);
 318                 break;
 319         case 4:
 320                 err = __get_user(x, (unsigned int __user *) ea);
 321                 break;
 322 #ifdef __powerpc64__
 323         case 8:
 324                 err = __get_user(x, (unsigned long __user *) ea);
 325                 break;
 326 #endif
 327         }
 328         if (!err)
 329                 *dest = x;
 330         else
 331                 regs->dar = ea;
 332         return err;
 333 }
 334
 335 /*
 336  * Copy from userspace to a buffer, using the largest possible
 337  * aligned accesses, up to sizeof(long).
 338  */
 339 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 340                                        struct pt_regs *regs)
 341 {
 342         int err = 0;
 343         int c;
 344
 345         for (; nb > 0; nb -= c) {
 346                 c = max_align(ea);
 347                 if (c > nb)
 348                         c = max_align(nb);
 349                 switch (c) {
 350                 case 1:
 351                         err = __get_user(*dest, (unsigned char __user *) ea);
 352                         break;
 353                 case 2:
 354                         err = __get_user(*(u16 *)dest,
 355                                          (unsigned short __user *) ea);
 356                         break;
 357                 case 4:
 358                         err = __get_user(*(u32 *)dest,
 359                                          (unsigned int __user *) ea);
 360                         break;
 361 #ifdef __powerpc64__
 362                 case 8:
 363                         err = __get_user(*(unsigned long *)dest,
 364                                          (unsigned long __user *) ea);
 365                         break;
 366 #endif
 367                 }
 368                 if (err) {
 369                         regs->dar = ea;
 370                         return err;
 371                 }
 372                 dest += c;
 373                 ea += c;
 374         }
 375         return 0;
 376 }
 377
 378 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 379                                               unsigned long ea, int nb,
 380                                               struct pt_regs *regs)
 381 {
 382         union {
 383                 unsigned long ul;
 384                 u8 b[sizeof(unsigned long)];
 385         } u;
 386         int i;
 387         int err;
 388
 389         u.ul = 0;
 390         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 391         err = copy_mem_in(&u.b[i], ea, nb, regs);
 392         if (!err)
 393                 *dest = u.ul;
 394         return err;
 395 }
 396
 397 /*
 398  * Read memory at address ea for nb bytes, return 0 for success
 399  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 400  * If nb < sizeof(long), the result is right-justified on BE systems.
 401  */
 402 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 403                               struct pt_regs *regs)
 404 {
 405         if (!address_ok(regs, ea, nb))
 406                 return -EFAULT;
 407         if ((ea & (nb - 1)) == 0)
 408                 return read_mem_aligned(dest, ea, nb, regs);
 409         return read_mem_unaligned(dest, ea, nb, regs);
 410 }
 411 NOKPROBE_SYMBOL(read_mem);
 412
 413 static nokprobe_inline int write_mem_aligned(unsigned long val,
 414                                              unsigned long ea, int nb,
 415                                              struct pt_regs *regs)
 416 {
 417         int err = 0;
 418
 419         switch (nb) {
 420         case 1:
 421                 err = __put_user(val, (unsigned char __user *) ea);
 422                 break;
 423         case 2:
 424                 err = __put_user(val, (unsigned short __user *) ea);
 425                 break;
 426         case 4:
 427                 err = __put_user(val, (unsigned int __user *) ea);
 428                 break;
 429 #ifdef __powerpc64__
 430         case 8:
 431                 err = __put_user(val, (unsigned long __user *) ea);
 432                 break;
 433 #endif
 434         }
 435         if (err)
 436                 regs->dar = ea;
 437         return err;
 438 }
 439
 440 /*
 441  * Copy from a buffer to userspace, using the largest possible
 442  * aligned accesses, up to sizeof(long).
 443  */
 444 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 445                                         struct pt_regs *regs)
 446 {
 447         int err = 0;
 448         int c;
 449
 450         for (; nb > 0; nb -= c) {
 451                 c = max_align(ea);
 452                 if (c > nb)
 453                         c = max_align(nb);
 454                 switch (c) {
 455                 case 1:
 456                         err = __put_user(*dest, (unsigned char __user *) ea);
 457                         break;
 458                 case 2:
 459                         err = __put_user(*(u16 *)dest,
 460                                          (unsigned short __user *) ea);
 461                         break;
 462                 case 4:
 463                         err = __put_user(*(u32 *)dest,
 464                                          (unsigned int __user *) ea);
 465                         break;
 466 #ifdef __powerpc64__
 467                 case 8:
 468                         err = __put_user(*(unsigned long *)dest,
 469                                          (unsigned long __user *) ea);
 470                         break;
 471 #endif
 472                 }
 473                 if (err) {
 474                         regs->dar = ea;
 475                         return err;
 476                 }
 477                 dest += c;
 478                 ea += c;
 479         }
 480         return 0;
 481 }
 482
 483 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 484                                                unsigned long ea, int nb,
 485                                                struct pt_regs *regs)
 486 {
 487         union {
 488                 unsigned long ul;
 489                 u8 b[sizeof(unsigned long)];
 490         } u;
 491         int i;
 492
 493         u.ul = val;
 494         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 495         return copy_mem_out(&u.b[i], ea, nb, regs);
 496 }
 497
 498 /*
 499  * Write memory at address ea for nb bytes, return 0 for success
 500  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 501  */
 502 static int write_mem(unsigned long val, unsigned long ea, int nb,
 503                                struct pt_regs *regs)
 504 {
 505         if (!address_ok(regs, ea, nb))
 506                 return -EFAULT;
 507         if ((ea & (nb - 1)) == 0)
 508                 return write_mem_aligned(val, ea, nb, regs);
 509         return write_mem_unaligned(val, ea, nb, regs);
 510 }
 511 NOKPROBE_SYMBOL(write_mem);
 512
 513 #ifdef CONFIG_PPC_FPU
 514 /*
 515  * These access either the real FP register or the image in the
 516  * thread_struct, depending on regs->msr & MSR_FP.
 517  */
 518 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 519                       struct pt_regs *regs, bool cross_endian)
 520 {
 521         int err, rn, nb;
 522         union {
 523                 int i;
 524                 unsigned int u;
 525                 float f;
 526                 double d[2];
 527                 unsigned long l[2];
 528                 u8 b[2 * sizeof(double)];
 529         } u;
 530
 531         nb = GETSIZE(op->type);
 532         if (!address_ok(regs, ea, nb))
 533                 return -EFAULT;
 534         rn = op->reg;
 535         err = copy_mem_in(u.b, ea, nb, regs);
 536         if (err)
 537                 return err;
 538         if (unlikely(cross_endian)) {
 539                 do_byte_reverse(u.b, min(nb, 8));
 540                 if (nb == 16)
 541                         do_byte_reverse(&u.b[8], 8);
 542         }
 543         preempt_disable();
 544         if (nb == 4) {
 545                 if (op->type & FPCONV)
 546                         conv_sp_to_dp(&u.f, &u.d[0]);
 547                 else if (op->type & SIGNEXT)
 548                         u.l[0] = u.i;
 549                 else
 550                         u.l[0] = u.u;
 551         }
 552         if (regs->msr & MSR_FP)
 553                 put_fpr(rn, &u.d[0]);
 554         else
 555                 current->thread.TS_FPR(rn) = u.l[0];
 556         if (nb == 16) {
 557                 /* lfdp */
 558                 rn |= 1;
 559                 if (regs->msr & MSR_FP)
 560                         put_fpr(rn, &u.d[1]);
 561                 else
 562                         current->thread.TS_FPR(rn) = u.l[1];
 563         }
 564         preempt_enable();
 565         return 0;
 566 }
 567 NOKPROBE_SYMBOL(do_fp_load);
 568
 569 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 570                        struct pt_regs *regs, bool cross_endian)
 571 {
 572         int rn, nb;
 573         union {
 574                 unsigned int u;
 575                 float f;
 576                 double d[2];
 577                 unsigned long l[2];
 578                 u8 b[2 * sizeof(double)];
 579         } u;
 580
 581         nb = GETSIZE(op->type);
 582         if (!address_ok(regs, ea, nb))
 583                 return -EFAULT;
 584         rn = op->reg;
 585         preempt_disable();
 586         if (regs->msr & MSR_FP)
 587                 get_fpr(rn, &u.d[0]);
 588         else
 589                 u.l[0] = current->thread.TS_FPR(rn);
 590         if (nb == 4) {
 591                 if (op->type & FPCONV)
 592                         conv_dp_to_sp(&u.d[0], &u.f);
 593                 else
 594                         u.u = u.l[0];
 595         }
 596         if (nb == 16) {
 597                 rn |= 1;
 598                 if (regs->msr & MSR_FP)
 599                         get_fpr(rn, &u.d[1]);
 600                 else
 601                         u.l[1] = current->thread.TS_FPR(rn);
 602         }
 603         preempt_enable();
 604         if (unlikely(cross_endian)) {
 605                 do_byte_reverse(u.b, min(nb, 8));
 606                 if (nb == 16)
 607                         do_byte_reverse(&u.b[8], 8);
 608         }
 609         return copy_mem_out(u.b, ea, nb, regs);
 610 }
 611 NOKPROBE_SYMBOL(do_fp_store);
 612 #endif
 613
 614 #ifdef CONFIG_ALTIVEC
 615 /* For Altivec/VMX, no need to worry about alignment */
 616 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 617                                        int size, struct pt_regs *regs,
 618                                        bool cross_endian)
 619 {
 620         int err;
 621         union {
 622                 __vector128 v;
 623                 u8 b[sizeof(__vector128)];
 624         } u = {};
 625
 626         if (!address_ok(regs, ea & ~0xfUL, 16))
 627                 return -EFAULT;
 628         /* align to multiple of size */
 629         ea &= ~(size - 1);
 630         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 631         if (err)
 632                 return err;
 633         if (unlikely(cross_endian))
 634                 do_byte_reverse(&u.b[ea & 0xf], size);
 635         preempt_disable();
 636         if (regs->msr & MSR_VEC)
 637                 put_vr(rn, &u.v);
 638         else
 639                 current->thread.vr_state.vr[rn] = u.v;
 640         preempt_enable();
 641         return 0;
 642 }
 643
 644 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 645                                         int size, struct pt_regs *regs,
 646                                         bool cross_endian)
 647 {
 648         union {
 649                 __vector128 v;
 650                 u8 b[sizeof(__vector128)];
 651         } u;
 652
 653         if (!address_ok(regs, ea & ~0xfUL, 16))
 654                 return -EFAULT;
 655         /* align to multiple of size */
 656         ea &= ~(size - 1);
 657
 658         preempt_disable();
 659         if (regs->msr & MSR_VEC)
 660                 get_vr(rn, &u.v);
 661         else
 662                 u.v = current->thread.vr_state.vr[rn];
 663         preempt_enable();
 664         if (unlikely(cross_endian))
 665                 do_byte_reverse(&u.b[ea & 0xf], size);
 666         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 667 }
 668 #endif /* CONFIG_ALTIVEC */
 669
 670 #ifdef __powerpc64__
 671 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 672                                       int reg, bool cross_endian)
 673 {
 674         int err;
 675
 676         if (!address_ok(regs, ea, 16))
 677                 return -EFAULT;
 678         /* if aligned, should be atomic */
 679         if ((ea & 0xf) == 0) {
 680                 err = do_lq(ea, &regs->gpr[reg]);
 681         } else {
 682                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 683                 if (!err)
 684                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 685         }
 686         if (!err && unlikely(cross_endian))
 687                 do_byte_reverse(&regs->gpr[reg], 16);
 688         return err;
 689 }
 690
 691 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 692                                        int reg, bool cross_endian)
 693 {
 694         int err;
 695         unsigned long vals[2];
 696
 697         if (!address_ok(regs, ea, 16))
 698                 return -EFAULT;
 699         vals[0] = regs->gpr[reg];
 700         vals[1] = regs->gpr[reg + 1];
 701         if (unlikely(cross_endian))
 702                 do_byte_reverse(vals, 16);
 703
 704         /* if aligned, should be atomic */
 705         if ((ea & 0xf) == 0)
 706                 return do_stq(ea, vals[0], vals[1]);
 707
 708         err = write_mem(vals[IS_LE], ea, 8, regs);
 709         if (!err)
 710                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 711         return err;
 712 }
 713 #endif /* __powerpc64 */
 714
 715 #ifdef CONFIG_VSX
 716 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 717                       const void *mem, bool rev)
 718 {
 719         int size, read_size;
 720         int i, j;
 721         const unsigned int *wp;
 722         const unsigned short *hp;
 723         const unsigned char *bp;
 724
 725         size = GETSIZE(op->type);
 726         reg->d[0] = reg->d[1] = 0;
 727
 728         switch (op->element_size) {
 729         case 32:
 730                 /* [p]lxvp[x] */
 731         case 16:
 732                 /* whole vector; lxv[x] or lxvl[l] */
 733                 if (size == 0)
 734                         break;
 735                 memcpy(reg, mem, size);
 736                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 737                         rev = !rev;
 738                 if (rev)
 739                         do_byte_reverse(reg, size);
 740                 break;
 741         case 8:
 742                 /* scalar loads, lxvd2x, lxvdsx */
 743                 read_size = (size >= 8) ? 8 : size;
 744                 i = IS_LE ? 8 : 8 - read_size;
 745                 memcpy(&reg->b[i], mem, read_size);
 746                 if (rev)
 747                         do_byte_reverse(&reg->b[i], 8);
 748                 if (size < 8) {
 749                         if (op->type & SIGNEXT) {
 750                                 /* size == 4 is the only case here */
 751                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 752                         } else if (op->vsx_flags & VSX_FPCONV) {
 753                                 preempt_disable();
 754                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 755                                               &reg->dp[IS_LE]);
 756                                 preempt_enable();
 757                         }
 758                 } else {
 759                         if (size == 16) {
 760                                 unsigned long v = *(unsigned long *)(mem + 8);
 761                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 762                         } else if (op->vsx_flags & VSX_SPLAT)
 763                                 reg->d[IS_BE] = reg->d[IS_LE];
 764                 }
 765                 break;
 766         case 4:
 767                 /* lxvw4x, lxvwsx */
 768                 wp = mem;
 769                 for (j = 0; j < size / 4; ++j) {
 770                         i = IS_LE ? 3 - j : j;
 771                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 772                 }
 773                 if (op->vsx_flags & VSX_SPLAT) {
 774                         u32 val = reg->w[IS_LE ? 3 : 0];
 775                         for (; j < 4; ++j) {
 776                                 i = IS_LE ? 3 - j : j;
 777                                 reg->w[i] = val;
 778                         }
 779                 }
 780                 break;
 781         case 2:
 782                 /* lxvh8x */
 783                 hp = mem;
 784                 for (j = 0; j < size / 2; ++j) {
 785                         i = IS_LE ? 7 - j : j;
 786                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 787                 }
 788                 break;
 789         case 1:
 790                 /* lxvb16x */
 791                 bp = mem;
 792                 for (j = 0; j < size; ++j) {
 793                         i = IS_LE ? 15 - j : j;
 794                         reg->b[i] = *bp++;
 795                 }
 796                 break;
 797         }
 798 }
 799 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 800 NOKPROBE_SYMBOL(emulate_vsx_load);
 801
 802 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 803                        void *mem, bool rev)
 804 {
 805         int size, write_size;
 806         int i, j;
 807         union vsx_reg buf;
 808         unsigned int *wp;
 809         unsigned short *hp;
 810         unsigned char *bp;
 811
 812         size = GETSIZE(op->type);
 813
 814         switch (op->element_size) {
 815         case 32:
 816                 /* [p]stxvp[x] */
 817                 if (size == 0)
 818                         break;
 819                 if (rev) {
 820                         /* reverse 32 bytes */
 821                         buf.d[0] = byterev_8(reg->d[3]);
 822                         buf.d[1] = byterev_8(reg->d[2]);
 823                         buf.d[2] = byterev_8(reg->d[1]);
 824                         buf.d[3] = byterev_8(reg->d[0]);
 825                         reg = &buf;
 826                 }
 827                 memcpy(mem, reg, size);
 828                 break;
 829         case 16:
 830                 /* stxv, stxvx, stxvl, stxvll */
 831                 if (size == 0)
 832                         break;
 833                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 834                         rev = !rev;
 835                 if (rev) {
 836                         /* reverse 16 bytes */
 837                         buf.d[0] = byterev_8(reg->d[1]);
 838                         buf.d[1] = byterev_8(reg->d[0]);
 839                         reg = &buf;
 840                 }
 841                 memcpy(mem, reg, size);
 842                 break;
 843         case 8:
 844                 /* scalar stores, stxvd2x */
 845                 write_size = (size >= 8) ? 8 : size;
 846                 i = IS_LE ? 8 : 8 - write_size;
 847                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 848                         buf.d[0] = buf.d[1] = 0;
 849                         preempt_disable();
 850                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 851                         preempt_enable();
 852                         reg = &buf;
 853                 }
 854                 memcpy(mem, &reg->b[i], write_size);
 855                 if (size == 16)
 856                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 857                 if (unlikely(rev)) {
 858                         do_byte_reverse(mem, write_size);
 859                         if (size == 16)
 860                                 do_byte_reverse(mem + 8, 8);
 861                 }
 862                 break;
 863         case 4:
 864                 /* stxvw4x */
 865                 wp = mem;
 866                 for (j = 0; j < size / 4; ++j) {
 867                         i = IS_LE ? 3 - j : j;
 868                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 869                 }
 870                 break;
 871         case 2:
 872                 /* stxvh8x */
 873                 hp = mem;
 874                 for (j = 0; j < size / 2; ++j) {
 875                         i = IS_LE ? 7 - j : j;
 876                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 877                 }
 878                 break;
 879         case 1:
 880                 /* stvxb16x */
 881                 bp = mem;
 882                 for (j = 0; j < size; ++j) {
 883                         i = IS_LE ? 15 - j : j;
 884                         *bp++ = reg->b[i];
 885                 }
 886                 break;
 887         }
 888 }
 889 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 890 NOKPROBE_SYMBOL(emulate_vsx_store);
 891
 892 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 893                                        unsigned long ea, struct pt_regs *regs,
 894                                        bool cross_endian)
 895 {
 896         int reg = op->reg;
 897         int i, j, nr_vsx_regs;
 898         u8 mem[32];
 899         union vsx_reg buf[2];
 900         int size = GETSIZE(op->type);
 901
 902         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 903                 return -EFAULT;
 904
 905         nr_vsx_regs = size / sizeof(__vector128);
 906         emulate_vsx_load(op, buf, mem, cross_endian);
 907         preempt_disable();
 908         if (reg < 32) {
 909                 /* FP regs + extensions */
 910                 if (regs->msr & MSR_FP) {
 911                         for (i = 0; i < nr_vsx_regs; i++) {
 912                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 913                                 load_vsrn(reg + i, &buf[j].v);
 914                         }
 915                 } else {
 916                         for (i = 0; i < nr_vsx_regs; i++) {
 917                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 918                                 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
 919                                 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
 920                         }
 921                 }
 922         } else {
 923                 if (regs->msr & MSR_VEC) {
 924                         for (i = 0; i < nr_vsx_regs; i++) {
 925                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 926                                 load_vsrn(reg + i, &buf[j].v);
 927                         }
 928                 } else {
 929                         for (i = 0; i < nr_vsx_regs; i++) {
 930                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 931                                 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
 932                         }
 933                 }
 934         }
 935         preempt_enable();
 936         return 0;
 937 }
 938
 939 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 940                                         unsigned long ea, struct pt_regs *regs,
 941                                         bool cross_endian)
 942 {
 943         int reg = op->reg;
 944         int i, j, nr_vsx_regs;
 945         u8 mem[32];
 946         union vsx_reg buf[2];
 947         int size = GETSIZE(op->type);
 948
 949         if (!address_ok(regs, ea, size))
 950                 return -EFAULT;
 951
 952         nr_vsx_regs = size / sizeof(__vector128);
 953         preempt_disable();
 954         if (reg < 32) {
 955                 /* FP regs + extensions */
 956                 if (regs->msr & MSR_FP) {
 957                         for (i = 0; i < nr_vsx_regs; i++) {
 958                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 959                                 store_vsrn(reg + i, &buf[j].v);
 960                         }
 961                 } else {
 962                         for (i = 0; i < nr_vsx_regs; i++) {
 963                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 964                                 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
 965                                 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
 966                         }
 967                 }
 968         } else {
 969                 if (regs->msr & MSR_VEC) {
 970                         for (i = 0; i < nr_vsx_regs; i++) {
 971                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 972                                 store_vsrn(reg + i, &buf[j].v);
 973                         }
 974                 } else {
 975                         for (i = 0; i < nr_vsx_regs; i++) {
 976                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 977                                 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
 978                         }
 979                 }
 980         }
 981         preempt_enable();
 982         emulate_vsx_store(op, buf, mem, cross_endian);
 983         return  copy_mem_out(mem, ea, size, regs);
 984 }
 985 #endif /* CONFIG_VSX */
 986
 987 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 988 {
 989         int err;
 990         unsigned long i, size;
 991
 992 #ifdef __powerpc64__
 993         size = ppc64_caches.l1d.block_size;
 994         if (!(regs->msr & MSR_64BIT))
 995                 ea &= 0xffffffffUL;
 996 #else
 997         size = L1_CACHE_BYTES;
 998 #endif
 999         ea &= ~(size - 1);
1000         if (!address_ok(regs, ea, size))
1001                 return -EFAULT;
1002         for (i = 0; i < size; i += sizeof(long)) {
1003                 err = __put_user(0, (unsigned long __user *) (ea + i));
1004                 if (err) {
1005                         regs->dar = ea;
1006                         return err;
1007                 }
1008         }
1009         return 0;
1010 }
1011 NOKPROBE_SYMBOL(emulate_dcbz);
1012
1013 #define __put_user_asmx(x, addr, err, op, cr)           \
1014         __asm__ __volatile__(                           \
1015                 "1:     " op " %2,0,%3\n"               \
1016                 "       mfcr    %1\n"                   \
1017                 "2:\n"                                  \
1018                 ".section .fixup,\"ax\"\n"              \
1019                 "3:     li      %0,%4\n"                \
1020                 "       b       2b\n"                   \
1021                 ".previous\n"                           \
1022                 EX_TABLE(1b, 3b)                        \
1023                 : "=r" (err), "=r" (cr)                 \
1024                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1025
1026 #define __get_user_asmx(x, addr, err, op)               \
1027         __asm__ __volatile__(                           \
1028                 "1:     "op" %1,0,%2\n"                 \
1029                 "2:\n"                                  \
1030                 ".section .fixup,\"ax\"\n"              \
1031                 "3:     li      %0,%3\n"                \
1032                 "       b       2b\n"                   \
1033                 ".previous\n"                           \
1034                 EX_TABLE(1b, 3b)                        \
1035                 : "=r" (err), "=r" (x)                  \
1036                 : "r" (addr), "i" (-EFAULT), "0" (err))
1037
1038 #define __cacheop_user_asmx(addr, err, op)              \
1039         __asm__ __volatile__(                           \
1040                 "1:     "op" 0,%1\n"                    \
1041                 "2:\n"                                  \
1042                 ".section .fixup,\"ax\"\n"              \
1043                 "3:     li      %0,%3\n"                \
1044                 "       b       2b\n"                   \
1045                 ".previous\n"                           \
1046                 EX_TABLE(1b, 3b)                        \
1047                 : "=r" (err)                            \
1048                 : "r" (addr), "i" (-EFAULT), "0" (err))
1049
1050 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1051                                     struct instruction_op *op)
1052 {
1053         long val = op->val;
1054
1055         op->type |= SETCC;
1056         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1057 #ifdef __powerpc64__
1058         if (!(regs->msr & MSR_64BIT))
1059                 val = (int) val;
1060 #endif
1061         if (val < 0)
1062                 op->ccval |= 0x80000000;
1063         else if (val > 0)
1064                 op->ccval |= 0x40000000;
1065         else
1066                 op->ccval |= 0x20000000;
1067 }
1068
1069 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1070 {
1071         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1072                 if (val)
1073                         op->xerval |= XER_CA32;
1074                 else
1075                         op->xerval &= ~XER_CA32;
1076         }
1077 }
1078
1079 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1080                                      struct instruction_op *op, int rd,
1081                                      unsigned long val1, unsigned long val2,
1082                                      unsigned long carry_in)
1083 {
1084         unsigned long val = val1 + val2;
1085
1086         if (carry_in)
1087                 ++val;
1088         op->type = COMPUTE + SETREG + SETXER;
1089         op->reg = rd;
1090         op->val = val;
1091 #ifdef __powerpc64__
1092         if (!(regs->msr & MSR_64BIT)) {
1093                 val = (unsigned int) val;
1094                 val1 = (unsigned int) val1;
1095         }
1096 #endif
1097         op->xerval = regs->xer;
1098         if (val < val1 || (carry_in && val == val1))
1099                 op->xerval |= XER_CA;
1100         else
1101                 op->xerval &= ~XER_CA;
1102
1103         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1104                         (carry_in && (unsigned int)val == (unsigned int)val1));
1105 }
1106
1107 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1108                                           struct instruction_op *op,
1109                                           long v1, long v2, int crfld)
1110 {
1111         unsigned int crval, shift;
1112
1113         op->type = COMPUTE + SETCC;
1114         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1115         if (v1 < v2)
1116                 crval |= 8;
1117         else if (v1 > v2)
1118                 crval |= 4;
1119         else
1120                 crval |= 2;
1121         shift = (7 - crfld) * 4;
1122         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1123 }
1124
1125 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1126                                             struct instruction_op *op,
1127                                             unsigned long v1,
1128                                             unsigned long v2, int crfld)
1129 {
1130         unsigned int crval, shift;
1131
1132         op->type = COMPUTE + SETCC;
1133         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1134         if (v1 < v2)
1135                 crval |= 8;
1136         else if (v1 > v2)
1137                 crval |= 4;
1138         else
1139                 crval |= 2;
1140         shift = (7 - crfld) * 4;
1141         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1142 }
1143
1144 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1145                                     struct instruction_op *op,
1146                                     unsigned long v1, unsigned long v2)
1147 {
1148         unsigned long long out_val, mask;
1149         int i;
1150
1151         out_val = 0;
1152         for (i = 0; i < 8; i++) {
1153                 mask = 0xffUL << (i * 8);
1154                 if ((v1 & mask) == (v2 & mask))
1155                         out_val |= mask;
1156         }
1157         op->val = out_val;
1158 }
1159
1160 /*
1161  * The size parameter is used to adjust the equivalent popcnt instruction.
1162  * popcntb = 8, popcntw = 32, popcntd = 64
1163  */
1164 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1165                                       struct instruction_op *op,
1166                                       unsigned long v1, int size)
1167 {
1168         unsigned long long out = v1;
1169
1170         out -= (out >> 1) & 0x5555555555555555ULL;
1171         out = (0x3333333333333333ULL & out) +
1172               (0x3333333333333333ULL & (out >> 2));
1173         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1174
1175         if (size == 8) {        /* popcntb */
1176                 op->val = out;
1177                 return;
1178         }
1179         out += out >> 8;
1180         out += out >> 16;
1181         if (size == 32) {       /* popcntw */
1182                 op->val = out & 0x0000003f0000003fULL;
1183                 return;
1184         }
1185
1186         out = (out + (out >> 32)) & 0x7f;
1187         op->val = out;  /* popcntd */
1188 }
1189
1190 #ifdef CONFIG_PPC64
1191 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1192                                       struct instruction_op *op,
1193                                       unsigned long v1, unsigned long v2)
1194 {
1195         unsigned char perm, idx;
1196         unsigned int i;
1197
1198         perm = 0;
1199         for (i = 0; i < 8; i++) {
1200                 idx = (v1 >> (i * 8)) & 0xff;
1201                 if (idx < 64)
1202                         if (v2 & PPC_BIT(idx))
1203                                 perm |= 1 << i;
1204         }
1205         op->val = perm;
1206 }
1207 #endif /* CONFIG_PPC64 */
1208 /*
1209  * The size parameter adjusts the equivalent prty instruction.
1210  * prtyw = 32, prtyd = 64
1211  */
1212 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1213                                     struct instruction_op *op,
1214                                     unsigned long v, int size)
1215 {
1216         unsigned long long res = v ^ (v >> 8);
1217
1218         res ^= res >> 16;
1219         if (size == 32) {               /* prtyw */
1220                 op->val = res & 0x0000000100000001ULL;
1221                 return;
1222         }
1223
1224         res ^= res >> 32;
1225         op->val = res & 1;      /*prtyd */
1226 }
1227
1228 static nokprobe_inline int trap_compare(long v1, long v2)
1229 {
1230         int ret = 0;
1231
1232         if (v1 < v2)
1233                 ret |= 0x10;
1234         else if (v1 > v2)
1235                 ret |= 0x08;
1236         else
1237                 ret |= 0x04;
1238         if ((unsigned long)v1 < (unsigned long)v2)
1239                 ret |= 0x02;
1240         else if ((unsigned long)v1 > (unsigned long)v2)
1241                 ret |= 0x01;
1242         return ret;
1243 }
1244
1245 /*
1246  * Elements of 32-bit rotate and mask instructions.
1247  */
1248 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1249                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1250 #ifdef __powerpc64__
1251 #define MASK64_L(mb)    (~0UL >> (mb))
1252 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1253 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1254 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1255 #else
1256 #define DATA32(x)       (x)
1257 #endif
1258 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1259
1260 /*
1261  * Decode an instruction, and return information about it in *op
1262  * without changing *regs.
1263  * Integer arithmetic and logical instructions, branches, and barrier
1264  * instructions can be emulated just using the information in *op.
1265  *
1266  * Return value is 1 if the instruction can be emulated just by
1267  * updating *regs with the information in *op, -1 if we need the
1268  * GPRs but *regs doesn't contain the full register set, or 0
1269  * otherwise.
1270  */
1271 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1272                   struct ppc_inst instr)
1273 {
1274 #ifdef CONFIG_PPC64
1275         unsigned int suffixopcode, prefixtype, prefix_r;
1276 #endif
1277         unsigned int opcode, ra, rb, rc, rd, spr, u;
1278         unsigned long int imm;
1279         unsigned long int val, val2;
1280         unsigned int mb, me, sh;
1281         unsigned int word, suffix;
1282         long ival;
1283
1284         word = ppc_inst_val(instr);
1285         suffix = ppc_inst_suffix(instr);
1286
1287         op->type = COMPUTE;
1288
1289         opcode = ppc_inst_primary_opcode(instr);
1290         switch (opcode) {
1291         case 16:        /* bc */
1292                 op->type = BRANCH;
1293                 imm = (signed short)(word & 0xfffc);
1294                 if ((word & 2) == 0)
1295                         imm += regs->nip;
1296                 op->val = truncate_if_32bit(regs->msr, imm);
1297                 if (word & 1)
1298                         op->type |= SETLK;
1299                 if (branch_taken(word, regs, op))
1300                         op->type |= BRTAKEN;
1301                 return 1;
1302 #ifdef CONFIG_PPC64
1303         case 17:        /* sc */
1304                 if ((word & 0xfe2) == 2)
1305                         op->type = SYSCALL;
1306                 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1307                                 (word & 0xfe3) == 1) {  /* scv */
1308                         op->type = SYSCALL_VECTORED_0;
1309                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1310                                 goto unknown_opcode;
1311                 } else
1312                         op->type = UNKNOWN;
1313                 return 0;
1314 #endif
1315         case 18:        /* b */
1316                 op->type = BRANCH | BRTAKEN;
1317                 imm = word & 0x03fffffc;
1318                 if (imm & 0x02000000)
1319                         imm -= 0x04000000;
1320                 if ((word & 2) == 0)
1321                         imm += regs->nip;
1322                 op->val = truncate_if_32bit(regs->msr, imm);
1323                 if (word & 1)
1324                         op->type |= SETLK;
1325                 return 1;
1326         case 19:
1327                 switch ((word >> 1) & 0x3ff) {
1328                 case 0:         /* mcrf */
1329                         op->type = COMPUTE + SETCC;
1330                         rd = 7 - ((word >> 23) & 0x7);
1331                         ra = 7 - ((word >> 18) & 0x7);
1332                         rd *= 4;
1333                         ra *= 4;
1334                         val = (regs->ccr >> ra) & 0xf;
1335                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1336                         return 1;
1337
1338                 case 16:        /* bclr */
1339                 case 528:       /* bcctr */
1340                         op->type = BRANCH;
1341                         imm = (word & 0x400)? regs->ctr: regs->link;
1342                         op->val = truncate_if_32bit(regs->msr, imm);
1343                         if (word & 1)
1344                                 op->type |= SETLK;
1345                         if (branch_taken(word, regs, op))
1346                                 op->type |= BRTAKEN;
1347                         return 1;
1348
1349                 case 18:        /* rfid, scary */
1350                         if (regs->msr & MSR_PR)
1351                                 goto priv;
1352                         op->type = RFI;
1353                         return 0;
1354
1355                 case 150:       /* isync */
1356                         op->type = BARRIER | BARRIER_ISYNC;
1357                         return 1;
1358
1359                 case 33:        /* crnor */
1360                 case 129:       /* crandc */
1361                 case 193:       /* crxor */
1362                 case 225:       /* crnand */
1363                 case 257:       /* crand */
1364                 case 289:       /* creqv */
1365                 case 417:       /* crorc */
1366                 case 449:       /* cror */
1367                         op->type = COMPUTE + SETCC;
1368                         ra = (word >> 16) & 0x1f;
1369                         rb = (word >> 11) & 0x1f;
1370                         rd = (word >> 21) & 0x1f;
1371                         ra = (regs->ccr >> (31 - ra)) & 1;
1372                         rb = (regs->ccr >> (31 - rb)) & 1;
1373                         val = (word >> (6 + ra * 2 + rb)) & 1;
1374                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1375                                 (val << (31 - rd));
1376                         return 1;
1377                 }
1378                 break;
1379         case 31:
1380                 switch ((word >> 1) & 0x3ff) {
1381                 case 598:       /* sync */
1382                         op->type = BARRIER + BARRIER_SYNC;
1383 #ifdef __powerpc64__
1384                         switch ((word >> 21) & 3) {
1385                         case 1:         /* lwsync */
1386                                 op->type = BARRIER + BARRIER_LWSYNC;
1387                                 break;
1388                         case 2:         /* ptesync */
1389                                 op->type = BARRIER + BARRIER_PTESYNC;
1390                                 break;
1391                         }
1392 #endif
1393                         return 1;
1394
1395                 case 854:       /* eieio */
1396                         op->type = BARRIER + BARRIER_EIEIO;
1397                         return 1;
1398                 }
1399                 break;
1400         }
1401
1402         /* Following cases refer to regs->gpr[], so we need all regs */
1403         if (!FULL_REGS(regs))
1404                 return -1;
1405
1406         rd = (word >> 21) & 0x1f;
1407         ra = (word >> 16) & 0x1f;
1408         rb = (word >> 11) & 0x1f;
1409         rc = (word >> 6) & 0x1f;
1410
1411         switch (opcode) {
1412 #ifdef __powerpc64__
1413         case 1:
1414                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1415                         goto unknown_opcode;
1416
1417                 prefix_r = GET_PREFIX_R(word);
1418                 ra = GET_PREFIX_RA(suffix);
1419                 rd = (suffix >> 21) & 0x1f;
1420                 op->reg = rd;
1421                 op->val = regs->gpr[rd];
1422                 suffixopcode = get_op(suffix);
1423                 prefixtype = (word >> 24) & 0x3;
1424                 switch (prefixtype) {
1425                 case 2:
1426                         if (prefix_r && ra)
1427                                 return 0;
1428                         switch (suffixopcode) {
1429                         case 14:        /* paddi */
1430                                 op->type = COMPUTE | PREFIXED;
1431                                 op->val = mlsd_8lsd_ea(word, suffix, regs);
1432                                 goto compute_done;
1433                         }
1434                 }
1435                 break;
1436         case 2:         /* tdi */
1437                 if (rd & trap_compare(regs->gpr[ra], (short) word))
1438                         goto trap;
1439                 return 1;
1440 #endif
1441         case 3:         /* twi */
1442                 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1443                         goto trap;
1444                 return 1;
1445
1446 #ifdef __powerpc64__
1447         case 4:
1448                 /*
1449                  * There are very many instructions with this primary opcode
1450                  * introduced in the ISA as early as v2.03. However, the ones
1451                  * we currently emulate were all introduced with ISA 3.0
1452                  */
1453                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1454                         goto unknown_opcode;
1455
1456                 switch (word & 0x3f) {
1457                 case 48:        /* maddhd */
1458                         asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1459                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1460                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1461                         goto compute_done;
1462
1463                 case 49:        /* maddhdu */
1464                         asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1465                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1466                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1467                         goto compute_done;
1468
1469                 case 51:        /* maddld */
1470                         asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1471                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1472                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1473                         goto compute_done;
1474                 }
1475
1476                 /*
1477                  * There are other instructions from ISA 3.0 with the same
1478                  * primary opcode which do not have emulation support yet.
1479                  */
1480                 goto unknown_opcode;
1481 #endif
1482
1483         case 7:         /* mulli */
1484                 op->val = regs->gpr[ra] * (short) word;
1485                 goto compute_done;
1486
1487         case 8:         /* subfic */
1488                 imm = (short) word;
1489                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1490                 return 1;
1491
1492         case 10:        /* cmpli */
1493                 imm = (unsigned short) word;
1494                 val = regs->gpr[ra];
1495 #ifdef __powerpc64__
1496                 if ((rd & 1) == 0)
1497                         val = (unsigned int) val;
1498 #endif
1499                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1500                 return 1;
1501
1502         case 11:        /* cmpi */
1503                 imm = (short) word;
1504                 val = regs->gpr[ra];
1505 #ifdef __powerpc64__
1506                 if ((rd & 1) == 0)
1507                         val = (int) val;
1508 #endif
1509                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1510                 return 1;
1511
1512         case 12:        /* addic */
1513                 imm = (short) word;
1514                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1515                 return 1;
1516
1517         case 13:        /* addic. */
1518                 imm = (short) word;
1519                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1520                 set_cr0(regs, op);
1521                 return 1;
1522
1523         case 14:        /* addi */
1524                 imm = (short) word;
1525                 if (ra)
1526                         imm += regs->gpr[ra];
1527                 op->val = imm;
1528                 goto compute_done;
1529
1530         case 15:        /* addis */
1531                 imm = ((short) word) << 16;
1532                 if (ra)
1533                         imm += regs->gpr[ra];
1534                 op->val = imm;
1535                 goto compute_done;
1536
1537         case 19:
1538                 if (((word >> 1) & 0x1f) == 2) {
1539                         /* addpcis */
1540                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1541                                 goto unknown_opcode;
1542                         imm = (short) (word & 0xffc1);  /* d0 + d2 fields */
1543                         imm |= (word >> 15) & 0x3e;     /* d1 field */
1544                         op->val = regs->nip + (imm << 16) + 4;
1545                         goto compute_done;
1546                 }
1547                 op->type = UNKNOWN;
1548                 return 0;
1549
1550         case 20:        /* rlwimi */
1551                 mb = (word >> 6) & 0x1f;
1552                 me = (word >> 1) & 0x1f;
1553                 val = DATA32(regs->gpr[rd]);
1554                 imm = MASK32(mb, me);
1555                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1556                 goto logical_done;
1557
1558         case 21:        /* rlwinm */
1559                 mb = (word >> 6) & 0x1f;
1560                 me = (word >> 1) & 0x1f;
1561                 val = DATA32(regs->gpr[rd]);
1562                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1563                 goto logical_done;
1564
1565         case 23:        /* rlwnm */
1566                 mb = (word >> 6) & 0x1f;
1567                 me = (word >> 1) & 0x1f;
1568                 rb = regs->gpr[rb] & 0x1f;
1569                 val = DATA32(regs->gpr[rd]);
1570                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1571                 goto logical_done;
1572
1573         case 24:        /* ori */
1574                 op->val = regs->gpr[rd] | (unsigned short) word;
1575                 goto logical_done_nocc;
1576
1577         case 25:        /* oris */
1578                 imm = (unsigned short) word;
1579                 op->val = regs->gpr[rd] | (imm << 16);
1580                 goto logical_done_nocc;
1581
1582         case 26:        /* xori */
1583                 op->val = regs->gpr[rd] ^ (unsigned short) word;
1584                 goto logical_done_nocc;
1585
1586         case 27:        /* xoris */
1587                 imm = (unsigned short) word;
1588                 op->val = regs->gpr[rd] ^ (imm << 16);
1589                 goto logical_done_nocc;
1590
1591         case 28:        /* andi. */
1592                 op->val = regs->gpr[rd] & (unsigned short) word;
1593                 set_cr0(regs, op);
1594                 goto logical_done_nocc;
1595
1596         case 29:        /* andis. */
1597                 imm = (unsigned short) word;
1598                 op->val = regs->gpr[rd] & (imm << 16);
1599                 set_cr0(regs, op);
1600                 goto logical_done_nocc;
1601
1602 #ifdef __powerpc64__
1603         case 30:        /* rld* */
1604                 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1605                 val = regs->gpr[rd];
1606                 if ((word & 0x10) == 0) {
1607                         sh = rb | ((word & 2) << 4);
1608                         val = ROTATE(val, sh);
1609                         switch ((word >> 2) & 3) {
1610                         case 0:         /* rldicl */
1611                                 val &= MASK64_L(mb);
1612                                 break;
1613                         case 1:         /* rldicr */
1614                                 val &= MASK64_R(mb);
1615                                 break;
1616                         case 2:         /* rldic */
1617                                 val &= MASK64(mb, 63 - sh);
1618                                 break;
1619                         case 3:         /* rldimi */
1620                                 imm = MASK64(mb, 63 - sh);
1621                                 val = (regs->gpr[ra] & ~imm) |
1622                                         (val & imm);
1623                         }
1624                         op->val = val;
1625                         goto logical_done;
1626                 } else {
1627                         sh = regs->gpr[rb] & 0x3f;
1628                         val = ROTATE(val, sh);
1629                         switch ((word >> 1) & 7) {
1630                         case 0:         /* rldcl */
1631                                 op->val = val & MASK64_L(mb);
1632                                 goto logical_done;
1633                         case 1:         /* rldcr */
1634                                 op->val = val & MASK64_R(mb);
1635                                 goto logical_done;
1636                         }
1637                 }
1638 #endif
1639                 op->type = UNKNOWN;     /* illegal instruction */
1640                 return 0;
1641
1642         case 31:
1643                 /* isel occupies 32 minor opcodes */
1644                 if (((word >> 1) & 0x1f) == 15) {
1645                         mb = (word >> 6) & 0x1f; /* bc field */
1646                         val = (regs->ccr >> (31 - mb)) & 1;
1647                         val2 = (ra) ? regs->gpr[ra] : 0;
1648
1649                         op->val = (val) ? val2 : regs->gpr[rb];
1650                         goto compute_done;
1651                 }
1652
1653                 switch ((word >> 1) & 0x3ff) {
1654                 case 4:         /* tw */
1655                         if (rd == 0x1f ||
1656                             (rd & trap_compare((int)regs->gpr[ra],
1657                                                (int)regs->gpr[rb])))
1658                                 goto trap;
1659                         return 1;
1660 #ifdef __powerpc64__
1661                 case 68:        /* td */
1662                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1663                                 goto trap;
1664                         return 1;
1665 #endif
1666                 case 83:        /* mfmsr */
1667                         if (regs->msr & MSR_PR)
1668                                 goto priv;
1669                         op->type = MFMSR;
1670                         op->reg = rd;
1671                         return 0;
1672                 case 146:       /* mtmsr */
1673                         if (regs->msr & MSR_PR)
1674                                 goto priv;
1675                         op->type = MTMSR;
1676                         op->reg = rd;
1677                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1678                         return 0;
1679 #ifdef CONFIG_PPC64
1680                 case 178:       /* mtmsrd */
1681                         if (regs->msr & MSR_PR)
1682                                 goto priv;
1683                         op->type = MTMSR;
1684                         op->reg = rd;
1685                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1686                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1687                         imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1688                         op->val = imm;
1689                         return 0;
1690 #endif
1691
1692                 case 19:        /* mfcr */
1693                         imm = 0xffffffffUL;
1694                         if ((word >> 20) & 1) {
1695                                 imm = 0xf0000000UL;
1696                                 for (sh = 0; sh < 8; ++sh) {
1697                                         if (word & (0x80000 >> sh))
1698                                                 break;
1699                                         imm >>= 4;
1700                                 }
1701                         }
1702                         op->val = regs->ccr & imm;
1703                         goto compute_done;
1704
1705                 case 144:       /* mtcrf */
1706                         op->type = COMPUTE + SETCC;
1707                         imm = 0xf0000000UL;
1708                         val = regs->gpr[rd];
1709                         op->ccval = regs->ccr;
1710                         for (sh = 0; sh < 8; ++sh) {
1711                                 if (word & (0x80000 >> sh))
1712                                         op->ccval = (op->ccval & ~imm) |
1713                                                 (val & imm);
1714                                 imm >>= 4;
1715                         }
1716                         return 1;
1717
1718                 case 339:       /* mfspr */
1719                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1720                         op->type = MFSPR;
1721                         op->reg = rd;
1722                         op->spr = spr;
1723                         if (spr == SPRN_XER || spr == SPRN_LR ||
1724                             spr == SPRN_CTR)
1725                                 return 1;
1726                         return 0;
1727
1728                 case 467:       /* mtspr */
1729                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1730                         op->type = MTSPR;
1731                         op->val = regs->gpr[rd];
1732                         op->spr = spr;
1733                         if (spr == SPRN_XER || spr == SPRN_LR ||
1734                             spr == SPRN_CTR)
1735                                 return 1;
1736                         return 0;
1737
1738 /*
1739  * Compare instructions
1740  */
1741                 case 0: /* cmp */
1742                         val = regs->gpr[ra];
1743                         val2 = regs->gpr[rb];
1744 #ifdef __powerpc64__
1745                         if ((rd & 1) == 0) {
1746                                 /* word (32-bit) compare */
1747                                 val = (int) val;
1748                                 val2 = (int) val2;
1749                         }
1750 #endif
1751                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1752                         return 1;
1753
1754                 case 32:        /* cmpl */
1755                         val = regs->gpr[ra];
1756                         val2 = regs->gpr[rb];
1757 #ifdef __powerpc64__
1758                         if ((rd & 1) == 0) {
1759                                 /* word (32-bit) compare */
1760                                 val = (unsigned int) val;
1761                                 val2 = (unsigned int) val2;
1762                         }
1763 #endif
1764                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1765                         return 1;
1766
1767                 case 508: /* cmpb */
1768                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1769                         goto logical_done_nocc;
1770
1771 /*
1772  * Arithmetic instructions
1773  */
1774                 case 8: /* subfc */
1775                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1776                                        regs->gpr[rb], 1);
1777                         goto arith_done;
1778 #ifdef __powerpc64__
1779                 case 9: /* mulhdu */
1780                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1781                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1782                         goto arith_done;
1783 #endif
1784                 case 10:        /* addc */
1785                         add_with_carry(regs, op, rd, regs->gpr[ra],
1786                                        regs->gpr[rb], 0);
1787                         goto arith_done;
1788
1789                 case 11:        /* mulhwu */
1790                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1791                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1792                         goto arith_done;
1793
1794                 case 40:        /* subf */
1795                         op->val = regs->gpr[rb] - regs->gpr[ra];
1796                         goto arith_done;
1797 #ifdef __powerpc64__
1798                 case 73:        /* mulhd */
1799                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1800                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1801                         goto arith_done;
1802 #endif
1803                 case 75:        /* mulhw */
1804                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1805                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1806                         goto arith_done;
1807
1808                 case 104:       /* neg */
1809                         op->val = -regs->gpr[ra];
1810                         goto arith_done;
1811
1812                 case 136:       /* subfe */
1813                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1814                                        regs->gpr[rb], regs->xer & XER_CA);
1815                         goto arith_done;
1816
1817                 case 138:       /* adde */
1818                         add_with_carry(regs, op, rd, regs->gpr[ra],
1819                                        regs->gpr[rb], regs->xer & XER_CA);
1820                         goto arith_done;
1821
1822                 case 200:       /* subfze */
1823                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1824                                        regs->xer & XER_CA);
1825                         goto arith_done;
1826
1827                 case 202:       /* addze */
1828                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1829                                        regs->xer & XER_CA);
1830                         goto arith_done;
1831
1832                 case 232:       /* subfme */
1833                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1834                                        regs->xer & XER_CA);
1835                         goto arith_done;
1836 #ifdef __powerpc64__
1837                 case 233:       /* mulld */
1838                         op->val = regs->gpr[ra] * regs->gpr[rb];
1839                         goto arith_done;
1840 #endif
1841                 case 234:       /* addme */
1842                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1843                                        regs->xer & XER_CA);
1844                         goto arith_done;
1845
1846                 case 235:       /* mullw */
1847                         op->val = (long)(int) regs->gpr[ra] *
1848                                 (int) regs->gpr[rb];
1849
1850                         goto arith_done;
1851 #ifdef __powerpc64__
1852                 case 265:       /* modud */
1853                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1854                                 goto unknown_opcode;
1855                         op->val = regs->gpr[ra] % regs->gpr[rb];
1856                         goto compute_done;
1857 #endif
1858                 case 266:       /* add */
1859                         op->val = regs->gpr[ra] + regs->gpr[rb];
1860                         goto arith_done;
1861
1862                 case 267:       /* moduw */
1863                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1864                                 goto unknown_opcode;
1865                         op->val = (unsigned int) regs->gpr[ra] %
1866                                 (unsigned int) regs->gpr[rb];
1867                         goto compute_done;
1868 #ifdef __powerpc64__
1869                 case 457:       /* divdu */
1870                         op->val = regs->gpr[ra] / regs->gpr[rb];
1871                         goto arith_done;
1872 #endif
1873                 case 459:       /* divwu */
1874                         op->val = (unsigned int) regs->gpr[ra] /
1875                                 (unsigned int) regs->gpr[rb];
1876                         goto arith_done;
1877 #ifdef __powerpc64__
1878                 case 489:       /* divd */
1879                         op->val = (long int) regs->gpr[ra] /
1880                                 (long int) regs->gpr[rb];
1881                         goto arith_done;
1882 #endif
1883                 case 491:       /* divw */
1884                         op->val = (int) regs->gpr[ra] /
1885                                 (int) regs->gpr[rb];
1886                         goto arith_done;
1887 #ifdef __powerpc64__
1888                 case 425:       /* divde[.] */
1889                         asm volatile(PPC_DIVDE(%0, %1, %2) :
1890                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1891                                 "r" (regs->gpr[rb]));
1892                         goto arith_done;
1893                 case 393:       /* divdeu[.] */
1894                         asm volatile(PPC_DIVDEU(%0, %1, %2) :
1895                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1896                                 "r" (regs->gpr[rb]));
1897                         goto arith_done;
1898 #endif
1899                 case 755:       /* darn */
1900                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1901                                 goto unknown_opcode;
1902                         switch (ra & 0x3) {
1903                         case 0:
1904                                 /* 32-bit conditioned */
1905                                 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1906                                 goto compute_done;
1907
1908                         case 1:
1909                                 /* 64-bit conditioned */
1910                                 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1911                                 goto compute_done;
1912
1913                         case 2:
1914                                 /* 64-bit raw */
1915                                 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1916                                 goto compute_done;
1917                         }
1918
1919                         return -1;
1920 #ifdef __powerpc64__
1921                 case 777:       /* modsd */
1922                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1923                                 goto unknown_opcode;
1924                         op->val = (long int) regs->gpr[ra] %
1925                                 (long int) regs->gpr[rb];
1926                         goto compute_done;
1927 #endif
1928                 case 779:       /* modsw */
1929                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1930                                 goto unknown_opcode;
1931                         op->val = (int) regs->gpr[ra] %
1932                                 (int) regs->gpr[rb];
1933                         goto compute_done;
1934
1935
1936 /*
1937  * Logical instructions
1938  */
1939                 case 26:        /* cntlzw */
1940                         val = (unsigned int) regs->gpr[rd];
1941                         op->val = ( val ? __builtin_clz(val) : 32 );
1942                         goto logical_done;
1943 #ifdef __powerpc64__
1944                 case 58:        /* cntlzd */
1945                         val = regs->gpr[rd];
1946                         op->val = ( val ? __builtin_clzl(val) : 64 );
1947                         goto logical_done;
1948 #endif
1949                 case 28:        /* and */
1950                         op->val = regs->gpr[rd] & regs->gpr[rb];
1951                         goto logical_done;
1952
1953                 case 60:        /* andc */
1954                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1955                         goto logical_done;
1956
1957                 case 122:       /* popcntb */
1958                         do_popcnt(regs, op, regs->gpr[rd], 8);
1959                         goto logical_done_nocc;
1960
1961                 case 124:       /* nor */
1962                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1963                         goto logical_done;
1964
1965                 case 154:       /* prtyw */
1966                         do_prty(regs, op, regs->gpr[rd], 32);
1967                         goto logical_done_nocc;
1968
1969                 case 186:       /* prtyd */
1970                         do_prty(regs, op, regs->gpr[rd], 64);
1971                         goto logical_done_nocc;
1972 #ifdef CONFIG_PPC64
1973                 case 252:       /* bpermd */
1974                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1975                         goto logical_done_nocc;
1976 #endif
1977                 case 284:       /* xor */
1978                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1979                         goto logical_done;
1980
1981                 case 316:       /* xor */
1982                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1983                         goto logical_done;
1984
1985                 case 378:       /* popcntw */
1986                         do_popcnt(regs, op, regs->gpr[rd], 32);
1987                         goto logical_done_nocc;
1988
1989                 case 412:       /* orc */
1990                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1991                         goto logical_done;
1992
1993                 case 444:       /* or */
1994                         op->val = regs->gpr[rd] | regs->gpr[rb];
1995                         goto logical_done;
1996
1997                 case 476:       /* nand */
1998                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1999                         goto logical_done;
2000 #ifdef CONFIG_PPC64
2001                 case 506:       /* popcntd */
2002                         do_popcnt(regs, op, regs->gpr[rd], 64);
2003                         goto logical_done_nocc;
2004 #endif
2005                 case 538:       /* cnttzw */
2006                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2007                                 goto unknown_opcode;
2008                         val = (unsigned int) regs->gpr[rd];
2009                         op->val = (val ? __builtin_ctz(val) : 32);
2010                         goto logical_done;
2011 #ifdef __powerpc64__
2012                 case 570:       /* cnttzd */
2013                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2014                                 goto unknown_opcode;
2015                         val = regs->gpr[rd];
2016                         op->val = (val ? __builtin_ctzl(val) : 64);
2017                         goto logical_done;
2018 #endif
2019                 case 922:       /* extsh */
2020                         op->val = (signed short) regs->gpr[rd];
2021                         goto logical_done;
2022
2023                 case 954:       /* extsb */
2024                         op->val = (signed char) regs->gpr[rd];
2025                         goto logical_done;
2026 #ifdef __powerpc64__
2027                 case 986:       /* extsw */
2028                         op->val = (signed int) regs->gpr[rd];
2029                         goto logical_done;
2030 #endif
2031
2032 /*
2033  * Shift instructions
2034  */
2035                 case 24:        /* slw */
2036                         sh = regs->gpr[rb] & 0x3f;
2037                         if (sh < 32)
2038                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2039                         else
2040                                 op->val = 0;
2041                         goto logical_done;
2042
2043                 case 536:       /* srw */
2044                         sh = regs->gpr[rb] & 0x3f;
2045                         if (sh < 32)
2046                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2047                         else
2048                                 op->val = 0;
2049                         goto logical_done;
2050
2051                 case 792:       /* sraw */
2052                         op->type = COMPUTE + SETREG + SETXER;
2053                         sh = regs->gpr[rb] & 0x3f;
2054                         ival = (signed int) regs->gpr[rd];
2055                         op->val = ival >> (sh < 32 ? sh : 31);
2056                         op->xerval = regs->xer;
2057                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2058                                 op->xerval |= XER_CA;
2059                         else
2060                                 op->xerval &= ~XER_CA;
2061                         set_ca32(op, op->xerval & XER_CA);
2062                         goto logical_done;
2063
2064                 case 824:       /* srawi */
2065                         op->type = COMPUTE + SETREG + SETXER;
2066                         sh = rb;
2067                         ival = (signed int) regs->gpr[rd];
2068                         op->val = ival >> sh;
2069                         op->xerval = regs->xer;
2070                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2071                                 op->xerval |= XER_CA;
2072                         else
2073                                 op->xerval &= ~XER_CA;
2074                         set_ca32(op, op->xerval & XER_CA);
2075                         goto logical_done;
2076
2077 #ifdef __powerpc64__
2078                 case 27:        /* sld */
2079                         sh = regs->gpr[rb] & 0x7f;
2080                         if (sh < 64)
2081                                 op->val = regs->gpr[rd] << sh;
2082                         else
2083                                 op->val = 0;
2084                         goto logical_done;
2085
2086                 case 539:       /* srd */
2087                         sh = regs->gpr[rb] & 0x7f;
2088                         if (sh < 64)
2089                                 op->val = regs->gpr[rd] >> sh;
2090                         else
2091                                 op->val = 0;
2092                         goto logical_done;
2093
2094                 case 794:       /* srad */
2095                         op->type = COMPUTE + SETREG + SETXER;
2096                         sh = regs->gpr[rb] & 0x7f;
2097                         ival = (signed long int) regs->gpr[rd];
2098                         op->val = ival >> (sh < 64 ? sh : 63);
2099                         op->xerval = regs->xer;
2100                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2101                                 op->xerval |= XER_CA;
2102                         else
2103                                 op->xerval &= ~XER_CA;
2104                         set_ca32(op, op->xerval & XER_CA);
2105                         goto logical_done;
2106
2107                 case 826:       /* sradi with sh_5 = 0 */
2108                 case 827:       /* sradi with sh_5 = 1 */
2109                         op->type = COMPUTE + SETREG + SETXER;
2110                         sh = rb | ((word & 2) << 4);
2111                         ival = (signed long int) regs->gpr[rd];
2112                         op->val = ival >> sh;
2113                         op->xerval = regs->xer;
2114                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2115                                 op->xerval |= XER_CA;
2116                         else
2117                                 op->xerval &= ~XER_CA;
2118                         set_ca32(op, op->xerval & XER_CA);
2119                         goto logical_done;
2120
2121                 case 890:       /* extswsli with sh_5 = 0 */
2122                 case 891:       /* extswsli with sh_5 = 1 */
2123                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2124                                 goto unknown_opcode;
2125                         op->type = COMPUTE + SETREG;
2126                         sh = rb | ((word & 2) << 4);
2127                         val = (signed int) regs->gpr[rd];
2128                         if (sh)
2129                                 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2130                         else
2131                                 op->val = val;
2132                         goto logical_done;
2133
2134 #endif /* __powerpc64__ */
2135
2136 /*
2137  * Cache instructions
2138  */
2139                 case 54:        /* dcbst */
2140                         op->type = MKOP(CACHEOP, DCBST, 0);
2141                         op->ea = xform_ea(word, regs);
2142                         return 0;
2143
2144                 case 86:        /* dcbf */
2145                         op->type = MKOP(CACHEOP, DCBF, 0);
2146                         op->ea = xform_ea(word, regs);
2147                         return 0;
2148
2149                 case 246:       /* dcbtst */
2150                         op->type = MKOP(CACHEOP, DCBTST, 0);
2151                         op->ea = xform_ea(word, regs);
2152                         op->reg = rd;
2153                         return 0;
2154
2155                 case 278:       /* dcbt */
2156                         op->type = MKOP(CACHEOP, DCBTST, 0);
2157                         op->ea = xform_ea(word, regs);
2158                         op->reg = rd;
2159                         return 0;
2160
2161                 case 982:       /* icbi */
2162                         op->type = MKOP(CACHEOP, ICBI, 0);
2163                         op->ea = xform_ea(word, regs);
2164                         return 0;
2165
2166                 case 1014:      /* dcbz */
2167                         op->type = MKOP(CACHEOP, DCBZ, 0);
2168                         op->ea = xform_ea(word, regs);
2169                         return 0;
2170                 }
2171                 break;
2172         }
2173
2174 /*
2175  * Loads and stores.
2176  */
2177         op->type = UNKNOWN;
2178         op->update_reg = ra;
2179         op->reg = rd;
2180         op->val = regs->gpr[rd];
2181         u = (word >> 20) & UPDATE;
2182         op->vsx_flags = 0;
2183
2184         switch (opcode) {
2185         case 31:
2186                 u = word & UPDATE;
2187                 op->ea = xform_ea(word, regs);
2188                 switch ((word >> 1) & 0x3ff) {
2189                 case 20:        /* lwarx */
2190                         op->type = MKOP(LARX, 0, 4);
2191                         break;
2192
2193                 case 150:       /* stwcx. */
2194                         op->type = MKOP(STCX, 0, 4);
2195                         break;
2196
2197 #ifdef __powerpc64__
2198                 case 84:        /* ldarx */
2199                         op->type = MKOP(LARX, 0, 8);
2200                         break;
2201
2202                 case 214:       /* stdcx. */
2203                         op->type = MKOP(STCX, 0, 8);
2204                         break;
2205
2206                 case 52:        /* lbarx */
2207                         op->type = MKOP(LARX, 0, 1);
2208                         break;
2209
2210                 case 694:       /* stbcx. */
2211                         op->type = MKOP(STCX, 0, 1);
2212                         break;
2213
2214                 case 116:       /* lharx */
2215                         op->type = MKOP(LARX, 0, 2);
2216                         break;
2217
2218                 case 726:       /* sthcx. */
2219                         op->type = MKOP(STCX, 0, 2);
2220                         break;
2221
2222                 case 276:       /* lqarx */
2223                         if (!((rd & 1) || rd == ra || rd == rb))
2224                                 op->type = MKOP(LARX, 0, 16);
2225                         break;
2226
2227                 case 182:       /* stqcx. */
2228                         if (!(rd & 1))
2229                                 op->type = MKOP(STCX, 0, 16);
2230                         break;
2231 #endif
2232
2233                 case 23:        /* lwzx */
2234                 case 55:        /* lwzux */
2235                         op->type = MKOP(LOAD, u, 4);
2236                         break;
2237
2238                 case 87:        /* lbzx */
2239                 case 119:       /* lbzux */
2240                         op->type = MKOP(LOAD, u, 1);
2241                         break;
2242
2243 #ifdef CONFIG_ALTIVEC
2244                 /*
2245                  * Note: for the load/store vector element instructions,
2246                  * bits of the EA say which field of the VMX register to use.
2247                  */
2248                 case 7:         /* lvebx */
2249                         op->type = MKOP(LOAD_VMX, 0, 1);
2250                         op->element_size = 1;
2251                         break;
2252
2253                 case 39:        /* lvehx */
2254                         op->type = MKOP(LOAD_VMX, 0, 2);
2255                         op->element_size = 2;
2256                         break;
2257
2258                 case 71:        /* lvewx */
2259                         op->type = MKOP(LOAD_VMX, 0, 4);
2260                         op->element_size = 4;
2261                         break;
2262
2263                 case 103:       /* lvx */
2264                 case 359:       /* lvxl */
2265                         op->type = MKOP(LOAD_VMX, 0, 16);
2266                         op->element_size = 16;
2267                         break;
2268
2269                 case 135:       /* stvebx */
2270                         op->type = MKOP(STORE_VMX, 0, 1);
2271                         op->element_size = 1;
2272                         break;
2273
2274                 case 167:       /* stvehx */
2275                         op->type = MKOP(STORE_VMX, 0, 2);
2276                         op->element_size = 2;
2277                         break;
2278
2279                 case 199:       /* stvewx */
2280                         op->type = MKOP(STORE_VMX, 0, 4);
2281                         op->element_size = 4;
2282                         break;
2283
2284                 case 231:       /* stvx */
2285                 case 487:       /* stvxl */
2286                         op->type = MKOP(STORE_VMX, 0, 16);
2287                         break;
2288 #endif /* CONFIG_ALTIVEC */
2289
2290 #ifdef __powerpc64__
2291                 case 21:        /* ldx */
2292                 case 53:        /* ldux */
2293                         op->type = MKOP(LOAD, u, 8);
2294                         break;
2295
2296                 case 149:       /* stdx */
2297                 case 181:       /* stdux */
2298                         op->type = MKOP(STORE, u, 8);
2299                         break;
2300 #endif
2301
2302                 case 151:       /* stwx */
2303                 case 183:       /* stwux */
2304                         op->type = MKOP(STORE, u, 4);
2305                         break;
2306
2307                 case 215:       /* stbx */
2308                 case 247:       /* stbux */
2309                         op->type = MKOP(STORE, u, 1);
2310                         break;
2311
2312                 case 279:       /* lhzx */
2313                 case 311:       /* lhzux */
2314                         op->type = MKOP(LOAD, u, 2);
2315                         break;
2316
2317 #ifdef __powerpc64__
2318                 case 341:       /* lwax */
2319                 case 373:       /* lwaux */
2320                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2321                         break;
2322 #endif
2323
2324                 case 343:       /* lhax */
2325                 case 375:       /* lhaux */
2326                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2327                         break;
2328
2329                 case 407:       /* sthx */
2330                 case 439:       /* sthux */
2331                         op->type = MKOP(STORE, u, 2);
2332                         break;
2333
2334 #ifdef __powerpc64__
2335                 case 532:       /* ldbrx */
2336                         op->type = MKOP(LOAD, BYTEREV, 8);
2337                         break;
2338
2339 #endif
2340                 case 533:       /* lswx */
2341                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2342                         break;
2343
2344                 case 534:       /* lwbrx */
2345                         op->type = MKOP(LOAD, BYTEREV, 4);
2346                         break;
2347
2348                 case 597:       /* lswi */
2349                         if (rb == 0)
2350                                 rb = 32;        /* # bytes to load */
2351                         op->type = MKOP(LOAD_MULTI, 0, rb);
2352                         op->ea = ra ? regs->gpr[ra] : 0;
2353                         break;
2354
2355 #ifdef CONFIG_PPC_FPU
2356                 case 535:       /* lfsx */
2357                 case 567:       /* lfsux */
2358                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2359                         break;
2360
2361                 case 599:       /* lfdx */
2362                 case 631:       /* lfdux */
2363                         op->type = MKOP(LOAD_FP, u, 8);
2364                         break;
2365
2366                 case 663:       /* stfsx */
2367                 case 695:       /* stfsux */
2368                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2369                         break;
2370
2371                 case 727:       /* stfdx */
2372                 case 759:       /* stfdux */
2373                         op->type = MKOP(STORE_FP, u, 8);
2374                         break;
2375
2376 #ifdef __powerpc64__
2377                 case 791:       /* lfdpx */
2378                         op->type = MKOP(LOAD_FP, 0, 16);
2379                         break;
2380
2381                 case 855:       /* lfiwax */
2382                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2383                         break;
2384
2385                 case 887:       /* lfiwzx */
2386                         op->type = MKOP(LOAD_FP, 0, 4);
2387                         break;
2388
2389                 case 919:       /* stfdpx */
2390                         op->type = MKOP(STORE_FP, 0, 16);
2391                         break;
2392
2393                 case 983:       /* stfiwx */
2394                         op->type = MKOP(STORE_FP, 0, 4);
2395                         break;
2396 #endif /* __powerpc64 */
2397 #endif /* CONFIG_PPC_FPU */
2398
2399 #ifdef __powerpc64__
2400                 case 660:       /* stdbrx */
2401                         op->type = MKOP(STORE, BYTEREV, 8);
2402                         op->val = byterev_8(regs->gpr[rd]);
2403                         break;
2404
2405 #endif
2406                 case 661:       /* stswx */
2407                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2408                         break;
2409
2410                 case 662:       /* stwbrx */
2411                         op->type = MKOP(STORE, BYTEREV, 4);
2412                         op->val = byterev_4(regs->gpr[rd]);
2413                         break;
2414
2415                 case 725:       /* stswi */
2416                         if (rb == 0)
2417                                 rb = 32;        /* # bytes to store */
2418                         op->type = MKOP(STORE_MULTI, 0, rb);
2419                         op->ea = ra ? regs->gpr[ra] : 0;
2420                         break;
2421
2422                 case 790:       /* lhbrx */
2423                         op->type = MKOP(LOAD, BYTEREV, 2);
2424                         break;
2425
2426                 case 918:       /* sthbrx */
2427                         op->type = MKOP(STORE, BYTEREV, 2);
2428                         op->val = byterev_2(regs->gpr[rd]);
2429                         break;
2430
2431 #ifdef CONFIG_VSX
2432                 case 12:        /* lxsiwzx */
2433                         op->reg = rd | ((word & 1) << 5);
2434                         op->type = MKOP(LOAD_VSX, 0, 4);
2435                         op->element_size = 8;
2436                         break;
2437
2438                 case 76:        /* lxsiwax */
2439                         op->reg = rd | ((word & 1) << 5);
2440                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2441                         op->element_size = 8;
2442                         break;
2443
2444                 case 140:       /* stxsiwx */
2445                         op->reg = rd | ((word & 1) << 5);
2446                         op->type = MKOP(STORE_VSX, 0, 4);
2447                         op->element_size = 8;
2448                         break;
2449
2450                 case 268:       /* lxvx */
2451                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2452                                 goto unknown_opcode;
2453                         op->reg = rd | ((word & 1) << 5);
2454                         op->type = MKOP(LOAD_VSX, 0, 16);
2455                         op->element_size = 16;
2456                         op->vsx_flags = VSX_CHECK_VEC;
2457                         break;
2458
2459                 case 269:       /* lxvl */
2460                 case 301: {     /* lxvll */
2461                         int nb;
2462                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2463                                 goto unknown_opcode;
2464                         op->reg = rd | ((word & 1) << 5);
2465                         op->ea = ra ? regs->gpr[ra] : 0;
2466                         nb = regs->gpr[rb] & 0xff;
2467                         if (nb > 16)
2468                                 nb = 16;
2469                         op->type = MKOP(LOAD_VSX, 0, nb);
2470                         op->element_size = 16;
2471                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2472                                 VSX_CHECK_VEC;
2473                         break;
2474                 }
2475                 case 332:       /* lxvdsx */
2476                         op->reg = rd | ((word & 1) << 5);
2477                         op->type = MKOP(LOAD_VSX, 0, 8);
2478                         op->element_size = 8;
2479                         op->vsx_flags = VSX_SPLAT;
2480                         break;
2481
2482                 case 333:       /* lxvpx */
2483                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2484                                 goto unknown_opcode;
2485                         op->reg = VSX_REGISTER_XTP(rd);
2486                         op->type = MKOP(LOAD_VSX, 0, 32);
2487                         op->element_size = 32;
2488                         break;
2489
2490                 case 364:       /* lxvwsx */
2491                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2492                                 goto unknown_opcode;
2493                         op->reg = rd | ((word & 1) << 5);
2494                         op->type = MKOP(LOAD_VSX, 0, 4);
2495                         op->element_size = 4;
2496                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2497                         break;
2498
2499                 case 396:       /* stxvx */
2500                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2501                                 goto unknown_opcode;
2502                         op->reg = rd | ((word & 1) << 5);
2503                         op->type = MKOP(STORE_VSX, 0, 16);
2504                         op->element_size = 16;
2505                         op->vsx_flags = VSX_CHECK_VEC;
2506                         break;
2507
2508                 case 397:       /* stxvl */
2509                 case 429: {     /* stxvll */
2510                         int nb;
2511                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2512                                 goto unknown_opcode;
2513                         op->reg = rd | ((word & 1) << 5);
2514                         op->ea = ra ? regs->gpr[ra] : 0;
2515                         nb = regs->gpr[rb] & 0xff;
2516                         if (nb > 16)
2517                                 nb = 16;
2518                         op->type = MKOP(STORE_VSX, 0, nb);
2519                         op->element_size = 16;
2520                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2521                                 VSX_CHECK_VEC;
2522                         break;
2523                 }
2524                 case 461:       /* stxvpx */
2525                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2526                                 goto unknown_opcode;
2527                         op->reg = VSX_REGISTER_XTP(rd);
2528                         op->type = MKOP(STORE_VSX, 0, 32);
2529                         op->element_size = 32;
2530                         break;
2531                 case 524:       /* lxsspx */
2532                         op->reg = rd | ((word & 1) << 5);
2533                         op->type = MKOP(LOAD_VSX, 0, 4);
2534                         op->element_size = 8;
2535                         op->vsx_flags = VSX_FPCONV;
2536                         break;
2537
2538                 case 588:       /* lxsdx */
2539                         op->reg = rd | ((word & 1) << 5);
2540                         op->type = MKOP(LOAD_VSX, 0, 8);
2541                         op->element_size = 8;
2542                         break;
2543
2544                 case 652:       /* stxsspx */
2545                         op->reg = rd | ((word & 1) << 5);
2546                         op->type = MKOP(STORE_VSX, 0, 4);
2547                         op->element_size = 8;
2548                         op->vsx_flags = VSX_FPCONV;
2549                         break;
2550
2551                 case 716:       /* stxsdx */
2552                         op->reg = rd | ((word & 1) << 5);
2553                         op->type = MKOP(STORE_VSX, 0, 8);
2554                         op->element_size = 8;
2555                         break;
2556
2557                 case 780:       /* lxvw4x */
2558                         op->reg = rd | ((word & 1) << 5);
2559                         op->type = MKOP(LOAD_VSX, 0, 16);
2560                         op->element_size = 4;
2561                         break;
2562
2563                 case 781:       /* lxsibzx */
2564                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2565                                 goto unknown_opcode;
2566                         op->reg = rd | ((word & 1) << 5);
2567                         op->type = MKOP(LOAD_VSX, 0, 1);
2568                         op->element_size = 8;
2569                         op->vsx_flags = VSX_CHECK_VEC;
2570                         break;
2571
2572                 case 812:       /* lxvh8x */
2573                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2574                                 goto unknown_opcode;
2575                         op->reg = rd | ((word & 1) << 5);
2576                         op->type = MKOP(LOAD_VSX, 0, 16);
2577                         op->element_size = 2;
2578                         op->vsx_flags = VSX_CHECK_VEC;
2579                         break;
2580
2581                 case 813:       /* lxsihzx */
2582                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2583                                 goto unknown_opcode;
2584                         op->reg = rd | ((word & 1) << 5);
2585                         op->type = MKOP(LOAD_VSX, 0, 2);
2586                         op->element_size = 8;
2587                         op->vsx_flags = VSX_CHECK_VEC;
2588                         break;
2589
2590                 case 844:       /* lxvd2x */
2591                         op->reg = rd | ((word & 1) << 5);
2592                         op->type = MKOP(LOAD_VSX, 0, 16);
2593                         op->element_size = 8;
2594                         break;
2595
2596                 case 876:       /* lxvb16x */
2597                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2598                                 goto unknown_opcode;
2599                         op->reg = rd | ((word & 1) << 5);
2600                         op->type = MKOP(LOAD_VSX, 0, 16);
2601                         op->element_size = 1;
2602                         op->vsx_flags = VSX_CHECK_VEC;
2603                         break;
2604
2605                 case 908:       /* stxvw4x */
2606                         op->reg = rd | ((word & 1) << 5);
2607                         op->type = MKOP(STORE_VSX, 0, 16);
2608                         op->element_size = 4;
2609                         break;
2610
2611                 case 909:       /* stxsibx */
2612                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2613                                 goto unknown_opcode;
2614                         op->reg = rd | ((word & 1) << 5);
2615                         op->type = MKOP(STORE_VSX, 0, 1);
2616                         op->element_size = 8;
2617                         op->vsx_flags = VSX_CHECK_VEC;
2618                         break;
2619
2620                 case 940:       /* stxvh8x */
2621                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2622                                 goto unknown_opcode;
2623                         op->reg = rd | ((word & 1) << 5);
2624                         op->type = MKOP(STORE_VSX, 0, 16);
2625                         op->element_size = 2;
2626                         op->vsx_flags = VSX_CHECK_VEC;
2627                         break;
2628
2629                 case 941:       /* stxsihx */
2630                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2631                                 goto unknown_opcode;
2632                         op->reg = rd | ((word & 1) << 5);
2633                         op->type = MKOP(STORE_VSX, 0, 2);
2634                         op->element_size = 8;
2635                         op->vsx_flags = VSX_CHECK_VEC;
2636                         break;
2637
2638                 case 972:       /* stxvd2x */
2639                         op->reg = rd | ((word & 1) << 5);
2640                         op->type = MKOP(STORE_VSX, 0, 16);
2641                         op->element_size = 8;
2642                         break;
2643
2644                 case 1004:      /* stxvb16x */
2645                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2646                                 goto unknown_opcode;
2647                         op->reg = rd | ((word & 1) << 5);
2648                         op->type = MKOP(STORE_VSX, 0, 16);
2649                         op->element_size = 1;
2650                         op->vsx_flags = VSX_CHECK_VEC;
2651                         break;
2652
2653 #endif /* CONFIG_VSX */
2654                 }
2655                 break;
2656
2657         case 32:        /* lwz */
2658         case 33:        /* lwzu */
2659                 op->type = MKOP(LOAD, u, 4);
2660                 op->ea = dform_ea(word, regs);
2661                 break;
2662
2663         case 34:        /* lbz */
2664         case 35:        /* lbzu */
2665                 op->type = MKOP(LOAD, u, 1);
2666                 op->ea = dform_ea(word, regs);
2667                 break;
2668
2669         case 36:        /* stw */
2670         case 37:        /* stwu */
2671                 op->type = MKOP(STORE, u, 4);
2672                 op->ea = dform_ea(word, regs);
2673                 break;
2674
2675         case 38:        /* stb */
2676         case 39:        /* stbu */
2677                 op->type = MKOP(STORE, u, 1);
2678                 op->ea = dform_ea(word, regs);
2679                 break;
2680
2681         case 40:        /* lhz */
2682         case 41:        /* lhzu */
2683                 op->type = MKOP(LOAD, u, 2);
2684                 op->ea = dform_ea(word, regs);
2685                 break;
2686
2687         case 42:        /* lha */
2688         case 43:        /* lhau */
2689                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2690                 op->ea = dform_ea(word, regs);
2691                 break;
2692
2693         case 44:        /* sth */
2694         case 45:        /* sthu */
2695                 op->type = MKOP(STORE, u, 2);
2696                 op->ea = dform_ea(word, regs);
2697                 break;
2698
2699         case 46:        /* lmw */
2700                 if (ra >= rd)
2701                         break;          /* invalid form, ra in range to load */
2702                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2703                 op->ea = dform_ea(word, regs);
2704                 break;
2705
2706         case 47:        /* stmw */
2707                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2708                 op->ea = dform_ea(word, regs);
2709                 break;
2710
2711 #ifdef CONFIG_PPC_FPU
2712         case 48:        /* lfs */
2713         case 49:        /* lfsu */
2714                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2715                 op->ea = dform_ea(word, regs);
2716                 break;
2717
2718         case 50:        /* lfd */
2719         case 51:        /* lfdu */
2720                 op->type = MKOP(LOAD_FP, u, 8);
2721                 op->ea = dform_ea(word, regs);
2722                 break;
2723
2724         case 52:        /* stfs */
2725         case 53:        /* stfsu */
2726                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2727                 op->ea = dform_ea(word, regs);
2728                 break;
2729
2730         case 54:        /* stfd */
2731         case 55:        /* stfdu */
2732                 op->type = MKOP(STORE_FP, u, 8);
2733                 op->ea = dform_ea(word, regs);
2734                 break;
2735 #endif
2736
2737 #ifdef __powerpc64__
2738         case 56:        /* lq */
2739                 if (!((rd & 1) || (rd == ra)))
2740                         op->type = MKOP(LOAD, 0, 16);
2741                 op->ea = dqform_ea(word, regs);
2742                 break;
2743 #endif
2744
2745 #ifdef CONFIG_VSX
2746         case 57:        /* lfdp, lxsd, lxssp */
2747                 op->ea = dsform_ea(word, regs);
2748                 switch (word & 3) {
2749                 case 0:         /* lfdp */
2750                         if (rd & 1)
2751                                 break;          /* reg must be even */
2752                         op->type = MKOP(LOAD_FP, 0, 16);
2753                         break;
2754                 case 2:         /* lxsd */
2755                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2756                                 goto unknown_opcode;
2757                         op->reg = rd + 32;
2758                         op->type = MKOP(LOAD_VSX, 0, 8);
2759                         op->element_size = 8;
2760                         op->vsx_flags = VSX_CHECK_VEC;
2761                         break;
2762                 case 3:         /* lxssp */
2763                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2764                                 goto unknown_opcode;
2765                         op->reg = rd + 32;
2766                         op->type = MKOP(LOAD_VSX, 0, 4);
2767                         op->element_size = 8;
2768                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2769                         break;
2770                 }
2771                 break;
2772 #endif /* CONFIG_VSX */
2773
2774 #ifdef __powerpc64__
2775         case 58:        /* ld[u], lwa */
2776                 op->ea = dsform_ea(word, regs);
2777                 switch (word & 3) {
2778                 case 0:         /* ld */
2779                         op->type = MKOP(LOAD, 0, 8);
2780                         break;
2781                 case 1:         /* ldu */
2782                         op->type = MKOP(LOAD, UPDATE, 8);
2783                         break;
2784                 case 2:         /* lwa */
2785                         op->type = MKOP(LOAD, SIGNEXT, 4);
2786                         break;
2787                 }
2788                 break;
2789 #endif
2790
2791 #ifdef CONFIG_VSX
2792         case 6:
2793                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2794                         goto unknown_opcode;
2795                 op->ea = dqform_ea(word, regs);
2796                 op->reg = VSX_REGISTER_XTP(rd);
2797                 op->element_size = 32;
2798                 switch (word & 0xf) {
2799                 case 0:         /* lxvp */
2800                         op->type = MKOP(LOAD_VSX, 0, 32);
2801                         break;
2802                 case 1:         /* stxvp */
2803                         op->type = MKOP(STORE_VSX, 0, 32);
2804                         break;
2805                 }
2806                 break;
2807
2808         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2809                 switch (word & 7) {
2810                 case 0:         /* stfdp with LSB of DS field = 0 */
2811                 case 4:         /* stfdp with LSB of DS field = 1 */
2812                         op->ea = dsform_ea(word, regs);
2813                         op->type = MKOP(STORE_FP, 0, 16);
2814                         break;
2815
2816                 case 1:         /* lxv */
2817                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2818                                 goto unknown_opcode;
2819                         op->ea = dqform_ea(word, regs);
2820                         if (word & 8)
2821                                 op->reg = rd + 32;
2822                         op->type = MKOP(LOAD_VSX, 0, 16);
2823                         op->element_size = 16;
2824                         op->vsx_flags = VSX_CHECK_VEC;
2825                         break;
2826
2827                 case 2:         /* stxsd with LSB of DS field = 0 */
2828                 case 6:         /* stxsd with LSB of DS field = 1 */
2829                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2830                                 goto unknown_opcode;
2831                         op->ea = dsform_ea(word, regs);
2832                         op->reg = rd + 32;
2833                         op->type = MKOP(STORE_VSX, 0, 8);
2834                         op->element_size = 8;
2835                         op->vsx_flags = VSX_CHECK_VEC;
2836                         break;
2837
2838                 case 3:         /* stxssp with LSB of DS field = 0 */
2839                 case 7:         /* stxssp with LSB of DS field = 1 */
2840                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2841                                 goto unknown_opcode;
2842                         op->ea = dsform_ea(word, regs);
2843                         op->reg = rd + 32;
2844                         op->type = MKOP(STORE_VSX, 0, 4);
2845                         op->element_size = 8;
2846                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2847                         break;
2848
2849                 case 5:         /* stxv */
2850                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2851                                 goto unknown_opcode;
2852                         op->ea = dqform_ea(word, regs);
2853                         if (word & 8)
2854                                 op->reg = rd + 32;
2855                         op->type = MKOP(STORE_VSX, 0, 16);
2856                         op->element_size = 16;
2857                         op->vsx_flags = VSX_CHECK_VEC;
2858                         break;
2859                 }
2860                 break;
2861 #endif /* CONFIG_VSX */
2862
2863 #ifdef __powerpc64__
2864         case 62:        /* std[u] */
2865                 op->ea = dsform_ea(word, regs);
2866                 switch (word & 3) {
2867                 case 0:         /* std */
2868                         op->type = MKOP(STORE, 0, 8);
2869                         break;
2870                 case 1:         /* stdu */
2871                         op->type = MKOP(STORE, UPDATE, 8);
2872                         break;
2873                 case 2:         /* stq */
2874                         if (!(rd & 1))
2875                                 op->type = MKOP(STORE, 0, 16);
2876                         break;
2877                 }
2878                 break;
2879         case 1: /* Prefixed instructions */
2880                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2881                         goto unknown_opcode;
2882
2883                 prefix_r = GET_PREFIX_R(word);
2884                 ra = GET_PREFIX_RA(suffix);
2885                 op->update_reg = ra;
2886                 rd = (suffix >> 21) & 0x1f;
2887                 op->reg = rd;
2888                 op->val = regs->gpr[rd];
2889
2890                 suffixopcode = get_op(suffix);
2891                 prefixtype = (word >> 24) & 0x3;
2892                 switch (prefixtype) {
2893                 case 0: /* Type 00  Eight-Byte Load/Store */
2894                         if (prefix_r && ra)
2895                                 break;
2896                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2897                         switch (suffixopcode) {
2898                         case 41:        /* plwa */
2899                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2900                                 break;
2901 #ifdef CONFIG_VSX
2902                         case 42:        /* plxsd */
2903                                 op->reg = rd + 32;
2904                                 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2905                                 op->element_size = 8;
2906                                 op->vsx_flags = VSX_CHECK_VEC;
2907                                 break;
2908                         case 43:        /* plxssp */
2909                                 op->reg = rd + 32;
2910                                 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2911                                 op->element_size = 8;
2912                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2913                                 break;
2914                         case 46:        /* pstxsd */
2915                                 op->reg = rd + 32;
2916                                 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2917                                 op->element_size = 8;
2918                                 op->vsx_flags = VSX_CHECK_VEC;
2919                                 break;
2920                         case 47:        /* pstxssp */
2921                                 op->reg = rd + 32;
2922                                 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2923                                 op->element_size = 8;
2924                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2925                                 break;
2926                         case 51:        /* plxv1 */
2927                                 op->reg += 32;
2928                                 fallthrough;
2929                         case 50:        /* plxv0 */
2930                                 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2931                                 op->element_size = 16;
2932                                 op->vsx_flags = VSX_CHECK_VEC;
2933                                 break;
2934                         case 55:        /* pstxv1 */
2935                                 op->reg = rd + 32;
2936                                 fallthrough;
2937                         case 54:        /* pstxv0 */
2938                                 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2939                                 op->element_size = 16;
2940                                 op->vsx_flags = VSX_CHECK_VEC;
2941                                 break;
2942 #endif /* CONFIG_VSX */
2943                         case 56:        /* plq */
2944                                 op->type = MKOP(LOAD, PREFIXED, 16);
2945                                 break;
2946                         case 57:        /* pld */
2947                                 op->type = MKOP(LOAD, PREFIXED, 8);
2948                                 break;
2949 #ifdef CONFIG_VSX
2950                         case 58:        /* plxvp */
2951                                 op->reg = VSX_REGISTER_XTP(rd);
2952                                 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
2953                                 op->element_size = 32;
2954                                 break;
2955 #endif /* CONFIG_VSX */
2956                         case 60:        /* pstq */
2957                                 op->type = MKOP(STORE, PREFIXED, 16);
2958                                 break;
2959                         case 61:        /* pstd */
2960                                 op->type = MKOP(STORE, PREFIXED, 8);
2961                                 break;
2962 #ifdef CONFIG_VSX
2963                         case 62:        /* pstxvp */
2964                                 op->reg = VSX_REGISTER_XTP(rd);
2965                                 op->type = MKOP(STORE_VSX, PREFIXED, 32);
2966                                 op->element_size = 32;
2967                                 break;
2968 #endif /* CONFIG_VSX */
2969                         }
2970                         break;
2971                 case 1: /* Type 01 Eight-Byte Register-to-Register */
2972                         break;
2973                 case 2: /* Type 10 Modified Load/Store */
2974                         if (prefix_r && ra)
2975                                 break;
2976                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2977                         switch (suffixopcode) {
2978                         case 32:        /* plwz */
2979                                 op->type = MKOP(LOAD, PREFIXED, 4);
2980                                 break;
2981                         case 34:        /* plbz */
2982                                 op->type = MKOP(LOAD, PREFIXED, 1);
2983                                 break;
2984                         case 36:        /* pstw */
2985                                 op->type = MKOP(STORE, PREFIXED, 4);
2986                                 break;
2987                         case 38:        /* pstb */
2988                                 op->type = MKOP(STORE, PREFIXED, 1);
2989                                 break;
2990                         case 40:        /* plhz */
2991                                 op->type = MKOP(LOAD, PREFIXED, 2);
2992                                 break;
2993                         case 42:        /* plha */
2994                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2995                                 break;
2996                         case 44:        /* psth */
2997                                 op->type = MKOP(STORE, PREFIXED, 2);
2998                                 break;
2999                         case 48:        /* plfs */
3000                                 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
3001                                 break;
3002                         case 50:        /* plfd */
3003                                 op->type = MKOP(LOAD_FP, PREFIXED, 8);
3004                                 break;
3005                         case 52:        /* pstfs */
3006                                 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
3007                                 break;
3008                         case 54:        /* pstfd */
3009                                 op->type = MKOP(STORE_FP, PREFIXED, 8);
3010                                 break;
3011                         }
3012                         break;
3013                 case 3: /* Type 11 Modified Register-to-Register */
3014                         break;
3015                 }
3016 #endif /* __powerpc64__ */
3017
3018         }
3019
3020 #ifdef CONFIG_VSX
3021         if ((GETTYPE(op->type) == LOAD_VSX ||
3022              GETTYPE(op->type) == STORE_VSX) &&
3023             !cpu_has_feature(CPU_FTR_VSX)) {
3024                 return -1;
3025         }
3026 #endif /* CONFIG_VSX */
3027
3028         return 0;
3029
3030  unknown_opcode:
3031         op->type = UNKNOWN;
3032         return 0;
3033
3034  logical_done:
3035         if (word & 1)
3036                 set_cr0(regs, op);
3037  logical_done_nocc:
3038         op->reg = ra;
3039         op->type |= SETREG;
3040         return 1;
3041
3042  arith_done:
3043         if (word & 1)
3044                 set_cr0(regs, op);
3045  compute_done:
3046         op->reg = rd;
3047         op->type |= SETREG;
3048         return 1;
3049
3050  priv:
3051         op->type = INTERRUPT | 0x700;
3052         op->val = SRR1_PROGPRIV;
3053         return 0;
3054
3055  trap:
3056         op->type = INTERRUPT | 0x700;
3057         op->val = SRR1_PROGTRAP;
3058         return 0;
3059 }
3060 EXPORT_SYMBOL_GPL(analyse_instr);
3061 NOKPROBE_SYMBOL(analyse_instr);
3062
3063 /*
3064  * For PPC32 we always use stwu with r1 to change the stack pointer.
3065  * So this emulated store may corrupt the exception frame, now we
3066  * have to provide the exception frame trampoline, which is pushed
3067  * below the kprobed function stack. So we only update gpr[1] but
3068  * don't emulate the real store operation. We will do real store
3069  * operation safely in exception return code by checking this flag.
3070  */
3071 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3072 {
3073 #ifdef CONFIG_PPC32
3074         /*
3075          * Check if we will touch kernel stack overflow
3076          */
3077         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
3078                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
3079                 return -EINVAL;
3080         }
3081 #endif /* CONFIG_PPC32 */
3082         /*
3083          * Check if we already set since that means we'll
3084          * lose the previous value.
3085          */
3086         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3087         set_thread_flag(TIF_EMULATE_STACK_STORE);
3088         return 0;
3089 }
3090
3091 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3092 {
3093         switch (size) {
3094         case 2:
3095                 *valp = (signed short) *valp;
3096                 break;
3097         case 4:
3098                 *valp = (signed int) *valp;
3099                 break;
3100         }
3101 }
3102
3103 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3104 {
3105         switch (size) {
3106         case 2:
3107                 *valp = byterev_2(*valp);
3108                 break;
3109         case 4:
3110                 *valp = byterev_4(*valp);
3111                 break;
3112 #ifdef __powerpc64__
3113         case 8:
3114                 *valp = byterev_8(*valp);
3115                 break;
3116 #endif
3117         }
3118 }
3119
3120 /*
3121  * Emulate an instruction that can be executed just by updating
3122  * fields in *regs.
3123  */
3124 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3125 {
3126         unsigned long next_pc;
3127
3128         next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3129         switch (GETTYPE(op->type)) {
3130         case COMPUTE:
3131                 if (op->type & SETREG)
3132                         regs->gpr[op->reg] = op->val;
3133                 if (op->type & SETCC)
3134                         regs->ccr = op->ccval;
3135                 if (op->type & SETXER)
3136                         regs->xer = op->xerval;
3137                 break;
3138
3139         case BRANCH:
3140                 if (op->type & SETLK)
3141                         regs->link = next_pc;
3142                 if (op->type & BRTAKEN)
3143                         next_pc = op->val;
3144                 if (op->type & DECCTR)
3145                         --regs->ctr;
3146                 break;
3147
3148         case BARRIER:
3149                 switch (op->type & BARRIER_MASK) {
3150                 case BARRIER_SYNC:
3151                         mb();
3152                         break;
3153                 case BARRIER_ISYNC:
3154                         isync();
3155                         break;
3156                 case BARRIER_EIEIO:
3157                         eieio();
3158                         break;
3159                 case BARRIER_LWSYNC:
3160                         asm volatile("lwsync" : : : "memory");
3161                         break;
3162                 case BARRIER_PTESYNC:
3163                         asm volatile("ptesync" : : : "memory");
3164                         break;
3165                 }
3166                 break;
3167
3168         case MFSPR:
3169                 switch (op->spr) {
3170                 case SPRN_XER:
3171                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3172                         break;
3173                 case SPRN_LR:
3174                         regs->gpr[op->reg] = regs->link;
3175                         break;
3176                 case SPRN_CTR:
3177                         regs->gpr[op->reg] = regs->ctr;
3178                         break;
3179                 default:
3180                         WARN_ON_ONCE(1);
3181                 }
3182                 break;
3183
3184         case MTSPR:
3185                 switch (op->spr) {
3186                 case SPRN_XER:
3187                         regs->xer = op->val & 0xffffffffUL;
3188                         break;
3189                 case SPRN_LR:
3190                         regs->link = op->val;
3191                         break;
3192                 case SPRN_CTR:
3193                         regs->ctr = op->val;
3194                         break;
3195                 default:
3196                         WARN_ON_ONCE(1);
3197                 }
3198                 break;
3199
3200         default:
3201                 WARN_ON_ONCE(1);
3202         }
3203         regs->nip = next_pc;
3204 }
3205 NOKPROBE_SYMBOL(emulate_update_regs);
3206
3207 /*
3208  * Emulate a previously-analysed load or store instruction.
3209  * Return values are:
3210  * 0 = instruction emulated successfully
3211  * -EFAULT = address out of range or access faulted (regs->dar
3212  *           contains the faulting address)
3213  * -EACCES = misaligned access, instruction requires alignment
3214  * -EINVAL = unknown operation in *op
3215  */
3216 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3217 {
3218         int err, size, type;
3219         int i, rd, nb;
3220         unsigned int cr;
3221         unsigned long val;
3222         unsigned long ea;
3223         bool cross_endian;
3224
3225         err = 0;
3226         size = GETSIZE(op->type);
3227         type = GETTYPE(op->type);
3228         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3229         ea = truncate_if_32bit(regs->msr, op->ea);
3230
3231         switch (type) {
3232         case LARX:
3233                 if (ea & (size - 1))
3234                         return -EACCES;         /* can't handle misaligned */
3235                 if (!address_ok(regs, ea, size))
3236                         return -EFAULT;
3237                 err = 0;
3238                 val = 0;
3239                 switch (size) {
3240 #ifdef __powerpc64__
3241                 case 1:
3242                         __get_user_asmx(val, ea, err, "lbarx");
3243                         break;
3244                 case 2:
3245                         __get_user_asmx(val, ea, err, "lharx");
3246                         break;
3247 #endif
3248                 case 4:
3249                         __get_user_asmx(val, ea, err, "lwarx");
3250                         break;
3251 #ifdef __powerpc64__
3252                 case 8:
3253                         __get_user_asmx(val, ea, err, "ldarx");
3254                         break;
3255                 case 16:
3256                         err = do_lqarx(ea, &regs->gpr[op->reg]);
3257                         break;
3258 #endif
3259                 default:
3260                         return -EINVAL;
3261                 }
3262                 if (err) {
3263                         regs->dar = ea;
3264                         break;
3265                 }
3266                 if (size < 16)
3267                         regs->gpr[op->reg] = val;
3268                 break;
3269
3270         case STCX:
3271                 if (ea & (size - 1))
3272                         return -EACCES;         /* can't handle misaligned */
3273                 if (!address_ok(regs, ea, size))
3274                         return -EFAULT;
3275                 err = 0;
3276                 switch (size) {
3277 #ifdef __powerpc64__
3278                 case 1:
3279                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3280                         break;
3281                 case 2:
3282                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3283                         break;
3284 #endif
3285                 case 4:
3286                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3287                         break;
3288 #ifdef __powerpc64__
3289                 case 8:
3290                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3291                         break;
3292                 case 16:
3293                         err = do_stqcx(ea, regs->gpr[op->reg],
3294                                        regs->gpr[op->reg + 1], &cr);
3295                         break;
3296 #endif
3297                 default:
3298                         return -EINVAL;
3299                 }
3300                 if (!err)
3301                         regs->ccr = (regs->ccr & 0x0fffffff) |
3302                                 (cr & 0xe0000000) |
3303                                 ((regs->xer >> 3) & 0x10000000);
3304                 else
3305                         regs->dar = ea;
3306                 break;
3307
3308         case LOAD:
3309 #ifdef __powerpc64__
3310                 if (size == 16) {
3311                         err = emulate_lq(regs, ea, op->reg, cross_endian);
3312                         break;
3313                 }
3314 #endif
3315                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
3316                 if (!err) {
3317                         if (op->type & SIGNEXT)
3318                                 do_signext(&regs->gpr[op->reg], size);
3319                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3320                                 do_byterev(&regs->gpr[op->reg], size);
3321                 }
3322                 break;
3323
3324 #ifdef CONFIG_PPC_FPU
3325         case LOAD_FP:
3326                 /*
3327                  * If the instruction is in userspace, we can emulate it even
3328                  * if the VMX state is not live, because we have the state
3329                  * stored in the thread_struct.  If the instruction is in
3330                  * the kernel, we must not touch the state in the thread_struct.
3331                  */
3332                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3333                         return 0;
3334                 err = do_fp_load(op, ea, regs, cross_endian);
3335                 break;
3336 #endif
3337 #ifdef CONFIG_ALTIVEC
3338         case LOAD_VMX:
3339                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3340                         return 0;
3341                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3342                 break;
3343 #endif
3344 #ifdef CONFIG_VSX
3345         case LOAD_VSX: {
3346                 unsigned long msrbit = MSR_VSX;
3347
3348                 /*
3349                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3350                  * when the target of the instruction is a vector register.
3351                  */
3352                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3353                         msrbit = MSR_VEC;
3354                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3355                         return 0;
3356                 err = do_vsx_load(op, ea, regs, cross_endian);
3357                 break;
3358         }
3359 #endif
3360         case LOAD_MULTI:
3361                 if (!address_ok(regs, ea, size))
3362                         return -EFAULT;
3363                 rd = op->reg;
3364                 for (i = 0; i < size; i += 4) {
3365                         unsigned int v32 = 0;
3366
3367                         nb = size - i;
3368                         if (nb > 4)
3369                                 nb = 4;
3370                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3371                         if (err)
3372                                 break;
3373                         if (unlikely(cross_endian))
3374                                 v32 = byterev_4(v32);
3375                         regs->gpr[rd] = v32;
3376                         ea += 4;
3377                         /* reg number wraps from 31 to 0 for lsw[ix] */
3378                         rd = (rd + 1) & 0x1f;
3379                 }
3380                 break;
3381
3382         case STORE:
3383 #ifdef __powerpc64__
3384                 if (size == 16) {
3385                         err = emulate_stq(regs, ea, op->reg, cross_endian);
3386                         break;
3387                 }
3388 #endif
3389                 if ((op->type & UPDATE) && size == sizeof(long) &&
3390                     op->reg == 1 && op->update_reg == 1 &&
3391                     !(regs->msr & MSR_PR) &&
3392                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3393                         err = handle_stack_update(ea, regs);
3394                         break;
3395                 }
3396                 if (unlikely(cross_endian))
3397                         do_byterev(&op->val, size);
3398                 err = write_mem(op->val, ea, size, regs);
3399                 break;
3400
3401 #ifdef CONFIG_PPC_FPU
3402         case STORE_FP:
3403                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3404                         return 0;
3405                 err = do_fp_store(op, ea, regs, cross_endian);
3406                 break;
3407 #endif
3408 #ifdef CONFIG_ALTIVEC
3409         case STORE_VMX:
3410                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3411                         return 0;
3412                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3413                 break;
3414 #endif
3415 #ifdef CONFIG_VSX
3416         case STORE_VSX: {
3417                 unsigned long msrbit = MSR_VSX;
3418
3419                 /*
3420                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3421                  * when the target of the instruction is a vector register.
3422                  */
3423                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3424                         msrbit = MSR_VEC;
3425                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3426                         return 0;
3427                 err = do_vsx_store(op, ea, regs, cross_endian);
3428                 break;
3429         }
3430 #endif
3431         case STORE_MULTI:
3432                 if (!address_ok(regs, ea, size))
3433                         return -EFAULT;
3434                 rd = op->reg;
3435                 for (i = 0; i < size; i += 4) {
3436                         unsigned int v32 = regs->gpr[rd];
3437
3438                         nb = size - i;
3439                         if (nb > 4)
3440                                 nb = 4;
3441                         if (unlikely(cross_endian))
3442                                 v32 = byterev_4(v32);
3443                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3444                         if (err)
3445                                 break;
3446                         ea += 4;
3447                         /* reg number wraps from 31 to 0 for stsw[ix] */
3448                         rd = (rd + 1) & 0x1f;
3449                 }
3450                 break;
3451
3452         default:
3453                 return -EINVAL;
3454         }
3455
3456         if (err)
3457                 return err;
3458
3459         if (op->type & UPDATE)
3460                 regs->gpr[op->update_reg] = op->ea;
3461
3462         return 0;
3463 }
3464 NOKPROBE_SYMBOL(emulate_loadstore);
3465
3466 /*
3467  * Emulate instructions that cause a transfer of control,
3468  * loads and stores, and a few other instructions.
3469  * Returns 1 if the step was emulated, 0 if not,
3470  * or -1 if the instruction is one that should not be stepped,
3471  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3472  */
3473 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3474 {
3475         struct instruction_op op;
3476         int r, err, type;
3477         unsigned long val;
3478         unsigned long ea;
3479
3480         r = analyse_instr(&op, regs, instr);
3481         if (r < 0)
3482                 return r;
3483         if (r > 0) {
3484                 emulate_update_regs(regs, &op);
3485                 return 1;
3486         }
3487
3488         err = 0;
3489         type = GETTYPE(op.type);
3490
3491         if (OP_IS_LOAD_STORE(type)) {
3492                 err = emulate_loadstore(regs, &op);
3493                 if (err)
3494                         return 0;
3495                 goto instr_done;
3496         }
3497
3498         switch (type) {
3499         case CACHEOP:
3500                 ea = truncate_if_32bit(regs->msr, op.ea);
3501                 if (!address_ok(regs, ea, 8))
3502                         return 0;
3503                 switch (op.type & CACHEOP_MASK) {
3504                 case DCBST:
3505                         __cacheop_user_asmx(ea, err, "dcbst");
3506                         break;
3507                 case DCBF:
3508                         __cacheop_user_asmx(ea, err, "dcbf");
3509                         break;
3510                 case DCBTST:
3511                         if (op.reg == 0)
3512                                 prefetchw((void *) ea);
3513                         break;
3514                 case DCBT:
3515                         if (op.reg == 0)
3516                                 prefetch((void *) ea);
3517                         break;
3518                 case ICBI:
3519                         __cacheop_user_asmx(ea, err, "icbi");
3520                         break;
3521                 case DCBZ:
3522                         err = emulate_dcbz(ea, regs);
3523                         break;
3524                 }
3525                 if (err) {
3526                         regs->dar = ea;
3527                         return 0;
3528                 }
3529                 goto instr_done;
3530
3531         case MFMSR:
3532                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3533                 goto instr_done;
3534
3535         case MTMSR:
3536                 val = regs->gpr[op.reg];
3537                 if ((val & MSR_RI) == 0)
3538                         /* can't step mtmsr[d] that would clear MSR_RI */
3539                         return -1;
3540                 /* here op.val is the mask of bits to change */
3541                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3542                 goto instr_done;
3543
3544 #ifdef CONFIG_PPC64
3545         case SYSCALL:   /* sc */
3546                 /*
3547                  * N.B. this uses knowledge about how the syscall
3548                  * entry code works.  If that is changed, this will
3549                  * need to be changed also.
3550                  */
3551                 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3552                                 cpu_has_feature(CPU_FTR_REAL_LE) &&
3553                                 regs->gpr[0] == 0x1ebe) {
3554                         regs->msr ^= MSR_LE;
3555                         goto instr_done;
3556                 }
3557                 regs->gpr[9] = regs->gpr[13];
3558                 regs->gpr[10] = MSR_KERNEL;
3559                 regs->gpr[11] = regs->nip + 4;
3560                 regs->gpr[12] = regs->msr & MSR_MASK;
3561                 regs->gpr[13] = (unsigned long) get_paca();
3562                 regs->nip = (unsigned long) &system_call_common;
3563                 regs->msr = MSR_KERNEL;
3564                 return 1;
3565
3566 #ifdef CONFIG_PPC_BOOK3S_64
3567         case SYSCALL_VECTORED_0:        /* scv 0 */
3568                 regs->gpr[9] = regs->gpr[13];
3569                 regs->gpr[10] = MSR_KERNEL;
3570                 regs->gpr[11] = regs->nip + 4;
3571                 regs->gpr[12] = regs->msr & MSR_MASK;
3572                 regs->gpr[13] = (unsigned long) get_paca();
3573                 regs->nip = (unsigned long) &system_call_vectored_emulate;
3574                 regs->msr = MSR_KERNEL;
3575                 return 1;
3576 #endif
3577
3578         case RFI:
3579                 return -1;
3580 #endif
3581         }
3582         return 0;
3583
3584  instr_done:
3585         regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3586         return 1;
3587 }
3588 NOKPROBE_SYMBOL(emulate_step);