arch/powerpc/lib/sstep.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Single-step support.
   4  *
   5  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/kprobes.h>
   9 #include <linux/ptrace.h>
  10 #include <linux/prefetch.h>
  11 #include <asm/sstep.h>
  12 #include <asm/processor.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/cpu_has_feature.h>
  15 #include <asm/cputable.h>
  16 #include <asm/disassemble.h>
  17
  18 extern char system_call_common[];
  19 extern char system_call_vectored_emulate[];
  20
  21 #ifdef CONFIG_PPC64
  22 /* Bits in SRR1 that are copied from MSR */
  23 #define MSR_MASK        0xffffffff87c0ffffUL
  24 #else
  25 #define MSR_MASK        0x87c0ffff
  26 #endif
  27
  28 /* Bits in XER */
  29 #define XER_SO          0x80000000U
  30 #define XER_OV          0x40000000U
  31 #define XER_CA          0x20000000U
  32 #define XER_OV32        0x00080000U
  33 #define XER_CA32        0x00040000U
  34
  35 #ifdef CONFIG_VSX
  36 #define VSX_REGISTER_XTP(rd)   ((((rd) & 1) << 5) | ((rd) & 0xfe))
  37 #endif
  38
  39 #ifdef CONFIG_PPC_FPU
  40 /*
  41  * Functions in ldstfp.S
  42  */
  43 extern void get_fpr(int rn, double *p);
  44 extern void put_fpr(int rn, const double *p);
  45 extern void get_vr(int rn, __vector128 *p);
  46 extern void put_vr(int rn, __vector128 *p);
  47 extern void load_vsrn(int vsr, const void *p);
  48 extern void store_vsrn(int vsr, void *p);
  49 extern void conv_sp_to_dp(const float *sp, double *dp);
  50 extern void conv_dp_to_sp(const double *dp, float *sp);
  51 #endif
  52
  53 #ifdef __powerpc64__
  54 /*
  55  * Functions in quad.S
  56  */
  57 extern int do_lq(unsigned long ea, unsigned long *regs);
  58 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  59 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  60 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  61                     unsigned int *crp);
  62 #endif
  63
  64 #ifdef __LITTLE_ENDIAN__
  65 #define IS_LE   1
  66 #define IS_BE   0
  67 #else
  68 #define IS_LE   0
  69 #define IS_BE   1
  70 #endif
  71
  72 /*
  73  * Emulate the truncation of 64 bit values in 32-bit mode.
  74  */
  75 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  76                                                         unsigned long val)
  77 {
  78 #ifdef __powerpc64__
  79         if ((msr & MSR_64BIT) == 0)
  80                 val &= 0xffffffffUL;
  81 #endif
  82         return val;
  83 }
  84
  85 /*
  86  * Determine whether a conditional branch instruction would branch.
  87  */
  88 static nokprobe_inline int branch_taken(unsigned int instr,
  89                                         const struct pt_regs *regs,
  90                                         struct instruction_op *op)
  91 {
  92         unsigned int bo = (instr >> 21) & 0x1f;
  93         unsigned int bi;
  94
  95         if ((bo & 4) == 0) {
  96                 /* decrement counter */
  97                 op->type |= DECCTR;
  98                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  99                         return 0;
 100         }
 101         if ((bo & 0x10) == 0) {
 102                 /* check bit from CR */
 103                 bi = (instr >> 16) & 0x1f;
 104                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 105                         return 0;
 106         }
 107         return 1;
 108 }
 109
 110 static nokprobe_inline long address_ok(struct pt_regs *regs,
 111                                        unsigned long ea, int nb)
 112 {
 113         if (!user_mode(regs))
 114                 return 1;
 115         if (__access_ok(ea, nb))
 116                 return 1;
 117         if (__access_ok(ea, 1))
 118                 /* Access overlaps the end of the user region */
 119                 regs->dar = TASK_SIZE_MAX - 1;
 120         else
 121                 regs->dar = ea;
 122         return 0;
 123 }
 124
 125 /*
 126  * Calculate effective address for a D-form instruction
 127  */
 128 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 129                                               const struct pt_regs *regs)
 130 {
 131         int ra;
 132         unsigned long ea;
 133
 134         ra = (instr >> 16) & 0x1f;
 135         ea = (signed short) instr;              /* sign-extend */
 136         if (ra)
 137                 ea += regs->gpr[ra];
 138
 139         return ea;
 140 }
 141
 142 #ifdef __powerpc64__
 143 /*
 144  * Calculate effective address for a DS-form instruction
 145  */
 146 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 147                                                const struct pt_regs *regs)
 148 {
 149         int ra;
 150         unsigned long ea;
 151
 152         ra = (instr >> 16) & 0x1f;
 153         ea = (signed short) (instr & ~3);       /* sign-extend */
 154         if (ra)
 155                 ea += regs->gpr[ra];
 156
 157         return ea;
 158 }
 159
 160 /*
 161  * Calculate effective address for a DQ-form instruction
 162  */
 163 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 164                                                const struct pt_regs *regs)
 165 {
 166         int ra;
 167         unsigned long ea;
 168
 169         ra = (instr >> 16) & 0x1f;
 170         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 171         if (ra)
 172                 ea += regs->gpr[ra];
 173
 174         return ea;
 175 }
 176 #endif /* __powerpc64 */
 177
 178 /*
 179  * Calculate effective address for an X-form instruction
 180  */
 181 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 182                                               const struct pt_regs *regs)
 183 {
 184         int ra, rb;
 185         unsigned long ea;
 186
 187         ra = (instr >> 16) & 0x1f;
 188         rb = (instr >> 11) & 0x1f;
 189         ea = regs->gpr[rb];
 190         if (ra)
 191                 ea += regs->gpr[ra];
 192
 193         return ea;
 194 }
 195
 196 /*
 197  * Calculate effective address for a MLS:D-form / 8LS:D-form
 198  * prefixed instruction
 199  */
 200 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
 201                                                   unsigned int suffix,
 202                                                   const struct pt_regs *regs)
 203 {
 204         int ra, prefix_r;
 205         unsigned int  dd;
 206         unsigned long ea, d0, d1, d;
 207
 208         prefix_r = GET_PREFIX_R(instr);
 209         ra = GET_PREFIX_RA(suffix);
 210
 211         d0 = instr & 0x3ffff;
 212         d1 = suffix & 0xffff;
 213         d = (d0 << 16) | d1;
 214
 215         /*
 216          * sign extend a 34 bit number
 217          */
 218         dd = (unsigned int)(d >> 2);
 219         ea = (signed int)dd;
 220         ea = (ea << 2) | (d & 0x3);
 221
 222         if (!prefix_r && ra)
 223                 ea += regs->gpr[ra];
 224         else if (!prefix_r && !ra)
 225                 ; /* Leave ea as is */
 226         else if (prefix_r)
 227                 ea += regs->nip;
 228
 229         /*
 230          * (prefix_r && ra) is an invalid form. Should already be
 231          * checked for by caller!
 232          */
 233
 234         return ea;
 235 }
 236
 237 /*
 238  * Return the largest power of 2, not greater than sizeof(unsigned long),
 239  * such that x is a multiple of it.
 240  */
 241 static nokprobe_inline unsigned long max_align(unsigned long x)
 242 {
 243         x |= sizeof(unsigned long);
 244         return x & -x;          /* isolates rightmost bit */
 245 }
 246
 247 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 248 {
 249         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 250 }
 251
 252 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 253 {
 254         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 255                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 256 }
 257
 258 #ifdef __powerpc64__
 259 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 260 {
 261         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 262 }
 263 #endif
 264
 265 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 266 {
 267         switch (nb) {
 268         case 2:
 269                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 270                 break;
 271         case 4:
 272                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 273                 break;
 274 #ifdef __powerpc64__
 275         case 8:
 276                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 277                 break;
 278         case 16: {
 279                 unsigned long *up = (unsigned long *)ptr;
 280                 unsigned long tmp;
 281                 tmp = byterev_8(up[0]);
 282                 up[0] = byterev_8(up[1]);
 283                 up[1] = tmp;
 284                 break;
 285         }
 286         case 32: {
 287                 unsigned long *up = (unsigned long *)ptr;
 288                 unsigned long tmp;
 289
 290                 tmp = byterev_8(up[0]);
 291                 up[0] = byterev_8(up[3]);
 292                 up[3] = tmp;
 293                 tmp = byterev_8(up[2]);
 294                 up[2] = byterev_8(up[1]);
 295                 up[1] = tmp;
 296                 break;
 297         }
 298
 299 #endif
 300         default:
 301                 WARN_ON_ONCE(1);
 302         }
 303 }
 304
 305 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 306                                             unsigned long ea, int nb,
 307                                             struct pt_regs *regs)
 308 {
 309         int err = 0;
 310         unsigned long x = 0;
 311
 312         switch (nb) {
 313         case 1:
 314                 err = __get_user(x, (unsigned char __user *) ea);
 315                 break;
 316         case 2:
 317                 err = __get_user(x, (unsigned short __user *) ea);
 318                 break;
 319         case 4:
 320                 err = __get_user(x, (unsigned int __user *) ea);
 321                 break;
 322 #ifdef __powerpc64__
 323         case 8:
 324                 err = __get_user(x, (unsigned long __user *) ea);
 325                 break;
 326 #endif
 327         }
 328         if (!err)
 329                 *dest = x;
 330         else
 331                 regs->dar = ea;
 332         return err;
 333 }
 334
 335 /*
 336  * Copy from userspace to a buffer, using the largest possible
 337  * aligned accesses, up to sizeof(long).
 338  */
 339 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 340                                        struct pt_regs *regs)
 341 {
 342         int err = 0;
 343         int c;
 344
 345         for (; nb > 0; nb -= c) {
 346                 c = max_align(ea);
 347                 if (c > nb)
 348                         c = max_align(nb);
 349                 switch (c) {
 350                 case 1:
 351                         err = __get_user(*dest, (unsigned char __user *) ea);
 352                         break;
 353                 case 2:
 354                         err = __get_user(*(u16 *)dest,
 355                                          (unsigned short __user *) ea);
 356                         break;
 357                 case 4:
 358                         err = __get_user(*(u32 *)dest,
 359                                          (unsigned int __user *) ea);
 360                         break;
 361 #ifdef __powerpc64__
 362                 case 8:
 363                         err = __get_user(*(unsigned long *)dest,
 364                                          (unsigned long __user *) ea);
 365                         break;
 366 #endif
 367                 }
 368                 if (err) {
 369                         regs->dar = ea;
 370                         return err;
 371                 }
 372                 dest += c;
 373                 ea += c;
 374         }
 375         return 0;
 376 }
 377
 378 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 379                                               unsigned long ea, int nb,
 380                                               struct pt_regs *regs)
 381 {
 382         union {
 383                 unsigned long ul;
 384                 u8 b[sizeof(unsigned long)];
 385         } u;
 386         int i;
 387         int err;
 388
 389         u.ul = 0;
 390         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 391         err = copy_mem_in(&u.b[i], ea, nb, regs);
 392         if (!err)
 393                 *dest = u.ul;
 394         return err;
 395 }
 396
 397 /*
 398  * Read memory at address ea for nb bytes, return 0 for success
 399  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 400  * If nb < sizeof(long), the result is right-justified on BE systems.
 401  */
 402 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 403                               struct pt_regs *regs)
 404 {
 405         if (!address_ok(regs, ea, nb))
 406                 return -EFAULT;
 407         if ((ea & (nb - 1)) == 0)
 408                 return read_mem_aligned(dest, ea, nb, regs);
 409         return read_mem_unaligned(dest, ea, nb, regs);
 410 }
 411 NOKPROBE_SYMBOL(read_mem);
 412
 413 static nokprobe_inline int write_mem_aligned(unsigned long val,
 414                                              unsigned long ea, int nb,
 415                                              struct pt_regs *regs)
 416 {
 417         int err = 0;
 418
 419         switch (nb) {
 420         case 1:
 421                 err = __put_user(val, (unsigned char __user *) ea);
 422                 break;
 423         case 2:
 424                 err = __put_user(val, (unsigned short __user *) ea);
 425                 break;
 426         case 4:
 427                 err = __put_user(val, (unsigned int __user *) ea);
 428                 break;
 429 #ifdef __powerpc64__
 430         case 8:
 431                 err = __put_user(val, (unsigned long __user *) ea);
 432                 break;
 433 #endif
 434         }
 435         if (err)
 436                 regs->dar = ea;
 437         return err;
 438 }
 439
 440 /*
 441  * Copy from a buffer to userspace, using the largest possible
 442  * aligned accesses, up to sizeof(long).
 443  */
 444 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 445                                         struct pt_regs *regs)
 446 {
 447         int err = 0;
 448         int c;
 449
 450         for (; nb > 0; nb -= c) {
 451                 c = max_align(ea);
 452                 if (c > nb)
 453                         c = max_align(nb);
 454                 switch (c) {
 455                 case 1:
 456                         err = __put_user(*dest, (unsigned char __user *) ea);
 457                         break;
 458                 case 2:
 459                         err = __put_user(*(u16 *)dest,
 460                                          (unsigned short __user *) ea);
 461                         break;
 462                 case 4:
 463                         err = __put_user(*(u32 *)dest,
 464                                          (unsigned int __user *) ea);
 465                         break;
 466 #ifdef __powerpc64__
 467                 case 8:
 468                         err = __put_user(*(unsigned long *)dest,
 469                                          (unsigned long __user *) ea);
 470                         break;
 471 #endif
 472                 }
 473                 if (err) {
 474                         regs->dar = ea;
 475                         return err;
 476                 }
 477                 dest += c;
 478                 ea += c;
 479         }
 480         return 0;
 481 }
 482
 483 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 484                                                unsigned long ea, int nb,
 485                                                struct pt_regs *regs)
 486 {
 487         union {
 488                 unsigned long ul;
 489                 u8 b[sizeof(unsigned long)];
 490         } u;
 491         int i;
 492
 493         u.ul = val;
 494         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 495         return copy_mem_out(&u.b[i], ea, nb, regs);
 496 }
 497
 498 /*
 499  * Write memory at address ea for nb bytes, return 0 for success
 500  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 501  */
 502 static int write_mem(unsigned long val, unsigned long ea, int nb,
 503                                struct pt_regs *regs)
 504 {
 505         if (!address_ok(regs, ea, nb))
 506                 return -EFAULT;
 507         if ((ea & (nb - 1)) == 0)
 508                 return write_mem_aligned(val, ea, nb, regs);
 509         return write_mem_unaligned(val, ea, nb, regs);
 510 }
 511 NOKPROBE_SYMBOL(write_mem);
 512
 513 #ifdef CONFIG_PPC_FPU
 514 /*
 515  * These access either the real FP register or the image in the
 516  * thread_struct, depending on regs->msr & MSR_FP.
 517  */
 518 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 519                       struct pt_regs *regs, bool cross_endian)
 520 {
 521         int err, rn, nb;
 522         union {
 523                 int i;
 524                 unsigned int u;
 525                 float f;
 526                 double d[2];
 527                 unsigned long l[2];
 528                 u8 b[2 * sizeof(double)];
 529         } u;
 530
 531         nb = GETSIZE(op->type);
 532         if (!address_ok(regs, ea, nb))
 533                 return -EFAULT;
 534         rn = op->reg;
 535         err = copy_mem_in(u.b, ea, nb, regs);
 536         if (err)
 537                 return err;
 538         if (unlikely(cross_endian)) {
 539                 do_byte_reverse(u.b, min(nb, 8));
 540                 if (nb == 16)
 541                         do_byte_reverse(&u.b[8], 8);
 542         }
 543         preempt_disable();
 544         if (nb == 4) {
 545                 if (op->type & FPCONV)
 546                         conv_sp_to_dp(&u.f, &u.d[0]);
 547                 else if (op->type & SIGNEXT)
 548                         u.l[0] = u.i;
 549                 else
 550                         u.l[0] = u.u;
 551         }
 552         if (regs->msr & MSR_FP)
 553                 put_fpr(rn, &u.d[0]);
 554         else
 555                 current->thread.TS_FPR(rn) = u.l[0];
 556         if (nb == 16) {
 557                 /* lfdp */
 558                 rn |= 1;
 559                 if (regs->msr & MSR_FP)
 560                         put_fpr(rn, &u.d[1]);
 561                 else
 562                         current->thread.TS_FPR(rn) = u.l[1];
 563         }
 564         preempt_enable();
 565         return 0;
 566 }
 567 NOKPROBE_SYMBOL(do_fp_load);
 568
 569 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 570                        struct pt_regs *regs, bool cross_endian)
 571 {
 572         int rn, nb;
 573         union {
 574                 unsigned int u;
 575                 float f;
 576                 double d[2];
 577                 unsigned long l[2];
 578                 u8 b[2 * sizeof(double)];
 579         } u;
 580
 581         nb = GETSIZE(op->type);
 582         if (!address_ok(regs, ea, nb))
 583                 return -EFAULT;
 584         rn = op->reg;
 585         preempt_disable();
 586         if (regs->msr & MSR_FP)
 587                 get_fpr(rn, &u.d[0]);
 588         else
 589                 u.l[0] = current->thread.TS_FPR(rn);
 590         if (nb == 4) {
 591                 if (op->type & FPCONV)
 592                         conv_dp_to_sp(&u.d[0], &u.f);
 593                 else
 594                         u.u = u.l[0];
 595         }
 596         if (nb == 16) {
 597                 rn |= 1;
 598                 if (regs->msr & MSR_FP)
 599                         get_fpr(rn, &u.d[1]);
 600                 else
 601                         u.l[1] = current->thread.TS_FPR(rn);
 602         }
 603         preempt_enable();
 604         if (unlikely(cross_endian)) {
 605                 do_byte_reverse(u.b, min(nb, 8));
 606                 if (nb == 16)
 607                         do_byte_reverse(&u.b[8], 8);
 608         }
 609         return copy_mem_out(u.b, ea, nb, regs);
 610 }
 611 NOKPROBE_SYMBOL(do_fp_store);
 612 #endif
 613
 614 #ifdef CONFIG_ALTIVEC
 615 /* For Altivec/VMX, no need to worry about alignment */
 616 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 617                                        int size, struct pt_regs *regs,
 618                                        bool cross_endian)
 619 {
 620         int err;
 621         union {
 622                 __vector128 v;
 623                 u8 b[sizeof(__vector128)];
 624         } u = {};
 625
 626         if (!address_ok(regs, ea & ~0xfUL, 16))
 627                 return -EFAULT;
 628         /* align to multiple of size */
 629         ea &= ~(size - 1);
 630         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 631         if (err)
 632                 return err;
 633         if (unlikely(cross_endian))
 634                 do_byte_reverse(&u.b[ea & 0xf], size);
 635         preempt_disable();
 636         if (regs->msr & MSR_VEC)
 637                 put_vr(rn, &u.v);
 638         else
 639                 current->thread.vr_state.vr[rn] = u.v;
 640         preempt_enable();
 641         return 0;
 642 }
 643
 644 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 645                                         int size, struct pt_regs *regs,
 646                                         bool cross_endian)
 647 {
 648         union {
 649                 __vector128 v;
 650                 u8 b[sizeof(__vector128)];
 651         } u;
 652
 653         if (!address_ok(regs, ea & ~0xfUL, 16))
 654                 return -EFAULT;
 655         /* align to multiple of size */
 656         ea &= ~(size - 1);
 657
 658         preempt_disable();
 659         if (regs->msr & MSR_VEC)
 660                 get_vr(rn, &u.v);
 661         else
 662                 u.v = current->thread.vr_state.vr[rn];
 663         preempt_enable();
 664         if (unlikely(cross_endian))
 665                 do_byte_reverse(&u.b[ea & 0xf], size);
 666         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 667 }
 668 #endif /* CONFIG_ALTIVEC */
 669
 670 #ifdef __powerpc64__
 671 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 672                                       int reg, bool cross_endian)
 673 {
 674         int err;
 675
 676         if (!address_ok(regs, ea, 16))
 677                 return -EFAULT;
 678         /* if aligned, should be atomic */
 679         if ((ea & 0xf) == 0) {
 680                 err = do_lq(ea, &regs->gpr[reg]);
 681         } else {
 682                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 683                 if (!err)
 684                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 685         }
 686         if (!err && unlikely(cross_endian))
 687                 do_byte_reverse(&regs->gpr[reg], 16);
 688         return err;
 689 }
 690
 691 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 692                                        int reg, bool cross_endian)
 693 {
 694         int err;
 695         unsigned long vals[2];
 696
 697         if (!address_ok(regs, ea, 16))
 698                 return -EFAULT;
 699         vals[0] = regs->gpr[reg];
 700         vals[1] = regs->gpr[reg + 1];
 701         if (unlikely(cross_endian))
 702                 do_byte_reverse(vals, 16);
 703
 704         /* if aligned, should be atomic */
 705         if ((ea & 0xf) == 0)
 706                 return do_stq(ea, vals[0], vals[1]);
 707
 708         err = write_mem(vals[IS_LE], ea, 8, regs);
 709         if (!err)
 710                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 711         return err;
 712 }
 713 #endif /* __powerpc64 */
 714
 715 #ifdef CONFIG_VSX
 716 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 717                       const void *mem, bool rev)
 718 {
 719         int size, read_size;
 720         int i, j;
 721         const unsigned int *wp;
 722         const unsigned short *hp;
 723         const unsigned char *bp;
 724
 725         size = GETSIZE(op->type);
 726         reg->d[0] = reg->d[1] = 0;
 727
 728         switch (op->element_size) {
 729         case 32:
 730                 /* [p]lxvp[x] */
 731         case 16:
 732                 /* whole vector; lxv[x] or lxvl[l] */
 733                 if (size == 0)
 734                         break;
 735                 memcpy(reg, mem, size);
 736                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 737                         rev = !rev;
 738                 if (rev)
 739                         do_byte_reverse(reg, size);
 740                 break;
 741         case 8:
 742                 /* scalar loads, lxvd2x, lxvdsx */
 743                 read_size = (size >= 8) ? 8 : size;
 744                 i = IS_LE ? 8 : 8 - read_size;
 745                 memcpy(&reg->b[i], mem, read_size);
 746                 if (rev)
 747                         do_byte_reverse(&reg->b[i], 8);
 748                 if (size < 8) {
 749                         if (op->type & SIGNEXT) {
 750                                 /* size == 4 is the only case here */
 751                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 752                         } else if (op->vsx_flags & VSX_FPCONV) {
 753                                 preempt_disable();
 754                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 755                                               &reg->dp[IS_LE]);
 756                                 preempt_enable();
 757                         }
 758                 } else {
 759                         if (size == 16) {
 760                                 unsigned long v = *(unsigned long *)(mem + 8);
 761                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 762                         } else if (op->vsx_flags & VSX_SPLAT)
 763                                 reg->d[IS_BE] = reg->d[IS_LE];
 764                 }
 765                 break;
 766         case 4:
 767                 /* lxvw4x, lxvwsx */
 768                 wp = mem;
 769                 for (j = 0; j < size / 4; ++j) {
 770                         i = IS_LE ? 3 - j : j;
 771                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 772                 }
 773                 if (op->vsx_flags & VSX_SPLAT) {
 774                         u32 val = reg->w[IS_LE ? 3 : 0];
 775                         for (; j < 4; ++j) {
 776                                 i = IS_LE ? 3 - j : j;
 777                                 reg->w[i] = val;
 778                         }
 779                 }
 780                 break;
 781         case 2:
 782                 /* lxvh8x */
 783                 hp = mem;
 784                 for (j = 0; j < size / 2; ++j) {
 785                         i = IS_LE ? 7 - j : j;
 786                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 787                 }
 788                 break;
 789         case 1:
 790                 /* lxvb16x */
 791                 bp = mem;
 792                 for (j = 0; j < size; ++j) {
 793                         i = IS_LE ? 15 - j : j;
 794                         reg->b[i] = *bp++;
 795                 }
 796                 break;
 797         }
 798 }
 799 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 800 NOKPROBE_SYMBOL(emulate_vsx_load);
 801
 802 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 803                        void *mem, bool rev)
 804 {
 805         int size, write_size;
 806         int i, j;
 807         union vsx_reg buf;
 808         unsigned int *wp;
 809         unsigned short *hp;
 810         unsigned char *bp;
 811
 812         size = GETSIZE(op->type);
 813
 814         switch (op->element_size) {
 815         case 32:
 816                 /* [p]stxvp[x] */
 817                 if (size == 0)
 818                         break;
 819                 if (rev) {
 820                         /* reverse 32 bytes */
 821                         buf.d[0] = byterev_8(reg->d[3]);
 822                         buf.d[1] = byterev_8(reg->d[2]);
 823                         buf.d[2] = byterev_8(reg->d[1]);
 824                         buf.d[3] = byterev_8(reg->d[0]);
 825                         reg = &buf;
 826                 }
 827                 memcpy(mem, reg, size);
 828                 break;
 829         case 16:
 830                 /* stxv, stxvx, stxvl, stxvll */
 831                 if (size == 0)
 832                         break;
 833                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 834                         rev = !rev;
 835                 if (rev) {
 836                         /* reverse 16 bytes */
 837                         buf.d[0] = byterev_8(reg->d[1]);
 838                         buf.d[1] = byterev_8(reg->d[0]);
 839                         reg = &buf;
 840                 }
 841                 memcpy(mem, reg, size);
 842                 break;
 843         case 8:
 844                 /* scalar stores, stxvd2x */
 845                 write_size = (size >= 8) ? 8 : size;
 846                 i = IS_LE ? 8 : 8 - write_size;
 847                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 848                         buf.d[0] = buf.d[1] = 0;
 849                         preempt_disable();
 850                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 851                         preempt_enable();
 852                         reg = &buf;
 853                 }
 854                 memcpy(mem, &reg->b[i], write_size);
 855                 if (size == 16)
 856                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 857                 if (unlikely(rev)) {
 858                         do_byte_reverse(mem, write_size);
 859                         if (size == 16)
 860                                 do_byte_reverse(mem + 8, 8);
 861                 }
 862                 break;
 863         case 4:
 864                 /* stxvw4x */
 865                 wp = mem;
 866                 for (j = 0; j < size / 4; ++j) {
 867                         i = IS_LE ? 3 - j : j;
 868                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 869                 }
 870                 break;
 871         case 2:
 872                 /* stxvh8x */
 873                 hp = mem;
 874                 for (j = 0; j < size / 2; ++j) {
 875                         i = IS_LE ? 7 - j : j;
 876                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 877                 }
 878                 break;
 879         case 1:
 880                 /* stvxb16x */
 881                 bp = mem;
 882                 for (j = 0; j < size; ++j) {
 883                         i = IS_LE ? 15 - j : j;
 884                         *bp++ = reg->b[i];
 885                 }
 886                 break;
 887         }
 888 }
 889 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 890 NOKPROBE_SYMBOL(emulate_vsx_store);
 891
 892 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 893                                        unsigned long ea, struct pt_regs *regs,
 894                                        bool cross_endian)
 895 {
 896         int reg = op->reg;
 897         int i, j, nr_vsx_regs;
 898         u8 mem[32];
 899         union vsx_reg buf[2];
 900         int size = GETSIZE(op->type);
 901
 902         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 903                 return -EFAULT;
 904
 905         nr_vsx_regs = size / sizeof(__vector128);
 906         emulate_vsx_load(op, buf, mem, cross_endian);
 907         preempt_disable();
 908         if (reg < 32) {
 909                 /* FP regs + extensions */
 910                 if (regs->msr & MSR_FP) {
 911                         for (i = 0; i < nr_vsx_regs; i++) {
 912                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 913                                 load_vsrn(reg + i, &buf[j].v);
 914                         }
 915                 } else {
 916                         for (i = 0; i < nr_vsx_regs; i++) {
 917                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 918                                 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
 919                                 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
 920                         }
 921                 }
 922         } else {
 923                 if (regs->msr & MSR_VEC) {
 924                         for (i = 0; i < nr_vsx_regs; i++) {
 925                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 926                                 load_vsrn(reg + i, &buf[j].v);
 927                         }
 928                 } else {
 929                         for (i = 0; i < nr_vsx_regs; i++) {
 930                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 931                                 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
 932                         }
 933                 }
 934         }
 935         preempt_enable();
 936         return 0;
 937 }
 938
 939 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 940                                         unsigned long ea, struct pt_regs *regs,
 941                                         bool cross_endian)
 942 {
 943         int reg = op->reg;
 944         int i, j, nr_vsx_regs;
 945         u8 mem[32];
 946         union vsx_reg buf[2];
 947         int size = GETSIZE(op->type);
 948
 949         if (!address_ok(regs, ea, size))
 950                 return -EFAULT;
 951
 952         nr_vsx_regs = size / sizeof(__vector128);
 953         preempt_disable();
 954         if (reg < 32) {
 955                 /* FP regs + extensions */
 956                 if (regs->msr & MSR_FP) {
 957                         for (i = 0; i < nr_vsx_regs; i++) {
 958                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 959                                 store_vsrn(reg + i, &buf[j].v);
 960                         }
 961                 } else {
 962                         for (i = 0; i < nr_vsx_regs; i++) {
 963                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 964                                 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
 965                                 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
 966                         }
 967                 }
 968         } else {
 969                 if (regs->msr & MSR_VEC) {
 970                         for (i = 0; i < nr_vsx_regs; i++) {
 971                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 972                                 store_vsrn(reg + i, &buf[j].v);
 973                         }
 974                 } else {
 975                         for (i = 0; i < nr_vsx_regs; i++) {
 976                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 977                                 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
 978                         }
 979                 }
 980         }
 981         preempt_enable();
 982         emulate_vsx_store(op, buf, mem, cross_endian);
 983         return  copy_mem_out(mem, ea, size, regs);
 984 }
 985 #endif /* CONFIG_VSX */
 986
 987 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 988 {
 989         int err;
 990         unsigned long i, size;
 991
 992 #ifdef __powerpc64__
 993         size = ppc64_caches.l1d.block_size;
 994         if (!(regs->msr & MSR_64BIT))
 995                 ea &= 0xffffffffUL;
 996 #else
 997         size = L1_CACHE_BYTES;
 998 #endif
 999         ea &= ~(size - 1);
1000         if (!address_ok(regs, ea, size))
1001                 return -EFAULT;
1002         for (i = 0; i < size; i += sizeof(long)) {
1003                 err = __put_user(0, (unsigned long __user *) (ea + i));
1004                 if (err) {
1005                         regs->dar = ea;
1006                         return err;
1007                 }
1008         }
1009         return 0;
1010 }
1011 NOKPROBE_SYMBOL(emulate_dcbz);
1012
1013 #define __put_user_asmx(x, addr, err, op, cr)           \
1014         __asm__ __volatile__(                           \
1015                 "1:     " op " %2,0,%3\n"               \
1016                 "       mfcr    %1\n"                   \
1017                 "2:\n"                                  \
1018                 ".section .fixup,\"ax\"\n"              \
1019                 "3:     li      %0,%4\n"                \
1020                 "       b       2b\n"                   \
1021                 ".previous\n"                           \
1022                 EX_TABLE(1b, 3b)                        \
1023                 : "=r" (err), "=r" (cr)                 \
1024                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1025
1026 #define __get_user_asmx(x, addr, err, op)               \
1027         __asm__ __volatile__(                           \
1028                 "1:     "op" %1,0,%2\n"                 \
1029                 "2:\n"                                  \
1030                 ".section .fixup,\"ax\"\n"              \
1031                 "3:     li      %0,%3\n"                \
1032                 "       b       2b\n"                   \
1033                 ".previous\n"                           \
1034                 EX_TABLE(1b, 3b)                        \
1035                 : "=r" (err), "=r" (x)                  \
1036                 : "r" (addr), "i" (-EFAULT), "0" (err))
1037
1038 #define __cacheop_user_asmx(addr, err, op)              \
1039         __asm__ __volatile__(                           \
1040                 "1:     "op" 0,%1\n"                    \
1041                 "2:\n"                                  \
1042                 ".section .fixup,\"ax\"\n"              \
1043                 "3:     li      %0,%3\n"                \
1044                 "       b       2b\n"                   \
1045                 ".previous\n"                           \
1046                 EX_TABLE(1b, 3b)                        \
1047                 : "=r" (err)                            \
1048                 : "r" (addr), "i" (-EFAULT), "0" (err))
1049
1050 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1051                                     struct instruction_op *op)
1052 {
1053         long val = op->val;
1054
1055         op->type |= SETCC;
1056         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1057 #ifdef __powerpc64__
1058         if (!(regs->msr & MSR_64BIT))
1059                 val = (int) val;
1060 #endif
1061         if (val < 0)
1062                 op->ccval |= 0x80000000;
1063         else if (val > 0)
1064                 op->ccval |= 0x40000000;
1065         else
1066                 op->ccval |= 0x20000000;
1067 }
1068
1069 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1070 {
1071         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1072                 if (val)
1073                         op->xerval |= XER_CA32;
1074                 else
1075                         op->xerval &= ~XER_CA32;
1076         }
1077 }
1078
1079 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1080                                      struct instruction_op *op, int rd,
1081                                      unsigned long val1, unsigned long val2,
1082                                      unsigned long carry_in)
1083 {
1084         unsigned long val = val1 + val2;
1085
1086         if (carry_in)
1087                 ++val;
1088         op->type = COMPUTE + SETREG + SETXER;
1089         op->reg = rd;
1090         op->val = val;
1091 #ifdef __powerpc64__
1092         if (!(regs->msr & MSR_64BIT)) {
1093                 val = (unsigned int) val;
1094                 val1 = (unsigned int) val1;
1095         }
1096 #endif
1097         op->xerval = regs->xer;
1098         if (val < val1 || (carry_in && val == val1))
1099                 op->xerval |= XER_CA;
1100         else
1101                 op->xerval &= ~XER_CA;
1102
1103         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1104                         (carry_in && (unsigned int)val == (unsigned int)val1));
1105 }
1106
1107 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1108                                           struct instruction_op *op,
1109                                           long v1, long v2, int crfld)
1110 {
1111         unsigned int crval, shift;
1112
1113         op->type = COMPUTE + SETCC;
1114         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1115         if (v1 < v2)
1116                 crval |= 8;
1117         else if (v1 > v2)
1118                 crval |= 4;
1119         else
1120                 crval |= 2;
1121         shift = (7 - crfld) * 4;
1122         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1123 }
1124
1125 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1126                                             struct instruction_op *op,
1127                                             unsigned long v1,
1128                                             unsigned long v2, int crfld)
1129 {
1130         unsigned int crval, shift;
1131
1132         op->type = COMPUTE + SETCC;
1133         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1134         if (v1 < v2)
1135                 crval |= 8;
1136         else if (v1 > v2)
1137                 crval |= 4;
1138         else
1139                 crval |= 2;
1140         shift = (7 - crfld) * 4;
1141         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1142 }
1143
1144 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1145                                     struct instruction_op *op,
1146                                     unsigned long v1, unsigned long v2)
1147 {
1148         unsigned long long out_val, mask;
1149         int i;
1150
1151         out_val = 0;
1152         for (i = 0; i < 8; i++) {
1153                 mask = 0xffUL << (i * 8);
1154                 if ((v1 & mask) == (v2 & mask))
1155                         out_val |= mask;
1156         }
1157         op->val = out_val;
1158 }
1159
1160 /*
1161  * The size parameter is used to adjust the equivalent popcnt instruction.
1162  * popcntb = 8, popcntw = 32, popcntd = 64
1163  */
1164 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1165                                       struct instruction_op *op,
1166                                       unsigned long v1, int size)
1167 {
1168         unsigned long long out = v1;
1169
1170         out -= (out >> 1) & 0x5555555555555555ULL;
1171         out = (0x3333333333333333ULL & out) +
1172               (0x3333333333333333ULL & (out >> 2));
1173         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1174
1175         if (size == 8) {        /* popcntb */
1176                 op->val = out;
1177                 return;
1178         }
1179         out += out >> 8;
1180         out += out >> 16;
1181         if (size == 32) {       /* popcntw */
1182                 op->val = out & 0x0000003f0000003fULL;
1183                 return;
1184         }
1185
1186         out = (out + (out >> 32)) & 0x7f;
1187         op->val = out;  /* popcntd */
1188 }
1189
1190 #ifdef CONFIG_PPC64
1191 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1192                                       struct instruction_op *op,
1193                                       unsigned long v1, unsigned long v2)
1194 {
1195         unsigned char perm, idx;
1196         unsigned int i;
1197
1198         perm = 0;
1199         for (i = 0; i < 8; i++) {
1200                 idx = (v1 >> (i * 8)) & 0xff;
1201                 if (idx < 64)
1202                         if (v2 & PPC_BIT(idx))
1203                                 perm |= 1 << i;
1204         }
1205         op->val = perm;
1206 }
1207 #endif /* CONFIG_PPC64 */
1208 /*
1209  * The size parameter adjusts the equivalent prty instruction.
1210  * prtyw = 32, prtyd = 64
1211  */
1212 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1213                                     struct instruction_op *op,
1214                                     unsigned long v, int size)
1215 {
1216         unsigned long long res = v ^ (v >> 8);
1217
1218         res ^= res >> 16;
1219         if (size == 32) {               /* prtyw */
1220                 op->val = res & 0x0000000100000001ULL;
1221                 return;
1222         }
1223
1224         res ^= res >> 32;
1225         op->val = res & 1;      /*prtyd */
1226 }
1227
1228 static nokprobe_inline int trap_compare(long v1, long v2)
1229 {
1230         int ret = 0;
1231
1232         if (v1 < v2)
1233                 ret |= 0x10;
1234         else if (v1 > v2)
1235                 ret |= 0x08;
1236         else
1237                 ret |= 0x04;
1238         if ((unsigned long)v1 < (unsigned long)v2)
1239                 ret |= 0x02;
1240         else if ((unsigned long)v1 > (unsigned long)v2)
1241                 ret |= 0x01;
1242         return ret;
1243 }
1244
1245 /*
1246  * Elements of 32-bit rotate and mask instructions.
1247  */
1248 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1249                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1250 #ifdef __powerpc64__
1251 #define MASK64_L(mb)    (~0UL >> (mb))
1252 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1253 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1254 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1255 #else
1256 #define DATA32(x)       (x)
1257 #endif
1258 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1259
1260 /*
1261  * Decode an instruction, and return information about it in *op
1262  * without changing *regs.
1263  * Integer arithmetic and logical instructions, branches, and barrier
1264  * instructions can be emulated just using the information in *op.
1265  *
1266  * Return value is 1 if the instruction can be emulated just by
1267  * updating *regs with the information in *op, -1 if we need the
1268  * GPRs but *regs doesn't contain the full register set, or 0
1269  * otherwise.
1270  */
1271 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1272                   struct ppc_inst instr)
1273 {
1274 #ifdef CONFIG_PPC64
1275         unsigned int suffixopcode, prefixtype, prefix_r;
1276 #endif
1277         unsigned int opcode, ra, rb, rc, rd, spr, u;
1278         unsigned long int imm;
1279         unsigned long int val, val2;
1280         unsigned int mb, me, sh;
1281         unsigned int word, suffix;
1282         long ival;
1283
1284         word = ppc_inst_val(instr);
1285         suffix = ppc_inst_suffix(instr);
1286
1287         op->type = COMPUTE;
1288
1289         opcode = ppc_inst_primary_opcode(instr);
1290         switch (opcode) {
1291         case 16:        /* bc */
1292                 op->type = BRANCH;
1293                 imm = (signed short)(word & 0xfffc);
1294                 if ((word & 2) == 0)
1295                         imm += regs->nip;
1296                 op->val = truncate_if_32bit(regs->msr, imm);
1297                 if (word & 1)
1298                         op->type |= SETLK;
1299                 if (branch_taken(word, regs, op))
1300                         op->type |= BRTAKEN;
1301                 return 1;
1302 #ifdef CONFIG_PPC64
1303         case 17:        /* sc */
1304                 if ((word & 0xfe2) == 2)
1305                         op->type = SYSCALL;
1306                 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1307                                 (word & 0xfe3) == 1)
1308                         op->type = SYSCALL_VECTORED_0;
1309                 else
1310                         op->type = UNKNOWN;
1311                 return 0;
1312 #endif
1313         case 18:        /* b */
1314                 op->type = BRANCH | BRTAKEN;
1315                 imm = word & 0x03fffffc;
1316                 if (imm & 0x02000000)
1317                         imm -= 0x04000000;
1318                 if ((word & 2) == 0)
1319                         imm += regs->nip;
1320                 op->val = truncate_if_32bit(regs->msr, imm);
1321                 if (word & 1)
1322                         op->type |= SETLK;
1323                 return 1;
1324         case 19:
1325                 switch ((word >> 1) & 0x3ff) {
1326                 case 0:         /* mcrf */
1327                         op->type = COMPUTE + SETCC;
1328                         rd = 7 - ((word >> 23) & 0x7);
1329                         ra = 7 - ((word >> 18) & 0x7);
1330                         rd *= 4;
1331                         ra *= 4;
1332                         val = (regs->ccr >> ra) & 0xf;
1333                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1334                         return 1;
1335
1336                 case 16:        /* bclr */
1337                 case 528:       /* bcctr */
1338                         op->type = BRANCH;
1339                         imm = (word & 0x400)? regs->ctr: regs->link;
1340                         op->val = truncate_if_32bit(regs->msr, imm);
1341                         if (word & 1)
1342                                 op->type |= SETLK;
1343                         if (branch_taken(word, regs, op))
1344                                 op->type |= BRTAKEN;
1345                         return 1;
1346
1347                 case 18:        /* rfid, scary */
1348                         if (regs->msr & MSR_PR)
1349                                 goto priv;
1350                         op->type = RFI;
1351                         return 0;
1352
1353                 case 150:       /* isync */
1354                         op->type = BARRIER | BARRIER_ISYNC;
1355                         return 1;
1356
1357                 case 33:        /* crnor */
1358                 case 129:       /* crandc */
1359                 case 193:       /* crxor */
1360                 case 225:       /* crnand */
1361                 case 257:       /* crand */
1362                 case 289:       /* creqv */
1363                 case 417:       /* crorc */
1364                 case 449:       /* cror */
1365                         op->type = COMPUTE + SETCC;
1366                         ra = (word >> 16) & 0x1f;
1367                         rb = (word >> 11) & 0x1f;
1368                         rd = (word >> 21) & 0x1f;
1369                         ra = (regs->ccr >> (31 - ra)) & 1;
1370                         rb = (regs->ccr >> (31 - rb)) & 1;
1371                         val = (word >> (6 + ra * 2 + rb)) & 1;
1372                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1373                                 (val << (31 - rd));
1374                         return 1;
1375                 }
1376                 break;
1377         case 31:
1378                 switch ((word >> 1) & 0x3ff) {
1379                 case 598:       /* sync */
1380                         op->type = BARRIER + BARRIER_SYNC;
1381 #ifdef __powerpc64__
1382                         switch ((word >> 21) & 3) {
1383                         case 1:         /* lwsync */
1384                                 op->type = BARRIER + BARRIER_LWSYNC;
1385                                 break;
1386                         case 2:         /* ptesync */
1387                                 op->type = BARRIER + BARRIER_PTESYNC;
1388                                 break;
1389                         }
1390 #endif
1391                         return 1;
1392
1393                 case 854:       /* eieio */
1394                         op->type = BARRIER + BARRIER_EIEIO;
1395                         return 1;
1396                 }
1397                 break;
1398         }
1399
1400         /* Following cases refer to regs->gpr[], so we need all regs */
1401         if (!FULL_REGS(regs))
1402                 return -1;
1403
1404         rd = (word >> 21) & 0x1f;
1405         ra = (word >> 16) & 0x1f;
1406         rb = (word >> 11) & 0x1f;
1407         rc = (word >> 6) & 0x1f;
1408
1409         switch (opcode) {
1410 #ifdef __powerpc64__
1411         case 1:
1412                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1413                         return -1;
1414
1415                 prefix_r = GET_PREFIX_R(word);
1416                 ra = GET_PREFIX_RA(suffix);
1417                 rd = (suffix >> 21) & 0x1f;
1418                 op->reg = rd;
1419                 op->val = regs->gpr[rd];
1420                 suffixopcode = get_op(suffix);
1421                 prefixtype = (word >> 24) & 0x3;
1422                 switch (prefixtype) {
1423                 case 2:
1424                         if (prefix_r && ra)
1425                                 return 0;
1426                         switch (suffixopcode) {
1427                         case 14:        /* paddi */
1428                                 op->type = COMPUTE | PREFIXED;
1429                                 op->val = mlsd_8lsd_ea(word, suffix, regs);
1430                                 goto compute_done;
1431                         }
1432                 }
1433                 break;
1434         case 2:         /* tdi */
1435                 if (rd & trap_compare(regs->gpr[ra], (short) word))
1436                         goto trap;
1437                 return 1;
1438 #endif
1439         case 3:         /* twi */
1440                 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1441                         goto trap;
1442                 return 1;
1443
1444 #ifdef __powerpc64__
1445         case 4:
1446                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1447                         return -1;
1448
1449                 switch (word & 0x3f) {
1450                 case 48:        /* maddhd */
1451                         asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1452                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1453                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1454                         goto compute_done;
1455
1456                 case 49:        /* maddhdu */
1457                         asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1458                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1459                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1460                         goto compute_done;
1461
1462                 case 51:        /* maddld */
1463                         asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1464                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1465                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1466                         goto compute_done;
1467                 }
1468
1469                 /*
1470                  * There are other instructions from ISA 3.0 with the same
1471                  * primary opcode which do not have emulation support yet.
1472                  */
1473                 return -1;
1474 #endif
1475
1476         case 7:         /* mulli */
1477                 op->val = regs->gpr[ra] * (short) word;
1478                 goto compute_done;
1479
1480         case 8:         /* subfic */
1481                 imm = (short) word;
1482                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1483                 return 1;
1484
1485         case 10:        /* cmpli */
1486                 imm = (unsigned short) word;
1487                 val = regs->gpr[ra];
1488 #ifdef __powerpc64__
1489                 if ((rd & 1) == 0)
1490                         val = (unsigned int) val;
1491 #endif
1492                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1493                 return 1;
1494
1495         case 11:        /* cmpi */
1496                 imm = (short) word;
1497                 val = regs->gpr[ra];
1498 #ifdef __powerpc64__
1499                 if ((rd & 1) == 0)
1500                         val = (int) val;
1501 #endif
1502                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1503                 return 1;
1504
1505         case 12:        /* addic */
1506                 imm = (short) word;
1507                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1508                 return 1;
1509
1510         case 13:        /* addic. */
1511                 imm = (short) word;
1512                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1513                 set_cr0(regs, op);
1514                 return 1;
1515
1516         case 14:        /* addi */
1517                 imm = (short) word;
1518                 if (ra)
1519                         imm += regs->gpr[ra];
1520                 op->val = imm;
1521                 goto compute_done;
1522
1523         case 15:        /* addis */
1524                 imm = ((short) word) << 16;
1525                 if (ra)
1526                         imm += regs->gpr[ra];
1527                 op->val = imm;
1528                 goto compute_done;
1529
1530         case 19:
1531                 if (((word >> 1) & 0x1f) == 2) {
1532                         /* addpcis */
1533                         imm = (short) (word & 0xffc1);  /* d0 + d2 fields */
1534                         imm |= (word >> 15) & 0x3e;     /* d1 field */
1535                         op->val = regs->nip + (imm << 16) + 4;
1536                         goto compute_done;
1537                 }
1538                 op->type = UNKNOWN;
1539                 return 0;
1540
1541         case 20:        /* rlwimi */
1542                 mb = (word >> 6) & 0x1f;
1543                 me = (word >> 1) & 0x1f;
1544                 val = DATA32(regs->gpr[rd]);
1545                 imm = MASK32(mb, me);
1546                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1547                 goto logical_done;
1548
1549         case 21:        /* rlwinm */
1550                 mb = (word >> 6) & 0x1f;
1551                 me = (word >> 1) & 0x1f;
1552                 val = DATA32(regs->gpr[rd]);
1553                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1554                 goto logical_done;
1555
1556         case 23:        /* rlwnm */
1557                 mb = (word >> 6) & 0x1f;
1558                 me = (word >> 1) & 0x1f;
1559                 rb = regs->gpr[rb] & 0x1f;
1560                 val = DATA32(regs->gpr[rd]);
1561                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1562                 goto logical_done;
1563
1564         case 24:        /* ori */
1565                 op->val = regs->gpr[rd] | (unsigned short) word;
1566                 goto logical_done_nocc;
1567
1568         case 25:        /* oris */
1569                 imm = (unsigned short) word;
1570                 op->val = regs->gpr[rd] | (imm << 16);
1571                 goto logical_done_nocc;
1572
1573         case 26:        /* xori */
1574                 op->val = regs->gpr[rd] ^ (unsigned short) word;
1575                 goto logical_done_nocc;
1576
1577         case 27:        /* xoris */
1578                 imm = (unsigned short) word;
1579                 op->val = regs->gpr[rd] ^ (imm << 16);
1580                 goto logical_done_nocc;
1581
1582         case 28:        /* andi. */
1583                 op->val = regs->gpr[rd] & (unsigned short) word;
1584                 set_cr0(regs, op);
1585                 goto logical_done_nocc;
1586
1587         case 29:        /* andis. */
1588                 imm = (unsigned short) word;
1589                 op->val = regs->gpr[rd] & (imm << 16);
1590                 set_cr0(regs, op);
1591                 goto logical_done_nocc;
1592
1593 #ifdef __powerpc64__
1594         case 30:        /* rld* */
1595                 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1596                 val = regs->gpr[rd];
1597                 if ((word & 0x10) == 0) {
1598                         sh = rb | ((word & 2) << 4);
1599                         val = ROTATE(val, sh);
1600                         switch ((word >> 2) & 3) {
1601                         case 0:         /* rldicl */
1602                                 val &= MASK64_L(mb);
1603                                 break;
1604                         case 1:         /* rldicr */
1605                                 val &= MASK64_R(mb);
1606                                 break;
1607                         case 2:         /* rldic */
1608                                 val &= MASK64(mb, 63 - sh);
1609                                 break;
1610                         case 3:         /* rldimi */
1611                                 imm = MASK64(mb, 63 - sh);
1612                                 val = (regs->gpr[ra] & ~imm) |
1613                                         (val & imm);
1614                         }
1615                         op->val = val;
1616                         goto logical_done;
1617                 } else {
1618                         sh = regs->gpr[rb] & 0x3f;
1619                         val = ROTATE(val, sh);
1620                         switch ((word >> 1) & 7) {
1621                         case 0:         /* rldcl */
1622                                 op->val = val & MASK64_L(mb);
1623                                 goto logical_done;
1624                         case 1:         /* rldcr */
1625                                 op->val = val & MASK64_R(mb);
1626                                 goto logical_done;
1627                         }
1628                 }
1629 #endif
1630                 op->type = UNKNOWN;     /* illegal instruction */
1631                 return 0;
1632
1633         case 31:
1634                 /* isel occupies 32 minor opcodes */
1635                 if (((word >> 1) & 0x1f) == 15) {
1636                         mb = (word >> 6) & 0x1f; /* bc field */
1637                         val = (regs->ccr >> (31 - mb)) & 1;
1638                         val2 = (ra) ? regs->gpr[ra] : 0;
1639
1640                         op->val = (val) ? val2 : regs->gpr[rb];
1641                         goto compute_done;
1642                 }
1643
1644                 switch ((word >> 1) & 0x3ff) {
1645                 case 4:         /* tw */
1646                         if (rd == 0x1f ||
1647                             (rd & trap_compare((int)regs->gpr[ra],
1648                                                (int)regs->gpr[rb])))
1649                                 goto trap;
1650                         return 1;
1651 #ifdef __powerpc64__
1652                 case 68:        /* td */
1653                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1654                                 goto trap;
1655                         return 1;
1656 #endif
1657                 case 83:        /* mfmsr */
1658                         if (regs->msr & MSR_PR)
1659                                 goto priv;
1660                         op->type = MFMSR;
1661                         op->reg = rd;
1662                         return 0;
1663                 case 146:       /* mtmsr */
1664                         if (regs->msr & MSR_PR)
1665                                 goto priv;
1666                         op->type = MTMSR;
1667                         op->reg = rd;
1668                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1669                         return 0;
1670 #ifdef CONFIG_PPC64
1671                 case 178:       /* mtmsrd */
1672                         if (regs->msr & MSR_PR)
1673                                 goto priv;
1674                         op->type = MTMSR;
1675                         op->reg = rd;
1676                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1677                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1678                         imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1679                         op->val = imm;
1680                         return 0;
1681 #endif
1682
1683                 case 19:        /* mfcr */
1684                         imm = 0xffffffffUL;
1685                         if ((word >> 20) & 1) {
1686                                 imm = 0xf0000000UL;
1687                                 for (sh = 0; sh < 8; ++sh) {
1688                                         if (word & (0x80000 >> sh))
1689                                                 break;
1690                                         imm >>= 4;
1691                                 }
1692                         }
1693                         op->val = regs->ccr & imm;
1694                         goto compute_done;
1695
1696                 case 144:       /* mtcrf */
1697                         op->type = COMPUTE + SETCC;
1698                         imm = 0xf0000000UL;
1699                         val = regs->gpr[rd];
1700                         op->ccval = regs->ccr;
1701                         for (sh = 0; sh < 8; ++sh) {
1702                                 if (word & (0x80000 >> sh))
1703                                         op->ccval = (op->ccval & ~imm) |
1704                                                 (val & imm);
1705                                 imm >>= 4;
1706                         }
1707                         return 1;
1708
1709                 case 339:       /* mfspr */
1710                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1711                         op->type = MFSPR;
1712                         op->reg = rd;
1713                         op->spr = spr;
1714                         if (spr == SPRN_XER || spr == SPRN_LR ||
1715                             spr == SPRN_CTR)
1716                                 return 1;
1717                         return 0;
1718
1719                 case 467:       /* mtspr */
1720                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1721                         op->type = MTSPR;
1722                         op->val = regs->gpr[rd];
1723                         op->spr = spr;
1724                         if (spr == SPRN_XER || spr == SPRN_LR ||
1725                             spr == SPRN_CTR)
1726                                 return 1;
1727                         return 0;
1728
1729 /*
1730  * Compare instructions
1731  */
1732                 case 0: /* cmp */
1733                         val = regs->gpr[ra];
1734                         val2 = regs->gpr[rb];
1735 #ifdef __powerpc64__
1736                         if ((rd & 1) == 0) {
1737                                 /* word (32-bit) compare */
1738                                 val = (int) val;
1739                                 val2 = (int) val2;
1740                         }
1741 #endif
1742                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1743                         return 1;
1744
1745                 case 32:        /* cmpl */
1746                         val = regs->gpr[ra];
1747                         val2 = regs->gpr[rb];
1748 #ifdef __powerpc64__
1749                         if ((rd & 1) == 0) {
1750                                 /* word (32-bit) compare */
1751                                 val = (unsigned int) val;
1752                                 val2 = (unsigned int) val2;
1753                         }
1754 #endif
1755                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1756                         return 1;
1757
1758                 case 508: /* cmpb */
1759                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1760                         goto logical_done_nocc;
1761
1762 /*
1763  * Arithmetic instructions
1764  */
1765                 case 8: /* subfc */
1766                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1767                                        regs->gpr[rb], 1);
1768                         goto arith_done;
1769 #ifdef __powerpc64__
1770                 case 9: /* mulhdu */
1771                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1772                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1773                         goto arith_done;
1774 #endif
1775                 case 10:        /* addc */
1776                         add_with_carry(regs, op, rd, regs->gpr[ra],
1777                                        regs->gpr[rb], 0);
1778                         goto arith_done;
1779
1780                 case 11:        /* mulhwu */
1781                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1782                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1783                         goto arith_done;
1784
1785                 case 40:        /* subf */
1786                         op->val = regs->gpr[rb] - regs->gpr[ra];
1787                         goto arith_done;
1788 #ifdef __powerpc64__
1789                 case 73:        /* mulhd */
1790                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1791                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1792                         goto arith_done;
1793 #endif
1794                 case 75:        /* mulhw */
1795                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1796                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1797                         goto arith_done;
1798
1799                 case 104:       /* neg */
1800                         op->val = -regs->gpr[ra];
1801                         goto arith_done;
1802
1803                 case 136:       /* subfe */
1804                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1805                                        regs->gpr[rb], regs->xer & XER_CA);
1806                         goto arith_done;
1807
1808                 case 138:       /* adde */
1809                         add_with_carry(regs, op, rd, regs->gpr[ra],
1810                                        regs->gpr[rb], regs->xer & XER_CA);
1811                         goto arith_done;
1812
1813                 case 200:       /* subfze */
1814                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1815                                        regs->xer & XER_CA);
1816                         goto arith_done;
1817
1818                 case 202:       /* addze */
1819                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1820                                        regs->xer & XER_CA);
1821                         goto arith_done;
1822
1823                 case 232:       /* subfme */
1824                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1825                                        regs->xer & XER_CA);
1826                         goto arith_done;
1827 #ifdef __powerpc64__
1828                 case 233:       /* mulld */
1829                         op->val = regs->gpr[ra] * regs->gpr[rb];
1830                         goto arith_done;
1831 #endif
1832                 case 234:       /* addme */
1833                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1834                                        regs->xer & XER_CA);
1835                         goto arith_done;
1836
1837                 case 235:       /* mullw */
1838                         op->val = (long)(int) regs->gpr[ra] *
1839                                 (int) regs->gpr[rb];
1840
1841                         goto arith_done;
1842 #ifdef __powerpc64__
1843                 case 265:       /* modud */
1844                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1845                                 return -1;
1846                         op->val = regs->gpr[ra] % regs->gpr[rb];
1847                         goto compute_done;
1848 #endif
1849                 case 266:       /* add */
1850                         op->val = regs->gpr[ra] + regs->gpr[rb];
1851                         goto arith_done;
1852
1853                 case 267:       /* moduw */
1854                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1855                                 return -1;
1856                         op->val = (unsigned int) regs->gpr[ra] %
1857                                 (unsigned int) regs->gpr[rb];
1858                         goto compute_done;
1859 #ifdef __powerpc64__
1860                 case 457:       /* divdu */
1861                         op->val = regs->gpr[ra] / regs->gpr[rb];
1862                         goto arith_done;
1863 #endif
1864                 case 459:       /* divwu */
1865                         op->val = (unsigned int) regs->gpr[ra] /
1866                                 (unsigned int) regs->gpr[rb];
1867                         goto arith_done;
1868 #ifdef __powerpc64__
1869                 case 489:       /* divd */
1870                         op->val = (long int) regs->gpr[ra] /
1871                                 (long int) regs->gpr[rb];
1872                         goto arith_done;
1873 #endif
1874                 case 491:       /* divw */
1875                         op->val = (int) regs->gpr[ra] /
1876                                 (int) regs->gpr[rb];
1877                         goto arith_done;
1878 #ifdef __powerpc64__
1879                 case 425:       /* divde[.] */
1880                         asm volatile(PPC_DIVDE(%0, %1, %2) :
1881                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1882                                 "r" (regs->gpr[rb]));
1883                         goto arith_done;
1884                 case 393:       /* divdeu[.] */
1885                         asm volatile(PPC_DIVDEU(%0, %1, %2) :
1886                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1887                                 "r" (regs->gpr[rb]));
1888                         goto arith_done;
1889 #endif
1890                 case 755:       /* darn */
1891                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1892                                 return -1;
1893                         switch (ra & 0x3) {
1894                         case 0:
1895                                 /* 32-bit conditioned */
1896                                 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1897                                 goto compute_done;
1898
1899                         case 1:
1900                                 /* 64-bit conditioned */
1901                                 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1902                                 goto compute_done;
1903
1904                         case 2:
1905                                 /* 64-bit raw */
1906                                 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1907                                 goto compute_done;
1908                         }
1909
1910                         return -1;
1911 #ifdef __powerpc64__
1912                 case 777:       /* modsd */
1913                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1914                                 return -1;
1915                         op->val = (long int) regs->gpr[ra] %
1916                                 (long int) regs->gpr[rb];
1917                         goto compute_done;
1918 #endif
1919                 case 779:       /* modsw */
1920                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1921                                 return -1;
1922                         op->val = (int) regs->gpr[ra] %
1923                                 (int) regs->gpr[rb];
1924                         goto compute_done;
1925
1926
1927 /*
1928  * Logical instructions
1929  */
1930                 case 26:        /* cntlzw */
1931                         val = (unsigned int) regs->gpr[rd];
1932                         op->val = ( val ? __builtin_clz(val) : 32 );
1933                         goto logical_done;
1934 #ifdef __powerpc64__
1935                 case 58:        /* cntlzd */
1936                         val = regs->gpr[rd];
1937                         op->val = ( val ? __builtin_clzl(val) : 64 );
1938                         goto logical_done;
1939 #endif
1940                 case 28:        /* and */
1941                         op->val = regs->gpr[rd] & regs->gpr[rb];
1942                         goto logical_done;
1943
1944                 case 60:        /* andc */
1945                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1946                         goto logical_done;
1947
1948                 case 122:       /* popcntb */
1949                         do_popcnt(regs, op, regs->gpr[rd], 8);
1950                         goto logical_done_nocc;
1951
1952                 case 124:       /* nor */
1953                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1954                         goto logical_done;
1955
1956                 case 154:       /* prtyw */
1957                         do_prty(regs, op, regs->gpr[rd], 32);
1958                         goto logical_done_nocc;
1959
1960                 case 186:       /* prtyd */
1961                         do_prty(regs, op, regs->gpr[rd], 64);
1962                         goto logical_done_nocc;
1963 #ifdef CONFIG_PPC64
1964                 case 252:       /* bpermd */
1965                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1966                         goto logical_done_nocc;
1967 #endif
1968                 case 284:       /* xor */
1969                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1970                         goto logical_done;
1971
1972                 case 316:       /* xor */
1973                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1974                         goto logical_done;
1975
1976                 case 378:       /* popcntw */
1977                         do_popcnt(regs, op, regs->gpr[rd], 32);
1978                         goto logical_done_nocc;
1979
1980                 case 412:       /* orc */
1981                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1982                         goto logical_done;
1983
1984                 case 444:       /* or */
1985                         op->val = regs->gpr[rd] | regs->gpr[rb];
1986                         goto logical_done;
1987
1988                 case 476:       /* nand */
1989                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1990                         goto logical_done;
1991 #ifdef CONFIG_PPC64
1992                 case 506:       /* popcntd */
1993                         do_popcnt(regs, op, regs->gpr[rd], 64);
1994                         goto logical_done_nocc;
1995 #endif
1996                 case 538:       /* cnttzw */
1997                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1998                                 return -1;
1999                         val = (unsigned int) regs->gpr[rd];
2000                         op->val = (val ? __builtin_ctz(val) : 32);
2001                         goto logical_done;
2002 #ifdef __powerpc64__
2003                 case 570:       /* cnttzd */
2004                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2005                                 return -1;
2006                         val = regs->gpr[rd];
2007                         op->val = (val ? __builtin_ctzl(val) : 64);
2008                         goto logical_done;
2009 #endif
2010                 case 922:       /* extsh */
2011                         op->val = (signed short) regs->gpr[rd];
2012                         goto logical_done;
2013
2014                 case 954:       /* extsb */
2015                         op->val = (signed char) regs->gpr[rd];
2016                         goto logical_done;
2017 #ifdef __powerpc64__
2018                 case 986:       /* extsw */
2019                         op->val = (signed int) regs->gpr[rd];
2020                         goto logical_done;
2021 #endif
2022
2023 /*
2024  * Shift instructions
2025  */
2026                 case 24:        /* slw */
2027                         sh = regs->gpr[rb] & 0x3f;
2028                         if (sh < 32)
2029                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2030                         else
2031                                 op->val = 0;
2032                         goto logical_done;
2033
2034                 case 536:       /* srw */
2035                         sh = regs->gpr[rb] & 0x3f;
2036                         if (sh < 32)
2037                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2038                         else
2039                                 op->val = 0;
2040                         goto logical_done;
2041
2042                 case 792:       /* sraw */
2043                         op->type = COMPUTE + SETREG + SETXER;
2044                         sh = regs->gpr[rb] & 0x3f;
2045                         ival = (signed int) regs->gpr[rd];
2046                         op->val = ival >> (sh < 32 ? sh : 31);
2047                         op->xerval = regs->xer;
2048                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2049                                 op->xerval |= XER_CA;
2050                         else
2051                                 op->xerval &= ~XER_CA;
2052                         set_ca32(op, op->xerval & XER_CA);
2053                         goto logical_done;
2054
2055                 case 824:       /* srawi */
2056                         op->type = COMPUTE + SETREG + SETXER;
2057                         sh = rb;
2058                         ival = (signed int) regs->gpr[rd];
2059                         op->val = ival >> sh;
2060                         op->xerval = regs->xer;
2061                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2062                                 op->xerval |= XER_CA;
2063                         else
2064                                 op->xerval &= ~XER_CA;
2065                         set_ca32(op, op->xerval & XER_CA);
2066                         goto logical_done;
2067
2068 #ifdef __powerpc64__
2069                 case 27:        /* sld */
2070                         sh = regs->gpr[rb] & 0x7f;
2071                         if (sh < 64)
2072                                 op->val = regs->gpr[rd] << sh;
2073                         else
2074                                 op->val = 0;
2075                         goto logical_done;
2076
2077                 case 539:       /* srd */
2078                         sh = regs->gpr[rb] & 0x7f;
2079                         if (sh < 64)
2080                                 op->val = regs->gpr[rd] >> sh;
2081                         else
2082                                 op->val = 0;
2083                         goto logical_done;
2084
2085                 case 794:       /* srad */
2086                         op->type = COMPUTE + SETREG + SETXER;
2087                         sh = regs->gpr[rb] & 0x7f;
2088                         ival = (signed long int) regs->gpr[rd];
2089                         op->val = ival >> (sh < 64 ? sh : 63);
2090                         op->xerval = regs->xer;
2091                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2092                                 op->xerval |= XER_CA;
2093                         else
2094                                 op->xerval &= ~XER_CA;
2095                         set_ca32(op, op->xerval & XER_CA);
2096                         goto logical_done;
2097
2098                 case 826:       /* sradi with sh_5 = 0 */
2099                 case 827:       /* sradi with sh_5 = 1 */
2100                         op->type = COMPUTE + SETREG + SETXER;
2101                         sh = rb | ((word & 2) << 4);
2102                         ival = (signed long int) regs->gpr[rd];
2103                         op->val = ival >> sh;
2104                         op->xerval = regs->xer;
2105                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2106                                 op->xerval |= XER_CA;
2107                         else
2108                                 op->xerval &= ~XER_CA;
2109                         set_ca32(op, op->xerval & XER_CA);
2110                         goto logical_done;
2111
2112                 case 890:       /* extswsli with sh_5 = 0 */
2113                 case 891:       /* extswsli with sh_5 = 1 */
2114                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2115                                 return -1;
2116                         op->type = COMPUTE + SETREG;
2117                         sh = rb | ((word & 2) << 4);
2118                         val = (signed int) regs->gpr[rd];
2119                         if (sh)
2120                                 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2121                         else
2122                                 op->val = val;
2123                         goto logical_done;
2124
2125 #endif /* __powerpc64__ */
2126
2127 /*
2128  * Cache instructions
2129  */
2130                 case 54:        /* dcbst */
2131                         op->type = MKOP(CACHEOP, DCBST, 0);
2132                         op->ea = xform_ea(word, regs);
2133                         return 0;
2134
2135                 case 86:        /* dcbf */
2136                         op->type = MKOP(CACHEOP, DCBF, 0);
2137                         op->ea = xform_ea(word, regs);
2138                         return 0;
2139
2140                 case 246:       /* dcbtst */
2141                         op->type = MKOP(CACHEOP, DCBTST, 0);
2142                         op->ea = xform_ea(word, regs);
2143                         op->reg = rd;
2144                         return 0;
2145
2146                 case 278:       /* dcbt */
2147                         op->type = MKOP(CACHEOP, DCBTST, 0);
2148                         op->ea = xform_ea(word, regs);
2149                         op->reg = rd;
2150                         return 0;
2151
2152                 case 982:       /* icbi */
2153                         op->type = MKOP(CACHEOP, ICBI, 0);
2154                         op->ea = xform_ea(word, regs);
2155                         return 0;
2156
2157                 case 1014:      /* dcbz */
2158                         op->type = MKOP(CACHEOP, DCBZ, 0);
2159                         op->ea = xform_ea(word, regs);
2160                         return 0;
2161                 }
2162                 break;
2163         }
2164
2165 /*
2166  * Loads and stores.
2167  */
2168         op->type = UNKNOWN;
2169         op->update_reg = ra;
2170         op->reg = rd;
2171         op->val = regs->gpr[rd];
2172         u = (word >> 20) & UPDATE;
2173         op->vsx_flags = 0;
2174
2175         switch (opcode) {
2176         case 31:
2177                 u = word & UPDATE;
2178                 op->ea = xform_ea(word, regs);
2179                 switch ((word >> 1) & 0x3ff) {
2180                 case 20:        /* lwarx */
2181                         op->type = MKOP(LARX, 0, 4);
2182                         break;
2183
2184                 case 150:       /* stwcx. */
2185                         op->type = MKOP(STCX, 0, 4);
2186                         break;
2187
2188 #ifdef __powerpc64__
2189                 case 84:        /* ldarx */
2190                         op->type = MKOP(LARX, 0, 8);
2191                         break;
2192
2193                 case 214:       /* stdcx. */
2194                         op->type = MKOP(STCX, 0, 8);
2195                         break;
2196
2197                 case 52:        /* lbarx */
2198                         op->type = MKOP(LARX, 0, 1);
2199                         break;
2200
2201                 case 694:       /* stbcx. */
2202                         op->type = MKOP(STCX, 0, 1);
2203                         break;
2204
2205                 case 116:       /* lharx */
2206                         op->type = MKOP(LARX, 0, 2);
2207                         break;
2208
2209                 case 726:       /* sthcx. */
2210                         op->type = MKOP(STCX, 0, 2);
2211                         break;
2212
2213                 case 276:       /* lqarx */
2214                         if (!((rd & 1) || rd == ra || rd == rb))
2215                                 op->type = MKOP(LARX, 0, 16);
2216                         break;
2217
2218                 case 182:       /* stqcx. */
2219                         if (!(rd & 1))
2220                                 op->type = MKOP(STCX, 0, 16);
2221                         break;
2222 #endif
2223
2224                 case 23:        /* lwzx */
2225                 case 55:        /* lwzux */
2226                         op->type = MKOP(LOAD, u, 4);
2227                         break;
2228
2229                 case 87:        /* lbzx */
2230                 case 119:       /* lbzux */
2231                         op->type = MKOP(LOAD, u, 1);
2232                         break;
2233
2234 #ifdef CONFIG_ALTIVEC
2235                 /*
2236                  * Note: for the load/store vector element instructions,
2237                  * bits of the EA say which field of the VMX register to use.
2238                  */
2239                 case 7:         /* lvebx */
2240                         op->type = MKOP(LOAD_VMX, 0, 1);
2241                         op->element_size = 1;
2242                         break;
2243
2244                 case 39:        /* lvehx */
2245                         op->type = MKOP(LOAD_VMX, 0, 2);
2246                         op->element_size = 2;
2247                         break;
2248
2249                 case 71:        /* lvewx */
2250                         op->type = MKOP(LOAD_VMX, 0, 4);
2251                         op->element_size = 4;
2252                         break;
2253
2254                 case 103:       /* lvx */
2255                 case 359:       /* lvxl */
2256                         op->type = MKOP(LOAD_VMX, 0, 16);
2257                         op->element_size = 16;
2258                         break;
2259
2260                 case 135:       /* stvebx */
2261                         op->type = MKOP(STORE_VMX, 0, 1);
2262                         op->element_size = 1;
2263                         break;
2264
2265                 case 167:       /* stvehx */
2266                         op->type = MKOP(STORE_VMX, 0, 2);
2267                         op->element_size = 2;
2268                         break;
2269
2270                 case 199:       /* stvewx */
2271                         op->type = MKOP(STORE_VMX, 0, 4);
2272                         op->element_size = 4;
2273                         break;
2274
2275                 case 231:       /* stvx */
2276                 case 487:       /* stvxl */
2277                         op->type = MKOP(STORE_VMX, 0, 16);
2278                         break;
2279 #endif /* CONFIG_ALTIVEC */
2280
2281 #ifdef __powerpc64__
2282                 case 21:        /* ldx */
2283                 case 53:        /* ldux */
2284                         op->type = MKOP(LOAD, u, 8);
2285                         break;
2286
2287                 case 149:       /* stdx */
2288                 case 181:       /* stdux */
2289                         op->type = MKOP(STORE, u, 8);
2290                         break;
2291 #endif
2292
2293                 case 151:       /* stwx */
2294                 case 183:       /* stwux */
2295                         op->type = MKOP(STORE, u, 4);
2296                         break;
2297
2298                 case 215:       /* stbx */
2299                 case 247:       /* stbux */
2300                         op->type = MKOP(STORE, u, 1);
2301                         break;
2302
2303                 case 279:       /* lhzx */
2304                 case 311:       /* lhzux */
2305                         op->type = MKOP(LOAD, u, 2);
2306                         break;
2307
2308 #ifdef __powerpc64__
2309                 case 341:       /* lwax */
2310                 case 373:       /* lwaux */
2311                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2312                         break;
2313 #endif
2314
2315                 case 343:       /* lhax */
2316                 case 375:       /* lhaux */
2317                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2318                         break;
2319
2320                 case 407:       /* sthx */
2321                 case 439:       /* sthux */
2322                         op->type = MKOP(STORE, u, 2);
2323                         break;
2324
2325 #ifdef __powerpc64__
2326                 case 532:       /* ldbrx */
2327                         op->type = MKOP(LOAD, BYTEREV, 8);
2328                         break;
2329
2330 #endif
2331                 case 533:       /* lswx */
2332                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2333                         break;
2334
2335                 case 534:       /* lwbrx */
2336                         op->type = MKOP(LOAD, BYTEREV, 4);
2337                         break;
2338
2339                 case 597:       /* lswi */
2340                         if (rb == 0)
2341                                 rb = 32;        /* # bytes to load */
2342                         op->type = MKOP(LOAD_MULTI, 0, rb);
2343                         op->ea = ra ? regs->gpr[ra] : 0;
2344                         break;
2345
2346 #ifdef CONFIG_PPC_FPU
2347                 case 535:       /* lfsx */
2348                 case 567:       /* lfsux */
2349                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2350                         break;
2351
2352                 case 599:       /* lfdx */
2353                 case 631:       /* lfdux */
2354                         op->type = MKOP(LOAD_FP, u, 8);
2355                         break;
2356
2357                 case 663:       /* stfsx */
2358                 case 695:       /* stfsux */
2359                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2360                         break;
2361
2362                 case 727:       /* stfdx */
2363                 case 759:       /* stfdux */
2364                         op->type = MKOP(STORE_FP, u, 8);
2365                         break;
2366
2367 #ifdef __powerpc64__
2368                 case 791:       /* lfdpx */
2369                         op->type = MKOP(LOAD_FP, 0, 16);
2370                         break;
2371
2372                 case 855:       /* lfiwax */
2373                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2374                         break;
2375
2376                 case 887:       /* lfiwzx */
2377                         op->type = MKOP(LOAD_FP, 0, 4);
2378                         break;
2379
2380                 case 919:       /* stfdpx */
2381                         op->type = MKOP(STORE_FP, 0, 16);
2382                         break;
2383
2384                 case 983:       /* stfiwx */
2385                         op->type = MKOP(STORE_FP, 0, 4);
2386                         break;
2387 #endif /* __powerpc64 */
2388 #endif /* CONFIG_PPC_FPU */
2389
2390 #ifdef __powerpc64__
2391                 case 660:       /* stdbrx */
2392                         op->type = MKOP(STORE, BYTEREV, 8);
2393                         op->val = byterev_8(regs->gpr[rd]);
2394                         break;
2395
2396 #endif
2397                 case 661:       /* stswx */
2398                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2399                         break;
2400
2401                 case 662:       /* stwbrx */
2402                         op->type = MKOP(STORE, BYTEREV, 4);
2403                         op->val = byterev_4(regs->gpr[rd]);
2404                         break;
2405
2406                 case 725:       /* stswi */
2407                         if (rb == 0)
2408                                 rb = 32;        /* # bytes to store */
2409                         op->type = MKOP(STORE_MULTI, 0, rb);
2410                         op->ea = ra ? regs->gpr[ra] : 0;
2411                         break;
2412
2413                 case 790:       /* lhbrx */
2414                         op->type = MKOP(LOAD, BYTEREV, 2);
2415                         break;
2416
2417                 case 918:       /* sthbrx */
2418                         op->type = MKOP(STORE, BYTEREV, 2);
2419                         op->val = byterev_2(regs->gpr[rd]);
2420                         break;
2421
2422 #ifdef CONFIG_VSX
2423                 case 12:        /* lxsiwzx */
2424                         op->reg = rd | ((word & 1) << 5);
2425                         op->type = MKOP(LOAD_VSX, 0, 4);
2426                         op->element_size = 8;
2427                         break;
2428
2429                 case 76:        /* lxsiwax */
2430                         op->reg = rd | ((word & 1) << 5);
2431                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2432                         op->element_size = 8;
2433                         break;
2434
2435                 case 140:       /* stxsiwx */
2436                         op->reg = rd | ((word & 1) << 5);
2437                         op->type = MKOP(STORE_VSX, 0, 4);
2438                         op->element_size = 8;
2439                         break;
2440
2441                 case 268:       /* lxvx */
2442                         op->reg = rd | ((word & 1) << 5);
2443                         op->type = MKOP(LOAD_VSX, 0, 16);
2444                         op->element_size = 16;
2445                         op->vsx_flags = VSX_CHECK_VEC;
2446                         break;
2447
2448                 case 269:       /* lxvl */
2449                 case 301: {     /* lxvll */
2450                         int nb;
2451                         op->reg = rd | ((word & 1) << 5);
2452                         op->ea = ra ? regs->gpr[ra] : 0;
2453                         nb = regs->gpr[rb] & 0xff;
2454                         if (nb > 16)
2455                                 nb = 16;
2456                         op->type = MKOP(LOAD_VSX, 0, nb);
2457                         op->element_size = 16;
2458                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2459                                 VSX_CHECK_VEC;
2460                         break;
2461                 }
2462                 case 332:       /* lxvdsx */
2463                         op->reg = rd | ((word & 1) << 5);
2464                         op->type = MKOP(LOAD_VSX, 0, 8);
2465                         op->element_size = 8;
2466                         op->vsx_flags = VSX_SPLAT;
2467                         break;
2468
2469                 case 333:       /* lxvpx */
2470                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2471                                 return -1;
2472                         op->reg = VSX_REGISTER_XTP(rd);
2473                         op->type = MKOP(LOAD_VSX, 0, 32);
2474                         op->element_size = 32;
2475                         break;
2476
2477                 case 364:       /* lxvwsx */
2478                         op->reg = rd | ((word & 1) << 5);
2479                         op->type = MKOP(LOAD_VSX, 0, 4);
2480                         op->element_size = 4;
2481                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2482                         break;
2483
2484                 case 396:       /* stxvx */
2485                         op->reg = rd | ((word & 1) << 5);
2486                         op->type = MKOP(STORE_VSX, 0, 16);
2487                         op->element_size = 16;
2488                         op->vsx_flags = VSX_CHECK_VEC;
2489                         break;
2490
2491                 case 397:       /* stxvl */
2492                 case 429: {     /* stxvll */
2493                         int nb;
2494                         op->reg = rd | ((word & 1) << 5);
2495                         op->ea = ra ? regs->gpr[ra] : 0;
2496                         nb = regs->gpr[rb] & 0xff;
2497                         if (nb > 16)
2498                                 nb = 16;
2499                         op->type = MKOP(STORE_VSX, 0, nb);
2500                         op->element_size = 16;
2501                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2502                                 VSX_CHECK_VEC;
2503                         break;
2504                 }
2505                 case 461:       /* stxvpx */
2506                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2507                                 return -1;
2508                         op->reg = VSX_REGISTER_XTP(rd);
2509                         op->type = MKOP(STORE_VSX, 0, 32);
2510                         op->element_size = 32;
2511                         break;
2512                 case 524:       /* lxsspx */
2513                         op->reg = rd | ((word & 1) << 5);
2514                         op->type = MKOP(LOAD_VSX, 0, 4);
2515                         op->element_size = 8;
2516                         op->vsx_flags = VSX_FPCONV;
2517                         break;
2518
2519                 case 588:       /* lxsdx */
2520                         op->reg = rd | ((word & 1) << 5);
2521                         op->type = MKOP(LOAD_VSX, 0, 8);
2522                         op->element_size = 8;
2523                         break;
2524
2525                 case 652:       /* stxsspx */
2526                         op->reg = rd | ((word & 1) << 5);
2527                         op->type = MKOP(STORE_VSX, 0, 4);
2528                         op->element_size = 8;
2529                         op->vsx_flags = VSX_FPCONV;
2530                         break;
2531
2532                 case 716:       /* stxsdx */
2533                         op->reg = rd | ((word & 1) << 5);
2534                         op->type = MKOP(STORE_VSX, 0, 8);
2535                         op->element_size = 8;
2536                         break;
2537
2538                 case 780:       /* lxvw4x */
2539                         op->reg = rd | ((word & 1) << 5);
2540                         op->type = MKOP(LOAD_VSX, 0, 16);
2541                         op->element_size = 4;
2542                         break;
2543
2544                 case 781:       /* lxsibzx */
2545                         op->reg = rd | ((word & 1) << 5);
2546                         op->type = MKOP(LOAD_VSX, 0, 1);
2547                         op->element_size = 8;
2548                         op->vsx_flags = VSX_CHECK_VEC;
2549                         break;
2550
2551                 case 812:       /* lxvh8x */
2552                         op->reg = rd | ((word & 1) << 5);
2553                         op->type = MKOP(LOAD_VSX, 0, 16);
2554                         op->element_size = 2;
2555                         op->vsx_flags = VSX_CHECK_VEC;
2556                         break;
2557
2558                 case 813:       /* lxsihzx */
2559                         op->reg = rd | ((word & 1) << 5);
2560                         op->type = MKOP(LOAD_VSX, 0, 2);
2561                         op->element_size = 8;
2562                         op->vsx_flags = VSX_CHECK_VEC;
2563                         break;
2564
2565                 case 844:       /* lxvd2x */
2566                         op->reg = rd | ((word & 1) << 5);
2567                         op->type = MKOP(LOAD_VSX, 0, 16);
2568                         op->element_size = 8;
2569                         break;
2570
2571                 case 876:       /* lxvb16x */
2572                         op->reg = rd | ((word & 1) << 5);
2573                         op->type = MKOP(LOAD_VSX, 0, 16);
2574                         op->element_size = 1;
2575                         op->vsx_flags = VSX_CHECK_VEC;
2576                         break;
2577
2578                 case 908:       /* stxvw4x */
2579                         op->reg = rd | ((word & 1) << 5);
2580                         op->type = MKOP(STORE_VSX, 0, 16);
2581                         op->element_size = 4;
2582                         break;
2583
2584                 case 909:       /* stxsibx */
2585                         op->reg = rd | ((word & 1) << 5);
2586                         op->type = MKOP(STORE_VSX, 0, 1);
2587                         op->element_size = 8;
2588                         op->vsx_flags = VSX_CHECK_VEC;
2589                         break;
2590
2591                 case 940:       /* stxvh8x */
2592                         op->reg = rd | ((word & 1) << 5);
2593                         op->type = MKOP(STORE_VSX, 0, 16);
2594                         op->element_size = 2;
2595                         op->vsx_flags = VSX_CHECK_VEC;
2596                         break;
2597
2598                 case 941:       /* stxsihx */
2599                         op->reg = rd | ((word & 1) << 5);
2600                         op->type = MKOP(STORE_VSX, 0, 2);
2601                         op->element_size = 8;
2602                         op->vsx_flags = VSX_CHECK_VEC;
2603                         break;
2604
2605                 case 972:       /* stxvd2x */
2606                         op->reg = rd | ((word & 1) << 5);
2607                         op->type = MKOP(STORE_VSX, 0, 16);
2608                         op->element_size = 8;
2609                         break;
2610
2611                 case 1004:      /* stxvb16x */
2612                         op->reg = rd | ((word & 1) << 5);
2613                         op->type = MKOP(STORE_VSX, 0, 16);
2614                         op->element_size = 1;
2615                         op->vsx_flags = VSX_CHECK_VEC;
2616                         break;
2617
2618 #endif /* CONFIG_VSX */
2619                 }
2620                 break;
2621
2622         case 32:        /* lwz */
2623         case 33:        /* lwzu */
2624                 op->type = MKOP(LOAD, u, 4);
2625                 op->ea = dform_ea(word, regs);
2626                 break;
2627
2628         case 34:        /* lbz */
2629         case 35:        /* lbzu */
2630                 op->type = MKOP(LOAD, u, 1);
2631                 op->ea = dform_ea(word, regs);
2632                 break;
2633
2634         case 36:        /* stw */
2635         case 37:        /* stwu */
2636                 op->type = MKOP(STORE, u, 4);
2637                 op->ea = dform_ea(word, regs);
2638                 break;
2639
2640         case 38:        /* stb */
2641         case 39:        /* stbu */
2642                 op->type = MKOP(STORE, u, 1);
2643                 op->ea = dform_ea(word, regs);
2644                 break;
2645
2646         case 40:        /* lhz */
2647         case 41:        /* lhzu */
2648                 op->type = MKOP(LOAD, u, 2);
2649                 op->ea = dform_ea(word, regs);
2650                 break;
2651
2652         case 42:        /* lha */
2653         case 43:        /* lhau */
2654                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2655                 op->ea = dform_ea(word, regs);
2656                 break;
2657
2658         case 44:        /* sth */
2659         case 45:        /* sthu */
2660                 op->type = MKOP(STORE, u, 2);
2661                 op->ea = dform_ea(word, regs);
2662                 break;
2663
2664         case 46:        /* lmw */
2665                 if (ra >= rd)
2666                         break;          /* invalid form, ra in range to load */
2667                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2668                 op->ea = dform_ea(word, regs);
2669                 break;
2670
2671         case 47:        /* stmw */
2672                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2673                 op->ea = dform_ea(word, regs);
2674                 break;
2675
2676 #ifdef CONFIG_PPC_FPU
2677         case 48:        /* lfs */
2678         case 49:        /* lfsu */
2679                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2680                 op->ea = dform_ea(word, regs);
2681                 break;
2682
2683         case 50:        /* lfd */
2684         case 51:        /* lfdu */
2685                 op->type = MKOP(LOAD_FP, u, 8);
2686                 op->ea = dform_ea(word, regs);
2687                 break;
2688
2689         case 52:        /* stfs */
2690         case 53:        /* stfsu */
2691                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2692                 op->ea = dform_ea(word, regs);
2693                 break;
2694
2695         case 54:        /* stfd */
2696         case 55:        /* stfdu */
2697                 op->type = MKOP(STORE_FP, u, 8);
2698                 op->ea = dform_ea(word, regs);
2699                 break;
2700 #endif
2701
2702 #ifdef __powerpc64__
2703         case 56:        /* lq */
2704                 if (!((rd & 1) || (rd == ra)))
2705                         op->type = MKOP(LOAD, 0, 16);
2706                 op->ea = dqform_ea(word, regs);
2707                 break;
2708 #endif
2709
2710 #ifdef CONFIG_VSX
2711         case 57:        /* lfdp, lxsd, lxssp */
2712                 op->ea = dsform_ea(word, regs);
2713                 switch (word & 3) {
2714                 case 0:         /* lfdp */
2715                         if (rd & 1)
2716                                 break;          /* reg must be even */
2717                         op->type = MKOP(LOAD_FP, 0, 16);
2718                         break;
2719                 case 2:         /* lxsd */
2720                         op->reg = rd + 32;
2721                         op->type = MKOP(LOAD_VSX, 0, 8);
2722                         op->element_size = 8;
2723                         op->vsx_flags = VSX_CHECK_VEC;
2724                         break;
2725                 case 3:         /* lxssp */
2726                         op->reg = rd + 32;
2727                         op->type = MKOP(LOAD_VSX, 0, 4);
2728                         op->element_size = 8;
2729                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2730                         break;
2731                 }
2732                 break;
2733 #endif /* CONFIG_VSX */
2734
2735 #ifdef __powerpc64__
2736         case 58:        /* ld[u], lwa */
2737                 op->ea = dsform_ea(word, regs);
2738                 switch (word & 3) {
2739                 case 0:         /* ld */
2740                         op->type = MKOP(LOAD, 0, 8);
2741                         break;
2742                 case 1:         /* ldu */
2743                         op->type = MKOP(LOAD, UPDATE, 8);
2744                         break;
2745                 case 2:         /* lwa */
2746                         op->type = MKOP(LOAD, SIGNEXT, 4);
2747                         break;
2748                 }
2749                 break;
2750 #endif
2751
2752 #ifdef CONFIG_VSX
2753         case 6:
2754                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2755                         return -1;
2756                 op->ea = dqform_ea(word, regs);
2757                 op->reg = VSX_REGISTER_XTP(rd);
2758                 op->element_size = 32;
2759                 switch (word & 0xf) {
2760                 case 0:         /* lxvp */
2761                         op->type = MKOP(LOAD_VSX, 0, 32);
2762                         break;
2763                 case 1:         /* stxvp */
2764                         op->type = MKOP(STORE_VSX, 0, 32);
2765                         break;
2766                 }
2767                 break;
2768
2769         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2770                 switch (word & 7) {
2771                 case 0:         /* stfdp with LSB of DS field = 0 */
2772                 case 4:         /* stfdp with LSB of DS field = 1 */
2773                         op->ea = dsform_ea(word, regs);
2774                         op->type = MKOP(STORE_FP, 0, 16);
2775                         break;
2776
2777                 case 1:         /* lxv */
2778                         op->ea = dqform_ea(word, regs);
2779                         if (word & 8)
2780                                 op->reg = rd + 32;
2781                         op->type = MKOP(LOAD_VSX, 0, 16);
2782                         op->element_size = 16;
2783                         op->vsx_flags = VSX_CHECK_VEC;
2784                         break;
2785
2786                 case 2:         /* stxsd with LSB of DS field = 0 */
2787                 case 6:         /* stxsd with LSB of DS field = 1 */
2788                         op->ea = dsform_ea(word, regs);
2789                         op->reg = rd + 32;
2790                         op->type = MKOP(STORE_VSX, 0, 8);
2791                         op->element_size = 8;
2792                         op->vsx_flags = VSX_CHECK_VEC;
2793                         break;
2794
2795                 case 3:         /* stxssp with LSB of DS field = 0 */
2796                 case 7:         /* stxssp with LSB of DS field = 1 */
2797                         op->ea = dsform_ea(word, regs);
2798                         op->reg = rd + 32;
2799                         op->type = MKOP(STORE_VSX, 0, 4);
2800                         op->element_size = 8;
2801                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2802                         break;
2803
2804                 case 5:         /* stxv */
2805                         op->ea = dqform_ea(word, regs);
2806                         if (word & 8)
2807                                 op->reg = rd + 32;
2808                         op->type = MKOP(STORE_VSX, 0, 16);
2809                         op->element_size = 16;
2810                         op->vsx_flags = VSX_CHECK_VEC;
2811                         break;
2812                 }
2813                 break;
2814 #endif /* CONFIG_VSX */
2815
2816 #ifdef __powerpc64__
2817         case 62:        /* std[u] */
2818                 op->ea = dsform_ea(word, regs);
2819                 switch (word & 3) {
2820                 case 0:         /* std */
2821                         op->type = MKOP(STORE, 0, 8);
2822                         break;
2823                 case 1:         /* stdu */
2824                         op->type = MKOP(STORE, UPDATE, 8);
2825                         break;
2826                 case 2:         /* stq */
2827                         if (!(rd & 1))
2828                                 op->type = MKOP(STORE, 0, 16);
2829                         break;
2830                 }
2831                 break;
2832         case 1: /* Prefixed instructions */
2833                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2834                         return -1;
2835
2836                 prefix_r = GET_PREFIX_R(word);
2837                 ra = GET_PREFIX_RA(suffix);
2838                 op->update_reg = ra;
2839                 rd = (suffix >> 21) & 0x1f;
2840                 op->reg = rd;
2841                 op->val = regs->gpr[rd];
2842
2843                 suffixopcode = get_op(suffix);
2844                 prefixtype = (word >> 24) & 0x3;
2845                 switch (prefixtype) {
2846                 case 0: /* Type 00  Eight-Byte Load/Store */
2847                         if (prefix_r && ra)
2848                                 break;
2849                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2850                         switch (suffixopcode) {
2851                         case 41:        /* plwa */
2852                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2853                                 break;
2854 #ifdef CONFIG_VSX
2855                         case 42:        /* plxsd */
2856                                 op->reg = rd + 32;
2857                                 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2858                                 op->element_size = 8;
2859                                 op->vsx_flags = VSX_CHECK_VEC;
2860                                 break;
2861                         case 43:        /* plxssp */
2862                                 op->reg = rd + 32;
2863                                 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2864                                 op->element_size = 8;
2865                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2866                                 break;
2867                         case 46:        /* pstxsd */
2868                                 op->reg = rd + 32;
2869                                 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2870                                 op->element_size = 8;
2871                                 op->vsx_flags = VSX_CHECK_VEC;
2872                                 break;
2873                         case 47:        /* pstxssp */
2874                                 op->reg = rd + 32;
2875                                 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2876                                 op->element_size = 8;
2877                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2878                                 break;
2879                         case 51:        /* plxv1 */
2880                                 op->reg += 32;
2881                                 fallthrough;
2882                         case 50:        /* plxv0 */
2883                                 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2884                                 op->element_size = 16;
2885                                 op->vsx_flags = VSX_CHECK_VEC;
2886                                 break;
2887                         case 55:        /* pstxv1 */
2888                                 op->reg = rd + 32;
2889                                 fallthrough;
2890                         case 54:        /* pstxv0 */
2891                                 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2892                                 op->element_size = 16;
2893                                 op->vsx_flags = VSX_CHECK_VEC;
2894                                 break;
2895 #endif /* CONFIG_VSX */
2896                         case 56:        /* plq */
2897                                 op->type = MKOP(LOAD, PREFIXED, 16);
2898                                 break;
2899                         case 57:        /* pld */
2900                                 op->type = MKOP(LOAD, PREFIXED, 8);
2901                                 break;
2902 #ifdef CONFIG_VSX
2903                         case 58:        /* plxvp */
2904                                 op->reg = VSX_REGISTER_XTP(rd);
2905                                 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
2906                                 op->element_size = 32;
2907                                 break;
2908 #endif /* CONFIG_VSX */
2909                         case 60:        /* pstq */
2910                                 op->type = MKOP(STORE, PREFIXED, 16);
2911                                 break;
2912                         case 61:        /* pstd */
2913                                 op->type = MKOP(STORE, PREFIXED, 8);
2914                                 break;
2915 #ifdef CONFIG_VSX
2916                         case 62:        /* pstxvp */
2917                                 op->reg = VSX_REGISTER_XTP(rd);
2918                                 op->type = MKOP(STORE_VSX, PREFIXED, 32);
2919                                 op->element_size = 32;
2920                                 break;
2921 #endif /* CONFIG_VSX */
2922                         }
2923                         break;
2924                 case 1: /* Type 01 Eight-Byte Register-to-Register */
2925                         break;
2926                 case 2: /* Type 10 Modified Load/Store */
2927                         if (prefix_r && ra)
2928                                 break;
2929                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2930                         switch (suffixopcode) {
2931                         case 32:        /* plwz */
2932                                 op->type = MKOP(LOAD, PREFIXED, 4);
2933                                 break;
2934                         case 34:        /* plbz */
2935                                 op->type = MKOP(LOAD, PREFIXED, 1);
2936                                 break;
2937                         case 36:        /* pstw */
2938                                 op->type = MKOP(STORE, PREFIXED, 4);
2939                                 break;
2940                         case 38:        /* pstb */
2941                                 op->type = MKOP(STORE, PREFIXED, 1);
2942                                 break;
2943                         case 40:        /* plhz */
2944                                 op->type = MKOP(LOAD, PREFIXED, 2);
2945                                 break;
2946                         case 42:        /* plha */
2947                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2948                                 break;
2949                         case 44:        /* psth */
2950                                 op->type = MKOP(STORE, PREFIXED, 2);
2951                                 break;
2952                         case 48:        /* plfs */
2953                                 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2954                                 break;
2955                         case 50:        /* plfd */
2956                                 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2957                                 break;
2958                         case 52:        /* pstfs */
2959                                 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2960                                 break;
2961                         case 54:        /* pstfd */
2962                                 op->type = MKOP(STORE_FP, PREFIXED, 8);
2963                                 break;
2964                         }
2965                         break;
2966                 case 3: /* Type 11 Modified Register-to-Register */
2967                         break;
2968                 }
2969 #endif /* __powerpc64__ */
2970
2971         }
2972
2973 #ifdef CONFIG_VSX
2974         if ((GETTYPE(op->type) == LOAD_VSX ||
2975              GETTYPE(op->type) == STORE_VSX) &&
2976             !cpu_has_feature(CPU_FTR_VSX)) {
2977                 return -1;
2978         }
2979 #endif /* CONFIG_VSX */
2980
2981         return 0;
2982
2983  logical_done:
2984         if (word & 1)
2985                 set_cr0(regs, op);
2986  logical_done_nocc:
2987         op->reg = ra;
2988         op->type |= SETREG;
2989         return 1;
2990
2991  arith_done:
2992         if (word & 1)
2993                 set_cr0(regs, op);
2994  compute_done:
2995         op->reg = rd;
2996         op->type |= SETREG;
2997         return 1;
2998
2999  priv:
3000         op->type = INTERRUPT | 0x700;
3001         op->val = SRR1_PROGPRIV;
3002         return 0;
3003
3004  trap:
3005         op->type = INTERRUPT | 0x700;
3006         op->val = SRR1_PROGTRAP;
3007         return 0;
3008 }
3009 EXPORT_SYMBOL_GPL(analyse_instr);
3010 NOKPROBE_SYMBOL(analyse_instr);
3011
3012 /*
3013  * For PPC32 we always use stwu with r1 to change the stack pointer.
3014  * So this emulated store may corrupt the exception frame, now we
3015  * have to provide the exception frame trampoline, which is pushed
3016  * below the kprobed function stack. So we only update gpr[1] but
3017  * don't emulate the real store operation. We will do real store
3018  * operation safely in exception return code by checking this flag.
3019  */
3020 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3021 {
3022 #ifdef CONFIG_PPC32
3023         /*
3024          * Check if we will touch kernel stack overflow
3025          */
3026         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
3027                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
3028                 return -EINVAL;
3029         }
3030 #endif /* CONFIG_PPC32 */
3031         /*
3032          * Check if we already set since that means we'll
3033          * lose the previous value.
3034          */
3035         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3036         set_thread_flag(TIF_EMULATE_STACK_STORE);
3037         return 0;
3038 }
3039
3040 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3041 {
3042         switch (size) {
3043         case 2:
3044                 *valp = (signed short) *valp;
3045                 break;
3046         case 4:
3047                 *valp = (signed int) *valp;
3048                 break;
3049         }
3050 }
3051
3052 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3053 {
3054         switch (size) {
3055         case 2:
3056                 *valp = byterev_2(*valp);
3057                 break;
3058         case 4:
3059                 *valp = byterev_4(*valp);
3060                 break;
3061 #ifdef __powerpc64__
3062         case 8:
3063                 *valp = byterev_8(*valp);
3064                 break;
3065 #endif
3066         }
3067 }
3068
3069 /*
3070  * Emulate an instruction that can be executed just by updating
3071  * fields in *regs.
3072  */
3073 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3074 {
3075         unsigned long next_pc;
3076
3077         next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3078         switch (GETTYPE(op->type)) {
3079         case COMPUTE:
3080                 if (op->type & SETREG)
3081                         regs->gpr[op->reg] = op->val;
3082                 if (op->type & SETCC)
3083                         regs->ccr = op->ccval;
3084                 if (op->type & SETXER)
3085                         regs->xer = op->xerval;
3086                 break;
3087
3088         case BRANCH:
3089                 if (op->type & SETLK)
3090                         regs->link = next_pc;
3091                 if (op->type & BRTAKEN)
3092                         next_pc = op->val;
3093                 if (op->type & DECCTR)
3094                         --regs->ctr;
3095                 break;
3096
3097         case BARRIER:
3098                 switch (op->type & BARRIER_MASK) {
3099                 case BARRIER_SYNC:
3100                         mb();
3101                         break;
3102                 case BARRIER_ISYNC:
3103                         isync();
3104                         break;
3105                 case BARRIER_EIEIO:
3106                         eieio();
3107                         break;
3108                 case BARRIER_LWSYNC:
3109                         asm volatile("lwsync" : : : "memory");
3110                         break;
3111                 case BARRIER_PTESYNC:
3112                         asm volatile("ptesync" : : : "memory");
3113                         break;
3114                 }
3115                 break;
3116
3117         case MFSPR:
3118                 switch (op->spr) {
3119                 case SPRN_XER:
3120                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3121                         break;
3122                 case SPRN_LR:
3123                         regs->gpr[op->reg] = regs->link;
3124                         break;
3125                 case SPRN_CTR:
3126                         regs->gpr[op->reg] = regs->ctr;
3127                         break;
3128                 default:
3129                         WARN_ON_ONCE(1);
3130                 }
3131                 break;
3132
3133         case MTSPR:
3134                 switch (op->spr) {
3135                 case SPRN_XER:
3136                         regs->xer = op->val & 0xffffffffUL;
3137                         break;
3138                 case SPRN_LR:
3139                         regs->link = op->val;
3140                         break;
3141                 case SPRN_CTR:
3142                         regs->ctr = op->val;
3143                         break;
3144                 default:
3145                         WARN_ON_ONCE(1);
3146                 }
3147                 break;
3148
3149         default:
3150                 WARN_ON_ONCE(1);
3151         }
3152         regs->nip = next_pc;
3153 }
3154 NOKPROBE_SYMBOL(emulate_update_regs);
3155
3156 /*
3157  * Emulate a previously-analysed load or store instruction.
3158  * Return values are:
3159  * 0 = instruction emulated successfully
3160  * -EFAULT = address out of range or access faulted (regs->dar
3161  *           contains the faulting address)
3162  * -EACCES = misaligned access, instruction requires alignment
3163  * -EINVAL = unknown operation in *op
3164  */
3165 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3166 {
3167         int err, size, type;
3168         int i, rd, nb;
3169         unsigned int cr;
3170         unsigned long val;
3171         unsigned long ea;
3172         bool cross_endian;
3173
3174         err = 0;
3175         size = GETSIZE(op->type);
3176         type = GETTYPE(op->type);
3177         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3178         ea = truncate_if_32bit(regs->msr, op->ea);
3179
3180         switch (type) {
3181         case LARX:
3182                 if (ea & (size - 1))
3183                         return -EACCES;         /* can't handle misaligned */
3184                 if (!address_ok(regs, ea, size))
3185                         return -EFAULT;
3186                 err = 0;
3187                 val = 0;
3188                 switch (size) {
3189 #ifdef __powerpc64__
3190                 case 1:
3191                         __get_user_asmx(val, ea, err, "lbarx");
3192                         break;
3193                 case 2:
3194                         __get_user_asmx(val, ea, err, "lharx");
3195                         break;
3196 #endif
3197                 case 4:
3198                         __get_user_asmx(val, ea, err, "lwarx");
3199                         break;
3200 #ifdef __powerpc64__
3201                 case 8:
3202                         __get_user_asmx(val, ea, err, "ldarx");
3203                         break;
3204                 case 16:
3205                         err = do_lqarx(ea, &regs->gpr[op->reg]);
3206                         break;
3207 #endif
3208                 default:
3209                         return -EINVAL;
3210                 }
3211                 if (err) {
3212                         regs->dar = ea;
3213                         break;
3214                 }
3215                 if (size < 16)
3216                         regs->gpr[op->reg] = val;
3217                 break;
3218
3219         case STCX:
3220                 if (ea & (size - 1))
3221                         return -EACCES;         /* can't handle misaligned */
3222                 if (!address_ok(regs, ea, size))
3223                         return -EFAULT;
3224                 err = 0;
3225                 switch (size) {
3226 #ifdef __powerpc64__
3227                 case 1:
3228                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3229                         break;
3230                 case 2:
3231                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3232                         break;
3233 #endif
3234                 case 4:
3235                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3236                         break;
3237 #ifdef __powerpc64__
3238                 case 8:
3239                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3240                         break;
3241                 case 16:
3242                         err = do_stqcx(ea, regs->gpr[op->reg],
3243                                        regs->gpr[op->reg + 1], &cr);
3244                         break;
3245 #endif
3246                 default:
3247                         return -EINVAL;
3248                 }
3249                 if (!err)
3250                         regs->ccr = (regs->ccr & 0x0fffffff) |
3251                                 (cr & 0xe0000000) |
3252                                 ((regs->xer >> 3) & 0x10000000);
3253                 else
3254                         regs->dar = ea;
3255                 break;
3256
3257         case LOAD:
3258 #ifdef __powerpc64__
3259                 if (size == 16) {
3260                         err = emulate_lq(regs, ea, op->reg, cross_endian);
3261                         break;
3262                 }
3263 #endif
3264                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
3265                 if (!err) {
3266                         if (op->type & SIGNEXT)
3267                                 do_signext(&regs->gpr[op->reg], size);
3268                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3269                                 do_byterev(&regs->gpr[op->reg], size);
3270                 }
3271                 break;
3272
3273 #ifdef CONFIG_PPC_FPU
3274         case LOAD_FP:
3275                 /*
3276                  * If the instruction is in userspace, we can emulate it even
3277                  * if the VMX state is not live, because we have the state
3278                  * stored in the thread_struct.  If the instruction is in
3279                  * the kernel, we must not touch the state in the thread_struct.
3280                  */
3281                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3282                         return 0;
3283                 err = do_fp_load(op, ea, regs, cross_endian);
3284                 break;
3285 #endif
3286 #ifdef CONFIG_ALTIVEC
3287         case LOAD_VMX:
3288                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3289                         return 0;
3290                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3291                 break;
3292 #endif
3293 #ifdef CONFIG_VSX
3294         case LOAD_VSX: {
3295                 unsigned long msrbit = MSR_VSX;
3296
3297                 /*
3298                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3299                  * when the target of the instruction is a vector register.
3300                  */
3301                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3302                         msrbit = MSR_VEC;
3303                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3304                         return 0;
3305                 err = do_vsx_load(op, ea, regs, cross_endian);
3306                 break;
3307         }
3308 #endif
3309         case LOAD_MULTI:
3310                 if (!address_ok(regs, ea, size))
3311                         return -EFAULT;
3312                 rd = op->reg;
3313                 for (i = 0; i < size; i += 4) {
3314                         unsigned int v32 = 0;
3315
3316                         nb = size - i;
3317                         if (nb > 4)
3318                                 nb = 4;
3319                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3320                         if (err)
3321                                 break;
3322                         if (unlikely(cross_endian))
3323                                 v32 = byterev_4(v32);
3324                         regs->gpr[rd] = v32;
3325                         ea += 4;
3326                         /* reg number wraps from 31 to 0 for lsw[ix] */
3327                         rd = (rd + 1) & 0x1f;
3328                 }
3329                 break;
3330
3331         case STORE:
3332 #ifdef __powerpc64__
3333                 if (size == 16) {
3334                         err = emulate_stq(regs, ea, op->reg, cross_endian);
3335                         break;
3336                 }
3337 #endif
3338                 if ((op->type & UPDATE) && size == sizeof(long) &&
3339                     op->reg == 1 && op->update_reg == 1 &&
3340                     !(regs->msr & MSR_PR) &&
3341                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3342                         err = handle_stack_update(ea, regs);
3343                         break;
3344                 }
3345                 if (unlikely(cross_endian))
3346                         do_byterev(&op->val, size);
3347                 err = write_mem(op->val, ea, size, regs);
3348                 break;
3349
3350 #ifdef CONFIG_PPC_FPU
3351         case STORE_FP:
3352                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3353                         return 0;
3354                 err = do_fp_store(op, ea, regs, cross_endian);
3355                 break;
3356 #endif
3357 #ifdef CONFIG_ALTIVEC
3358         case STORE_VMX:
3359                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3360                         return 0;
3361                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3362                 break;
3363 #endif
3364 #ifdef CONFIG_VSX
3365         case STORE_VSX: {
3366                 unsigned long msrbit = MSR_VSX;
3367
3368                 /*
3369                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3370                  * when the target of the instruction is a vector register.
3371                  */
3372                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3373                         msrbit = MSR_VEC;
3374                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3375                         return 0;
3376                 err = do_vsx_store(op, ea, regs, cross_endian);
3377                 break;
3378         }
3379 #endif
3380         case STORE_MULTI:
3381                 if (!address_ok(regs, ea, size))
3382                         return -EFAULT;
3383                 rd = op->reg;
3384                 for (i = 0; i < size; i += 4) {
3385                         unsigned int v32 = regs->gpr[rd];
3386
3387                         nb = size - i;
3388                         if (nb > 4)
3389                                 nb = 4;
3390                         if (unlikely(cross_endian))
3391                                 v32 = byterev_4(v32);
3392                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3393                         if (err)
3394                                 break;
3395                         ea += 4;
3396                         /* reg number wraps from 31 to 0 for stsw[ix] */
3397                         rd = (rd + 1) & 0x1f;
3398                 }
3399                 break;
3400
3401         default:
3402                 return -EINVAL;
3403         }
3404
3405         if (err)
3406                 return err;
3407
3408         if (op->type & UPDATE)
3409                 regs->gpr[op->update_reg] = op->ea;
3410
3411         return 0;
3412 }
3413 NOKPROBE_SYMBOL(emulate_loadstore);
3414
3415 /*
3416  * Emulate instructions that cause a transfer of control,
3417  * loads and stores, and a few other instructions.
3418  * Returns 1 if the step was emulated, 0 if not,
3419  * or -1 if the instruction is one that should not be stepped,
3420  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3421  */
3422 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3423 {
3424         struct instruction_op op;
3425         int r, err, type;
3426         unsigned long val;
3427         unsigned long ea;
3428
3429         r = analyse_instr(&op, regs, instr);
3430         if (r < 0)
3431                 return r;
3432         if (r > 0) {
3433                 emulate_update_regs(regs, &op);
3434                 return 1;
3435         }
3436
3437         err = 0;
3438         type = GETTYPE(op.type);
3439
3440         if (OP_IS_LOAD_STORE(type)) {
3441                 err = emulate_loadstore(regs, &op);
3442                 if (err)
3443                         return 0;
3444                 goto instr_done;
3445         }
3446
3447         switch (type) {
3448         case CACHEOP:
3449                 ea = truncate_if_32bit(regs->msr, op.ea);
3450                 if (!address_ok(regs, ea, 8))
3451                         return 0;
3452                 switch (op.type & CACHEOP_MASK) {
3453                 case DCBST:
3454                         __cacheop_user_asmx(ea, err, "dcbst");
3455                         break;
3456                 case DCBF:
3457                         __cacheop_user_asmx(ea, err, "dcbf");
3458                         break;
3459                 case DCBTST:
3460                         if (op.reg == 0)
3461                                 prefetchw((void *) ea);
3462                         break;
3463                 case DCBT:
3464                         if (op.reg == 0)
3465                                 prefetch((void *) ea);
3466                         break;
3467                 case ICBI:
3468                         __cacheop_user_asmx(ea, err, "icbi");
3469                         break;
3470                 case DCBZ:
3471                         err = emulate_dcbz(ea, regs);
3472                         break;
3473                 }
3474                 if (err) {
3475                         regs->dar = ea;
3476                         return 0;
3477                 }
3478                 goto instr_done;
3479
3480         case MFMSR:
3481                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3482                 goto instr_done;
3483
3484         case MTMSR:
3485                 val = regs->gpr[op.reg];
3486                 if ((val & MSR_RI) == 0)
3487                         /* can't step mtmsr[d] that would clear MSR_RI */
3488                         return -1;
3489                 /* here op.val is the mask of bits to change */
3490                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3491                 goto instr_done;
3492
3493 #ifdef CONFIG_PPC64
3494         case SYSCALL:   /* sc */
3495                 /*
3496                  * N.B. this uses knowledge about how the syscall
3497                  * entry code works.  If that is changed, this will
3498                  * need to be changed also.
3499                  */
3500                 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3501                                 cpu_has_feature(CPU_FTR_REAL_LE) &&
3502                                 regs->gpr[0] == 0x1ebe) {
3503                         regs->msr ^= MSR_LE;
3504                         goto instr_done;
3505                 }
3506                 regs->gpr[9] = regs->gpr[13];
3507                 regs->gpr[10] = MSR_KERNEL;
3508                 regs->gpr[11] = regs->nip + 4;
3509                 regs->gpr[12] = regs->msr & MSR_MASK;
3510                 regs->gpr[13] = (unsigned long) get_paca();
3511                 regs->nip = (unsigned long) &system_call_common;
3512                 regs->msr = MSR_KERNEL;
3513                 return 1;
3514
3515 #ifdef CONFIG_PPC_BOOK3S_64
3516         case SYSCALL_VECTORED_0:        /* scv 0 */
3517                 regs->gpr[9] = regs->gpr[13];
3518                 regs->gpr[10] = MSR_KERNEL;
3519                 regs->gpr[11] = regs->nip + 4;
3520                 regs->gpr[12] = regs->msr & MSR_MASK;
3521                 regs->gpr[13] = (unsigned long) get_paca();
3522                 regs->nip = (unsigned long) &system_call_vectored_emulate;
3523                 regs->msr = MSR_KERNEL;
3524                 return 1;
3525 #endif
3526
3527         case RFI:
3528                 return -1;
3529 #endif
3530         }
3531         return 0;
3532
3533  instr_done:
3534         regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3535         return 1;
3536 }
3537 NOKPROBE_SYMBOL(emulate_step);