arch/powerpc/lib/sstep.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Single-step support.
   4  *
   5  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/kprobes.h>
   9 #include <linux/ptrace.h>
  10 #include <linux/prefetch.h>
  11 #include <asm/sstep.h>
  12 #include <asm/processor.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/cpu_has_feature.h>
  15 #include <asm/cputable.h>
  16 #include <asm/disassemble.h>
  17
  18 extern char system_call_common[];
  19 extern char system_call_vectored_emulate[];
  20
  21 #ifdef CONFIG_PPC64
  22 /* Bits in SRR1 that are copied from MSR */
  23 #define MSR_MASK        0xffffffff87c0ffffUL
  24 #else
  25 #define MSR_MASK        0x87c0ffff
  26 #endif
  27
  28 /* Bits in XER */
  29 #define XER_SO          0x80000000U
  30 #define XER_OV          0x40000000U
  31 #define XER_CA          0x20000000U
  32 #define XER_OV32        0x00080000U
  33 #define XER_CA32        0x00040000U
  34
  35 #ifdef CONFIG_PPC_FPU
  36 /*
  37  * Functions in ldstfp.S
  38  */
  39 extern void get_fpr(int rn, double *p);
  40 extern void put_fpr(int rn, const double *p);
  41 extern void get_vr(int rn, __vector128 *p);
  42 extern void put_vr(int rn, __vector128 *p);
  43 extern void load_vsrn(int vsr, const void *p);
  44 extern void store_vsrn(int vsr, void *p);
  45 extern void conv_sp_to_dp(const float *sp, double *dp);
  46 extern void conv_dp_to_sp(const double *dp, float *sp);
  47 #endif
  48
  49 #ifdef __powerpc64__
  50 /*
  51  * Functions in quad.S
  52  */
  53 extern int do_lq(unsigned long ea, unsigned long *regs);
  54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  57                     unsigned int *crp);
  58 #endif
  59
  60 #ifdef __LITTLE_ENDIAN__
  61 #define IS_LE   1
  62 #define IS_BE   0
  63 #else
  64 #define IS_LE   0
  65 #define IS_BE   1
  66 #endif
  67
  68 /*
  69  * Emulate the truncation of 64 bit values in 32-bit mode.
  70  */
  71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  72                                                         unsigned long val)
  73 {
  74 #ifdef __powerpc64__
  75         if ((msr & MSR_64BIT) == 0)
  76                 val &= 0xffffffffUL;
  77 #endif
  78         return val;
  79 }
  80
  81 /*
  82  * Determine whether a conditional branch instruction would branch.
  83  */
  84 static nokprobe_inline int branch_taken(unsigned int instr,
  85                                         const struct pt_regs *regs,
  86                                         struct instruction_op *op)
  87 {
  88         unsigned int bo = (instr >> 21) & 0x1f;
  89         unsigned int bi;
  90
  91         if ((bo & 4) == 0) {
  92                 /* decrement counter */
  93                 op->type |= DECCTR;
  94                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  95                         return 0;
  96         }
  97         if ((bo & 0x10) == 0) {
  98                 /* check bit from CR */
  99                 bi = (instr >> 16) & 0x1f;
 100                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 101                         return 0;
 102         }
 103         return 1;
 104 }
 105
 106 static nokprobe_inline long address_ok(struct pt_regs *regs,
 107                                        unsigned long ea, int nb)
 108 {
 109         if (!user_mode(regs))
 110                 return 1;
 111         if (__access_ok(ea, nb, USER_DS))
 112                 return 1;
 113         if (__access_ok(ea, 1, USER_DS))
 114                 /* Access overlaps the end of the user region */
 115                 regs->dar = USER_DS.seg;
 116         else
 117                 regs->dar = ea;
 118         return 0;
 119 }
 120
 121 /*
 122  * Calculate effective address for a D-form instruction
 123  */
 124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 125                                               const struct pt_regs *regs)
 126 {
 127         int ra;
 128         unsigned long ea;
 129
 130         ra = (instr >> 16) & 0x1f;
 131         ea = (signed short) instr;              /* sign-extend */
 132         if (ra)
 133                 ea += regs->gpr[ra];
 134
 135         return ea;
 136 }
 137
 138 #ifdef __powerpc64__
 139 /*
 140  * Calculate effective address for a DS-form instruction
 141  */
 142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 143                                                const struct pt_regs *regs)
 144 {
 145         int ra;
 146         unsigned long ea;
 147
 148         ra = (instr >> 16) & 0x1f;
 149         ea = (signed short) (instr & ~3);       /* sign-extend */
 150         if (ra)
 151                 ea += regs->gpr[ra];
 152
 153         return ea;
 154 }
 155
 156 /*
 157  * Calculate effective address for a DQ-form instruction
 158  */
 159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 160                                                const struct pt_regs *regs)
 161 {
 162         int ra;
 163         unsigned long ea;
 164
 165         ra = (instr >> 16) & 0x1f;
 166         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 167         if (ra)
 168                 ea += regs->gpr[ra];
 169
 170         return ea;
 171 }
 172 #endif /* __powerpc64 */
 173
 174 /*
 175  * Calculate effective address for an X-form instruction
 176  */
 177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 178                                               const struct pt_regs *regs)
 179 {
 180         int ra, rb;
 181         unsigned long ea;
 182
 183         ra = (instr >> 16) & 0x1f;
 184         rb = (instr >> 11) & 0x1f;
 185         ea = regs->gpr[rb];
 186         if (ra)
 187                 ea += regs->gpr[ra];
 188
 189         return ea;
 190 }
 191
 192 /*
 193  * Calculate effective address for a MLS:D-form / 8LS:D-form
 194  * prefixed instruction
 195  */
 196 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
 197                                                   unsigned int suffix,
 198                                                   const struct pt_regs *regs)
 199 {
 200         int ra, prefix_r;
 201         unsigned int  dd;
 202         unsigned long ea, d0, d1, d;
 203
 204         prefix_r = instr & (1ul << 20);
 205         ra = (suffix >> 16) & 0x1f;
 206
 207         d0 = instr & 0x3ffff;
 208         d1 = suffix & 0xffff;
 209         d = (d0 << 16) | d1;
 210
 211         /*
 212          * sign extend a 34 bit number
 213          */
 214         dd = (unsigned int)(d >> 2);
 215         ea = (signed int)dd;
 216         ea = (ea << 2) | (d & 0x3);
 217
 218         if (!prefix_r && ra)
 219                 ea += regs->gpr[ra];
 220         else if (!prefix_r && !ra)
 221                 ; /* Leave ea as is */
 222         else if (prefix_r && !ra)
 223                 ea += regs->nip;
 224         else if (prefix_r && ra)
 225                 ; /* Invalid form. Should already be checked for by caller! */
 226
 227         return ea;
 228 }
 229
 230 /*
 231  * Return the largest power of 2, not greater than sizeof(unsigned long),
 232  * such that x is a multiple of it.
 233  */
 234 static nokprobe_inline unsigned long max_align(unsigned long x)
 235 {
 236         x |= sizeof(unsigned long);
 237         return x & -x;          /* isolates rightmost bit */
 238 }
 239
 240 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 241 {
 242         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 243 }
 244
 245 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 246 {
 247         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 248                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 249 }
 250
 251 #ifdef __powerpc64__
 252 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 253 {
 254         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 255 }
 256 #endif
 257
 258 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 259 {
 260         switch (nb) {
 261         case 2:
 262                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 263                 break;
 264         case 4:
 265                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 266                 break;
 267 #ifdef __powerpc64__
 268         case 8:
 269                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 270                 break;
 271         case 16: {
 272                 unsigned long *up = (unsigned long *)ptr;
 273                 unsigned long tmp;
 274                 tmp = byterev_8(up[0]);
 275                 up[0] = byterev_8(up[1]);
 276                 up[1] = tmp;
 277                 break;
 278         }
 279 #endif
 280         default:
 281                 WARN_ON_ONCE(1);
 282         }
 283 }
 284
 285 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 286                                             unsigned long ea, int nb,
 287                                             struct pt_regs *regs)
 288 {
 289         int err = 0;
 290         unsigned long x = 0;
 291
 292         switch (nb) {
 293         case 1:
 294                 err = __get_user(x, (unsigned char __user *) ea);
 295                 break;
 296         case 2:
 297                 err = __get_user(x, (unsigned short __user *) ea);
 298                 break;
 299         case 4:
 300                 err = __get_user(x, (unsigned int __user *) ea);
 301                 break;
 302 #ifdef __powerpc64__
 303         case 8:
 304                 err = __get_user(x, (unsigned long __user *) ea);
 305                 break;
 306 #endif
 307         }
 308         if (!err)
 309                 *dest = x;
 310         else
 311                 regs->dar = ea;
 312         return err;
 313 }
 314
 315 /*
 316  * Copy from userspace to a buffer, using the largest possible
 317  * aligned accesses, up to sizeof(long).
 318  */
 319 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 320                                        struct pt_regs *regs)
 321 {
 322         int err = 0;
 323         int c;
 324
 325         for (; nb > 0; nb -= c) {
 326                 c = max_align(ea);
 327                 if (c > nb)
 328                         c = max_align(nb);
 329                 switch (c) {
 330                 case 1:
 331                         err = __get_user(*dest, (unsigned char __user *) ea);
 332                         break;
 333                 case 2:
 334                         err = __get_user(*(u16 *)dest,
 335                                          (unsigned short __user *) ea);
 336                         break;
 337                 case 4:
 338                         err = __get_user(*(u32 *)dest,
 339                                          (unsigned int __user *) ea);
 340                         break;
 341 #ifdef __powerpc64__
 342                 case 8:
 343                         err = __get_user(*(unsigned long *)dest,
 344                                          (unsigned long __user *) ea);
 345                         break;
 346 #endif
 347                 }
 348                 if (err) {
 349                         regs->dar = ea;
 350                         return err;
 351                 }
 352                 dest += c;
 353                 ea += c;
 354         }
 355         return 0;
 356 }
 357
 358 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 359                                               unsigned long ea, int nb,
 360                                               struct pt_regs *regs)
 361 {
 362         union {
 363                 unsigned long ul;
 364                 u8 b[sizeof(unsigned long)];
 365         } u;
 366         int i;
 367         int err;
 368
 369         u.ul = 0;
 370         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 371         err = copy_mem_in(&u.b[i], ea, nb, regs);
 372         if (!err)
 373                 *dest = u.ul;
 374         return err;
 375 }
 376
 377 /*
 378  * Read memory at address ea for nb bytes, return 0 for success
 379  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 380  * If nb < sizeof(long), the result is right-justified on BE systems.
 381  */
 382 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 383                               struct pt_regs *regs)
 384 {
 385         if (!address_ok(regs, ea, nb))
 386                 return -EFAULT;
 387         if ((ea & (nb - 1)) == 0)
 388                 return read_mem_aligned(dest, ea, nb, regs);
 389         return read_mem_unaligned(dest, ea, nb, regs);
 390 }
 391 NOKPROBE_SYMBOL(read_mem);
 392
 393 static nokprobe_inline int write_mem_aligned(unsigned long val,
 394                                              unsigned long ea, int nb,
 395                                              struct pt_regs *regs)
 396 {
 397         int err = 0;
 398
 399         switch (nb) {
 400         case 1:
 401                 err = __put_user(val, (unsigned char __user *) ea);
 402                 break;
 403         case 2:
 404                 err = __put_user(val, (unsigned short __user *) ea);
 405                 break;
 406         case 4:
 407                 err = __put_user(val, (unsigned int __user *) ea);
 408                 break;
 409 #ifdef __powerpc64__
 410         case 8:
 411                 err = __put_user(val, (unsigned long __user *) ea);
 412                 break;
 413 #endif
 414         }
 415         if (err)
 416                 regs->dar = ea;
 417         return err;
 418 }
 419
 420 /*
 421  * Copy from a buffer to userspace, using the largest possible
 422  * aligned accesses, up to sizeof(long).
 423  */
 424 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 425                                         struct pt_regs *regs)
 426 {
 427         int err = 0;
 428         int c;
 429
 430         for (; nb > 0; nb -= c) {
 431                 c = max_align(ea);
 432                 if (c > nb)
 433                         c = max_align(nb);
 434                 switch (c) {
 435                 case 1:
 436                         err = __put_user(*dest, (unsigned char __user *) ea);
 437                         break;
 438                 case 2:
 439                         err = __put_user(*(u16 *)dest,
 440                                          (unsigned short __user *) ea);
 441                         break;
 442                 case 4:
 443                         err = __put_user(*(u32 *)dest,
 444                                          (unsigned int __user *) ea);
 445                         break;
 446 #ifdef __powerpc64__
 447                 case 8:
 448                         err = __put_user(*(unsigned long *)dest,
 449                                          (unsigned long __user *) ea);
 450                         break;
 451 #endif
 452                 }
 453                 if (err) {
 454                         regs->dar = ea;
 455                         return err;
 456                 }
 457                 dest += c;
 458                 ea += c;
 459         }
 460         return 0;
 461 }
 462
 463 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 464                                                unsigned long ea, int nb,
 465                                                struct pt_regs *regs)
 466 {
 467         union {
 468                 unsigned long ul;
 469                 u8 b[sizeof(unsigned long)];
 470         } u;
 471         int i;
 472
 473         u.ul = val;
 474         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 475         return copy_mem_out(&u.b[i], ea, nb, regs);
 476 }
 477
 478 /*
 479  * Write memory at address ea for nb bytes, return 0 for success
 480  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 481  */
 482 static int write_mem(unsigned long val, unsigned long ea, int nb,
 483                                struct pt_regs *regs)
 484 {
 485         if (!address_ok(regs, ea, nb))
 486                 return -EFAULT;
 487         if ((ea & (nb - 1)) == 0)
 488                 return write_mem_aligned(val, ea, nb, regs);
 489         return write_mem_unaligned(val, ea, nb, regs);
 490 }
 491 NOKPROBE_SYMBOL(write_mem);
 492
 493 #ifdef CONFIG_PPC_FPU
 494 /*
 495  * These access either the real FP register or the image in the
 496  * thread_struct, depending on regs->msr & MSR_FP.
 497  */
 498 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 499                       struct pt_regs *regs, bool cross_endian)
 500 {
 501         int err, rn, nb;
 502         union {
 503                 int i;
 504                 unsigned int u;
 505                 float f;
 506                 double d[2];
 507                 unsigned long l[2];
 508                 u8 b[2 * sizeof(double)];
 509         } u;
 510
 511         nb = GETSIZE(op->type);
 512         if (!address_ok(regs, ea, nb))
 513                 return -EFAULT;
 514         rn = op->reg;
 515         err = copy_mem_in(u.b, ea, nb, regs);
 516         if (err)
 517                 return err;
 518         if (unlikely(cross_endian)) {
 519                 do_byte_reverse(u.b, min(nb, 8));
 520                 if (nb == 16)
 521                         do_byte_reverse(&u.b[8], 8);
 522         }
 523         preempt_disable();
 524         if (nb == 4) {
 525                 if (op->type & FPCONV)
 526                         conv_sp_to_dp(&u.f, &u.d[0]);
 527                 else if (op->type & SIGNEXT)
 528                         u.l[0] = u.i;
 529                 else
 530                         u.l[0] = u.u;
 531         }
 532         if (regs->msr & MSR_FP)
 533                 put_fpr(rn, &u.d[0]);
 534         else
 535                 current->thread.TS_FPR(rn) = u.l[0];
 536         if (nb == 16) {
 537                 /* lfdp */
 538                 rn |= 1;
 539                 if (regs->msr & MSR_FP)
 540                         put_fpr(rn, &u.d[1]);
 541                 else
 542                         current->thread.TS_FPR(rn) = u.l[1];
 543         }
 544         preempt_enable();
 545         return 0;
 546 }
 547 NOKPROBE_SYMBOL(do_fp_load);
 548
 549 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 550                        struct pt_regs *regs, bool cross_endian)
 551 {
 552         int rn, nb;
 553         union {
 554                 unsigned int u;
 555                 float f;
 556                 double d[2];
 557                 unsigned long l[2];
 558                 u8 b[2 * sizeof(double)];
 559         } u;
 560
 561         nb = GETSIZE(op->type);
 562         if (!address_ok(regs, ea, nb))
 563                 return -EFAULT;
 564         rn = op->reg;
 565         preempt_disable();
 566         if (regs->msr & MSR_FP)
 567                 get_fpr(rn, &u.d[0]);
 568         else
 569                 u.l[0] = current->thread.TS_FPR(rn);
 570         if (nb == 4) {
 571                 if (op->type & FPCONV)
 572                         conv_dp_to_sp(&u.d[0], &u.f);
 573                 else
 574                         u.u = u.l[0];
 575         }
 576         if (nb == 16) {
 577                 rn |= 1;
 578                 if (regs->msr & MSR_FP)
 579                         get_fpr(rn, &u.d[1]);
 580                 else
 581                         u.l[1] = current->thread.TS_FPR(rn);
 582         }
 583         preempt_enable();
 584         if (unlikely(cross_endian)) {
 585                 do_byte_reverse(u.b, min(nb, 8));
 586                 if (nb == 16)
 587                         do_byte_reverse(&u.b[8], 8);
 588         }
 589         return copy_mem_out(u.b, ea, nb, regs);
 590 }
 591 NOKPROBE_SYMBOL(do_fp_store);
 592 #endif
 593
 594 #ifdef CONFIG_ALTIVEC
 595 /* For Altivec/VMX, no need to worry about alignment */
 596 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 597                                        int size, struct pt_regs *regs,
 598                                        bool cross_endian)
 599 {
 600         int err;
 601         union {
 602                 __vector128 v;
 603                 u8 b[sizeof(__vector128)];
 604         } u = {};
 605
 606         if (!address_ok(regs, ea & ~0xfUL, 16))
 607                 return -EFAULT;
 608         /* align to multiple of size */
 609         ea &= ~(size - 1);
 610         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 611         if (err)
 612                 return err;
 613         if (unlikely(cross_endian))
 614                 do_byte_reverse(&u.b[ea & 0xf], size);
 615         preempt_disable();
 616         if (regs->msr & MSR_VEC)
 617                 put_vr(rn, &u.v);
 618         else
 619                 current->thread.vr_state.vr[rn] = u.v;
 620         preempt_enable();
 621         return 0;
 622 }
 623
 624 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 625                                         int size, struct pt_regs *regs,
 626                                         bool cross_endian)
 627 {
 628         union {
 629                 __vector128 v;
 630                 u8 b[sizeof(__vector128)];
 631         } u;
 632
 633         if (!address_ok(regs, ea & ~0xfUL, 16))
 634                 return -EFAULT;
 635         /* align to multiple of size */
 636         ea &= ~(size - 1);
 637
 638         preempt_disable();
 639         if (regs->msr & MSR_VEC)
 640                 get_vr(rn, &u.v);
 641         else
 642                 u.v = current->thread.vr_state.vr[rn];
 643         preempt_enable();
 644         if (unlikely(cross_endian))
 645                 do_byte_reverse(&u.b[ea & 0xf], size);
 646         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 647 }
 648 #endif /* CONFIG_ALTIVEC */
 649
 650 #ifdef __powerpc64__
 651 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 652                                       int reg, bool cross_endian)
 653 {
 654         int err;
 655
 656         if (!address_ok(regs, ea, 16))
 657                 return -EFAULT;
 658         /* if aligned, should be atomic */
 659         if ((ea & 0xf) == 0) {
 660                 err = do_lq(ea, &regs->gpr[reg]);
 661         } else {
 662                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 663                 if (!err)
 664                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 665         }
 666         if (!err && unlikely(cross_endian))
 667                 do_byte_reverse(&regs->gpr[reg], 16);
 668         return err;
 669 }
 670
 671 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 672                                        int reg, bool cross_endian)
 673 {
 674         int err;
 675         unsigned long vals[2];
 676
 677         if (!address_ok(regs, ea, 16))
 678                 return -EFAULT;
 679         vals[0] = regs->gpr[reg];
 680         vals[1] = regs->gpr[reg + 1];
 681         if (unlikely(cross_endian))
 682                 do_byte_reverse(vals, 16);
 683
 684         /* if aligned, should be atomic */
 685         if ((ea & 0xf) == 0)
 686                 return do_stq(ea, vals[0], vals[1]);
 687
 688         err = write_mem(vals[IS_LE], ea, 8, regs);
 689         if (!err)
 690                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 691         return err;
 692 }
 693 #endif /* __powerpc64 */
 694
 695 #ifdef CONFIG_VSX
 696 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 697                       const void *mem, bool rev)
 698 {
 699         int size, read_size;
 700         int i, j;
 701         const unsigned int *wp;
 702         const unsigned short *hp;
 703         const unsigned char *bp;
 704
 705         size = GETSIZE(op->type);
 706         reg->d[0] = reg->d[1] = 0;
 707
 708         switch (op->element_size) {
 709         case 16:
 710                 /* whole vector; lxv[x] or lxvl[l] */
 711                 if (size == 0)
 712                         break;
 713                 memcpy(reg, mem, size);
 714                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 715                         rev = !rev;
 716                 if (rev)
 717                         do_byte_reverse(reg, 16);
 718                 break;
 719         case 8:
 720                 /* scalar loads, lxvd2x, lxvdsx */
 721                 read_size = (size >= 8) ? 8 : size;
 722                 i = IS_LE ? 8 : 8 - read_size;
 723                 memcpy(&reg->b[i], mem, read_size);
 724                 if (rev)
 725                         do_byte_reverse(&reg->b[i], 8);
 726                 if (size < 8) {
 727                         if (op->type & SIGNEXT) {
 728                                 /* size == 4 is the only case here */
 729                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 730                         } else if (op->vsx_flags & VSX_FPCONV) {
 731                                 preempt_disable();
 732                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 733                                               &reg->dp[IS_LE]);
 734                                 preempt_enable();
 735                         }
 736                 } else {
 737                         if (size == 16) {
 738                                 unsigned long v = *(unsigned long *)(mem + 8);
 739                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 740                         } else if (op->vsx_flags & VSX_SPLAT)
 741                                 reg->d[IS_BE] = reg->d[IS_LE];
 742                 }
 743                 break;
 744         case 4:
 745                 /* lxvw4x, lxvwsx */
 746                 wp = mem;
 747                 for (j = 0; j < size / 4; ++j) {
 748                         i = IS_LE ? 3 - j : j;
 749                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 750                 }
 751                 if (op->vsx_flags & VSX_SPLAT) {
 752                         u32 val = reg->w[IS_LE ? 3 : 0];
 753                         for (; j < 4; ++j) {
 754                                 i = IS_LE ? 3 - j : j;
 755                                 reg->w[i] = val;
 756                         }
 757                 }
 758                 break;
 759         case 2:
 760                 /* lxvh8x */
 761                 hp = mem;
 762                 for (j = 0; j < size / 2; ++j) {
 763                         i = IS_LE ? 7 - j : j;
 764                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 765                 }
 766                 break;
 767         case 1:
 768                 /* lxvb16x */
 769                 bp = mem;
 770                 for (j = 0; j < size; ++j) {
 771                         i = IS_LE ? 15 - j : j;
 772                         reg->b[i] = *bp++;
 773                 }
 774                 break;
 775         }
 776 }
 777 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 778 NOKPROBE_SYMBOL(emulate_vsx_load);
 779
 780 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 781                        void *mem, bool rev)
 782 {
 783         int size, write_size;
 784         int i, j;
 785         union vsx_reg buf;
 786         unsigned int *wp;
 787         unsigned short *hp;
 788         unsigned char *bp;
 789
 790         size = GETSIZE(op->type);
 791
 792         switch (op->element_size) {
 793         case 16:
 794                 /* stxv, stxvx, stxvl, stxvll */
 795                 if (size == 0)
 796                         break;
 797                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 798                         rev = !rev;
 799                 if (rev) {
 800                         /* reverse 16 bytes */
 801                         buf.d[0] = byterev_8(reg->d[1]);
 802                         buf.d[1] = byterev_8(reg->d[0]);
 803                         reg = &buf;
 804                 }
 805                 memcpy(mem, reg, size);
 806                 break;
 807         case 8:
 808                 /* scalar stores, stxvd2x */
 809                 write_size = (size >= 8) ? 8 : size;
 810                 i = IS_LE ? 8 : 8 - write_size;
 811                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 812                         buf.d[0] = buf.d[1] = 0;
 813                         preempt_disable();
 814                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 815                         preempt_enable();
 816                         reg = &buf;
 817                 }
 818                 memcpy(mem, &reg->b[i], write_size);
 819                 if (size == 16)
 820                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 821                 if (unlikely(rev)) {
 822                         do_byte_reverse(mem, write_size);
 823                         if (size == 16)
 824                                 do_byte_reverse(mem + 8, 8);
 825                 }
 826                 break;
 827         case 4:
 828                 /* stxvw4x */
 829                 wp = mem;
 830                 for (j = 0; j < size / 4; ++j) {
 831                         i = IS_LE ? 3 - j : j;
 832                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 833                 }
 834                 break;
 835         case 2:
 836                 /* stxvh8x */
 837                 hp = mem;
 838                 for (j = 0; j < size / 2; ++j) {
 839                         i = IS_LE ? 7 - j : j;
 840                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 841                 }
 842                 break;
 843         case 1:
 844                 /* stvxb16x */
 845                 bp = mem;
 846                 for (j = 0; j < size; ++j) {
 847                         i = IS_LE ? 15 - j : j;
 848                         *bp++ = reg->b[i];
 849                 }
 850                 break;
 851         }
 852 }
 853 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 854 NOKPROBE_SYMBOL(emulate_vsx_store);
 855
 856 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 857                                        unsigned long ea, struct pt_regs *regs,
 858                                        bool cross_endian)
 859 {
 860         int reg = op->reg;
 861         u8 mem[16];
 862         union vsx_reg buf;
 863         int size = GETSIZE(op->type);
 864
 865         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 866                 return -EFAULT;
 867
 868         emulate_vsx_load(op, &buf, mem, cross_endian);
 869         preempt_disable();
 870         if (reg < 32) {
 871                 /* FP regs + extensions */
 872                 if (regs->msr & MSR_FP) {
 873                         load_vsrn(reg, &buf);
 874                 } else {
 875                         current->thread.fp_state.fpr[reg][0] = buf.d[0];
 876                         current->thread.fp_state.fpr[reg][1] = buf.d[1];
 877                 }
 878         } else {
 879                 if (regs->msr & MSR_VEC)
 880                         load_vsrn(reg, &buf);
 881                 else
 882                         current->thread.vr_state.vr[reg - 32] = buf.v;
 883         }
 884         preempt_enable();
 885         return 0;
 886 }
 887
 888 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 889                                         unsigned long ea, struct pt_regs *regs,
 890                                         bool cross_endian)
 891 {
 892         int reg = op->reg;
 893         u8 mem[16];
 894         union vsx_reg buf;
 895         int size = GETSIZE(op->type);
 896
 897         if (!address_ok(regs, ea, size))
 898                 return -EFAULT;
 899
 900         preempt_disable();
 901         if (reg < 32) {
 902                 /* FP regs + extensions */
 903                 if (regs->msr & MSR_FP) {
 904                         store_vsrn(reg, &buf);
 905                 } else {
 906                         buf.d[0] = current->thread.fp_state.fpr[reg][0];
 907                         buf.d[1] = current->thread.fp_state.fpr[reg][1];
 908                 }
 909         } else {
 910                 if (regs->msr & MSR_VEC)
 911                         store_vsrn(reg, &buf);
 912                 else
 913                         buf.v = current->thread.vr_state.vr[reg - 32];
 914         }
 915         preempt_enable();
 916         emulate_vsx_store(op, &buf, mem, cross_endian);
 917         return  copy_mem_out(mem, ea, size, regs);
 918 }
 919 #endif /* CONFIG_VSX */
 920
 921 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 922 {
 923         int err;
 924         unsigned long i, size;
 925
 926 #ifdef __powerpc64__
 927         size = ppc64_caches.l1d.block_size;
 928         if (!(regs->msr & MSR_64BIT))
 929                 ea &= 0xffffffffUL;
 930 #else
 931         size = L1_CACHE_BYTES;
 932 #endif
 933         ea &= ~(size - 1);
 934         if (!address_ok(regs, ea, size))
 935                 return -EFAULT;
 936         for (i = 0; i < size; i += sizeof(long)) {
 937                 err = __put_user(0, (unsigned long __user *) (ea + i));
 938                 if (err) {
 939                         regs->dar = ea;
 940                         return err;
 941                 }
 942         }
 943         return 0;
 944 }
 945 NOKPROBE_SYMBOL(emulate_dcbz);
 946
 947 #define __put_user_asmx(x, addr, err, op, cr)           \
 948         __asm__ __volatile__(                           \
 949                 "1:     " op " %2,0,%3\n"               \
 950                 "       mfcr    %1\n"                   \
 951                 "2:\n"                                  \
 952                 ".section .fixup,\"ax\"\n"              \
 953                 "3:     li      %0,%4\n"                \
 954                 "       b       2b\n"                   \
 955                 ".previous\n"                           \
 956                 EX_TABLE(1b, 3b)                        \
 957                 : "=r" (err), "=r" (cr)                 \
 958                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 959
 960 #define __get_user_asmx(x, addr, err, op)               \
 961         __asm__ __volatile__(                           \
 962                 "1:     "op" %1,0,%2\n"                 \
 963                 "2:\n"                                  \
 964                 ".section .fixup,\"ax\"\n"              \
 965                 "3:     li      %0,%3\n"                \
 966                 "       b       2b\n"                   \
 967                 ".previous\n"                           \
 968                 EX_TABLE(1b, 3b)                        \
 969                 : "=r" (err), "=r" (x)                  \
 970                 : "r" (addr), "i" (-EFAULT), "0" (err))
 971
 972 #define __cacheop_user_asmx(addr, err, op)              \
 973         __asm__ __volatile__(                           \
 974                 "1:     "op" 0,%1\n"                    \
 975                 "2:\n"                                  \
 976                 ".section .fixup,\"ax\"\n"              \
 977                 "3:     li      %0,%3\n"                \
 978                 "       b       2b\n"                   \
 979                 ".previous\n"                           \
 980                 EX_TABLE(1b, 3b)                        \
 981                 : "=r" (err)                            \
 982                 : "r" (addr), "i" (-EFAULT), "0" (err))
 983
 984 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
 985                                     struct instruction_op *op)
 986 {
 987         long val = op->val;
 988
 989         op->type |= SETCC;
 990         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
 991 #ifdef __powerpc64__
 992         if (!(regs->msr & MSR_64BIT))
 993                 val = (int) val;
 994 #endif
 995         if (val < 0)
 996                 op->ccval |= 0x80000000;
 997         else if (val > 0)
 998                 op->ccval |= 0x40000000;
 999         else
1000                 op->ccval |= 0x20000000;
1001 }
1002
1003 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1004 {
1005         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1006                 if (val)
1007                         op->xerval |= XER_CA32;
1008                 else
1009                         op->xerval &= ~XER_CA32;
1010         }
1011 }
1012
1013 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1014                                      struct instruction_op *op, int rd,
1015                                      unsigned long val1, unsigned long val2,
1016                                      unsigned long carry_in)
1017 {
1018         unsigned long val = val1 + val2;
1019
1020         if (carry_in)
1021                 ++val;
1022         op->type = COMPUTE + SETREG + SETXER;
1023         op->reg = rd;
1024         op->val = val;
1025 #ifdef __powerpc64__
1026         if (!(regs->msr & MSR_64BIT)) {
1027                 val = (unsigned int) val;
1028                 val1 = (unsigned int) val1;
1029         }
1030 #endif
1031         op->xerval = regs->xer;
1032         if (val < val1 || (carry_in && val == val1))
1033                 op->xerval |= XER_CA;
1034         else
1035                 op->xerval &= ~XER_CA;
1036
1037         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1038                         (carry_in && (unsigned int)val == (unsigned int)val1));
1039 }
1040
1041 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1042                                           struct instruction_op *op,
1043                                           long v1, long v2, int crfld)
1044 {
1045         unsigned int crval, shift;
1046
1047         op->type = COMPUTE + SETCC;
1048         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1049         if (v1 < v2)
1050                 crval |= 8;
1051         else if (v1 > v2)
1052                 crval |= 4;
1053         else
1054                 crval |= 2;
1055         shift = (7 - crfld) * 4;
1056         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1057 }
1058
1059 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1060                                             struct instruction_op *op,
1061                                             unsigned long v1,
1062                                             unsigned long v2, int crfld)
1063 {
1064         unsigned int crval, shift;
1065
1066         op->type = COMPUTE + SETCC;
1067         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1068         if (v1 < v2)
1069                 crval |= 8;
1070         else if (v1 > v2)
1071                 crval |= 4;
1072         else
1073                 crval |= 2;
1074         shift = (7 - crfld) * 4;
1075         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1076 }
1077
1078 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1079                                     struct instruction_op *op,
1080                                     unsigned long v1, unsigned long v2)
1081 {
1082         unsigned long long out_val, mask;
1083         int i;
1084
1085         out_val = 0;
1086         for (i = 0; i < 8; i++) {
1087                 mask = 0xffUL << (i * 8);
1088                 if ((v1 & mask) == (v2 & mask))
1089                         out_val |= mask;
1090         }
1091         op->val = out_val;
1092 }
1093
1094 /*
1095  * The size parameter is used to adjust the equivalent popcnt instruction.
1096  * popcntb = 8, popcntw = 32, popcntd = 64
1097  */
1098 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1099                                       struct instruction_op *op,
1100                                       unsigned long v1, int size)
1101 {
1102         unsigned long long out = v1;
1103
1104         out -= (out >> 1) & 0x5555555555555555ULL;
1105         out = (0x3333333333333333ULL & out) +
1106               (0x3333333333333333ULL & (out >> 2));
1107         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1108
1109         if (size == 8) {        /* popcntb */
1110                 op->val = out;
1111                 return;
1112         }
1113         out += out >> 8;
1114         out += out >> 16;
1115         if (size == 32) {       /* popcntw */
1116                 op->val = out & 0x0000003f0000003fULL;
1117                 return;
1118         }
1119
1120         out = (out + (out >> 32)) & 0x7f;
1121         op->val = out;  /* popcntd */
1122 }
1123
1124 #ifdef CONFIG_PPC64
1125 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1126                                       struct instruction_op *op,
1127                                       unsigned long v1, unsigned long v2)
1128 {
1129         unsigned char perm, idx;
1130         unsigned int i;
1131
1132         perm = 0;
1133         for (i = 0; i < 8; i++) {
1134                 idx = (v1 >> (i * 8)) & 0xff;
1135                 if (idx < 64)
1136                         if (v2 & PPC_BIT(idx))
1137                                 perm |= 1 << i;
1138         }
1139         op->val = perm;
1140 }
1141 #endif /* CONFIG_PPC64 */
1142 /*
1143  * The size parameter adjusts the equivalent prty instruction.
1144  * prtyw = 32, prtyd = 64
1145  */
1146 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1147                                     struct instruction_op *op,
1148                                     unsigned long v, int size)
1149 {
1150         unsigned long long res = v ^ (v >> 8);
1151
1152         res ^= res >> 16;
1153         if (size == 32) {               /* prtyw */
1154                 op->val = res & 0x0000000100000001ULL;
1155                 return;
1156         }
1157
1158         res ^= res >> 32;
1159         op->val = res & 1;      /*prtyd */
1160 }
1161
1162 static nokprobe_inline int trap_compare(long v1, long v2)
1163 {
1164         int ret = 0;
1165
1166         if (v1 < v2)
1167                 ret |= 0x10;
1168         else if (v1 > v2)
1169                 ret |= 0x08;
1170         else
1171                 ret |= 0x04;
1172         if ((unsigned long)v1 < (unsigned long)v2)
1173                 ret |= 0x02;
1174         else if ((unsigned long)v1 > (unsigned long)v2)
1175                 ret |= 0x01;
1176         return ret;
1177 }
1178
1179 /*
1180  * Elements of 32-bit rotate and mask instructions.
1181  */
1182 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1183                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1184 #ifdef __powerpc64__
1185 #define MASK64_L(mb)    (~0UL >> (mb))
1186 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1187 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1188 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1189 #else
1190 #define DATA32(x)       (x)
1191 #endif
1192 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1193
1194 /*
1195  * Decode an instruction, and return information about it in *op
1196  * without changing *regs.
1197  * Integer arithmetic and logical instructions, branches, and barrier
1198  * instructions can be emulated just using the information in *op.
1199  *
1200  * Return value is 1 if the instruction can be emulated just by
1201  * updating *regs with the information in *op, -1 if we need the
1202  * GPRs but *regs doesn't contain the full register set, or 0
1203  * otherwise.
1204  */
1205 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1206                   struct ppc_inst instr)
1207 {
1208 #ifdef CONFIG_PPC64
1209         unsigned int suffixopcode, prefixtype, prefix_r;
1210 #endif
1211         unsigned int opcode, ra, rb, rc, rd, spr, u;
1212         unsigned long int imm;
1213         unsigned long int val, val2;
1214         unsigned int mb, me, sh;
1215         unsigned int word, suffix;
1216         long ival;
1217
1218         word = ppc_inst_val(instr);
1219         suffix = ppc_inst_suffix(instr);
1220
1221         op->type = COMPUTE;
1222
1223         opcode = ppc_inst_primary_opcode(instr);
1224         switch (opcode) {
1225         case 16:        /* bc */
1226                 op->type = BRANCH;
1227                 imm = (signed short)(word & 0xfffc);
1228                 if ((word & 2) == 0)
1229                         imm += regs->nip;
1230                 op->val = truncate_if_32bit(regs->msr, imm);
1231                 if (word & 1)
1232                         op->type |= SETLK;
1233                 if (branch_taken(word, regs, op))
1234                         op->type |= BRTAKEN;
1235                 return 1;
1236 #ifdef CONFIG_PPC64
1237         case 17:        /* sc */
1238                 if ((word & 0xfe2) == 2)
1239                         op->type = SYSCALL;
1240                 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1241                                 (word & 0xfe3) == 1)
1242                         op->type = SYSCALL_VECTORED_0;
1243                 else
1244                         op->type = UNKNOWN;
1245                 return 0;
1246 #endif
1247         case 18:        /* b */
1248                 op->type = BRANCH | BRTAKEN;
1249                 imm = word & 0x03fffffc;
1250                 if (imm & 0x02000000)
1251                         imm -= 0x04000000;
1252                 if ((word & 2) == 0)
1253                         imm += regs->nip;
1254                 op->val = truncate_if_32bit(regs->msr, imm);
1255                 if (word & 1)
1256                         op->type |= SETLK;
1257                 return 1;
1258         case 19:
1259                 switch ((word >> 1) & 0x3ff) {
1260                 case 0:         /* mcrf */
1261                         op->type = COMPUTE + SETCC;
1262                         rd = 7 - ((word >> 23) & 0x7);
1263                         ra = 7 - ((word >> 18) & 0x7);
1264                         rd *= 4;
1265                         ra *= 4;
1266                         val = (regs->ccr >> ra) & 0xf;
1267                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1268                         return 1;
1269
1270                 case 16:        /* bclr */
1271                 case 528:       /* bcctr */
1272                         op->type = BRANCH;
1273                         imm = (word & 0x400)? regs->ctr: regs->link;
1274                         op->val = truncate_if_32bit(regs->msr, imm);
1275                         if (word & 1)
1276                                 op->type |= SETLK;
1277                         if (branch_taken(word, regs, op))
1278                                 op->type |= BRTAKEN;
1279                         return 1;
1280
1281                 case 18:        /* rfid, scary */
1282                         if (regs->msr & MSR_PR)
1283                                 goto priv;
1284                         op->type = RFI;
1285                         return 0;
1286
1287                 case 150:       /* isync */
1288                         op->type = BARRIER | BARRIER_ISYNC;
1289                         return 1;
1290
1291                 case 33:        /* crnor */
1292                 case 129:       /* crandc */
1293                 case 193:       /* crxor */
1294                 case 225:       /* crnand */
1295                 case 257:       /* crand */
1296                 case 289:       /* creqv */
1297                 case 417:       /* crorc */
1298                 case 449:       /* cror */
1299                         op->type = COMPUTE + SETCC;
1300                         ra = (word >> 16) & 0x1f;
1301                         rb = (word >> 11) & 0x1f;
1302                         rd = (word >> 21) & 0x1f;
1303                         ra = (regs->ccr >> (31 - ra)) & 1;
1304                         rb = (regs->ccr >> (31 - rb)) & 1;
1305                         val = (word >> (6 + ra * 2 + rb)) & 1;
1306                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1307                                 (val << (31 - rd));
1308                         return 1;
1309                 }
1310                 break;
1311         case 31:
1312                 switch ((word >> 1) & 0x3ff) {
1313                 case 598:       /* sync */
1314                         op->type = BARRIER + BARRIER_SYNC;
1315 #ifdef __powerpc64__
1316                         switch ((word >> 21) & 3) {
1317                         case 1:         /* lwsync */
1318                                 op->type = BARRIER + BARRIER_LWSYNC;
1319                                 break;
1320                         case 2:         /* ptesync */
1321                                 op->type = BARRIER + BARRIER_PTESYNC;
1322                                 break;
1323                         }
1324 #endif
1325                         return 1;
1326
1327                 case 854:       /* eieio */
1328                         op->type = BARRIER + BARRIER_EIEIO;
1329                         return 1;
1330                 }
1331                 break;
1332         }
1333
1334         /* Following cases refer to regs->gpr[], so we need all regs */
1335         if (!FULL_REGS(regs))
1336                 return -1;
1337
1338         rd = (word >> 21) & 0x1f;
1339         ra = (word >> 16) & 0x1f;
1340         rb = (word >> 11) & 0x1f;
1341         rc = (word >> 6) & 0x1f;
1342
1343         switch (opcode) {
1344 #ifdef __powerpc64__
1345         case 1:
1346                 prefix_r = word & (1ul << 20);
1347                 ra = (suffix >> 16) & 0x1f;
1348                 rd = (suffix >> 21) & 0x1f;
1349                 op->reg = rd;
1350                 op->val = regs->gpr[rd];
1351                 suffixopcode = get_op(suffix);
1352                 prefixtype = (word >> 24) & 0x3;
1353                 switch (prefixtype) {
1354                 case 2:
1355                         if (prefix_r && ra)
1356                                 return 0;
1357                         switch (suffixopcode) {
1358                         case 14:        /* paddi */
1359                                 op->type = COMPUTE | PREFIXED;
1360                                 op->val = mlsd_8lsd_ea(word, suffix, regs);
1361                                 goto compute_done;
1362                         }
1363                 }
1364                 break;
1365         case 2:         /* tdi */
1366                 if (rd & trap_compare(regs->gpr[ra], (short) word))
1367                         goto trap;
1368                 return 1;
1369 #endif
1370         case 3:         /* twi */
1371                 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1372                         goto trap;
1373                 return 1;
1374
1375 #ifdef __powerpc64__
1376         case 4:
1377                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1378                         return -1;
1379
1380                 switch (word & 0x3f) {
1381                 case 48:        /* maddhd */
1382                         asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1383                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1384                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1385                         goto compute_done;
1386
1387                 case 49:        /* maddhdu */
1388                         asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1389                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1390                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1391                         goto compute_done;
1392
1393                 case 51:        /* maddld */
1394                         asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1395                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1396                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1397                         goto compute_done;
1398                 }
1399
1400                 /*
1401                  * There are other instructions from ISA 3.0 with the same
1402                  * primary opcode which do not have emulation support yet.
1403                  */
1404                 return -1;
1405 #endif
1406
1407         case 7:         /* mulli */
1408                 op->val = regs->gpr[ra] * (short) word;
1409                 goto compute_done;
1410
1411         case 8:         /* subfic */
1412                 imm = (short) word;
1413                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1414                 return 1;
1415
1416         case 10:        /* cmpli */
1417                 imm = (unsigned short) word;
1418                 val = regs->gpr[ra];
1419 #ifdef __powerpc64__
1420                 if ((rd & 1) == 0)
1421                         val = (unsigned int) val;
1422 #endif
1423                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1424                 return 1;
1425
1426         case 11:        /* cmpi */
1427                 imm = (short) word;
1428                 val = regs->gpr[ra];
1429 #ifdef __powerpc64__
1430                 if ((rd & 1) == 0)
1431                         val = (int) val;
1432 #endif
1433                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1434                 return 1;
1435
1436         case 12:        /* addic */
1437                 imm = (short) word;
1438                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1439                 return 1;
1440
1441         case 13:        /* addic. */
1442                 imm = (short) word;
1443                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1444                 set_cr0(regs, op);
1445                 return 1;
1446
1447         case 14:        /* addi */
1448                 imm = (short) word;
1449                 if (ra)
1450                         imm += regs->gpr[ra];
1451                 op->val = imm;
1452                 goto compute_done;
1453
1454         case 15:        /* addis */
1455                 imm = ((short) word) << 16;
1456                 if (ra)
1457                         imm += regs->gpr[ra];
1458                 op->val = imm;
1459                 goto compute_done;
1460
1461         case 19:
1462                 if (((word >> 1) & 0x1f) == 2) {
1463                         /* addpcis */
1464                         imm = (short) (word & 0xffc1);  /* d0 + d2 fields */
1465                         imm |= (word >> 15) & 0x3e;     /* d1 field */
1466                         op->val = regs->nip + (imm << 16) + 4;
1467                         goto compute_done;
1468                 }
1469                 op->type = UNKNOWN;
1470                 return 0;
1471
1472         case 20:        /* rlwimi */
1473                 mb = (word >> 6) & 0x1f;
1474                 me = (word >> 1) & 0x1f;
1475                 val = DATA32(regs->gpr[rd]);
1476                 imm = MASK32(mb, me);
1477                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1478                 goto logical_done;
1479
1480         case 21:        /* rlwinm */
1481                 mb = (word >> 6) & 0x1f;
1482                 me = (word >> 1) & 0x1f;
1483                 val = DATA32(regs->gpr[rd]);
1484                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1485                 goto logical_done;
1486
1487         case 23:        /* rlwnm */
1488                 mb = (word >> 6) & 0x1f;
1489                 me = (word >> 1) & 0x1f;
1490                 rb = regs->gpr[rb] & 0x1f;
1491                 val = DATA32(regs->gpr[rd]);
1492                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1493                 goto logical_done;
1494
1495         case 24:        /* ori */
1496                 op->val = regs->gpr[rd] | (unsigned short) word;
1497                 goto logical_done_nocc;
1498
1499         case 25:        /* oris */
1500                 imm = (unsigned short) word;
1501                 op->val = regs->gpr[rd] | (imm << 16);
1502                 goto logical_done_nocc;
1503
1504         case 26:        /* xori */
1505                 op->val = regs->gpr[rd] ^ (unsigned short) word;
1506                 goto logical_done_nocc;
1507
1508         case 27:        /* xoris */
1509                 imm = (unsigned short) word;
1510                 op->val = regs->gpr[rd] ^ (imm << 16);
1511                 goto logical_done_nocc;
1512
1513         case 28:        /* andi. */
1514                 op->val = regs->gpr[rd] & (unsigned short) word;
1515                 set_cr0(regs, op);
1516                 goto logical_done_nocc;
1517
1518         case 29:        /* andis. */
1519                 imm = (unsigned short) word;
1520                 op->val = regs->gpr[rd] & (imm << 16);
1521                 set_cr0(regs, op);
1522                 goto logical_done_nocc;
1523
1524 #ifdef __powerpc64__
1525         case 30:        /* rld* */
1526                 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1527                 val = regs->gpr[rd];
1528                 if ((word & 0x10) == 0) {
1529                         sh = rb | ((word & 2) << 4);
1530                         val = ROTATE(val, sh);
1531                         switch ((word >> 2) & 3) {
1532                         case 0:         /* rldicl */
1533                                 val &= MASK64_L(mb);
1534                                 break;
1535                         case 1:         /* rldicr */
1536                                 val &= MASK64_R(mb);
1537                                 break;
1538                         case 2:         /* rldic */
1539                                 val &= MASK64(mb, 63 - sh);
1540                                 break;
1541                         case 3:         /* rldimi */
1542                                 imm = MASK64(mb, 63 - sh);
1543                                 val = (regs->gpr[ra] & ~imm) |
1544                                         (val & imm);
1545                         }
1546                         op->val = val;
1547                         goto logical_done;
1548                 } else {
1549                         sh = regs->gpr[rb] & 0x3f;
1550                         val = ROTATE(val, sh);
1551                         switch ((word >> 1) & 7) {
1552                         case 0:         /* rldcl */
1553                                 op->val = val & MASK64_L(mb);
1554                                 goto logical_done;
1555                         case 1:         /* rldcr */
1556                                 op->val = val & MASK64_R(mb);
1557                                 goto logical_done;
1558                         }
1559                 }
1560 #endif
1561                 op->type = UNKNOWN;     /* illegal instruction */
1562                 return 0;
1563
1564         case 31:
1565                 /* isel occupies 32 minor opcodes */
1566                 if (((word >> 1) & 0x1f) == 15) {
1567                         mb = (word >> 6) & 0x1f; /* bc field */
1568                         val = (regs->ccr >> (31 - mb)) & 1;
1569                         val2 = (ra) ? regs->gpr[ra] : 0;
1570
1571                         op->val = (val) ? val2 : regs->gpr[rb];
1572                         goto compute_done;
1573                 }
1574
1575                 switch ((word >> 1) & 0x3ff) {
1576                 case 4:         /* tw */
1577                         if (rd == 0x1f ||
1578                             (rd & trap_compare((int)regs->gpr[ra],
1579                                                (int)regs->gpr[rb])))
1580                                 goto trap;
1581                         return 1;
1582 #ifdef __powerpc64__
1583                 case 68:        /* td */
1584                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1585                                 goto trap;
1586                         return 1;
1587 #endif
1588                 case 83:        /* mfmsr */
1589                         if (regs->msr & MSR_PR)
1590                                 goto priv;
1591                         op->type = MFMSR;
1592                         op->reg = rd;
1593                         return 0;
1594                 case 146:       /* mtmsr */
1595                         if (regs->msr & MSR_PR)
1596                                 goto priv;
1597                         op->type = MTMSR;
1598                         op->reg = rd;
1599                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1600                         return 0;
1601 #ifdef CONFIG_PPC64
1602                 case 178:       /* mtmsrd */
1603                         if (regs->msr & MSR_PR)
1604                                 goto priv;
1605                         op->type = MTMSR;
1606                         op->reg = rd;
1607                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1608                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1609                         imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1610                         op->val = imm;
1611                         return 0;
1612 #endif
1613
1614                 case 19:        /* mfcr */
1615                         imm = 0xffffffffUL;
1616                         if ((word >> 20) & 1) {
1617                                 imm = 0xf0000000UL;
1618                                 for (sh = 0; sh < 8; ++sh) {
1619                                         if (word & (0x80000 >> sh))
1620                                                 break;
1621                                         imm >>= 4;
1622                                 }
1623                         }
1624                         op->val = regs->ccr & imm;
1625                         goto compute_done;
1626
1627                 case 144:       /* mtcrf */
1628                         op->type = COMPUTE + SETCC;
1629                         imm = 0xf0000000UL;
1630                         val = regs->gpr[rd];
1631                         op->ccval = regs->ccr;
1632                         for (sh = 0; sh < 8; ++sh) {
1633                                 if (word & (0x80000 >> sh))
1634                                         op->ccval = (op->ccval & ~imm) |
1635                                                 (val & imm);
1636                                 imm >>= 4;
1637                         }
1638                         return 1;
1639
1640                 case 339:       /* mfspr */
1641                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1642                         op->type = MFSPR;
1643                         op->reg = rd;
1644                         op->spr = spr;
1645                         if (spr == SPRN_XER || spr == SPRN_LR ||
1646                             spr == SPRN_CTR)
1647                                 return 1;
1648                         return 0;
1649
1650                 case 467:       /* mtspr */
1651                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1652                         op->type = MTSPR;
1653                         op->val = regs->gpr[rd];
1654                         op->spr = spr;
1655                         if (spr == SPRN_XER || spr == SPRN_LR ||
1656                             spr == SPRN_CTR)
1657                                 return 1;
1658                         return 0;
1659
1660 /*
1661  * Compare instructions
1662  */
1663                 case 0: /* cmp */
1664                         val = regs->gpr[ra];
1665                         val2 = regs->gpr[rb];
1666 #ifdef __powerpc64__
1667                         if ((rd & 1) == 0) {
1668                                 /* word (32-bit) compare */
1669                                 val = (int) val;
1670                                 val2 = (int) val2;
1671                         }
1672 #endif
1673                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1674                         return 1;
1675
1676                 case 32:        /* cmpl */
1677                         val = regs->gpr[ra];
1678                         val2 = regs->gpr[rb];
1679 #ifdef __powerpc64__
1680                         if ((rd & 1) == 0) {
1681                                 /* word (32-bit) compare */
1682                                 val = (unsigned int) val;
1683                                 val2 = (unsigned int) val2;
1684                         }
1685 #endif
1686                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1687                         return 1;
1688
1689                 case 508: /* cmpb */
1690                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1691                         goto logical_done_nocc;
1692
1693 /*
1694  * Arithmetic instructions
1695  */
1696                 case 8: /* subfc */
1697                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1698                                        regs->gpr[rb], 1);
1699                         goto arith_done;
1700 #ifdef __powerpc64__
1701                 case 9: /* mulhdu */
1702                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1703                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1704                         goto arith_done;
1705 #endif
1706                 case 10:        /* addc */
1707                         add_with_carry(regs, op, rd, regs->gpr[ra],
1708                                        regs->gpr[rb], 0);
1709                         goto arith_done;
1710
1711                 case 11:        /* mulhwu */
1712                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1713                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1714                         goto arith_done;
1715
1716                 case 40:        /* subf */
1717                         op->val = regs->gpr[rb] - regs->gpr[ra];
1718                         goto arith_done;
1719 #ifdef __powerpc64__
1720                 case 73:        /* mulhd */
1721                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1722                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1723                         goto arith_done;
1724 #endif
1725                 case 75:        /* mulhw */
1726                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1727                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1728                         goto arith_done;
1729
1730                 case 104:       /* neg */
1731                         op->val = -regs->gpr[ra];
1732                         goto arith_done;
1733
1734                 case 136:       /* subfe */
1735                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1736                                        regs->gpr[rb], regs->xer & XER_CA);
1737                         goto arith_done;
1738
1739                 case 138:       /* adde */
1740                         add_with_carry(regs, op, rd, regs->gpr[ra],
1741                                        regs->gpr[rb], regs->xer & XER_CA);
1742                         goto arith_done;
1743
1744                 case 200:       /* subfze */
1745                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1746                                        regs->xer & XER_CA);
1747                         goto arith_done;
1748
1749                 case 202:       /* addze */
1750                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1751                                        regs->xer & XER_CA);
1752                         goto arith_done;
1753
1754                 case 232:       /* subfme */
1755                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1756                                        regs->xer & XER_CA);
1757                         goto arith_done;
1758 #ifdef __powerpc64__
1759                 case 233:       /* mulld */
1760                         op->val = regs->gpr[ra] * regs->gpr[rb];
1761                         goto arith_done;
1762 #endif
1763                 case 234:       /* addme */
1764                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1765                                        regs->xer & XER_CA);
1766                         goto arith_done;
1767
1768                 case 235:       /* mullw */
1769                         op->val = (long)(int) regs->gpr[ra] *
1770                                 (int) regs->gpr[rb];
1771
1772                         goto arith_done;
1773 #ifdef __powerpc64__
1774                 case 265:       /* modud */
1775                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1776                                 return -1;
1777                         op->val = regs->gpr[ra] % regs->gpr[rb];
1778                         goto compute_done;
1779 #endif
1780                 case 266:       /* add */
1781                         op->val = regs->gpr[ra] + regs->gpr[rb];
1782                         goto arith_done;
1783
1784                 case 267:       /* moduw */
1785                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1786                                 return -1;
1787                         op->val = (unsigned int) regs->gpr[ra] %
1788                                 (unsigned int) regs->gpr[rb];
1789                         goto compute_done;
1790 #ifdef __powerpc64__
1791                 case 457:       /* divdu */
1792                         op->val = regs->gpr[ra] / regs->gpr[rb];
1793                         goto arith_done;
1794 #endif
1795                 case 459:       /* divwu */
1796                         op->val = (unsigned int) regs->gpr[ra] /
1797                                 (unsigned int) regs->gpr[rb];
1798                         goto arith_done;
1799 #ifdef __powerpc64__
1800                 case 489:       /* divd */
1801                         op->val = (long int) regs->gpr[ra] /
1802                                 (long int) regs->gpr[rb];
1803                         goto arith_done;
1804 #endif
1805                 case 491:       /* divw */
1806                         op->val = (int) regs->gpr[ra] /
1807                                 (int) regs->gpr[rb];
1808                         goto arith_done;
1809
1810                 case 755:       /* darn */
1811                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1812                                 return -1;
1813                         switch (ra & 0x3) {
1814                         case 0:
1815                                 /* 32-bit conditioned */
1816                                 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1817                                 goto compute_done;
1818
1819                         case 1:
1820                                 /* 64-bit conditioned */
1821                                 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1822                                 goto compute_done;
1823
1824                         case 2:
1825                                 /* 64-bit raw */
1826                                 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1827                                 goto compute_done;
1828                         }
1829
1830                         return -1;
1831 #ifdef __powerpc64__
1832                 case 777:       /* modsd */
1833                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1834                                 return -1;
1835                         op->val = (long int) regs->gpr[ra] %
1836                                 (long int) regs->gpr[rb];
1837                         goto compute_done;
1838 #endif
1839                 case 779:       /* modsw */
1840                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1841                                 return -1;
1842                         op->val = (int) regs->gpr[ra] %
1843                                 (int) regs->gpr[rb];
1844                         goto compute_done;
1845
1846
1847 /*
1848  * Logical instructions
1849  */
1850                 case 26:        /* cntlzw */
1851                         val = (unsigned int) regs->gpr[rd];
1852                         op->val = ( val ? __builtin_clz(val) : 32 );
1853                         goto logical_done;
1854 #ifdef __powerpc64__
1855                 case 58:        /* cntlzd */
1856                         val = regs->gpr[rd];
1857                         op->val = ( val ? __builtin_clzl(val) : 64 );
1858                         goto logical_done;
1859 #endif
1860                 case 28:        /* and */
1861                         op->val = regs->gpr[rd] & regs->gpr[rb];
1862                         goto logical_done;
1863
1864                 case 60:        /* andc */
1865                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1866                         goto logical_done;
1867
1868                 case 122:       /* popcntb */
1869                         do_popcnt(regs, op, regs->gpr[rd], 8);
1870                         goto logical_done_nocc;
1871
1872                 case 124:       /* nor */
1873                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1874                         goto logical_done;
1875
1876                 case 154:       /* prtyw */
1877                         do_prty(regs, op, regs->gpr[rd], 32);
1878                         goto logical_done_nocc;
1879
1880                 case 186:       /* prtyd */
1881                         do_prty(regs, op, regs->gpr[rd], 64);
1882                         goto logical_done_nocc;
1883 #ifdef CONFIG_PPC64
1884                 case 252:       /* bpermd */
1885                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1886                         goto logical_done_nocc;
1887 #endif
1888                 case 284:       /* xor */
1889                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1890                         goto logical_done;
1891
1892                 case 316:       /* xor */
1893                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1894                         goto logical_done;
1895
1896                 case 378:       /* popcntw */
1897                         do_popcnt(regs, op, regs->gpr[rd], 32);
1898                         goto logical_done_nocc;
1899
1900                 case 412:       /* orc */
1901                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1902                         goto logical_done;
1903
1904                 case 444:       /* or */
1905                         op->val = regs->gpr[rd] | regs->gpr[rb];
1906                         goto logical_done;
1907
1908                 case 476:       /* nand */
1909                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1910                         goto logical_done;
1911 #ifdef CONFIG_PPC64
1912                 case 506:       /* popcntd */
1913                         do_popcnt(regs, op, regs->gpr[rd], 64);
1914                         goto logical_done_nocc;
1915 #endif
1916                 case 538:       /* cnttzw */
1917                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1918                                 return -1;
1919                         val = (unsigned int) regs->gpr[rd];
1920                         op->val = (val ? __builtin_ctz(val) : 32);
1921                         goto logical_done;
1922 #ifdef __powerpc64__
1923                 case 570:       /* cnttzd */
1924                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1925                                 return -1;
1926                         val = regs->gpr[rd];
1927                         op->val = (val ? __builtin_ctzl(val) : 64);
1928                         goto logical_done;
1929 #endif
1930                 case 922:       /* extsh */
1931                         op->val = (signed short) regs->gpr[rd];
1932                         goto logical_done;
1933
1934                 case 954:       /* extsb */
1935                         op->val = (signed char) regs->gpr[rd];
1936                         goto logical_done;
1937 #ifdef __powerpc64__
1938                 case 986:       /* extsw */
1939                         op->val = (signed int) regs->gpr[rd];
1940                         goto logical_done;
1941 #endif
1942
1943 /*
1944  * Shift instructions
1945  */
1946                 case 24:        /* slw */
1947                         sh = regs->gpr[rb] & 0x3f;
1948                         if (sh < 32)
1949                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1950                         else
1951                                 op->val = 0;
1952                         goto logical_done;
1953
1954                 case 536:       /* srw */
1955                         sh = regs->gpr[rb] & 0x3f;
1956                         if (sh < 32)
1957                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1958                         else
1959                                 op->val = 0;
1960                         goto logical_done;
1961
1962                 case 792:       /* sraw */
1963                         op->type = COMPUTE + SETREG + SETXER;
1964                         sh = regs->gpr[rb] & 0x3f;
1965                         ival = (signed int) regs->gpr[rd];
1966                         op->val = ival >> (sh < 32 ? sh : 31);
1967                         op->xerval = regs->xer;
1968                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1969                                 op->xerval |= XER_CA;
1970                         else
1971                                 op->xerval &= ~XER_CA;
1972                         set_ca32(op, op->xerval & XER_CA);
1973                         goto logical_done;
1974
1975                 case 824:       /* srawi */
1976                         op->type = COMPUTE + SETREG + SETXER;
1977                         sh = rb;
1978                         ival = (signed int) regs->gpr[rd];
1979                         op->val = ival >> sh;
1980                         op->xerval = regs->xer;
1981                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1982                                 op->xerval |= XER_CA;
1983                         else
1984                                 op->xerval &= ~XER_CA;
1985                         set_ca32(op, op->xerval & XER_CA);
1986                         goto logical_done;
1987
1988 #ifdef __powerpc64__
1989                 case 27:        /* sld */
1990                         sh = regs->gpr[rb] & 0x7f;
1991                         if (sh < 64)
1992                                 op->val = regs->gpr[rd] << sh;
1993                         else
1994                                 op->val = 0;
1995                         goto logical_done;
1996
1997                 case 539:       /* srd */
1998                         sh = regs->gpr[rb] & 0x7f;
1999                         if (sh < 64)
2000                                 op->val = regs->gpr[rd] >> sh;
2001                         else
2002                                 op->val = 0;
2003                         goto logical_done;
2004
2005                 case 794:       /* srad */
2006                         op->type = COMPUTE + SETREG + SETXER;
2007                         sh = regs->gpr[rb] & 0x7f;
2008                         ival = (signed long int) regs->gpr[rd];
2009                         op->val = ival >> (sh < 64 ? sh : 63);
2010                         op->xerval = regs->xer;
2011                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2012                                 op->xerval |= XER_CA;
2013                         else
2014                                 op->xerval &= ~XER_CA;
2015                         set_ca32(op, op->xerval & XER_CA);
2016                         goto logical_done;
2017
2018                 case 826:       /* sradi with sh_5 = 0 */
2019                 case 827:       /* sradi with sh_5 = 1 */
2020                         op->type = COMPUTE + SETREG + SETXER;
2021                         sh = rb | ((word & 2) << 4);
2022                         ival = (signed long int) regs->gpr[rd];
2023                         op->val = ival >> sh;
2024                         op->xerval = regs->xer;
2025                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2026                                 op->xerval |= XER_CA;
2027                         else
2028                                 op->xerval &= ~XER_CA;
2029                         set_ca32(op, op->xerval & XER_CA);
2030                         goto logical_done;
2031
2032                 case 890:       /* extswsli with sh_5 = 0 */
2033                 case 891:       /* extswsli with sh_5 = 1 */
2034                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2035                                 return -1;
2036                         op->type = COMPUTE + SETREG;
2037                         sh = rb | ((word & 2) << 4);
2038                         val = (signed int) regs->gpr[rd];
2039                         if (sh)
2040                                 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2041                         else
2042                                 op->val = val;
2043                         goto logical_done;
2044
2045 #endif /* __powerpc64__ */
2046
2047 /*
2048  * Cache instructions
2049  */
2050                 case 54:        /* dcbst */
2051                         op->type = MKOP(CACHEOP, DCBST, 0);
2052                         op->ea = xform_ea(word, regs);
2053                         return 0;
2054
2055                 case 86:        /* dcbf */
2056                         op->type = MKOP(CACHEOP, DCBF, 0);
2057                         op->ea = xform_ea(word, regs);
2058                         return 0;
2059
2060                 case 246:       /* dcbtst */
2061                         op->type = MKOP(CACHEOP, DCBTST, 0);
2062                         op->ea = xform_ea(word, regs);
2063                         op->reg = rd;
2064                         return 0;
2065
2066                 case 278:       /* dcbt */
2067                         op->type = MKOP(CACHEOP, DCBTST, 0);
2068                         op->ea = xform_ea(word, regs);
2069                         op->reg = rd;
2070                         return 0;
2071
2072                 case 982:       /* icbi */
2073                         op->type = MKOP(CACHEOP, ICBI, 0);
2074                         op->ea = xform_ea(word, regs);
2075                         return 0;
2076
2077                 case 1014:      /* dcbz */
2078                         op->type = MKOP(CACHEOP, DCBZ, 0);
2079                         op->ea = xform_ea(word, regs);
2080                         return 0;
2081                 }
2082                 break;
2083         }
2084
2085 /*
2086  * Loads and stores.
2087  */
2088         op->type = UNKNOWN;
2089         op->update_reg = ra;
2090         op->reg = rd;
2091         op->val = regs->gpr[rd];
2092         u = (word >> 20) & UPDATE;
2093         op->vsx_flags = 0;
2094
2095         switch (opcode) {
2096         case 31:
2097                 u = word & UPDATE;
2098                 op->ea = xform_ea(word, regs);
2099                 switch ((word >> 1) & 0x3ff) {
2100                 case 20:        /* lwarx */
2101                         op->type = MKOP(LARX, 0, 4);
2102                         break;
2103
2104                 case 150:       /* stwcx. */
2105                         op->type = MKOP(STCX, 0, 4);
2106                         break;
2107
2108 #ifdef __powerpc64__
2109                 case 84:        /* ldarx */
2110                         op->type = MKOP(LARX, 0, 8);
2111                         break;
2112
2113                 case 214:       /* stdcx. */
2114                         op->type = MKOP(STCX, 0, 8);
2115                         break;
2116
2117                 case 52:        /* lbarx */
2118                         op->type = MKOP(LARX, 0, 1);
2119                         break;
2120
2121                 case 694:       /* stbcx. */
2122                         op->type = MKOP(STCX, 0, 1);
2123                         break;
2124
2125                 case 116:       /* lharx */
2126                         op->type = MKOP(LARX, 0, 2);
2127                         break;
2128
2129                 case 726:       /* sthcx. */
2130                         op->type = MKOP(STCX, 0, 2);
2131                         break;
2132
2133                 case 276:       /* lqarx */
2134                         if (!((rd & 1) || rd == ra || rd == rb))
2135                                 op->type = MKOP(LARX, 0, 16);
2136                         break;
2137
2138                 case 182:       /* stqcx. */
2139                         if (!(rd & 1))
2140                                 op->type = MKOP(STCX, 0, 16);
2141                         break;
2142 #endif
2143
2144                 case 23:        /* lwzx */
2145                 case 55:        /* lwzux */
2146                         op->type = MKOP(LOAD, u, 4);
2147                         break;
2148
2149                 case 87:        /* lbzx */
2150                 case 119:       /* lbzux */
2151                         op->type = MKOP(LOAD, u, 1);
2152                         break;
2153
2154 #ifdef CONFIG_ALTIVEC
2155                 /*
2156                  * Note: for the load/store vector element instructions,
2157                  * bits of the EA say which field of the VMX register to use.
2158                  */
2159                 case 7:         /* lvebx */
2160                         op->type = MKOP(LOAD_VMX, 0, 1);
2161                         op->element_size = 1;
2162                         break;
2163
2164                 case 39:        /* lvehx */
2165                         op->type = MKOP(LOAD_VMX, 0, 2);
2166                         op->element_size = 2;
2167                         break;
2168
2169                 case 71:        /* lvewx */
2170                         op->type = MKOP(LOAD_VMX, 0, 4);
2171                         op->element_size = 4;
2172                         break;
2173
2174                 case 103:       /* lvx */
2175                 case 359:       /* lvxl */
2176                         op->type = MKOP(LOAD_VMX, 0, 16);
2177                         op->element_size = 16;
2178                         break;
2179
2180                 case 135:       /* stvebx */
2181                         op->type = MKOP(STORE_VMX, 0, 1);
2182                         op->element_size = 1;
2183                         break;
2184
2185                 case 167:       /* stvehx */
2186                         op->type = MKOP(STORE_VMX, 0, 2);
2187                         op->element_size = 2;
2188                         break;
2189
2190                 case 199:       /* stvewx */
2191                         op->type = MKOP(STORE_VMX, 0, 4);
2192                         op->element_size = 4;
2193                         break;
2194
2195                 case 231:       /* stvx */
2196                 case 487:       /* stvxl */
2197                         op->type = MKOP(STORE_VMX, 0, 16);
2198                         break;
2199 #endif /* CONFIG_ALTIVEC */
2200
2201 #ifdef __powerpc64__
2202                 case 21:        /* ldx */
2203                 case 53:        /* ldux */
2204                         op->type = MKOP(LOAD, u, 8);
2205                         break;
2206
2207                 case 149:       /* stdx */
2208                 case 181:       /* stdux */
2209                         op->type = MKOP(STORE, u, 8);
2210                         break;
2211 #endif
2212
2213                 case 151:       /* stwx */
2214                 case 183:       /* stwux */
2215                         op->type = MKOP(STORE, u, 4);
2216                         break;
2217
2218                 case 215:       /* stbx */
2219                 case 247:       /* stbux */
2220                         op->type = MKOP(STORE, u, 1);
2221                         break;
2222
2223                 case 279:       /* lhzx */
2224                 case 311:       /* lhzux */
2225                         op->type = MKOP(LOAD, u, 2);
2226                         break;
2227
2228 #ifdef __powerpc64__
2229                 case 341:       /* lwax */
2230                 case 373:       /* lwaux */
2231                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2232                         break;
2233 #endif
2234
2235                 case 343:       /* lhax */
2236                 case 375:       /* lhaux */
2237                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2238                         break;
2239
2240                 case 407:       /* sthx */
2241                 case 439:       /* sthux */
2242                         op->type = MKOP(STORE, u, 2);
2243                         break;
2244
2245 #ifdef __powerpc64__
2246                 case 532:       /* ldbrx */
2247                         op->type = MKOP(LOAD, BYTEREV, 8);
2248                         break;
2249
2250 #endif
2251                 case 533:       /* lswx */
2252                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2253                         break;
2254
2255                 case 534:       /* lwbrx */
2256                         op->type = MKOP(LOAD, BYTEREV, 4);
2257                         break;
2258
2259                 case 597:       /* lswi */
2260                         if (rb == 0)
2261                                 rb = 32;        /* # bytes to load */
2262                         op->type = MKOP(LOAD_MULTI, 0, rb);
2263                         op->ea = ra ? regs->gpr[ra] : 0;
2264                         break;
2265
2266 #ifdef CONFIG_PPC_FPU
2267                 case 535:       /* lfsx */
2268                 case 567:       /* lfsux */
2269                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2270                         break;
2271
2272                 case 599:       /* lfdx */
2273                 case 631:       /* lfdux */
2274                         op->type = MKOP(LOAD_FP, u, 8);
2275                         break;
2276
2277                 case 663:       /* stfsx */
2278                 case 695:       /* stfsux */
2279                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2280                         break;
2281
2282                 case 727:       /* stfdx */
2283                 case 759:       /* stfdux */
2284                         op->type = MKOP(STORE_FP, u, 8);
2285                         break;
2286
2287 #ifdef __powerpc64__
2288                 case 791:       /* lfdpx */
2289                         op->type = MKOP(LOAD_FP, 0, 16);
2290                         break;
2291
2292                 case 855:       /* lfiwax */
2293                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2294                         break;
2295
2296                 case 887:       /* lfiwzx */
2297                         op->type = MKOP(LOAD_FP, 0, 4);
2298                         break;
2299
2300                 case 919:       /* stfdpx */
2301                         op->type = MKOP(STORE_FP, 0, 16);
2302                         break;
2303
2304                 case 983:       /* stfiwx */
2305                         op->type = MKOP(STORE_FP, 0, 4);
2306                         break;
2307 #endif /* __powerpc64 */
2308 #endif /* CONFIG_PPC_FPU */
2309
2310 #ifdef __powerpc64__
2311                 case 660:       /* stdbrx */
2312                         op->type = MKOP(STORE, BYTEREV, 8);
2313                         op->val = byterev_8(regs->gpr[rd]);
2314                         break;
2315
2316 #endif
2317                 case 661:       /* stswx */
2318                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2319                         break;
2320
2321                 case 662:       /* stwbrx */
2322                         op->type = MKOP(STORE, BYTEREV, 4);
2323                         op->val = byterev_4(regs->gpr[rd]);
2324                         break;
2325
2326                 case 725:       /* stswi */
2327                         if (rb == 0)
2328                                 rb = 32;        /* # bytes to store */
2329                         op->type = MKOP(STORE_MULTI, 0, rb);
2330                         op->ea = ra ? regs->gpr[ra] : 0;
2331                         break;
2332
2333                 case 790:       /* lhbrx */
2334                         op->type = MKOP(LOAD, BYTEREV, 2);
2335                         break;
2336
2337                 case 918:       /* sthbrx */
2338                         op->type = MKOP(STORE, BYTEREV, 2);
2339                         op->val = byterev_2(regs->gpr[rd]);
2340                         break;
2341
2342 #ifdef CONFIG_VSX
2343                 case 12:        /* lxsiwzx */
2344                         op->reg = rd | ((word & 1) << 5);
2345                         op->type = MKOP(LOAD_VSX, 0, 4);
2346                         op->element_size = 8;
2347                         break;
2348
2349                 case 76:        /* lxsiwax */
2350                         op->reg = rd | ((word & 1) << 5);
2351                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2352                         op->element_size = 8;
2353                         break;
2354
2355                 case 140:       /* stxsiwx */
2356                         op->reg = rd | ((word & 1) << 5);
2357                         op->type = MKOP(STORE_VSX, 0, 4);
2358                         op->element_size = 8;
2359                         break;
2360
2361                 case 268:       /* lxvx */
2362                         op->reg = rd | ((word & 1) << 5);
2363                         op->type = MKOP(LOAD_VSX, 0, 16);
2364                         op->element_size = 16;
2365                         op->vsx_flags = VSX_CHECK_VEC;
2366                         break;
2367
2368                 case 269:       /* lxvl */
2369                 case 301: {     /* lxvll */
2370                         int nb;
2371                         op->reg = rd | ((word & 1) << 5);
2372                         op->ea = ra ? regs->gpr[ra] : 0;
2373                         nb = regs->gpr[rb] & 0xff;
2374                         if (nb > 16)
2375                                 nb = 16;
2376                         op->type = MKOP(LOAD_VSX, 0, nb);
2377                         op->element_size = 16;
2378                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2379                                 VSX_CHECK_VEC;
2380                         break;
2381                 }
2382                 case 332:       /* lxvdsx */
2383                         op->reg = rd | ((word & 1) << 5);
2384                         op->type = MKOP(LOAD_VSX, 0, 8);
2385                         op->element_size = 8;
2386                         op->vsx_flags = VSX_SPLAT;
2387                         break;
2388
2389                 case 364:       /* lxvwsx */
2390                         op->reg = rd | ((word & 1) << 5);
2391                         op->type = MKOP(LOAD_VSX, 0, 4);
2392                         op->element_size = 4;
2393                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2394                         break;
2395
2396                 case 396:       /* stxvx */
2397                         op->reg = rd | ((word & 1) << 5);
2398                         op->type = MKOP(STORE_VSX, 0, 16);
2399                         op->element_size = 16;
2400                         op->vsx_flags = VSX_CHECK_VEC;
2401                         break;
2402
2403                 case 397:       /* stxvl */
2404                 case 429: {     /* stxvll */
2405                         int nb;
2406                         op->reg = rd | ((word & 1) << 5);
2407                         op->ea = ra ? regs->gpr[ra] : 0;
2408                         nb = regs->gpr[rb] & 0xff;
2409                         if (nb > 16)
2410                                 nb = 16;
2411                         op->type = MKOP(STORE_VSX, 0, nb);
2412                         op->element_size = 16;
2413                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2414                                 VSX_CHECK_VEC;
2415                         break;
2416                 }
2417                 case 524:       /* lxsspx */
2418                         op->reg = rd | ((word & 1) << 5);
2419                         op->type = MKOP(LOAD_VSX, 0, 4);
2420                         op->element_size = 8;
2421                         op->vsx_flags = VSX_FPCONV;
2422                         break;
2423
2424                 case 588:       /* lxsdx */
2425                         op->reg = rd | ((word & 1) << 5);
2426                         op->type = MKOP(LOAD_VSX, 0, 8);
2427                         op->element_size = 8;
2428                         break;
2429
2430                 case 652:       /* stxsspx */
2431                         op->reg = rd | ((word & 1) << 5);
2432                         op->type = MKOP(STORE_VSX, 0, 4);
2433                         op->element_size = 8;
2434                         op->vsx_flags = VSX_FPCONV;
2435                         break;
2436
2437                 case 716:       /* stxsdx */
2438                         op->reg = rd | ((word & 1) << 5);
2439                         op->type = MKOP(STORE_VSX, 0, 8);
2440                         op->element_size = 8;
2441                         break;
2442
2443                 case 780:       /* lxvw4x */
2444                         op->reg = rd | ((word & 1) << 5);
2445                         op->type = MKOP(LOAD_VSX, 0, 16);
2446                         op->element_size = 4;
2447                         break;
2448
2449                 case 781:       /* lxsibzx */
2450                         op->reg = rd | ((word & 1) << 5);
2451                         op->type = MKOP(LOAD_VSX, 0, 1);
2452                         op->element_size = 8;
2453                         op->vsx_flags = VSX_CHECK_VEC;
2454                         break;
2455
2456                 case 812:       /* lxvh8x */
2457                         op->reg = rd | ((word & 1) << 5);
2458                         op->type = MKOP(LOAD_VSX, 0, 16);
2459                         op->element_size = 2;
2460                         op->vsx_flags = VSX_CHECK_VEC;
2461                         break;
2462
2463                 case 813:       /* lxsihzx */
2464                         op->reg = rd | ((word & 1) << 5);
2465                         op->type = MKOP(LOAD_VSX, 0, 2);
2466                         op->element_size = 8;
2467                         op->vsx_flags = VSX_CHECK_VEC;
2468                         break;
2469
2470                 case 844:       /* lxvd2x */
2471                         op->reg = rd | ((word & 1) << 5);
2472                         op->type = MKOP(LOAD_VSX, 0, 16);
2473                         op->element_size = 8;
2474                         break;
2475
2476                 case 876:       /* lxvb16x */
2477                         op->reg = rd | ((word & 1) << 5);
2478                         op->type = MKOP(LOAD_VSX, 0, 16);
2479                         op->element_size = 1;
2480                         op->vsx_flags = VSX_CHECK_VEC;
2481                         break;
2482
2483                 case 908:       /* stxvw4x */
2484                         op->reg = rd | ((word & 1) << 5);
2485                         op->type = MKOP(STORE_VSX, 0, 16);
2486                         op->element_size = 4;
2487                         break;
2488
2489                 case 909:       /* stxsibx */
2490                         op->reg = rd | ((word & 1) << 5);
2491                         op->type = MKOP(STORE_VSX, 0, 1);
2492                         op->element_size = 8;
2493                         op->vsx_flags = VSX_CHECK_VEC;
2494                         break;
2495
2496                 case 940:       /* stxvh8x */
2497                         op->reg = rd | ((word & 1) << 5);
2498                         op->type = MKOP(STORE_VSX, 0, 16);
2499                         op->element_size = 2;
2500                         op->vsx_flags = VSX_CHECK_VEC;
2501                         break;
2502
2503                 case 941:       /* stxsihx */
2504                         op->reg = rd | ((word & 1) << 5);
2505                         op->type = MKOP(STORE_VSX, 0, 2);
2506                         op->element_size = 8;
2507                         op->vsx_flags = VSX_CHECK_VEC;
2508                         break;
2509
2510                 case 972:       /* stxvd2x */
2511                         op->reg = rd | ((word & 1) << 5);
2512                         op->type = MKOP(STORE_VSX, 0, 16);
2513                         op->element_size = 8;
2514                         break;
2515
2516                 case 1004:      /* stxvb16x */
2517                         op->reg = rd | ((word & 1) << 5);
2518                         op->type = MKOP(STORE_VSX, 0, 16);
2519                         op->element_size = 1;
2520                         op->vsx_flags = VSX_CHECK_VEC;
2521                         break;
2522
2523 #endif /* CONFIG_VSX */
2524                 }
2525                 break;
2526
2527         case 32:        /* lwz */
2528         case 33:        /* lwzu */
2529                 op->type = MKOP(LOAD, u, 4);
2530                 op->ea = dform_ea(word, regs);
2531                 break;
2532
2533         case 34:        /* lbz */
2534         case 35:        /* lbzu */
2535                 op->type = MKOP(LOAD, u, 1);
2536                 op->ea = dform_ea(word, regs);
2537                 break;
2538
2539         case 36:        /* stw */
2540         case 37:        /* stwu */
2541                 op->type = MKOP(STORE, u, 4);
2542                 op->ea = dform_ea(word, regs);
2543                 break;
2544
2545         case 38:        /* stb */
2546         case 39:        /* stbu */
2547                 op->type = MKOP(STORE, u, 1);
2548                 op->ea = dform_ea(word, regs);
2549                 break;
2550
2551         case 40:        /* lhz */
2552         case 41:        /* lhzu */
2553                 op->type = MKOP(LOAD, u, 2);
2554                 op->ea = dform_ea(word, regs);
2555                 break;
2556
2557         case 42:        /* lha */
2558         case 43:        /* lhau */
2559                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2560                 op->ea = dform_ea(word, regs);
2561                 break;
2562
2563         case 44:        /* sth */
2564         case 45:        /* sthu */
2565                 op->type = MKOP(STORE, u, 2);
2566                 op->ea = dform_ea(word, regs);
2567                 break;
2568
2569         case 46:        /* lmw */
2570                 if (ra >= rd)
2571                         break;          /* invalid form, ra in range to load */
2572                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2573                 op->ea = dform_ea(word, regs);
2574                 break;
2575
2576         case 47:        /* stmw */
2577                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2578                 op->ea = dform_ea(word, regs);
2579                 break;
2580
2581 #ifdef CONFIG_PPC_FPU
2582         case 48:        /* lfs */
2583         case 49:        /* lfsu */
2584                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2585                 op->ea = dform_ea(word, regs);
2586                 break;
2587
2588         case 50:        /* lfd */
2589         case 51:        /* lfdu */
2590                 op->type = MKOP(LOAD_FP, u, 8);
2591                 op->ea = dform_ea(word, regs);
2592                 break;
2593
2594         case 52:        /* stfs */
2595         case 53:        /* stfsu */
2596                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2597                 op->ea = dform_ea(word, regs);
2598                 break;
2599
2600         case 54:        /* stfd */
2601         case 55:        /* stfdu */
2602                 op->type = MKOP(STORE_FP, u, 8);
2603                 op->ea = dform_ea(word, regs);
2604                 break;
2605 #endif
2606
2607 #ifdef __powerpc64__
2608         case 56:        /* lq */
2609                 if (!((rd & 1) || (rd == ra)))
2610                         op->type = MKOP(LOAD, 0, 16);
2611                 op->ea = dqform_ea(word, regs);
2612                 break;
2613 #endif
2614
2615 #ifdef CONFIG_VSX
2616         case 57:        /* lfdp, lxsd, lxssp */
2617                 op->ea = dsform_ea(word, regs);
2618                 switch (word & 3) {
2619                 case 0:         /* lfdp */
2620                         if (rd & 1)
2621                                 break;          /* reg must be even */
2622                         op->type = MKOP(LOAD_FP, 0, 16);
2623                         break;
2624                 case 2:         /* lxsd */
2625                         op->reg = rd + 32;
2626                         op->type = MKOP(LOAD_VSX, 0, 8);
2627                         op->element_size = 8;
2628                         op->vsx_flags = VSX_CHECK_VEC;
2629                         break;
2630                 case 3:         /* lxssp */
2631                         op->reg = rd + 32;
2632                         op->type = MKOP(LOAD_VSX, 0, 4);
2633                         op->element_size = 8;
2634                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2635                         break;
2636                 }
2637                 break;
2638 #endif /* CONFIG_VSX */
2639
2640 #ifdef __powerpc64__
2641         case 58:        /* ld[u], lwa */
2642                 op->ea = dsform_ea(word, regs);
2643                 switch (word & 3) {
2644                 case 0:         /* ld */
2645                         op->type = MKOP(LOAD, 0, 8);
2646                         break;
2647                 case 1:         /* ldu */
2648                         op->type = MKOP(LOAD, UPDATE, 8);
2649                         break;
2650                 case 2:         /* lwa */
2651                         op->type = MKOP(LOAD, SIGNEXT, 4);
2652                         break;
2653                 }
2654                 break;
2655 #endif
2656
2657 #ifdef CONFIG_VSX
2658         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2659                 switch (word & 7) {
2660                 case 0:         /* stfdp with LSB of DS field = 0 */
2661                 case 4:         /* stfdp with LSB of DS field = 1 */
2662                         op->ea = dsform_ea(word, regs);
2663                         op->type = MKOP(STORE_FP, 0, 16);
2664                         break;
2665
2666                 case 1:         /* lxv */
2667                         op->ea = dqform_ea(word, regs);
2668                         if (word & 8)
2669                                 op->reg = rd + 32;
2670                         op->type = MKOP(LOAD_VSX, 0, 16);
2671                         op->element_size = 16;
2672                         op->vsx_flags = VSX_CHECK_VEC;
2673                         break;
2674
2675                 case 2:         /* stxsd with LSB of DS field = 0 */
2676                 case 6:         /* stxsd with LSB of DS field = 1 */
2677                         op->ea = dsform_ea(word, regs);
2678                         op->reg = rd + 32;
2679                         op->type = MKOP(STORE_VSX, 0, 8);
2680                         op->element_size = 8;
2681                         op->vsx_flags = VSX_CHECK_VEC;
2682                         break;
2683
2684                 case 3:         /* stxssp with LSB of DS field = 0 */
2685                 case 7:         /* stxssp with LSB of DS field = 1 */
2686                         op->ea = dsform_ea(word, regs);
2687                         op->reg = rd + 32;
2688                         op->type = MKOP(STORE_VSX, 0, 4);
2689                         op->element_size = 8;
2690                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2691                         break;
2692
2693                 case 5:         /* stxv */
2694                         op->ea = dqform_ea(word, regs);
2695                         if (word & 8)
2696                                 op->reg = rd + 32;
2697                         op->type = MKOP(STORE_VSX, 0, 16);
2698                         op->element_size = 16;
2699                         op->vsx_flags = VSX_CHECK_VEC;
2700                         break;
2701                 }
2702                 break;
2703 #endif /* CONFIG_VSX */
2704
2705 #ifdef __powerpc64__
2706         case 62:        /* std[u] */
2707                 op->ea = dsform_ea(word, regs);
2708                 switch (word & 3) {
2709                 case 0:         /* std */
2710                         op->type = MKOP(STORE, 0, 8);
2711                         break;
2712                 case 1:         /* stdu */
2713                         op->type = MKOP(STORE, UPDATE, 8);
2714                         break;
2715                 case 2:         /* stq */
2716                         if (!(rd & 1))
2717                                 op->type = MKOP(STORE, 0, 16);
2718                         break;
2719                 }
2720                 break;
2721         case 1: /* Prefixed instructions */
2722                 prefix_r = word & (1ul << 20);
2723                 ra = (suffix >> 16) & 0x1f;
2724                 op->update_reg = ra;
2725                 rd = (suffix >> 21) & 0x1f;
2726                 op->reg = rd;
2727                 op->val = regs->gpr[rd];
2728
2729                 suffixopcode = get_op(suffix);
2730                 prefixtype = (word >> 24) & 0x3;
2731                 switch (prefixtype) {
2732                 case 0: /* Type 00  Eight-Byte Load/Store */
2733                         if (prefix_r && ra)
2734                                 break;
2735                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2736                         switch (suffixopcode) {
2737                         case 41:        /* plwa */
2738                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2739                                 break;
2740                         case 42:        /* plxsd */
2741                                 op->reg = rd + 32;
2742                                 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2743                                 op->element_size = 8;
2744                                 op->vsx_flags = VSX_CHECK_VEC;
2745                                 break;
2746                         case 43:        /* plxssp */
2747                                 op->reg = rd + 32;
2748                                 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2749                                 op->element_size = 8;
2750                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2751                                 break;
2752                         case 46:        /* pstxsd */
2753                                 op->reg = rd + 32;
2754                                 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2755                                 op->element_size = 8;
2756                                 op->vsx_flags = VSX_CHECK_VEC;
2757                                 break;
2758                         case 47:        /* pstxssp */
2759                                 op->reg = rd + 32;
2760                                 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2761                                 op->element_size = 8;
2762                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2763                                 break;
2764                         case 51:        /* plxv1 */
2765                                 op->reg += 32;
2766                                 fallthrough;
2767                         case 50:        /* plxv0 */
2768                                 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2769                                 op->element_size = 16;
2770                                 op->vsx_flags = VSX_CHECK_VEC;
2771                                 break;
2772                         case 55:        /* pstxv1 */
2773                                 op->reg = rd + 32;
2774                                 fallthrough;
2775                         case 54:        /* pstxv0 */
2776                                 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2777                                 op->element_size = 16;
2778                                 op->vsx_flags = VSX_CHECK_VEC;
2779                                 break;
2780                         case 56:        /* plq */
2781                                 op->type = MKOP(LOAD, PREFIXED, 16);
2782                                 break;
2783                         case 57:        /* pld */
2784                                 op->type = MKOP(LOAD, PREFIXED, 8);
2785                                 break;
2786                         case 60:        /* stq */
2787                                 op->type = MKOP(STORE, PREFIXED, 16);
2788                                 break;
2789                         case 61:        /* pstd */
2790                                 op->type = MKOP(STORE, PREFIXED, 8);
2791                                 break;
2792                         }
2793                         break;
2794                 case 1: /* Type 01 Eight-Byte Register-to-Register */
2795                         break;
2796                 case 2: /* Type 10 Modified Load/Store */
2797                         if (prefix_r && ra)
2798                                 break;
2799                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2800                         switch (suffixopcode) {
2801                         case 32:        /* plwz */
2802                                 op->type = MKOP(LOAD, PREFIXED, 4);
2803                                 break;
2804                         case 34:        /* plbz */
2805                                 op->type = MKOP(LOAD, PREFIXED, 1);
2806                                 break;
2807                         case 36:        /* pstw */
2808                                 op->type = MKOP(STORE, PREFIXED, 4);
2809                                 break;
2810                         case 38:        /* pstb */
2811                                 op->type = MKOP(STORE, PREFIXED, 1);
2812                                 break;
2813                         case 40:        /* plhz */
2814                                 op->type = MKOP(LOAD, PREFIXED, 2);
2815                                 break;
2816                         case 42:        /* plha */
2817                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2818                                 break;
2819                         case 44:        /* psth */
2820                                 op->type = MKOP(STORE, PREFIXED, 2);
2821                                 break;
2822                         case 48:        /* plfs */
2823                                 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2824                                 break;
2825                         case 50:        /* plfd */
2826                                 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2827                                 break;
2828                         case 52:        /* pstfs */
2829                                 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2830                                 break;
2831                         case 54:        /* pstfd */
2832                                 op->type = MKOP(STORE_FP, PREFIXED, 8);
2833                                 break;
2834                         }
2835                         break;
2836                 case 3: /* Type 11 Modified Register-to-Register */
2837                         break;
2838                 }
2839 #endif /* __powerpc64__ */
2840
2841         }
2842
2843 #ifdef CONFIG_VSX
2844         if ((GETTYPE(op->type) == LOAD_VSX ||
2845              GETTYPE(op->type) == STORE_VSX) &&
2846             !cpu_has_feature(CPU_FTR_VSX)) {
2847                 return -1;
2848         }
2849 #endif /* CONFIG_VSX */
2850
2851         return 0;
2852
2853  logical_done:
2854         if (word & 1)
2855                 set_cr0(regs, op);
2856  logical_done_nocc:
2857         op->reg = ra;
2858         op->type |= SETREG;
2859         return 1;
2860
2861  arith_done:
2862         if (word & 1)
2863                 set_cr0(regs, op);
2864  compute_done:
2865         op->reg = rd;
2866         op->type |= SETREG;
2867         return 1;
2868
2869  priv:
2870         op->type = INTERRUPT | 0x700;
2871         op->val = SRR1_PROGPRIV;
2872         return 0;
2873
2874  trap:
2875         op->type = INTERRUPT | 0x700;
2876         op->val = SRR1_PROGTRAP;
2877         return 0;
2878 }
2879 EXPORT_SYMBOL_GPL(analyse_instr);
2880 NOKPROBE_SYMBOL(analyse_instr);
2881
2882 /*
2883  * For PPC32 we always use stwu with r1 to change the stack pointer.
2884  * So this emulated store may corrupt the exception frame, now we
2885  * have to provide the exception frame trampoline, which is pushed
2886  * below the kprobed function stack. So we only update gpr[1] but
2887  * don't emulate the real store operation. We will do real store
2888  * operation safely in exception return code by checking this flag.
2889  */
2890 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2891 {
2892 #ifdef CONFIG_PPC32
2893         /*
2894          * Check if we will touch kernel stack overflow
2895          */
2896         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2897                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2898                 return -EINVAL;
2899         }
2900 #endif /* CONFIG_PPC32 */
2901         /*
2902          * Check if we already set since that means we'll
2903          * lose the previous value.
2904          */
2905         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2906         set_thread_flag(TIF_EMULATE_STACK_STORE);
2907         return 0;
2908 }
2909
2910 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2911 {
2912         switch (size) {
2913         case 2:
2914                 *valp = (signed short) *valp;
2915                 break;
2916         case 4:
2917                 *valp = (signed int) *valp;
2918                 break;
2919         }
2920 }
2921
2922 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2923 {
2924         switch (size) {
2925         case 2:
2926                 *valp = byterev_2(*valp);
2927                 break;
2928         case 4:
2929                 *valp = byterev_4(*valp);
2930                 break;
2931 #ifdef __powerpc64__
2932         case 8:
2933                 *valp = byterev_8(*valp);
2934                 break;
2935 #endif
2936         }
2937 }
2938
2939 /*
2940  * Emulate an instruction that can be executed just by updating
2941  * fields in *regs.
2942  */
2943 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2944 {
2945         unsigned long next_pc;
2946
2947         next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
2948         switch (GETTYPE(op->type)) {
2949         case COMPUTE:
2950                 if (op->type & SETREG)
2951                         regs->gpr[op->reg] = op->val;
2952                 if (op->type & SETCC)
2953                         regs->ccr = op->ccval;
2954                 if (op->type & SETXER)
2955                         regs->xer = op->xerval;
2956                 break;
2957
2958         case BRANCH:
2959                 if (op->type & SETLK)
2960                         regs->link = next_pc;
2961                 if (op->type & BRTAKEN)
2962                         next_pc = op->val;
2963                 if (op->type & DECCTR)
2964                         --regs->ctr;
2965                 break;
2966
2967         case BARRIER:
2968                 switch (op->type & BARRIER_MASK) {
2969                 case BARRIER_SYNC:
2970                         mb();
2971                         break;
2972                 case BARRIER_ISYNC:
2973                         isync();
2974                         break;
2975                 case BARRIER_EIEIO:
2976                         eieio();
2977                         break;
2978                 case BARRIER_LWSYNC:
2979                         asm volatile("lwsync" : : : "memory");
2980                         break;
2981                 case BARRIER_PTESYNC:
2982                         asm volatile("ptesync" : : : "memory");
2983                         break;
2984                 }
2985                 break;
2986
2987         case MFSPR:
2988                 switch (op->spr) {
2989                 case SPRN_XER:
2990                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2991                         break;
2992                 case SPRN_LR:
2993                         regs->gpr[op->reg] = regs->link;
2994                         break;
2995                 case SPRN_CTR:
2996                         regs->gpr[op->reg] = regs->ctr;
2997                         break;
2998                 default:
2999                         WARN_ON_ONCE(1);
3000                 }
3001                 break;
3002
3003         case MTSPR:
3004                 switch (op->spr) {
3005                 case SPRN_XER:
3006                         regs->xer = op->val & 0xffffffffUL;
3007                         break;
3008                 case SPRN_LR:
3009                         regs->link = op->val;
3010                         break;
3011                 case SPRN_CTR:
3012                         regs->ctr = op->val;
3013                         break;
3014                 default:
3015                         WARN_ON_ONCE(1);
3016                 }
3017                 break;
3018
3019         default:
3020                 WARN_ON_ONCE(1);
3021         }
3022         regs->nip = next_pc;
3023 }
3024 NOKPROBE_SYMBOL(emulate_update_regs);
3025
3026 /*
3027  * Emulate a previously-analysed load or store instruction.
3028  * Return values are:
3029  * 0 = instruction emulated successfully
3030  * -EFAULT = address out of range or access faulted (regs->dar
3031  *           contains the faulting address)
3032  * -EACCES = misaligned access, instruction requires alignment
3033  * -EINVAL = unknown operation in *op
3034  */
3035 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3036 {
3037         int err, size, type;
3038         int i, rd, nb;
3039         unsigned int cr;
3040         unsigned long val;
3041         unsigned long ea;
3042         bool cross_endian;
3043
3044         err = 0;
3045         size = GETSIZE(op->type);
3046         type = GETTYPE(op->type);
3047         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3048         ea = truncate_if_32bit(regs->msr, op->ea);
3049
3050         switch (type) {
3051         case LARX:
3052                 if (ea & (size - 1))
3053                         return -EACCES;         /* can't handle misaligned */
3054                 if (!address_ok(regs, ea, size))
3055                         return -EFAULT;
3056                 err = 0;
3057                 val = 0;
3058                 switch (size) {
3059 #ifdef __powerpc64__
3060                 case 1:
3061                         __get_user_asmx(val, ea, err, "lbarx");
3062                         break;
3063                 case 2:
3064                         __get_user_asmx(val, ea, err, "lharx");
3065                         break;
3066 #endif
3067                 case 4:
3068                         __get_user_asmx(val, ea, err, "lwarx");
3069                         break;
3070 #ifdef __powerpc64__
3071                 case 8:
3072                         __get_user_asmx(val, ea, err, "ldarx");
3073                         break;
3074                 case 16:
3075                         err = do_lqarx(ea, &regs->gpr[op->reg]);
3076                         break;
3077 #endif
3078                 default:
3079                         return -EINVAL;
3080                 }
3081                 if (err) {
3082                         regs->dar = ea;
3083                         break;
3084                 }
3085                 if (size < 16)
3086                         regs->gpr[op->reg] = val;
3087                 break;
3088
3089         case STCX:
3090                 if (ea & (size - 1))
3091                         return -EACCES;         /* can't handle misaligned */
3092                 if (!address_ok(regs, ea, size))
3093                         return -EFAULT;
3094                 err = 0;
3095                 switch (size) {
3096 #ifdef __powerpc64__
3097                 case 1:
3098                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3099                         break;
3100                 case 2:
3101                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3102                         break;
3103 #endif
3104                 case 4:
3105                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3106                         break;
3107 #ifdef __powerpc64__
3108                 case 8:
3109                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3110                         break;
3111                 case 16:
3112                         err = do_stqcx(ea, regs->gpr[op->reg],
3113                                        regs->gpr[op->reg + 1], &cr);
3114                         break;
3115 #endif
3116                 default:
3117                         return -EINVAL;
3118                 }
3119                 if (!err)
3120                         regs->ccr = (regs->ccr & 0x0fffffff) |
3121                                 (cr & 0xe0000000) |
3122                                 ((regs->xer >> 3) & 0x10000000);
3123                 else
3124                         regs->dar = ea;
3125                 break;
3126
3127         case LOAD:
3128 #ifdef __powerpc64__
3129                 if (size == 16) {
3130                         err = emulate_lq(regs, ea, op->reg, cross_endian);
3131                         break;
3132                 }
3133 #endif
3134                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
3135                 if (!err) {
3136                         if (op->type & SIGNEXT)
3137                                 do_signext(&regs->gpr[op->reg], size);
3138                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3139                                 do_byterev(&regs->gpr[op->reg], size);
3140                 }
3141                 break;
3142
3143 #ifdef CONFIG_PPC_FPU
3144         case LOAD_FP:
3145                 /*
3146                  * If the instruction is in userspace, we can emulate it even
3147                  * if the VMX state is not live, because we have the state
3148                  * stored in the thread_struct.  If the instruction is in
3149                  * the kernel, we must not touch the state in the thread_struct.
3150                  */
3151                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3152                         return 0;
3153                 err = do_fp_load(op, ea, regs, cross_endian);
3154                 break;
3155 #endif
3156 #ifdef CONFIG_ALTIVEC
3157         case LOAD_VMX:
3158                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3159                         return 0;
3160                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3161                 break;
3162 #endif
3163 #ifdef CONFIG_VSX
3164         case LOAD_VSX: {
3165                 unsigned long msrbit = MSR_VSX;
3166
3167                 /*
3168                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3169                  * when the target of the instruction is a vector register.
3170                  */
3171                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3172                         msrbit = MSR_VEC;
3173                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3174                         return 0;
3175                 err = do_vsx_load(op, ea, regs, cross_endian);
3176                 break;
3177         }
3178 #endif
3179         case LOAD_MULTI:
3180                 if (!address_ok(regs, ea, size))
3181                         return -EFAULT;
3182                 rd = op->reg;
3183                 for (i = 0; i < size; i += 4) {
3184                         unsigned int v32 = 0;
3185
3186                         nb = size - i;
3187                         if (nb > 4)
3188                                 nb = 4;
3189                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3190                         if (err)
3191                                 break;
3192                         if (unlikely(cross_endian))
3193                                 v32 = byterev_4(v32);
3194                         regs->gpr[rd] = v32;
3195                         ea += 4;
3196                         /* reg number wraps from 31 to 0 for lsw[ix] */
3197                         rd = (rd + 1) & 0x1f;
3198                 }
3199                 break;
3200
3201         case STORE:
3202 #ifdef __powerpc64__
3203                 if (size == 16) {
3204                         err = emulate_stq(regs, ea, op->reg, cross_endian);
3205                         break;
3206                 }
3207 #endif
3208                 if ((op->type & UPDATE) && size == sizeof(long) &&
3209                     op->reg == 1 && op->update_reg == 1 &&
3210                     !(regs->msr & MSR_PR) &&
3211                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3212                         err = handle_stack_update(ea, regs);
3213                         break;
3214                 }
3215                 if (unlikely(cross_endian))
3216                         do_byterev(&op->val, size);
3217                 err = write_mem(op->val, ea, size, regs);
3218                 break;
3219
3220 #ifdef CONFIG_PPC_FPU
3221         case STORE_FP:
3222                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3223                         return 0;
3224                 err = do_fp_store(op, ea, regs, cross_endian);
3225                 break;
3226 #endif
3227 #ifdef CONFIG_ALTIVEC
3228         case STORE_VMX:
3229                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3230                         return 0;
3231                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3232                 break;
3233 #endif
3234 #ifdef CONFIG_VSX
3235         case STORE_VSX: {
3236                 unsigned long msrbit = MSR_VSX;
3237
3238                 /*
3239                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3240                  * when the target of the instruction is a vector register.
3241                  */
3242                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3243                         msrbit = MSR_VEC;
3244                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3245                         return 0;
3246                 err = do_vsx_store(op, ea, regs, cross_endian);
3247                 break;
3248         }
3249 #endif
3250         case STORE_MULTI:
3251                 if (!address_ok(regs, ea, size))
3252                         return -EFAULT;
3253                 rd = op->reg;
3254                 for (i = 0; i < size; i += 4) {
3255                         unsigned int v32 = regs->gpr[rd];
3256
3257                         nb = size - i;
3258                         if (nb > 4)
3259                                 nb = 4;
3260                         if (unlikely(cross_endian))
3261                                 v32 = byterev_4(v32);
3262                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3263                         if (err)
3264                                 break;
3265                         ea += 4;
3266                         /* reg number wraps from 31 to 0 for stsw[ix] */
3267                         rd = (rd + 1) & 0x1f;
3268                 }
3269                 break;
3270
3271         default:
3272                 return -EINVAL;
3273         }
3274
3275         if (err)
3276                 return err;
3277
3278         if (op->type & UPDATE)
3279                 regs->gpr[op->update_reg] = op->ea;
3280
3281         return 0;
3282 }
3283 NOKPROBE_SYMBOL(emulate_loadstore);
3284
3285 /*
3286  * Emulate instructions that cause a transfer of control,
3287  * loads and stores, and a few other instructions.
3288  * Returns 1 if the step was emulated, 0 if not,
3289  * or -1 if the instruction is one that should not be stepped,
3290  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3291  */
3292 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3293 {
3294         struct instruction_op op;
3295         int r, err, type;
3296         unsigned long val;
3297         unsigned long ea;
3298
3299         r = analyse_instr(&op, regs, instr);
3300         if (r < 0)
3301                 return r;
3302         if (r > 0) {
3303                 emulate_update_regs(regs, &op);
3304                 return 1;
3305         }
3306
3307         err = 0;
3308         type = GETTYPE(op.type);
3309
3310         if (OP_IS_LOAD_STORE(type)) {
3311                 err = emulate_loadstore(regs, &op);
3312                 if (err)
3313                         return 0;
3314                 goto instr_done;
3315         }
3316
3317         switch (type) {
3318         case CACHEOP:
3319                 ea = truncate_if_32bit(regs->msr, op.ea);
3320                 if (!address_ok(regs, ea, 8))
3321                         return 0;
3322                 switch (op.type & CACHEOP_MASK) {
3323                 case DCBST:
3324                         __cacheop_user_asmx(ea, err, "dcbst");
3325                         break;
3326                 case DCBF:
3327                         __cacheop_user_asmx(ea, err, "dcbf");
3328                         break;
3329                 case DCBTST:
3330                         if (op.reg == 0)
3331                                 prefetchw((void *) ea);
3332                         break;
3333                 case DCBT:
3334                         if (op.reg == 0)
3335                                 prefetch((void *) ea);
3336                         break;
3337                 case ICBI:
3338                         __cacheop_user_asmx(ea, err, "icbi");
3339                         break;
3340                 case DCBZ:
3341                         err = emulate_dcbz(ea, regs);
3342                         break;
3343                 }
3344                 if (err) {
3345                         regs->dar = ea;
3346                         return 0;
3347                 }
3348                 goto instr_done;
3349
3350         case MFMSR:
3351                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3352                 goto instr_done;
3353
3354         case MTMSR:
3355                 val = regs->gpr[op.reg];
3356                 if ((val & MSR_RI) == 0)
3357                         /* can't step mtmsr[d] that would clear MSR_RI */
3358                         return -1;
3359                 /* here op.val is the mask of bits to change */
3360                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3361                 goto instr_done;
3362
3363 #ifdef CONFIG_PPC64
3364         case SYSCALL:   /* sc */
3365                 /*
3366                  * N.B. this uses knowledge about how the syscall
3367                  * entry code works.  If that is changed, this will
3368                  * need to be changed also.
3369                  */
3370                 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3371                                 cpu_has_feature(CPU_FTR_REAL_LE) &&
3372                                 regs->gpr[0] == 0x1ebe) {
3373                         regs->msr ^= MSR_LE;
3374                         goto instr_done;
3375                 }
3376                 regs->gpr[9] = regs->gpr[13];
3377                 regs->gpr[10] = MSR_KERNEL;
3378                 regs->gpr[11] = regs->nip + 4;
3379                 regs->gpr[12] = regs->msr & MSR_MASK;
3380                 regs->gpr[13] = (unsigned long) get_paca();
3381                 regs->nip = (unsigned long) &system_call_common;
3382                 regs->msr = MSR_KERNEL;
3383                 return 1;
3384
3385 #ifdef CONFIG_PPC64_BOOK3S
3386         case SYSCALL_VECTORED_0:        /* scv 0 */
3387                 regs->gpr[9] = regs->gpr[13];
3388                 regs->gpr[10] = MSR_KERNEL;
3389                 regs->gpr[11] = regs->nip + 4;
3390                 regs->gpr[12] = regs->msr & MSR_MASK;
3391                 regs->gpr[13] = (unsigned long) get_paca();
3392                 regs->nip = (unsigned long) &system_call_vectored_emulate;
3393                 regs->msr = MSR_KERNEL;
3394                 return 1;
3395 #endif
3396
3397         case RFI:
3398                 return -1;
3399 #endif
3400         }
3401         return 0;
3402
3403  instr_done:
3404         regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3405         return 1;
3406 }
3407 NOKPROBE_SYMBOL(emulate_step);