1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 * Derived from book3s_rmhandlers.S and other files, which are:
8 * Copyright SUSE Linux Products GmbH 2009
10 * Authors: Alexander Graf <agraf@suse.de>
13 #include <asm/ppc_asm.h>
14 #include <asm/code-patching-asm.h>
15 #include <asm/kvm_asm.h>
19 #include <asm/ptrace.h>
20 #include <asm/hvcall.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/exception-64s.h>
23 #include <asm/kvm_book3s_asm.h>
24 #include <asm/book3s/64/mmu-hash.h>
25 #include <asm/export.h>
28 #include <asm/xive-regs.h>
29 #include <asm/thread_info.h>
30 #include <asm/asm-compat.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/cpuidle.h>
33 #include <asm/ultravisor-api.h>
35 /* Sign-extend HDEC if not on POWER9 */
36 #define EXTEND_HDEC(reg) \
39 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41 /* Values in HSTATE_NAPPING(r13) */
42 #define NAPPING_CEDE 1
43 #define NAPPING_NOVCPU 2
44 #define NAPPING_UNSPLIT 3
46 /* Stack frame offsets for kvmppc_hv_entry */
48 #define STACK_SLOT_TRAP (SFS-4)
49 #define STACK_SLOT_SHORT_PATH (SFS-8)
50 #define STACK_SLOT_TID (SFS-16)
51 #define STACK_SLOT_PSSCR (SFS-24)
52 #define STACK_SLOT_PID (SFS-32)
53 #define STACK_SLOT_IAMR (SFS-40)
54 #define STACK_SLOT_CIABR (SFS-48)
55 #define STACK_SLOT_DAWR (SFS-56)
56 #define STACK_SLOT_DAWRX (SFS-64)
57 #define STACK_SLOT_HFSCR (SFS-72)
58 #define STACK_SLOT_AMR (SFS-80)
59 #define STACK_SLOT_UAMOR (SFS-88)
60 /* the following is used by the P9 short path */
61 #define STACK_SLOT_NVGPRS (SFS-152) /* 18 gprs */
64 * Call kvmppc_hv_entry in real mode.
65 * Must be called with interrupts hard-disabled.
69 * LR = return address to continue at after eventually re-enabling MMU
71 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
73 std r0, PPC_LR_STKOFF(r1)
76 std r10, HSTATE_HOST_MSR(r13)
77 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
82 mtmsrd r0,1 /* clear RI in MSR */
89 /* On P9, do LPCR setting, if necessary */
90 ld r3, HSTATE_SPLIT_MODE(r13)
93 lwz r4, KVM_SPLIT_DO_SET(r3)
99 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
101 ld r4, HSTATE_KVM_VCPU(r13)
104 /* Back from guest - restore host state and return to caller */
107 /* Restore host DABR and DABRX */
108 ld r5,HSTATE_DABR(r13)
112 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
115 ld r3,PACA_SPRG_VDSO(r13)
116 mtspr SPRN_SPRG_VDSO_WRITE,r3
118 /* Reload the host's PMU registers */
119 bl kvmhv_load_host_pmu
122 * Reload DEC. HDEC interrupts were disabled when
123 * we reloaded the host's LPCR value.
125 ld r3, HSTATE_DECEXP(r13)
130 /* hwthread_req may have got set by cede or no vcpu, so clear it */
132 stb r0, HSTATE_HWTHREAD_REQ(r13)
135 * For external interrupts we need to call the Linux
136 * handler to process the interrupt. We do that by jumping
137 * to absolute address 0x500 for external interrupts.
138 * The [h]rfid at the end of the handler will return to
139 * the book3s_hv_interrupts.S code. For other interrupts
140 * we do the rfid to get back to the book3s_hv_interrupts.S
143 ld r8, 112+PPC_LR_STKOFF(r1)
145 ld r7, HSTATE_HOST_MSR(r13)
147 /* Return the trap number on this thread as the return value */
151 * If we came back from the guest via a relocation-on interrupt,
152 * we will be in virtual mode at this point, which makes it a
153 * little easier to get back to the caller.
156 andi. r0, r0, MSR_IR /* in real mode? */
159 /* RFI into the highmem handler */
163 mtmsrd r6, 1 /* Clear RI in MSR */
168 /* Virtual-mode return */
173 kvmppc_primary_no_guest:
174 /* We handle this much like a ceded vcpu */
175 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
176 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
177 /* HDEC value came from DEC in the first place, it will fit */
181 * Make sure the primary has finished the MMU switch.
182 * We should never get here on a secondary thread, but
183 * check it for robustness' sake.
185 ld r5, HSTATE_KVM_VCORE(r13)
186 65: lbz r0, VCORE_IN_GUEST(r5)
193 /* set our bit in napping_threads */
194 ld r5, HSTATE_KVM_VCORE(r13)
195 lbz r7, HSTATE_PTID(r13)
198 addi r6, r5, VCORE_NAPPING_THREADS
203 /* order napping_threads update vs testing entry_exit_map */
206 lwz r7, VCORE_ENTRY_EXIT(r5)
208 bge kvm_novcpu_exit /* another thread already exiting */
209 li r3, NAPPING_NOVCPU
210 stb r3, HSTATE_NAPPING(r13)
212 li r3, 0 /* Don't wake on privileged (OS) doorbell */
217 * Entered from kvm_start_guest if kvm_hstate.napping is set
223 ld r1, HSTATE_HOST_R1(r13)
224 ld r5, HSTATE_KVM_VCORE(r13)
226 stb r0, HSTATE_NAPPING(r13)
228 /* check the wake reason */
229 bl kvmppc_check_wake_reason
232 * Restore volatile registers since we could have called
233 * a C routine in kvmppc_check_wake_reason.
236 ld r5, HSTATE_KVM_VCORE(r13)
238 /* see if any other thread is already exiting */
239 lwz r0, VCORE_ENTRY_EXIT(r5)
243 /* clear our bit in napping_threads */
244 lbz r7, HSTATE_PTID(r13)
247 addi r6, r5, VCORE_NAPPING_THREADS
253 /* See if the wake reason means we need to exit */
257 /* See if our timeslice has expired (HDEC is negative) */
260 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
264 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
265 ld r4, HSTATE_KVM_VCPU(r13)
267 beq kvmppc_primary_no_guest
269 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
270 addi r3, r4, VCPU_TB_RMENTRY
271 bl kvmhv_start_timing
276 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
277 ld r4, HSTATE_KVM_VCPU(r13)
280 addi r3, r4, VCPU_TB_RMEXIT
281 bl kvmhv_accumulate_time
284 stw r12, STACK_SLOT_TRAP(r1)
285 bl kvmhv_commence_exit
287 b kvmhv_switch_to_host
290 * We come in here when wakened from Linux offline idle code.
292 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
294 _GLOBAL(idle_kvm_start_guest)
295 ld r4,PACAEMERGSP(r13)
301 subi r1,r4,STACK_FRAME_OVERHEAD
305 * Could avoid this and pass it through in r3. For now,
306 * code expects it to be in SRR1.
311 stb r0,PACA_FTRACE_ENABLED(r13)
313 li r0,KVM_HWTHREAD_IN_KVM
314 stb r0,HSTATE_HWTHREAD_STATE(r13)
316 /* kvm cede / napping does not come through here */
317 lbz r0,HSTATE_NAPPING(r13)
324 stb r0, HSTATE_NAPPING(r13)
329 * We weren't napping due to cede, so this must be a secondary
330 * thread being woken up to run a guest, or being woken up due
331 * to a stray IPI. (Or due to some machine check or hypervisor
332 * maintenance interrupt while the core is in KVM.)
335 /* Check the wake reason in SRR1 to see why we got here */
336 bl kvmppc_check_wake_reason
338 * kvmppc_check_wake_reason could invoke a C routine, but we
339 * have no volatile registers to restore when we return.
345 /* get vcore pointer, NULL if we have nothing to run */
346 ld r5,HSTATE_KVM_VCORE(r13)
348 /* if we have no vcore to run, go back to sleep */
351 kvm_secondary_got_guest:
353 /* Set HSTATE_DSCR(r13) to something sensible */
354 ld r6, PACA_DSCR_DEFAULT(r13)
355 std r6, HSTATE_DSCR(r13)
357 /* On thread 0 of a subcore, set HDEC to max */
358 lbz r4, HSTATE_PTID(r13)
361 LOAD_REG_ADDR(r6, decrementer_max)
364 /* and set per-LPAR registers, if doing dynamic micro-threading */
365 ld r6, HSTATE_SPLIT_MODE(r13)
369 ld r0, KVM_SPLIT_RPR(r6)
371 ld r0, KVM_SPLIT_PMMAR(r6)
373 ld r0, KVM_SPLIT_LDBAR(r6)
377 /* On P9 we use the split_info for coordinating LPCR changes */
378 lwz r4, KVM_SPLIT_DO_SET(r6)
385 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
387 /* Order load of vcpu after load of vcore */
389 ld r4, HSTATE_KVM_VCPU(r13)
392 /* Back from the guest, go back to nap */
393 /* Clear our vcpu and vcore pointers so we don't come back in early */
395 std r0, HSTATE_KVM_VCPU(r13)
397 * Once we clear HSTATE_KVM_VCORE(r13), the code in
398 * kvmppc_run_core() is going to assume that all our vcpu
399 * state is visible in memory. This lwsync makes sure
403 std r0, HSTATE_KVM_VCORE(r13)
406 * All secondaries exiting guest will fall through this path.
407 * Before proceeding, just check for HMI interrupt and
408 * invoke opal hmi handler. By now we are sure that the
409 * primary thread on this core/subcore has already made partition
410 * switch/TB resync and we are good to call opal hmi handler.
412 cmpwi r12, BOOK3S_INTERRUPT_HMI
415 li r3,0 /* NULL argument */
416 bl hmi_exception_realmode
418 * At this point we have finished executing in the guest.
419 * We need to wait for hwthread_req to become zero, since
420 * we may not turn on the MMU while hwthread_req is non-zero.
421 * While waiting we also need to check if we get given a vcpu to run.
424 lbz r3, HSTATE_HWTHREAD_REQ(r13)
428 li r0, KVM_HWTHREAD_IN_KERNEL
429 stb r0, HSTATE_HWTHREAD_STATE(r13)
430 /* need to recheck hwthread_req after a barrier, to avoid race */
432 lbz r3, HSTATE_HWTHREAD_REQ(r13)
437 * Jump to idle_return_gpr_loss, which returns to the
438 * idle_kvm_start_guest caller.
442 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
444 /* set up r3 for return */
447 addi r1, r1, STACK_FRAME_OVERHEAD
456 ld r5, HSTATE_KVM_VCORE(r13)
459 ld r3, HSTATE_SPLIT_MODE(r13)
462 lwz r0, KVM_SPLIT_DO_SET(r3)
465 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
468 lbz r0, KVM_SPLIT_DO_NAP(r3)
474 b kvm_secondary_got_guest
476 54: li r0, KVM_HWTHREAD_IN_KVM
477 stb r0, HSTATE_HWTHREAD_STATE(r13)
481 /* Set LPCR, LPIDR etc. on P9 */
489 bl kvmhv_p9_restore_lpcr
494 * Here the primary thread is trying to return the core to
495 * whole-core mode, so we need to nap.
499 * When secondaries are napping in kvm_unsplit_nap() with
500 * hwthread_req = 1, HMI goes ignored even though subcores are
501 * already exited the guest. Hence HMI keeps waking up secondaries
502 * from nap in a loop and secondaries always go back to nap since
503 * no vcore is assigned to them. This makes impossible for primary
504 * thread to get hold of secondary threads resulting into a soft
505 * lockup in KVM path.
507 * Let us check if HMI is pending and handle it before we go to nap.
509 cmpwi r12, BOOK3S_INTERRUPT_HMI
511 li r3, 0 /* NULL argument */
512 bl hmi_exception_realmode
515 * Ensure that secondary doesn't nap when it has
516 * its vcore pointer set.
518 sync /* matches smp_mb() before setting split_info.do_nap */
519 ld r0, HSTATE_KVM_VCORE(r13)
522 /* clear any pending message */
524 lis r6, (PPC_DBELL_SERVER << (63-36))@h
526 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
527 /* Set kvm_split_mode.napped[tid] = 1 */
528 ld r3, HSTATE_SPLIT_MODE(r13)
530 lbz r4, HSTATE_TID(r13)
531 addi r4, r4, KVM_SPLIT_NAPPED
533 /* Check the do_nap flag again after setting napped[] */
535 lbz r0, KVM_SPLIT_DO_NAP(r3)
538 li r3, NAPPING_UNSPLIT
539 stb r3, HSTATE_NAPPING(r13)
540 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
542 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
549 /******************************************************************************
553 *****************************************************************************/
555 .global kvmppc_hv_entry
560 * R4 = vcpu pointer (or NULL)
565 * all other volatile GPRS = free
566 * Does not preserve non-volatile GPRs or CR fields
569 std r0, PPC_LR_STKOFF(r1)
572 /* Save R1 in the PACA */
573 std r1, HSTATE_HOST_R1(r13)
575 li r6, KVM_GUEST_MODE_HOST_HV
576 stb r6, HSTATE_IN_GUEST(r13)
578 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
579 /* Store initial timestamp */
582 addi r3, r4, VCPU_TB_RMENTRY
583 bl kvmhv_start_timing
587 ld r5, HSTATE_KVM_VCORE(r13)
588 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
591 * POWER7/POWER8 host -> guest partition switch code.
592 * We don't have to lock against concurrent tlbies,
593 * but we do have to coordinate across hardware threads.
595 /* Set bit in entry map iff exit map is zero. */
597 lbz r6, HSTATE_PTID(r13)
599 addi r8, r5, VCORE_ENTRY_EXIT
601 cmpwi r3, 0x100 /* any threads starting to exit? */
602 bge secondary_too_late /* if so we're too late to the party */
607 /* Primary thread switches to guest partition. */
614 li r0,LPID_RSVD /* switch to reserved LPID */
617 mtspr SPRN_SDR1,r6 /* switch to partition page table */
618 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
622 /* See if we need to flush the TLB. */
623 mr r3, r9 /* kvm pointer */
624 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
625 li r5, 0 /* nested vcpu pointer */
626 bl kvmppc_check_need_tlb_flush
628 ld r5, HSTATE_KVM_VCORE(r13)
630 /* Add timebase offset onto timebase */
631 22: ld r8,VCORE_TB_OFFSET(r5)
634 std r8, VCORE_TB_OFFSET_APPL(r5)
635 mftb r6 /* current host timebase */
637 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
638 mftb r7 /* check if lower 24 bits overflowed */
643 addis r8,r8,0x100 /* if so, increment upper 40 bits */
646 /* Load guest PCR value to select appropriate compat mode */
647 37: ld r7, VCORE_PCR(r5)
648 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
656 /* DPDES and VTB are shared between threads */
657 ld r8, VCORE_DPDES(r5)
661 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
663 /* Mark the subcore state as inside guest */
664 bl kvmppc_subcore_enter_guest
666 ld r5, HSTATE_KVM_VCORE(r13)
667 ld r4, HSTATE_KVM_VCPU(r13)
669 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
671 /* Do we have a guest vcpu to run? */
673 beq kvmppc_primary_no_guest
675 /* Increment yield count if they have a VPA */
679 li r6, LPPACA_YIELDCOUNT
684 stb r6, VCPU_VPA_DIRTY(r4)
687 /* Save purr/spurr */
690 std r5,HSTATE_PURR(r13)
691 std r6,HSTATE_SPURR(r13)
697 /* Save host values of some registers */
702 std r5, STACK_SLOT_TID(r1)
703 std r6, STACK_SLOT_PSSCR(r1)
704 std r7, STACK_SLOT_PID(r1)
706 std r5, STACK_SLOT_HFSCR(r1)
707 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
711 mfspr r7, SPRN_DAWRX0
713 std r5, STACK_SLOT_CIABR(r1)
714 std r6, STACK_SLOT_DAWR(r1)
715 std r7, STACK_SLOT_DAWRX(r1)
716 std r8, STACK_SLOT_IAMR(r1)
717 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
720 std r5, STACK_SLOT_AMR(r1)
722 std r6, STACK_SLOT_UAMOR(r1)
725 /* Set partition DABR */
726 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
727 lwz r5,VCPU_DABRX(r4)
732 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
734 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
736 * Branch around the call if both CPU_FTR_TM and
737 * CPU_FTR_P9_TM_HV_ASSIST are off.
741 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
743 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
747 li r5, 0 /* don't preserve non-vol regs */
748 bl kvmppc_restore_tm_hv
750 ld r4, HSTATE_KVM_VCPU(r13)
754 /* Load guest PMU registers; r4 = vcpu pointer here */
756 bl kvmhv_load_guest_pmu
758 /* Load up FP, VMX and VSX registers */
759 ld r4, HSTATE_KVM_VCPU(r13)
762 ld r14, VCPU_GPR(R14)(r4)
763 ld r15, VCPU_GPR(R15)(r4)
764 ld r16, VCPU_GPR(R16)(r4)
765 ld r17, VCPU_GPR(R17)(r4)
766 ld r18, VCPU_GPR(R18)(r4)
767 ld r19, VCPU_GPR(R19)(r4)
768 ld r20, VCPU_GPR(R20)(r4)
769 ld r21, VCPU_GPR(R21)(r4)
770 ld r22, VCPU_GPR(R22)(r4)
771 ld r23, VCPU_GPR(R23)(r4)
772 ld r24, VCPU_GPR(R24)(r4)
773 ld r25, VCPU_GPR(R25)(r4)
774 ld r26, VCPU_GPR(R26)(r4)
775 ld r27, VCPU_GPR(R27)(r4)
776 ld r28, VCPU_GPR(R28)(r4)
777 ld r29, VCPU_GPR(R29)(r4)
778 ld r30, VCPU_GPR(R30)(r4)
779 ld r31, VCPU_GPR(R31)(r4)
781 /* Switch DSCR to guest value */
786 /* Skip next section on POWER7 */
788 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
789 /* Load up POWER8-specific registers */
791 lwz r6, VCPU_PSPB(r4)
797 * Handle broken DAWR case by not writing it. This means we
798 * can still store the DAWR register for migration.
800 LOAD_REG_ADDR(r5, dawr_force_enable)
805 ld r6, VCPU_DAWRX(r4)
807 mtspr SPRN_DAWRX0, r6
809 ld r7, VCPU_CIABR(r4)
814 ld r8, VCPU_EBBHR(r4)
817 ld r5, VCPU_EBBRR(r4)
818 ld r6, VCPU_BESCR(r4)
819 lwz r7, VCPU_GUEST_PID(r4)
826 /* POWER8-only registers */
827 ld r5, VCPU_TCSCR(r4)
829 ld r7, VCPU_CSIGR(r4)
837 /* POWER9-only registers */
839 ld r6, VCPU_PSSCR(r4)
840 lbz r8, HSTATE_FAKE_SUSPEND(r13)
841 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
842 rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG
843 ld r7, VCPU_HFSCR(r4)
847 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
850 ld r5, VCPU_SPRG0(r4)
851 ld r6, VCPU_SPRG1(r4)
852 ld r7, VCPU_SPRG2(r4)
853 ld r8, VCPU_SPRG3(r4)
859 /* Load up DAR and DSISR */
861 lwz r6, VCPU_DSISR(r4)
865 /* Restore AMR and UAMOR, set AMOR to all 1s */
873 /* Restore state of CTRL run bit; assume 1 on entry */
881 /* Secondary threads wait for primary to have done partition switch */
882 ld r5, HSTATE_KVM_VCORE(r13)
883 lbz r6, HSTATE_PTID(r13)
886 lbz r0, VCORE_IN_GUEST(r5)
890 20: lwz r3, VCORE_ENTRY_EXIT(r5)
893 lbz r0, VCORE_IN_GUEST(r5)
904 * Set the decrementer to the guest decrementer.
906 ld r8,VCPU_DEC_EXPIRES(r4)
907 /* r8 is a host timebase value here, convert to guest TB */
908 ld r5,HSTATE_KVM_VCORE(r13)
909 ld r6,VCORE_TB_OFFSET_APPL(r5)
915 /* Check if HDEC expires soon */
918 cmpdi r3, 512 /* 1 microsecond */
921 /* For hash guest, clear out and reload the SLB */
923 lbz r0, KVM_RADIX(r6)
931 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
932 lwz r5,VCPU_SLB_MAX(r4)
937 1: ld r8,VCPU_SLB_E(r6)
940 addi r6,r6,VCPU_SLB_SIZE
944 #ifdef CONFIG_KVM_XICS
945 /* We are entering the guest on that thread, push VCPU to XIVE */
946 ld r11, VCPU_XIVE_SAVED_STATE(r4)
948 lwz r8, VCPU_XIVE_CAM_WORD(r4)
951 li r7, TM_QW1_OS + TM_WORD2
953 andi. r0, r0, MSR_DR /* in real mode? */
955 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
962 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
969 stb r9, VCPU_XIVE_PUSHED(r4)
973 * We clear the irq_pending flag. There is a small chance of a
974 * race vs. the escalation interrupt happening on another
975 * processor setting it again, but the only consequence is to
976 * cause a spurrious wakeup on the next H_CEDE which is not an
980 stb r0, VCPU_IRQ_PENDING(r4)
983 * In single escalation mode, if the escalation interrupt is
986 lbz r0, VCPU_XIVE_ESC_ON(r4)
989 li r9, XIVE_ESB_SET_PQ_01
990 beq 4f /* in real mode? */
991 ld r10, VCPU_XIVE_ESC_VADDR(r4)
994 4: ld r10, VCPU_XIVE_ESC_RADDR(r4)
998 /* We have a possible subtle race here: The escalation interrupt might
999 * have fired and be on its way to the host queue while we mask it,
1000 * and if we unmask it early enough (re-cede right away), there is
1001 * a theorical possibility that it fires again, thus landing in the
1002 * target queue more than once which is a big no-no.
1004 * Fortunately, solving this is rather easy. If the above load setting
1005 * PQ to 01 returns a previous value where P is set, then we know the
1006 * escalation interrupt is somewhere on its way to the host. In that
1007 * case we simply don't clear the xive_esc_on flag below. It will be
1008 * eventually cleared by the handler for the escalation interrupt.
1010 * Then, when doing a cede, we check that flag again before re-enabling
1011 * the escalation interrupt, and if set, we abort the cede.
1013 andi. r0, r0, XIVE_ESB_VAL_P
1016 /* Now P is 0, we can clear the flag */
1018 stb r0, VCPU_XIVE_ESC_ON(r4)
1021 #endif /* CONFIG_KVM_XICS */
1024 stw r0, STACK_SLOT_SHORT_PATH(r1)
1026 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
1027 /* Check if we can deliver an external or decrementer interrupt now */
1028 ld r0, VCPU_PENDING_EXC(r4)
1030 /* On POWER9, also check for emulated doorbell interrupt */
1031 lbz r3, VCPU_DBELL_REQ(r4)
1033 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1037 bl kvmppc_guest_entry_inject_int
1038 ld r4, HSTATE_KVM_VCPU(r13)
1040 ld r6, VCPU_SRR0(r4)
1041 ld r7, VCPU_SRR1(r4)
1047 ld r11, VCPU_MSR(r4)
1048 /* r11 = vcpu->arch.msr & ~MSR_HV */
1049 rldicl r11, r11, 63 - MSR_HV_LG, 1
1050 rotldi r11, r11, 1 + MSR_HV_LG
1051 ori r11, r11, MSR_ME
1061 * R10: value for HSRR0
1062 * R11: value for HSRR1
1067 stb r0,VCPU_CEDED(r4) /* cancel cede */
1068 mtspr SPRN_HSRR0,r10
1069 mtspr SPRN_HSRR1,r11
1071 /* Activate guest mode, so faults get handled by KVM */
1072 li r9, KVM_GUEST_MODE_GUEST_HV
1073 stb r9, HSTATE_IN_GUEST(r13)
1075 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1076 /* Accumulate timing */
1077 addi r3, r4, VCPU_TB_GUEST
1078 bl kvmhv_accumulate_time
1084 ld r5, VCPU_CFAR(r4)
1086 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1089 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1094 ld r1, VCPU_GPR(R1)(r4)
1095 ld r5, VCPU_GPR(R5)(r4)
1096 ld r8, VCPU_GPR(R8)(r4)
1097 ld r9, VCPU_GPR(R9)(r4)
1098 ld r10, VCPU_GPR(R10)(r4)
1099 ld r11, VCPU_GPR(R11)(r4)
1100 ld r12, VCPU_GPR(R12)(r4)
1101 ld r13, VCPU_GPR(R13)(r4)
1105 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1107 /* Move canary into DSISR to check for later */
1110 mtspr SPRN_HDSISR, r0
1111 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1114 lbz r7, KVM_SECURE_GUEST(r6)
1116 ld r6, VCPU_GPR(R6)(r4)
1117 ld r7, VCPU_GPR(R7)(r4)
1123 ld r0, VCPU_GPR(R0)(r4)
1124 ld r2, VCPU_GPR(R2)(r4)
1125 ld r3, VCPU_GPR(R3)(r4)
1126 ld r4, VCPU_GPR(R4)(r4)
1130 * Use UV_RETURN ultracall to return control back to the Ultravisor after
1131 * processing an hypercall or interrupt that was forwarded (a.k.a. reflected)
1132 * to the Hypervisor.
1134 * All registers have already been loaded, except:
1136 * R2 = SRR1, so UV can detect a synthesized interrupt (if any)
1143 ld r0, VCPU_GPR(R3)(r4)
1146 ori r3, r3, UV_RETURN
1147 ld r4, VCPU_GPR(R4)(r4)
1151 * Enter the guest on a P9 or later system where we have exactly
1152 * one vcpu per vcore and we don't need to go to real mode
1153 * (which implies that host and guest are both using radix MMU mode).
1155 * Most SPRs and all the VSRs have been loaded already.
1157 _GLOBAL(__kvmhv_vcpu_entry_p9)
1158 EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9)
1160 std r0, PPC_LR_STKOFF(r1)
1164 stw r0, STACK_SLOT_SHORT_PATH(r1)
1166 std r3, HSTATE_KVM_VCPU(r13)
1170 std r1, HSTATE_HOST_R1(r13)
1174 std reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1180 ld reg, __VCPU_GPR(reg)(r3)
1185 std r10, HSTATE_HOST_MSR(r13)
1188 b fast_guest_entry_c
1189 guest_exit_short_path:
1191 li r0, KVM_GUEST_MODE_NONE
1192 stb r0, HSTATE_IN_GUEST(r13)
1196 std reg, __VCPU_GPR(reg)(r9)
1202 ld reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1209 mr r3, r12 /* trap number */
1212 ld r0, PPC_LR_STKOFF(r1)
1215 /* If we are in real mode, do a rfid to get back to the caller */
1217 andi. r5, r4, MSR_IR
1219 rldicl r5, r4, 64 - MSR_TS_S_LG, 62 /* extract TS field */
1221 ld r10, HSTATE_HOST_MSR(r13)
1222 rldimi r10, r5, MSR_TS_S_LG, 63 - MSR_TS_T_LG
1223 mtspr SPRN_SRR1, r10
1229 stw r12, STACK_SLOT_TRAP(r1)
1232 stw r12, VCPU_TRAP(r4)
1233 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1234 addi r3, r4, VCPU_TB_RMEXIT
1235 bl kvmhv_accumulate_time
1237 11: b kvmhv_switch_to_host
1244 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1245 12: stw r12, VCPU_TRAP(r4)
1247 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1248 addi r3, r4, VCPU_TB_RMEXIT
1249 bl kvmhv_accumulate_time
1253 /******************************************************************************
1257 *****************************************************************************/
1260 * We come here from the first-level interrupt handlers.
1262 .globl kvmppc_interrupt_hv
1263 kvmppc_interrupt_hv:
1265 * Register contents:
1266 * R12 = (guest CR << 32) | interrupt vector
1268 * guest R12 saved in shadow VCPU SCRATCH0
1269 * guest R13 saved in SPRN_SCRATCH0
1271 std r9, HSTATE_SCRATCH2(r13)
1272 lbz r9, HSTATE_IN_GUEST(r13)
1273 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1274 beq kvmppc_bad_host_intr
1275 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1276 cmpwi r9, KVM_GUEST_MODE_GUEST
1277 ld r9, HSTATE_SCRATCH2(r13)
1278 beq kvmppc_interrupt_pr
1280 /* We're now back in the host but in guest MMU context */
1281 li r9, KVM_GUEST_MODE_HOST_HV
1282 stb r9, HSTATE_IN_GUEST(r13)
1284 ld r9, HSTATE_KVM_VCPU(r13)
1286 /* Save registers */
1288 std r0, VCPU_GPR(R0)(r9)
1289 std r1, VCPU_GPR(R1)(r9)
1290 std r2, VCPU_GPR(R2)(r9)
1291 std r3, VCPU_GPR(R3)(r9)
1292 std r4, VCPU_GPR(R4)(r9)
1293 std r5, VCPU_GPR(R5)(r9)
1294 std r6, VCPU_GPR(R6)(r9)
1295 std r7, VCPU_GPR(R7)(r9)
1296 std r8, VCPU_GPR(R8)(r9)
1297 ld r0, HSTATE_SCRATCH2(r13)
1298 std r0, VCPU_GPR(R9)(r9)
1299 std r10, VCPU_GPR(R10)(r9)
1300 std r11, VCPU_GPR(R11)(r9)
1301 ld r3, HSTATE_SCRATCH0(r13)
1302 std r3, VCPU_GPR(R12)(r9)
1303 /* CR is in the high half of r12 */
1307 ld r3, HSTATE_CFAR(r13)
1308 std r3, VCPU_CFAR(r9)
1309 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1311 ld r4, HSTATE_PPR(r13)
1312 std r4, VCPU_PPR(r9)
1313 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1315 /* Restore R1/R2 so we can handle faults */
1316 ld r1, HSTATE_HOST_R1(r13)
1319 mfspr r10, SPRN_SRR0
1320 mfspr r11, SPRN_SRR1
1321 std r10, VCPU_SRR0(r9)
1322 std r11, VCPU_SRR1(r9)
1323 /* trap is in the low half of r12, clear CR from the high half */
1325 andi. r0, r12, 2 /* need to read HSRR0/1? */
1327 mfspr r10, SPRN_HSRR0
1328 mfspr r11, SPRN_HSRR1
1330 1: std r10, VCPU_PC(r9)
1331 std r11, VCPU_MSR(r9)
1335 std r3, VCPU_GPR(R13)(r9)
1338 stw r12,VCPU_TRAP(r9)
1341 * Now that we have saved away SRR0/1 and HSRR0/1,
1342 * interrupts are recoverable in principle, so set MSR_RI.
1343 * This becomes important for relocation-on interrupts from
1344 * the guest, which we can get in radix mode on POWER9.
1349 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1350 addi r3, r9, VCPU_TB_RMINTR
1352 bl kvmhv_accumulate_time
1353 ld r5, VCPU_GPR(R5)(r9)
1354 ld r6, VCPU_GPR(R6)(r9)
1355 ld r7, VCPU_GPR(R7)(r9)
1356 ld r8, VCPU_GPR(R8)(r9)
1359 /* Save HEIR (HV emulation assist reg) in emul_inst
1360 if this is an HEI (HV emulation interrupt, e40) */
1361 li r3,KVM_INST_FETCH_FAILED
1362 stw r3,VCPU_LAST_INST(r9)
1363 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1366 11: stw r3,VCPU_HEIR(r9)
1368 /* these are volatile across C function calls */
1371 std r3, VCPU_CTR(r9)
1372 std r4, VCPU_XER(r9)
1374 /* Save more register state */
1377 std r3, VCPU_DAR(r9)
1378 stw r4, VCPU_DSISR(r9)
1380 /* If this is a page table miss then see if it's theirs or ours */
1381 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1383 std r3, VCPU_FAULT_DAR(r9)
1384 stw r4, VCPU_FAULT_DSISR(r9)
1385 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1388 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1389 /* For softpatch interrupt, go off and do TM instruction emulation */
1390 cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
1394 /* See if this is a leftover HDEC interrupt */
1395 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1401 bge fast_guest_return
1403 /* See if this is an hcall we can handle in real mode */
1404 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1405 beq hcall_try_real_mode
1407 /* Hypervisor doorbell - exit only if host IPI flag set */
1408 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1413 /* always exit if we're running a nested guest */
1414 ld r0, VCPU_NESTED(r9)
1417 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1418 lbz r0, HSTATE_HOST_IPI(r13)
1420 beq maybe_reenter_guest
1423 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1424 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1426 mfspr r3, SPRN_HFSCR
1427 std r3, VCPU_HFSCR(r9)
1430 /* External interrupt ? */
1431 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1432 beq kvmppc_guest_external
1433 /* See if it is a machine check */
1434 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1435 beq machine_check_realmode
1436 /* Or a hypervisor maintenance interrupt */
1437 cmpwi r12, BOOK3S_INTERRUPT_HMI
1440 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1442 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1443 addi r3, r9, VCPU_TB_RMEXIT
1445 bl kvmhv_accumulate_time
1447 #ifdef CONFIG_KVM_XICS
1448 /* We are exiting, pull the VP from the XIVE */
1449 lbz r0, VCPU_XIVE_PUSHED(r9)
1452 li r7, TM_SPC_PULL_OS_CTX
1455 andi. r0, r0, MSR_DR /* in real mode? */
1457 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1460 /* First load to pull the context, we ignore the value */
1463 /* Second load to recover the context state (Words 0 and 1) */
1466 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1469 /* First load to pull the context, we ignore the value */
1472 /* Second load to recover the context state (Words 0 and 1) */
1474 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1475 /* Fixup some of the state for the next load */
1478 stb r10, VCPU_XIVE_PUSHED(r9)
1479 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1480 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1483 #endif /* CONFIG_KVM_XICS */
1486 * Possibly flush the link stack here, before we do a blr in
1487 * guest_exit_short_path.
1490 patch_site 1b patch__call_kvm_flush_link_stack
1492 /* If we came in through the P9 short path, go back out to C now */
1493 lwz r0, STACK_SLOT_SHORT_PATH(r1)
1495 bne guest_exit_short_path
1497 /* For hash guest, read the guest SLB and save it away */
1499 lbz r0, KVM_RADIX(r5)
1502 bne 3f /* for radix, save 0 entries */
1503 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1508 andis. r0,r8,SLB_ESID_V@h
1510 add r8,r8,r6 /* put index in */
1512 std r8,VCPU_SLB_E(r7)
1513 std r3,VCPU_SLB_V(r7)
1514 addi r7,r7,VCPU_SLB_SIZE
1518 /* Finally clear out the SLB */
1523 3: stw r5,VCPU_SLB_MAX(r9)
1525 /* load host SLB entries */
1526 BEGIN_MMU_FTR_SECTION
1528 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1529 ld r8,PACA_SLBSHADOWPTR(r13)
1531 .rept SLB_NUM_BOLTED
1532 li r3, SLBSHADOW_SAVEAREA
1536 andis. r7,r5,SLB_ESID_V@h
1544 stw r12, STACK_SLOT_TRAP(r1)
1547 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1548 ld r3, HSTATE_KVM_VCORE(r13)
1551 /* On P9, if the guest has large decr enabled, don't sign extend */
1553 ld r4, VCORE_LPCR(r3)
1554 andis. r4, r4, LPCR_LD@h
1556 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1559 /* r5 is a guest timebase value here, convert to host TB */
1560 ld r4,VCORE_TB_OFFSET_APPL(r3)
1562 std r5,VCPU_DEC_EXPIRES(r9)
1564 /* Increment exit count, poke other threads to exit */
1566 bl kvmhv_commence_exit
1568 ld r9, HSTATE_KVM_VCPU(r13)
1570 /* Stop others sending VCPU interrupts to this physical CPU */
1572 stw r0, VCPU_CPU(r9)
1573 stw r0, VCPU_THREAD_CPU(r9)
1575 /* Save guest CTRL register, set runlatch to 1 */
1577 stw r6,VCPU_CTRL(r9)
1584 * Save the guest PURR/SPURR
1589 ld r8,VCPU_SPURR(r9)
1590 std r5,VCPU_PURR(r9)
1591 std r6,VCPU_SPURR(r9)
1596 * Restore host PURR/SPURR and add guest times
1597 * so that the time in the guest gets accounted.
1599 ld r3,HSTATE_PURR(r13)
1600 ld r4,HSTATE_SPURR(r13)
1608 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1609 /* Save POWER8-specific registers */
1613 std r5, VCPU_IAMR(r9)
1614 stw r6, VCPU_PSPB(r9)
1615 std r7, VCPU_FSCR(r9)
1619 std r7, VCPU_TAR(r9)
1620 mfspr r8, SPRN_EBBHR
1621 std r8, VCPU_EBBHR(r9)
1622 mfspr r5, SPRN_EBBRR
1623 mfspr r6, SPRN_BESCR
1626 std r5, VCPU_EBBRR(r9)
1627 std r6, VCPU_BESCR(r9)
1628 stw r7, VCPU_GUEST_PID(r9)
1629 std r8, VCPU_WORT(r9)
1631 mfspr r5, SPRN_TCSCR
1633 mfspr r7, SPRN_CSIGR
1635 std r5, VCPU_TCSCR(r9)
1636 std r6, VCPU_ACOP(r9)
1637 std r7, VCPU_CSIGR(r9)
1638 std r8, VCPU_TACR(r9)
1641 mfspr r6, SPRN_PSSCR
1642 std r5, VCPU_TID(r9)
1643 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1645 std r6, VCPU_PSSCR(r9)
1646 /* Restore host HFSCR value */
1647 ld r7, STACK_SLOT_HFSCR(r1)
1648 mtspr SPRN_HFSCR, r7
1649 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1651 * Restore various registers to 0, where non-zero values
1652 * set by the guest could disrupt the host.
1658 mtspr SPRN_TCSCR, r0
1659 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1662 mtspr SPRN_MMCRS, r0
1663 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1665 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1666 ld r8, STACK_SLOT_IAMR(r1)
1669 8: /* Power7 jumps back in here */
1673 std r6,VCPU_UAMOR(r9)
1674 ld r5,STACK_SLOT_AMR(r1)
1675 ld r6,STACK_SLOT_UAMOR(r1)
1677 mtspr SPRN_UAMOR, r6
1679 /* Switch DSCR back to host value */
1681 ld r7, HSTATE_DSCR(r13)
1682 std r8, VCPU_DSCR(r9)
1685 /* Save non-volatile GPRs */
1686 std r14, VCPU_GPR(R14)(r9)
1687 std r15, VCPU_GPR(R15)(r9)
1688 std r16, VCPU_GPR(R16)(r9)
1689 std r17, VCPU_GPR(R17)(r9)
1690 std r18, VCPU_GPR(R18)(r9)
1691 std r19, VCPU_GPR(R19)(r9)
1692 std r20, VCPU_GPR(R20)(r9)
1693 std r21, VCPU_GPR(R21)(r9)
1694 std r22, VCPU_GPR(R22)(r9)
1695 std r23, VCPU_GPR(R23)(r9)
1696 std r24, VCPU_GPR(R24)(r9)
1697 std r25, VCPU_GPR(R25)(r9)
1698 std r26, VCPU_GPR(R26)(r9)
1699 std r27, VCPU_GPR(R27)(r9)
1700 std r28, VCPU_GPR(R28)(r9)
1701 std r29, VCPU_GPR(R29)(r9)
1702 std r30, VCPU_GPR(R30)(r9)
1703 std r31, VCPU_GPR(R31)(r9)
1706 mfspr r3, SPRN_SPRG0
1707 mfspr r4, SPRN_SPRG1
1708 mfspr r5, SPRN_SPRG2
1709 mfspr r6, SPRN_SPRG3
1710 std r3, VCPU_SPRG0(r9)
1711 std r4, VCPU_SPRG1(r9)
1712 std r5, VCPU_SPRG2(r9)
1713 std r6, VCPU_SPRG3(r9)
1719 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1721 * Branch around the call if both CPU_FTR_TM and
1722 * CPU_FTR_P9_TM_HV_ASSIST are off.
1726 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
1728 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1732 li r5, 0 /* don't preserve non-vol regs */
1733 bl kvmppc_save_tm_hv
1735 ld r9, HSTATE_KVM_VCPU(r13)
1739 /* Increment yield count if they have a VPA */
1740 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1743 li r4, LPPACA_YIELDCOUNT
1748 stb r3, VCPU_VPA_DIRTY(r9)
1750 /* Save PMU registers if requested */
1751 /* r8 and cr0.eq are live here */
1754 beq 21f /* if no VPA, save PMU stuff anyway */
1755 lbz r4, LPPACA_PMCINUSE(r8)
1756 21: bl kvmhv_save_guest_pmu
1757 ld r9, HSTATE_KVM_VCPU(r13)
1759 /* Restore host values of some registers */
1761 ld r5, STACK_SLOT_CIABR(r1)
1762 ld r6, STACK_SLOT_DAWR(r1)
1763 ld r7, STACK_SLOT_DAWRX(r1)
1764 mtspr SPRN_CIABR, r5
1766 * If the DAWR doesn't work, it's ok to write these here as
1767 * this value should always be zero
1769 mtspr SPRN_DAWR0, r6
1770 mtspr SPRN_DAWRX0, r7
1771 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1773 ld r5, STACK_SLOT_TID(r1)
1774 ld r6, STACK_SLOT_PSSCR(r1)
1775 ld r7, STACK_SLOT_PID(r1)
1777 mtspr SPRN_PSSCR, r6
1779 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1781 #ifdef CONFIG_PPC_RADIX_MMU
1783 * Are we running hash or radix ?
1786 lbz r0, KVM_RADIX(r5)
1791 * Radix: do eieio; tlbsync; ptesync sequence in case we
1792 * interrupted the guest between a tlbie and a ptesync.
1799 /* Radix: Handle the case where the guest used an illegal PID */
1800 LOAD_REG_ADDR(r4, mmu_base_pid)
1801 lwz r3, VCPU_GUEST_PID(r9)
1807 * Illegal PID, the HW might have prefetched and cached in the TLB
1808 * some translations for the LPID 0 / guest PID combination which
1809 * Linux doesn't know about, so we need to flush that PID out of
1810 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1811 * the right context.
1817 /* Then do a congruence class local flush */
1819 lwz r0,KVM_TLB_SETS(r6)
1821 li r7,0x400 /* IS field = 0b01 */
1823 sldi r0,r3,32 /* RS has PID */
1824 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1828 END_FTR_SECTION_IFSET(CPU_FTR_P9_RADIX_PREFETCH_BUG)
1831 #endif /* CONFIG_PPC_RADIX_MMU */
1834 * cp_abort is required if the processor supports local copy-paste
1835 * to clear the copy buffer that was under control of the guest.
1839 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
1842 * POWER7/POWER8 guest -> host partition switch code.
1843 * We don't have to lock against tlbies but we do
1844 * have to coordinate the hardware threads.
1845 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1847 kvmhv_switch_to_host:
1848 /* Secondary threads wait for primary to do partition switch */
1849 ld r5,HSTATE_KVM_VCORE(r13)
1850 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1851 lbz r3,HSTATE_PTID(r13)
1855 13: lbz r3,VCORE_IN_GUEST(r5)
1861 /* Primary thread waits for all the secondaries to exit guest */
1862 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1863 rlwinm r0,r3,32-8,0xff
1869 /* Did we actually switch to the guest at all? */
1870 lbz r6, VCORE_IN_GUEST(r5)
1874 /* Primary thread switches back to host partition */
1875 lwz r7,KVM_HOST_LPID(r4)
1877 ld r6,KVM_HOST_SDR1(r4)
1878 li r8,LPID_RSVD /* switch to reserved LPID */
1881 mtspr SPRN_SDR1,r6 /* switch to host page table */
1882 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1887 /* DPDES and VTB are shared between threads */
1888 mfspr r7, SPRN_DPDES
1890 std r7, VCORE_DPDES(r5)
1891 std r8, VCORE_VTB(r5)
1892 /* clear DPDES so we don't get guest doorbells in the host */
1894 mtspr SPRN_DPDES, r8
1895 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1897 /* Subtract timebase offset from timebase */
1898 ld r8, VCORE_TB_OFFSET_APPL(r5)
1902 std r0, VCORE_TB_OFFSET_APPL(r5)
1903 mftb r6 /* current guest timebase */
1905 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1906 mftb r7 /* check if lower 24 bits overflowed */
1911 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1916 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1917 * above, which may or may not have already called
1918 * kvmppc_subcore_exit_guest. Fortunately, all that
1919 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1920 * it again here is benign even if kvmppc_realmode_hmi_handler
1921 * has already called it.
1923 bl kvmppc_subcore_exit_guest
1925 30: ld r5,HSTATE_KVM_VCORE(r13)
1926 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1929 ld r0, VCORE_PCR(r5)
1930 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
1935 /* Signal secondary CPUs to continue */
1937 stb r0,VCORE_IN_GUEST(r5)
1938 19: lis r8,0x7fff /* MAX_INT@h */
1943 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
1944 ld r3, HSTATE_SPLIT_MODE(r13)
1947 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
1950 bl kvmhv_p9_restore_lpcr
1954 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1955 ld r8,KVM_HOST_LPCR(r4)
1959 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1960 /* Finish timing, if we have a vcpu */
1961 ld r4, HSTATE_KVM_VCPU(r13)
1965 bl kvmhv_accumulate_time
1968 /* Unset guest mode */
1969 li r0, KVM_GUEST_MODE_NONE
1970 stb r0, HSTATE_IN_GUEST(r13)
1972 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1973 ld r0, SFS+PPC_LR_STKOFF(r1)
1979 .global kvm_flush_link_stack
1980 kvm_flush_link_stack:
1981 /* Save LR into r0 */
1984 /* Flush the link stack. On Power8 it's up to 32 entries in size. */
1989 /* And on Power9 it's up to 64. */
1994 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2000 kvmppc_guest_external:
2001 /* External interrupt, first check for host_ipi. If this is
2002 * set, we know the host wants us out so let's do it now
2007 * Restore the active volatile registers after returning from
2010 ld r9, HSTATE_KVM_VCPU(r13)
2011 li r12, BOOK3S_INTERRUPT_EXTERNAL
2014 * kvmppc_read_intr return codes:
2016 * Exit to host (r3 > 0)
2017 * 1 An interrupt is pending that needs to be handled by the host
2018 * Exit guest and return to host by branching to guest_exit_cont
2020 * 2 Passthrough that needs completion in the host
2021 * Exit guest and return to host by branching to guest_exit_cont
2022 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
2023 * to indicate to the host to complete handling the interrupt
2025 * Before returning to guest, we check if any CPU is heading out
2026 * to the host and if so, we head out also. If no CPUs are heading
2027 * check return values <= 0.
2029 * Return to guest (r3 <= 0)
2030 * 0 No external interrupt is pending
2031 * -1 A guest wakeup IPI (which has now been cleared)
2032 * In either case, we return to guest to deliver any pending
2035 * -2 A PCI passthrough external interrupt was handled
2036 * (interrupt was delivered directly to guest)
2037 * Return to guest to deliver any pending guest interrupts.
2043 /* Return code = 2 */
2044 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2045 stw r12, VCPU_TRAP(r9)
2048 1: /* Return code <= 1 */
2052 /* Return code <= 0 */
2053 maybe_reenter_guest:
2054 ld r5, HSTATE_KVM_VCORE(r13)
2055 lwz r0, VCORE_ENTRY_EXIT(r5)
2058 blt deliver_guest_interrupt
2061 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2063 * Softpatch interrupt for transactional memory emulation cases
2064 * on POWER9 DD2.2. This is early in the guest exit path - we
2065 * haven't saved registers or done a treclaim yet.
2068 /* Save instruction image in HEIR */
2070 stw r3, VCPU_HEIR(r9)
2073 * The cases we want to handle here are those where the guest
2074 * is in real suspend mode and is trying to transition to
2075 * transactional mode.
2077 lbz r0, HSTATE_FAKE_SUSPEND(r13)
2078 cmpwi r0, 0 /* keep exiting guest if in fake suspend */
2080 rldicl r3, r11, 64 - MSR_TS_S_LG, 62
2081 cmpwi r3, 1 /* or if not in suspend state */
2084 /* Call C code to do the emulation */
2086 bl kvmhv_p9_tm_emulation_early
2088 ld r9, HSTATE_KVM_VCPU(r13)
2089 li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
2091 beq guest_exit_cont /* continue exiting if not handled */
2093 ld r11, VCPU_MSR(r9)
2094 b fast_interrupt_c_return /* go back to guest if handled */
2095 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2098 * Check whether an HDSI is an HPTE not found fault or something else.
2099 * If it is an HPTE not found fault that is due to the guest accessing
2100 * a page that they have mapped but which we have paged out, then
2101 * we continue on with the guest exit path. In all other cases,
2102 * reflect the HDSI to the guest as a DSI.
2106 lbz r0, KVM_RADIX(r3)
2108 mfspr r6, SPRN_HDSISR
2110 /* Look for DSISR canary. If we find it, retry instruction */
2113 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2115 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2116 /* HPTE not found fault or protection fault? */
2117 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2118 beq 1f /* if not, send it to the guest */
2119 andi. r0, r11, MSR_DR /* data relocation enabled? */
2122 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2124 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2126 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2127 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2128 bne 7f /* if no SLB entry found */
2129 4: std r4, VCPU_FAULT_DAR(r9)
2130 stw r6, VCPU_FAULT_DSISR(r9)
2132 /* Search the hash table. */
2133 mr r3, r9 /* vcpu pointer */
2134 li r7, 1 /* data fault */
2135 bl kvmppc_hpte_hv_fault
2136 ld r9, HSTATE_KVM_VCPU(r13)
2138 ld r11, VCPU_MSR(r9)
2139 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2140 cmpdi r3, 0 /* retry the instruction */
2142 cmpdi r3, -1 /* handle in kernel mode */
2144 cmpdi r3, -2 /* MMIO emulation; need instr word */
2147 /* Synthesize a DSI (or DSegI) for the guest */
2148 ld r4, VCPU_FAULT_DAR(r9)
2150 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2151 mtspr SPRN_DSISR, r6
2152 7: mtspr SPRN_DAR, r4
2153 mtspr SPRN_SRR0, r10
2154 mtspr SPRN_SRR1, r11
2156 bl kvmppc_msr_interrupt
2157 fast_interrupt_c_return:
2158 6: ld r7, VCPU_CTR(r9)
2165 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2166 ld r5, KVM_VRMA_SLB_V(r5)
2169 /* If this is for emulated MMIO, load the instruction word */
2170 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2172 /* Set guest mode to 'jump over instruction' so if lwz faults
2173 * we'll just continue at the next IP. */
2174 li r0, KVM_GUEST_MODE_SKIP
2175 stb r0, HSTATE_IN_GUEST(r13)
2177 /* Do the access with MSR:DR enabled */
2179 ori r4, r3, MSR_DR /* Enable paging for data */
2184 /* Store the result */
2185 stw r8, VCPU_LAST_INST(r9)
2187 /* Unset guest mode. */
2188 li r0, KVM_GUEST_MODE_HOST_HV
2189 stb r0, HSTATE_IN_GUEST(r13)
2193 std r4, VCPU_FAULT_DAR(r9)
2194 stw r6, VCPU_FAULT_DSISR(r9)
2197 std r5, VCPU_FAULT_GPA(r9)
2201 * Similarly for an HISI, reflect it to the guest as an ISI unless
2202 * it is an HPTE not found fault for a page that we have paged out.
2206 lbz r0, KVM_RADIX(r3)
2208 bne .Lradix_hisi /* for radix, just save ASDR */
2209 andis. r0, r11, SRR1_ISI_NOPT@h
2211 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2214 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2216 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2218 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2219 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2220 bne 7f /* if no SLB entry found */
2222 /* Search the hash table. */
2223 mr r3, r9 /* vcpu pointer */
2226 li r7, 0 /* instruction fault */
2227 bl kvmppc_hpte_hv_fault
2228 ld r9, HSTATE_KVM_VCPU(r13)
2230 ld r11, VCPU_MSR(r9)
2231 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2232 cmpdi r3, 0 /* retry the instruction */
2233 beq fast_interrupt_c_return
2234 cmpdi r3, -1 /* handle in kernel mode */
2237 /* Synthesize an ISI (or ISegI) for the guest */
2239 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2240 7: mtspr SPRN_SRR0, r10
2241 mtspr SPRN_SRR1, r11
2243 bl kvmppc_msr_interrupt
2244 b fast_interrupt_c_return
2246 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2247 ld r5, KVM_VRMA_SLB_V(r6)
2251 * Try to handle an hcall in real mode.
2252 * Returns to the guest if we handle it, or continues on up to
2253 * the kernel if we can't (i.e. if we don't have a handler for
2254 * it, or if the handler returns H_TOO_HARD).
2256 * r5 - r8 contain hcall args,
2257 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2259 hcall_try_real_mode:
2260 ld r3,VCPU_GPR(R3)(r9)
2262 /* sc 1 from userspace - reflect to guest syscall */
2263 bne sc_1_fast_return
2264 /* sc 1 from nested guest - give it to L1 to handle */
2265 ld r0, VCPU_NESTED(r9)
2269 cmpldi r3,hcall_real_table_end - hcall_real_table
2271 /* See if this hcall is enabled for in-kernel handling */
2273 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2274 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2276 ld r0, KVM_ENABLED_HCALLS(r4)
2277 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2281 /* Get pointer to handler, if any, and call it */
2282 LOAD_REG_ADDR(r4, hcall_real_table)
2288 mr r3,r9 /* get vcpu pointer */
2289 ld r4,VCPU_GPR(R4)(r9)
2292 beq hcall_real_fallback
2293 ld r4,HSTATE_KVM_VCPU(r13)
2294 std r3,VCPU_GPR(R3)(r4)
2302 li r10, BOOK3S_INTERRUPT_SYSCALL
2303 bl kvmppc_msr_interrupt
2307 /* We've attempted a real mode hcall, but it's punted it back
2308 * to userspace. We need to restore some clobbered volatiles
2309 * before resuming the pass-it-to-qemu path */
2310 hcall_real_fallback:
2311 li r12,BOOK3S_INTERRUPT_SYSCALL
2312 ld r9, HSTATE_KVM_VCPU(r13)
2316 .globl hcall_real_table
2318 .long 0 /* 0 - unused */
2319 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2320 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2321 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2322 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2323 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2324 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2325 #ifdef CONFIG_SPAPR_TCE_IOMMU
2326 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2327 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2332 .long 0 /* 0x24 - H_SET_SPRG0 */
2333 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2334 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
2348 #ifdef CONFIG_KVM_XICS
2349 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2350 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2351 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2352 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2353 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2355 .long 0 /* 0x64 - H_EOI */
2356 .long 0 /* 0x68 - H_CPPR */
2357 .long 0 /* 0x6c - H_IPI */
2358 .long 0 /* 0x70 - H_IPOLL */
2359 .long 0 /* 0x74 - H_XIRR */
2387 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2388 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2404 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2408 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2409 #ifdef CONFIG_SPAPR_TCE_IOMMU
2410 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2411 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2527 #ifdef CONFIG_KVM_XICS
2528 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2530 .long 0 /* 0x2fc - H_XIRR_X*/
2532 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2533 .globl hcall_real_table_end
2534 hcall_real_table_end:
2536 _GLOBAL(kvmppc_h_set_xdabr)
2537 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2538 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2540 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2543 6: li r3, H_PARAMETER
2546 _GLOBAL(kvmppc_h_set_dabr)
2547 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2548 li r5, DABRX_USER | DABRX_KERNEL
2552 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2553 std r4,VCPU_DABR(r3)
2554 stw r5, VCPU_DABRX(r3)
2555 mtspr SPRN_DABRX, r5
2556 /* Work around P7 bug where DABR can get corrupted on mtspr */
2557 1: mtspr SPRN_DABR,r4
2566 LOAD_REG_ADDR(r11, dawr_force_enable)
2573 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2574 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2575 rlwimi r5, r4, 2, DAWRX_WT
2577 std r4, VCPU_DAWR(r3)
2578 std r5, VCPU_DAWRX(r3)
2580 * If came in through the real mode hcall handler then it is necessary
2581 * to write the registers since the return path won't. Otherwise it is
2582 * sufficient to store then in the vcpu struct as they will be loaded
2583 * next time the vcpu is run.
2586 andi. r6, r6, MSR_DR /* in real mode? */
2588 mtspr SPRN_DAWR0, r4
2589 mtspr SPRN_DAWRX0, r5
2593 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2595 std r11,VCPU_MSR(r3)
2597 stb r0,VCPU_CEDED(r3)
2598 sync /* order setting ceded vs. testing prodded */
2599 lbz r5,VCPU_PRODDED(r3)
2601 bne kvm_cede_prodded
2602 li r12,0 /* set trap to 0 to say hcall is handled */
2603 stw r12,VCPU_TRAP(r3)
2605 std r0,VCPU_GPR(R3)(r3)
2608 * Set our bit in the bitmask of napping threads unless all the
2609 * other threads are already napping, in which case we send this
2612 ld r5,HSTATE_KVM_VCORE(r13)
2613 lbz r6,HSTATE_PTID(r13)
2614 lwz r8,VCORE_ENTRY_EXIT(r5)
2618 addi r6,r5,VCORE_NAPPING_THREADS
2625 /* order napping_threads update vs testing entry_exit_map */
2628 stb r0,HSTATE_NAPPING(r13)
2629 lwz r7,VCORE_ENTRY_EXIT(r5)
2631 bge 33f /* another thread already exiting */
2634 * Although not specifically required by the architecture, POWER7
2635 * preserves the following registers in nap mode, even if an SMT mode
2636 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2637 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2639 /* Save non-volatile GPRs */
2640 std r14, VCPU_GPR(R14)(r3)
2641 std r15, VCPU_GPR(R15)(r3)
2642 std r16, VCPU_GPR(R16)(r3)
2643 std r17, VCPU_GPR(R17)(r3)
2644 std r18, VCPU_GPR(R18)(r3)
2645 std r19, VCPU_GPR(R19)(r3)
2646 std r20, VCPU_GPR(R20)(r3)
2647 std r21, VCPU_GPR(R21)(r3)
2648 std r22, VCPU_GPR(R22)(r3)
2649 std r23, VCPU_GPR(R23)(r3)
2650 std r24, VCPU_GPR(R24)(r3)
2651 std r25, VCPU_GPR(R25)(r3)
2652 std r26, VCPU_GPR(R26)(r3)
2653 std r27, VCPU_GPR(R27)(r3)
2654 std r28, VCPU_GPR(R28)(r3)
2655 std r29, VCPU_GPR(R29)(r3)
2656 std r30, VCPU_GPR(R30)(r3)
2657 std r31, VCPU_GPR(R31)(r3)
2662 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2664 * Branch around the call if both CPU_FTR_TM and
2665 * CPU_FTR_P9_TM_HV_ASSIST are off.
2669 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2671 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2673 ld r3, HSTATE_KVM_VCPU(r13)
2675 li r5, 0 /* don't preserve non-vol regs */
2676 bl kvmppc_save_tm_hv
2682 * Set DEC to the smaller of DEC and HDEC, so that we wake
2683 * no later than the end of our timeslice (HDEC interrupts
2684 * don't wake us from nap).
2690 /* On P9 check whether the guest has large decrementer mode enabled */
2691 ld r6, HSTATE_KVM_VCORE(r13)
2692 ld r6, VCORE_LPCR(r6)
2693 andis. r6, r6, LPCR_LD@h
2695 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2702 /* save expiry time of guest decrementer */
2704 ld r4, HSTATE_KVM_VCPU(r13)
2705 ld r5, HSTATE_KVM_VCORE(r13)
2706 ld r6, VCORE_TB_OFFSET_APPL(r5)
2707 subf r3, r6, r3 /* convert to host TB value */
2708 std r3, VCPU_DEC_EXPIRES(r4)
2710 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2711 ld r4, HSTATE_KVM_VCPU(r13)
2712 addi r3, r4, VCPU_TB_CEDE
2713 bl kvmhv_accumulate_time
2716 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2718 /* Go back to host stack */
2719 ld r1, HSTATE_HOST_R1(r13)
2722 * Take a nap until a decrementer or external or doobell interrupt
2723 * occurs, with PECE1 and PECE0 set in LPCR.
2724 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2725 * Also clear the runlatch bit before napping.
2728 mfspr r0, SPRN_CTRLF
2730 mtspr SPRN_CTRLT, r0
2733 stb r0,HSTATE_HWTHREAD_REQ(r13)
2735 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2737 ori r5, r5, LPCR_PECEDH
2738 rlwimi r5, r3, 0, LPCR_PECEDP
2739 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2741 kvm_nap_sequence: /* desired LPCR value in r5 */
2744 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2745 * enable state loss = 1 (allow SMT mode switch)
2746 * requested level = 0 (just stop dispatching)
2748 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2749 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2750 li r4, LPCR_PECE_HVEE@higher
2754 li r3, PNV_THREAD_NAP
2755 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2760 bl isa300_idle_stop_mayloss
2762 bl isa206_idle_insn_mayloss
2763 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2765 mfspr r0, SPRN_CTRLF
2767 mtspr SPRN_CTRLT, r0
2772 stb r0, PACA_FTRACE_ENABLED(r13)
2774 li r0, KVM_HWTHREAD_IN_KVM
2775 stb r0, HSTATE_HWTHREAD_STATE(r13)
2777 lbz r0, HSTATE_NAPPING(r13)
2778 cmpwi r0, NAPPING_CEDE
2780 cmpwi r0, NAPPING_NOVCPU
2781 beq kvm_novcpu_wakeup
2782 cmpwi r0, NAPPING_UNSPLIT
2783 beq kvm_unsplit_wakeup
2784 twi 31,0,0 /* Nap state must not be zero */
2792 /* Woken by external or decrementer interrupt */
2794 /* get vcpu pointer */
2795 ld r4, HSTATE_KVM_VCPU(r13)
2797 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2798 addi r3, r4, VCPU_TB_RMINTR
2799 bl kvmhv_accumulate_time
2802 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2804 * Branch around the call if both CPU_FTR_TM and
2805 * CPU_FTR_P9_TM_HV_ASSIST are off.
2809 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2811 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2815 li r5, 0 /* don't preserve non-vol regs */
2816 bl kvmppc_restore_tm_hv
2818 ld r4, HSTATE_KVM_VCPU(r13)
2822 /* load up FP state */
2825 /* Restore guest decrementer */
2826 ld r3, VCPU_DEC_EXPIRES(r4)
2827 ld r5, HSTATE_KVM_VCORE(r13)
2828 ld r6, VCORE_TB_OFFSET_APPL(r5)
2829 add r3, r3, r6 /* convert host TB to guest TB value */
2835 ld r14, VCPU_GPR(R14)(r4)
2836 ld r15, VCPU_GPR(R15)(r4)
2837 ld r16, VCPU_GPR(R16)(r4)
2838 ld r17, VCPU_GPR(R17)(r4)
2839 ld r18, VCPU_GPR(R18)(r4)
2840 ld r19, VCPU_GPR(R19)(r4)
2841 ld r20, VCPU_GPR(R20)(r4)
2842 ld r21, VCPU_GPR(R21)(r4)
2843 ld r22, VCPU_GPR(R22)(r4)
2844 ld r23, VCPU_GPR(R23)(r4)
2845 ld r24, VCPU_GPR(R24)(r4)
2846 ld r25, VCPU_GPR(R25)(r4)
2847 ld r26, VCPU_GPR(R26)(r4)
2848 ld r27, VCPU_GPR(R27)(r4)
2849 ld r28, VCPU_GPR(R28)(r4)
2850 ld r29, VCPU_GPR(R29)(r4)
2851 ld r30, VCPU_GPR(R30)(r4)
2852 ld r31, VCPU_GPR(R31)(r4)
2854 /* Check the wake reason in SRR1 to see why we got here */
2855 bl kvmppc_check_wake_reason
2858 * Restore volatile registers since we could have called a
2859 * C routine in kvmppc_check_wake_reason
2861 * r3 tells us whether we need to return to host or not
2862 * WARNING: it gets checked further down:
2863 * should not modify r3 until this check is done.
2865 ld r4, HSTATE_KVM_VCPU(r13)
2867 /* clear our bit in vcore->napping_threads */
2868 34: ld r5,HSTATE_KVM_VCORE(r13)
2869 lbz r7,HSTATE_PTID(r13)
2872 addi r6,r5,VCORE_NAPPING_THREADS
2878 stb r0,HSTATE_NAPPING(r13)
2880 /* See if the wake reason saved in r3 means we need to exit */
2881 stw r12, VCPU_TRAP(r4)
2885 b maybe_reenter_guest
2887 /* cede when already previously prodded case */
2890 stb r0,VCPU_PRODDED(r3)
2891 sync /* order testing prodded vs. clearing ceded */
2892 stb r0,VCPU_CEDED(r3)
2896 /* we've ceded but we want to give control to the host */
2898 ld r9, HSTATE_KVM_VCPU(r13)
2899 #ifdef CONFIG_KVM_XICS
2900 /* are we using XIVE with single escalation? */
2901 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2904 li r6, XIVE_ESB_SET_PQ_00
2906 * If we still have a pending escalation, abort the cede,
2907 * and we must set PQ to 10 rather than 00 so that we don't
2908 * potentially end up with two entries for the escalation
2909 * interrupt in the XIVE interrupt queue. In that case
2910 * we also don't want to set xive_esc_on to 1 here in
2911 * case we race with xive_esc_irq().
2913 lbz r5, VCPU_XIVE_ESC_ON(r9)
2917 stb r0, VCPU_CEDED(r9)
2919 * The escalation interrupts are special as we don't EOI them.
2920 * There is no need to use the load-after-store ordering offset
2921 * to set PQ to 10 as we won't use StoreEOI.
2923 li r6, XIVE_ESB_SET_PQ_10
2926 stb r0, VCPU_XIVE_ESC_ON(r9)
2927 /* make sure store to xive_esc_on is seen before xive_esc_irq runs */
2929 5: /* Enable XIVE escalation */
2931 andi. r0, r0, MSR_DR /* in real mode? */
2935 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2938 #endif /* CONFIG_KVM_XICS */
2939 3: b guest_exit_cont
2941 /* Try to do machine check recovery in real mode */
2942 machine_check_realmode:
2943 mr r3, r9 /* get vcpu pointer */
2944 bl kvmppc_realmode_machine_check
2946 /* all machine checks go to virtual mode for further handling */
2947 ld r9, HSTATE_KVM_VCPU(r13)
2948 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2952 * Call C code to handle a HMI in real mode.
2953 * Only the primary thread does the call, secondary threads are handled
2954 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2955 * r9 points to the vcpu on entry
2958 lbz r0, HSTATE_PTID(r13)
2961 bl kvmppc_realmode_hmi_handler
2962 ld r9, HSTATE_KVM_VCPU(r13)
2963 li r12, BOOK3S_INTERRUPT_HMI
2967 * Check the reason we woke from nap, and take appropriate action.
2969 * 0 if nothing needs to be done
2970 * 1 if something happened that needs to be handled by the host
2971 * -1 if there was a guest wakeup (IPI or msgsnd)
2972 * -2 if we handled a PCI passthrough interrupt (returned by
2973 * kvmppc_read_intr only)
2975 * Also sets r12 to the interrupt vector for any interrupt that needs
2976 * to be handled now by the host (0x500 for external interrupt), or zero.
2977 * Modifies all volatile registers (since it may call a C function).
2978 * This routine calls kvmppc_read_intr, a C function, if an external
2979 * interrupt is pending.
2981 kvmppc_check_wake_reason:
2984 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2986 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2987 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2988 cmpwi r6, 8 /* was it an external interrupt? */
2989 beq 7f /* if so, see what it was */
2992 cmpwi r6, 6 /* was it the decrementer? */
2995 cmpwi r6, 5 /* privileged doorbell? */
2997 cmpwi r6, 3 /* hypervisor doorbell? */
2999 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3000 cmpwi r6, 0xa /* Hypervisor maintenance ? */
3002 li r3, 1 /* anything else, return 1 */
3005 /* hypervisor doorbell */
3006 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
3009 * Clear the doorbell as we will invoke the handler
3010 * explicitly in the guest exit path.
3012 lis r6, (PPC_DBELL_SERVER << (63-36))@h
3014 /* see if it's a host IPI */
3019 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
3020 lbz r0, HSTATE_HOST_IPI(r13)
3023 /* if not, return -1 */
3027 /* Woken up due to Hypervisor maintenance interrupt */
3028 4: li r12, BOOK3S_INTERRUPT_HMI
3032 /* external interrupt - create a stack frame so we can call C */
3034 std r0, PPC_LR_STKOFF(r1)
3035 stdu r1, -PPC_MIN_STKFRM(r1)
3038 li r12, BOOK3S_INTERRUPT_EXTERNAL
3043 * Return code of 2 means PCI passthrough interrupt, but
3044 * we need to return back to host to complete handling the
3045 * interrupt. Trap reason is expected in r12 by guest
3048 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
3050 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
3051 addi r1, r1, PPC_MIN_STKFRM
3056 * Save away FP, VMX and VSX registers.
3058 * N.B. r30 and r31 are volatile across this function,
3059 * thus it is not callable from C.
3066 #ifdef CONFIG_ALTIVEC
3068 oris r8,r8,MSR_VEC@h
3069 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3073 oris r8,r8,MSR_VSX@h
3074 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3077 addi r3,r3,VCPU_FPRS
3079 #ifdef CONFIG_ALTIVEC
3081 addi r3,r31,VCPU_VRS
3083 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3085 mfspr r6,SPRN_VRSAVE
3086 stw r6,VCPU_VRSAVE(r31)
3091 * Load up FP, VMX and VSX registers
3093 * N.B. r30 and r31 are volatile across this function,
3094 * thus it is not callable from C.
3101 #ifdef CONFIG_ALTIVEC
3103 oris r8,r8,MSR_VEC@h
3104 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3108 oris r8,r8,MSR_VSX@h
3109 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3112 addi r3,r4,VCPU_FPRS
3114 #ifdef CONFIG_ALTIVEC
3116 addi r3,r31,VCPU_VRS
3118 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3120 lwz r7,VCPU_VRSAVE(r31)
3121 mtspr SPRN_VRSAVE,r7
3126 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3128 * Save transactional state and TM-related registers.
3129 * Called with r3 pointing to the vcpu struct and r4 containing
3130 * the guest MSR value.
3131 * r5 is non-zero iff non-volatile register state needs to be maintained.
3132 * If r5 == 0, this can modify all checkpointed registers, but
3133 * restores r1 and r2 before exit.
3135 _GLOBAL_TOC(kvmppc_save_tm_hv)
3136 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
3137 /* See if we need to handle fake suspend mode */
3140 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3142 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3144 beq __kvmppc_save_tm
3146 /* The following code handles the fake_suspend = 1 case */
3148 std r0, PPC_LR_STKOFF(r1)
3149 stdu r1, -PPC_MIN_STKFRM(r1)
3154 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3157 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3160 bl pnv_power9_force_smt4_catch
3161 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3164 /* We have to treclaim here because that's the only way to do S->N */
3165 li r3, TM_CAUSE_KVM_RESCHED
3169 * We were in fake suspend, so we are not going to save the
3170 * register state as the guest checkpointed state (since
3171 * we already have it), therefore we can now use any volatile GPR.
3172 * In fact treclaim in fake suspend state doesn't modify
3177 bl pnv_power9_force_smt4_release
3178 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3182 mfspr r3, SPRN_PSSCR
3183 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
3184 li r0, PSSCR_FAKE_SUSPEND
3186 mtspr SPRN_PSSCR, r3
3188 /* Don't save TEXASR, use value from last exit in real suspend state */
3189 ld r9, HSTATE_KVM_VCPU(r13)
3190 mfspr r5, SPRN_TFHAR
3191 mfspr r6, SPRN_TFIAR
3192 std r5, VCPU_TFHAR(r9)
3193 std r6, VCPU_TFIAR(r9)
3195 addi r1, r1, PPC_MIN_STKFRM
3196 ld r0, PPC_LR_STKOFF(r1)
3201 * Restore transactional state and TM-related registers.
3202 * Called with r3 pointing to the vcpu struct
3203 * and r4 containing the guest MSR value.
3204 * r5 is non-zero iff non-volatile register state needs to be maintained.
3205 * This potentially modifies all checkpointed registers.
3206 * It restores r1 and r2 from the PACA.
3208 _GLOBAL_TOC(kvmppc_restore_tm_hv)
3209 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
3211 * If we are doing TM emulation for the guest on a POWER9 DD2,
3212 * then we don't actually do a trechkpt -- we either set up
3213 * fake-suspend mode, or emulate a TM rollback.
3216 b __kvmppc_restore_tm
3217 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3219 std r0, PPC_LR_STKOFF(r1)
3222 stb r0, HSTATE_FAKE_SUSPEND(r13)
3224 /* Turn on TM so we can restore TM SPRs */
3227 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
3231 * The user may change these outside of a transaction, so they must
3232 * always be context switched.
3234 ld r5, VCPU_TFHAR(r3)
3235 ld r6, VCPU_TFIAR(r3)
3236 ld r7, VCPU_TEXASR(r3)
3237 mtspr SPRN_TFHAR, r5
3238 mtspr SPRN_TFIAR, r6
3239 mtspr SPRN_TEXASR, r7
3241 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
3242 beqlr /* TM not active in guest */
3244 /* Make sure the failure summary is set */
3245 oris r7, r7, (TEXASR_FS)@h
3246 mtspr SPRN_TEXASR, r7
3248 cmpwi r5, 1 /* check for suspended state */
3250 stb r5, HSTATE_FAKE_SUSPEND(r13)
3251 b 9f /* and return */
3252 10: stdu r1, -PPC_MIN_STKFRM(r1)
3253 /* guest is in transactional state, so simulate rollback */
3254 bl kvmhv_emulate_tm_rollback
3256 addi r1, r1, PPC_MIN_STKFRM
3257 9: ld r0, PPC_LR_STKOFF(r1)
3260 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
3263 * We come here if we get any exception or interrupt while we are
3264 * executing host real mode code while in guest MMU context.
3265 * r12 is (CR << 32) | vector
3266 * r13 points to our PACA
3267 * r12 is saved in HSTATE_SCRATCH0(r13)
3268 * r9 is saved in HSTATE_SCRATCH2(r13)
3269 * r13 is saved in HSPRG1
3270 * cfar is saved in HSTATE_CFAR(r13)
3271 * ppr is saved in HSTATE_PPR(r13)
3273 kvmppc_bad_host_intr:
3275 * Switch to the emergency stack, but start half-way down in
3276 * case we were already on it.
3280 ld r1, PACAEMERGSP(r13)
3281 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3294 mfspr r3, SPRN_HSRR0
3295 mfspr r4, SPRN_HSRR1
3297 mfspr r6, SPRN_HDSISR
3299 1: mfspr r3, SPRN_SRR0
3302 mfspr r6, SPRN_DSISR
3307 ld r9, HSTATE_SCRATCH2(r13)
3308 ld r12, HSTATE_SCRATCH0(r13)
3313 ld r5, HSTATE_CFAR(r13)
3314 std r5, ORIG_GPR3(r1)
3318 lbz r6, PACAIRQSOFTMASK(r13)
3324 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3325 std r3, STACK_FRAME_OVERHEAD-16(r1)
3328 * On POWER9 do a minimal restore of the MMU and call C code,
3329 * which will print a message and panic.
3330 * XXX On POWER7 and POWER8, we just spin here since we don't
3331 * know what the other threads are doing (and we don't want to
3332 * coordinate with them) - but at least we now have register state
3333 * in memory that we might be able to look at from another CPU.
3337 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3338 ld r9, HSTATE_KVM_VCPU(r13)
3339 ld r10, VCPU_KVM(r9)
3344 mtspr SPRN_CIABR, r0
3345 mtspr SPRN_DAWRX0, r0
3347 BEGIN_MMU_FTR_SECTION
3349 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3354 ld r8, PACA_SLBSHADOWPTR(r13)
3355 .rept SLB_NUM_BOLTED
3356 li r3, SLBSHADOW_SAVEAREA
3360 andis. r7, r5, SLB_ESID_V@h
3366 4: lwz r7, KVM_HOST_LPID(r10)
3369 ld r8, KVM_HOST_LPCR(r10)
3372 li r0, KVM_GUEST_MODE_NONE
3373 stb r0, HSTATE_IN_GUEST(r13)
3376 * Turn on the MMU and jump to C code
3380 addi r3, r3, 9f - 5b
3382 rldimi r3, r4, 62, 0 /* ensure 0xc000000000000000 bits are set */
3383 ld r4, PACAKMSR(r13)
3387 9: addi r3, r1, STACK_FRAME_OVERHEAD
3388 bl kvmppc_bad_interrupt
3392 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3393 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3394 * r11 has the guest MSR value (in/out)
3395 * r9 has a vcpu pointer (in)
3396 * r0 is used as a scratch register
3398 kvmppc_msr_interrupt:
3399 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3400 cmpwi r0, 2 /* Check if we are in transactional state.. */
3401 ld r11, VCPU_INTR_MSR(r9)
3403 /* ... if transactional, change to suspended */
3405 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3409 * Load up guest PMU state. R3 points to the vcpu struct.
3411 _GLOBAL(kvmhv_load_guest_pmu)
3412 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
3416 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3417 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3420 ld r3, VCPU_MMCR(r4)
3421 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3422 cmpwi r5, MMCR0_PMAO
3423 beql kvmppc_fix_pmao
3424 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3425 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
3426 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
3427 lwz r6, VCPU_PMC + 8(r4)
3428 lwz r7, VCPU_PMC + 12(r4)
3429 lwz r8, VCPU_PMC + 16(r4)
3430 lwz r9, VCPU_PMC + 20(r4)
3437 ld r3, VCPU_MMCR(r4)
3438 ld r5, VCPU_MMCR + 8(r4)
3439 ld r6, VCPU_MMCRA(r4)
3440 ld r7, VCPU_SIAR(r4)
3441 ld r8, VCPU_SDAR(r4)
3442 mtspr SPRN_MMCR1, r5
3443 mtspr SPRN_MMCRA, r6
3447 ld r5, VCPU_MMCR + 24(r4)
3448 ld r6, VCPU_SIER + 8(r4)
3449 ld r7, VCPU_SIER + 16(r4)
3450 mtspr SPRN_MMCR3, r5
3451 mtspr SPRN_SIER2, r6
3452 mtspr SPRN_SIER3, r7
3453 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
3455 ld r5, VCPU_MMCR + 16(r4)
3456 ld r6, VCPU_SIER(r4)
3457 mtspr SPRN_MMCR2, r5
3459 BEGIN_FTR_SECTION_NESTED(96)
3460 lwz r7, VCPU_PMC + 24(r4)
3461 lwz r8, VCPU_PMC + 28(r4)
3462 ld r9, VCPU_MMCRS(r4)
3463 mtspr SPRN_SPMC1, r7
3464 mtspr SPRN_SPMC2, r8
3465 mtspr SPRN_MMCRS, r9
3466 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3467 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3468 mtspr SPRN_MMCR0, r3
3474 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
3476 _GLOBAL(kvmhv_load_host_pmu)
3477 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
3479 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
3481 beq 23f /* skip if not */
3483 ld r3, HSTATE_MMCR0(r13)
3484 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3485 cmpwi r4, MMCR0_PMAO
3486 beql kvmppc_fix_pmao
3487 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3488 lwz r3, HSTATE_PMC1(r13)
3489 lwz r4, HSTATE_PMC2(r13)
3490 lwz r5, HSTATE_PMC3(r13)
3491 lwz r6, HSTATE_PMC4(r13)
3492 lwz r8, HSTATE_PMC5(r13)
3493 lwz r9, HSTATE_PMC6(r13)
3500 ld r3, HSTATE_MMCR0(r13)
3501 ld r4, HSTATE_MMCR1(r13)
3502 ld r5, HSTATE_MMCRA(r13)
3503 ld r6, HSTATE_SIAR(r13)
3504 ld r7, HSTATE_SDAR(r13)
3505 mtspr SPRN_MMCR1, r4
3506 mtspr SPRN_MMCRA, r5
3510 ld r8, HSTATE_MMCR2(r13)
3511 ld r9, HSTATE_SIER(r13)
3512 mtspr SPRN_MMCR2, r8
3514 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3516 ld r5, HSTATE_MMCR3(r13)
3517 ld r6, HSTATE_SIER2(r13)
3518 ld r7, HSTATE_SIER3(r13)
3519 mtspr SPRN_MMCR3, r5
3520 mtspr SPRN_SIER2, r6
3521 mtspr SPRN_SIER3, r7
3522 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
3523 mtspr SPRN_MMCR0, r3
3529 * Save guest PMU state into the vcpu struct.
3530 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
3532 _GLOBAL(kvmhv_save_guest_pmu)
3533 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
3538 * POWER8 seems to have a hardware bug where setting
3539 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
3540 * when some counters are already negative doesn't seem
3541 * to cause a performance monitor alert (and hence interrupt).
3542 * The effect of this is that when saving the PMU state,
3543 * if there is no PMU alert pending when we read MMCR0
3544 * before freezing the counters, but one becomes pending
3545 * before we read the counters, we lose it.
3546 * To work around this, we need a way to freeze the counters
3547 * before reading MMCR0. Normally, freezing the counters
3548 * is done by writing MMCR0 (to set MMCR0[FC]) which
3549 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
3550 * we can also freeze the counters using MMCR2, by writing
3551 * 1s to all the counter freeze condition bits (there are
3552 * 9 bits each for 6 counters).
3554 li r3, -1 /* set all freeze bits */
3556 mfspr r10, SPRN_MMCR2
3557 mtspr SPRN_MMCR2, r3
3559 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3561 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3562 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
3563 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3564 mfspr r6, SPRN_MMCRA
3565 /* Clear MMCRA in order to disable SDAR updates */
3567 mtspr SPRN_MMCRA, r7
3569 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
3571 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
3573 21: mfspr r5, SPRN_MMCR1
3576 std r4, VCPU_MMCR(r9)
3577 std r5, VCPU_MMCR + 8(r9)
3578 std r6, VCPU_MMCRA(r9)
3580 std r10, VCPU_MMCR + 16(r9)
3581 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3583 mfspr r5, SPRN_MMCR3
3584 mfspr r6, SPRN_SIER2
3585 mfspr r7, SPRN_SIER3
3586 std r5, VCPU_MMCR + 24(r9)
3587 std r6, VCPU_SIER + 8(r9)
3588 std r7, VCPU_SIER + 16(r9)
3589 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
3590 std r7, VCPU_SIAR(r9)
3591 std r8, VCPU_SDAR(r9)
3598 stw r3, VCPU_PMC(r9)
3599 stw r4, VCPU_PMC + 4(r9)
3600 stw r5, VCPU_PMC + 8(r9)
3601 stw r6, VCPU_PMC + 12(r9)
3602 stw r7, VCPU_PMC + 16(r9)
3603 stw r8, VCPU_PMC + 20(r9)
3606 std r5, VCPU_SIER(r9)
3607 BEGIN_FTR_SECTION_NESTED(96)
3608 mfspr r6, SPRN_SPMC1
3609 mfspr r7, SPRN_SPMC2
3610 mfspr r8, SPRN_MMCRS
3611 stw r6, VCPU_PMC + 24(r9)
3612 stw r7, VCPU_PMC + 28(r9)
3613 std r8, VCPU_MMCRS(r9)
3615 mtspr SPRN_MMCRS, r4
3616 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3617 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3621 * This works around a hardware bug on POWER8E processors, where
3622 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3623 * performance monitor interrupt. Instead, when we need to have
3624 * an interrupt pending, we have to arrange for a counter to overflow.
3628 mtspr SPRN_MMCR2, r3
3629 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3630 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3631 mtspr SPRN_MMCR0, r3
3638 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3640 * Start timing an activity
3641 * r3 = pointer to time accumulation struct, r4 = vcpu
3644 ld r5, HSTATE_KVM_VCORE(r13)
3645 ld r6, VCORE_TB_OFFSET_APPL(r5)
3647 subf r5, r6, r5 /* subtract current timebase offset */
3648 std r3, VCPU_CUR_ACTIVITY(r4)
3649 std r5, VCPU_ACTIVITY_START(r4)
3653 * Accumulate time to one activity and start another.
3654 * r3 = pointer to new time accumulation struct, r4 = vcpu
3656 kvmhv_accumulate_time:
3657 ld r5, HSTATE_KVM_VCORE(r13)
3658 ld r8, VCORE_TB_OFFSET_APPL(r5)
3659 ld r5, VCPU_CUR_ACTIVITY(r4)
3660 ld r6, VCPU_ACTIVITY_START(r4)
3661 std r3, VCPU_CUR_ACTIVITY(r4)
3663 subf r7, r8, r7 /* subtract current timebase offset */
3664 std r7, VCPU_ACTIVITY_START(r4)
3668 ld r8, TAS_SEQCOUNT(r5)
3671 std r8, TAS_SEQCOUNT(r5)
3673 ld r7, TAS_TOTAL(r5)
3675 std r7, TAS_TOTAL(r5)
3681 3: std r3, TAS_MIN(r5)
3687 std r8, TAS_SEQCOUNT(r5)
projects / linux-2.6-microblaze.git / blob