2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
35 /* Sign-extend HDEC if not on POWER9 */
36 #define EXTEND_HDEC(reg) \
39 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
43 /* Values in HSTATE_NAPPING(r13) */
44 #define NAPPING_CEDE 1
45 #define NAPPING_NOVCPU 2
47 /* Stack frame offsets for kvmppc_hv_entry */
49 #define STACK_SLOT_TRAP (SFS-4)
50 #define STACK_SLOT_TID (SFS-16)
51 #define STACK_SLOT_PSSCR (SFS-24)
52 #define STACK_SLOT_PID (SFS-32)
53 #define STACK_SLOT_IAMR (SFS-40)
54 #define STACK_SLOT_CIABR (SFS-48)
55 #define STACK_SLOT_DAWR (SFS-56)
56 #define STACK_SLOT_DAWRX (SFS-64)
57 #define STACK_SLOT_HFSCR (SFS-72)
60 * Call kvmppc_hv_entry in real mode.
61 * Must be called with interrupts hard-disabled.
65 * LR = return address to continue at after eventually re-enabling MMU
67 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
69 std r0, PPC_LR_STKOFF(r1)
72 std r10, HSTATE_HOST_MSR(r13)
73 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
78 mtmsrd r0,1 /* clear RI in MSR */
84 ld r4, HSTATE_KVM_VCPU(r13)
87 /* Back from guest - restore host state and return to caller */
90 /* Restore host DABR and DABRX */
91 ld r5,HSTATE_DABR(r13)
95 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
98 ld r3,PACA_SPRG_VDSO(r13)
99 mtspr SPRN_SPRG_VDSO_WRITE,r3
101 /* Reload the host's PMU registers */
102 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
103 lbz r4, LPPACA_PMCINUSE(r3)
105 beq 23f /* skip if not */
107 ld r3, HSTATE_MMCR0(r13)
108 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
111 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
112 lwz r3, HSTATE_PMC1(r13)
113 lwz r4, HSTATE_PMC2(r13)
114 lwz r5, HSTATE_PMC3(r13)
115 lwz r6, HSTATE_PMC4(r13)
116 lwz r8, HSTATE_PMC5(r13)
117 lwz r9, HSTATE_PMC6(r13)
124 ld r3, HSTATE_MMCR0(r13)
125 ld r4, HSTATE_MMCR1(r13)
126 ld r5, HSTATE_MMCRA(r13)
127 ld r6, HSTATE_SIAR(r13)
128 ld r7, HSTATE_SDAR(r13)
134 ld r8, HSTATE_MMCR2(r13)
135 ld r9, HSTATE_SIER(r13)
138 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
144 * Reload DEC. HDEC interrupts were disabled when
145 * we reloaded the host's LPCR value.
147 ld r3, HSTATE_DECEXP(r13)
152 /* hwthread_req may have got set by cede or no vcpu, so clear it */
154 stb r0, HSTATE_HWTHREAD_REQ(r13)
157 * For external interrupts we need to call the Linux
158 * handler to process the interrupt. We do that by jumping
159 * to absolute address 0x500 for external interrupts.
160 * The [h]rfid at the end of the handler will return to
161 * the book3s_hv_interrupts.S code. For other interrupts
162 * we do the rfid to get back to the book3s_hv_interrupts.S
165 ld r8, 112+PPC_LR_STKOFF(r1)
167 ld r7, HSTATE_HOST_MSR(r13)
169 /* Return the trap number on this thread as the return value */
173 * If we came back from the guest via a relocation-on interrupt,
174 * we will be in virtual mode at this point, which makes it a
175 * little easier to get back to the caller.
178 andi. r0, r0, MSR_IR /* in real mode? */
181 /* RFI into the highmem handler */
185 mtmsrd r6, 1 /* Clear RI in MSR */
190 /* Virtual-mode return */
195 kvmppc_primary_no_guest:
196 /* We handle this much like a ceded vcpu */
197 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
198 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
199 /* HDEC value came from DEC in the first place, it will fit */
203 * Make sure the primary has finished the MMU switch.
204 * We should never get here on a secondary thread, but
205 * check it for robustness' sake.
207 ld r5, HSTATE_KVM_VCORE(r13)
208 65: lbz r0, VCORE_IN_GUEST(r5)
215 /* set our bit in napping_threads */
216 ld r5, HSTATE_KVM_VCORE(r13)
217 lbz r7, HSTATE_PTID(r13)
220 addi r6, r5, VCORE_NAPPING_THREADS
225 /* order napping_threads update vs testing entry_exit_map */
228 lwz r7, VCORE_ENTRY_EXIT(r5)
230 bge kvm_novcpu_exit /* another thread already exiting */
231 li r3, NAPPING_NOVCPU
232 stb r3, HSTATE_NAPPING(r13)
234 li r3, 0 /* Don't wake on privileged (OS) doorbell */
239 * Entered from kvm_start_guest if kvm_hstate.napping is set
245 ld r1, HSTATE_HOST_R1(r13)
246 ld r5, HSTATE_KVM_VCORE(r13)
248 stb r0, HSTATE_NAPPING(r13)
250 /* check the wake reason */
251 bl kvmppc_check_wake_reason
254 * Restore volatile registers since we could have called
255 * a C routine in kvmppc_check_wake_reason.
258 ld r5, HSTATE_KVM_VCORE(r13)
260 /* see if any other thread is already exiting */
261 lwz r0, VCORE_ENTRY_EXIT(r5)
265 /* clear our bit in napping_threads */
266 lbz r7, HSTATE_PTID(r13)
269 addi r6, r5, VCORE_NAPPING_THREADS
275 /* See if the wake reason means we need to exit */
279 /* See if our timeslice has expired (HDEC is negative) */
282 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
286 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
287 ld r4, HSTATE_KVM_VCPU(r13)
289 beq kvmppc_primary_no_guest
291 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
292 addi r3, r4, VCPU_TB_RMENTRY
293 bl kvmhv_start_timing
298 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
299 ld r4, HSTATE_KVM_VCPU(r13)
302 addi r3, r4, VCPU_TB_RMEXIT
303 bl kvmhv_accumulate_time
306 stw r12, STACK_SLOT_TRAP(r1)
307 bl kvmhv_commence_exit
309 lwz r12, STACK_SLOT_TRAP(r1)
310 b kvmhv_switch_to_host
313 * We come in here when wakened from nap mode.
314 * Relocation is off and most register values are lost.
315 * r13 points to the PACA.
317 .globl kvm_start_guest
320 /* Set runlatch bit the minute you wake up from nap */
327 li r0,KVM_HWTHREAD_IN_KVM
328 stb r0,HSTATE_HWTHREAD_STATE(r13)
330 /* NV GPR values from power7_idle() will no longer be valid */
332 stb r0,PACA_NAPSTATELOST(r13)
334 /* were we napping due to cede? */
335 lbz r0,HSTATE_NAPPING(r13)
336 cmpwi r0,NAPPING_CEDE
338 cmpwi r0,NAPPING_NOVCPU
339 beq kvm_novcpu_wakeup
341 ld r1,PACAEMERGSP(r13)
342 subi r1,r1,STACK_FRAME_OVERHEAD
345 * We weren't napping due to cede, so this must be a secondary
346 * thread being woken up to run a guest, or being woken up due
347 * to a stray IPI. (Or due to some machine check or hypervisor
348 * maintenance interrupt while the core is in KVM.)
351 /* Check the wake reason in SRR1 to see why we got here */
352 bl kvmppc_check_wake_reason
354 * kvmppc_check_wake_reason could invoke a C routine, but we
355 * have no volatile registers to restore when we return.
361 /* get vcore pointer, NULL if we have nothing to run */
362 ld r5,HSTATE_KVM_VCORE(r13)
364 /* if we have no vcore to run, go back to sleep */
367 kvm_secondary_got_guest:
369 /* Set HSTATE_DSCR(r13) to something sensible */
370 ld r6, PACA_DSCR_DEFAULT(r13)
371 std r6, HSTATE_DSCR(r13)
373 /* On thread 0 of a subcore, set HDEC to max */
374 lbz r4, HSTATE_PTID(r13)
377 LOAD_REG_ADDR(r6, decrementer_max)
380 /* and set per-LPAR registers, if doing dynamic micro-threading */
381 ld r6, HSTATE_SPLIT_MODE(r13)
384 ld r0, KVM_SPLIT_RPR(r6)
386 ld r0, KVM_SPLIT_PMMAR(r6)
388 ld r0, KVM_SPLIT_LDBAR(r6)
392 /* Order load of vcpu after load of vcore */
394 ld r4, HSTATE_KVM_VCPU(r13)
397 /* Back from the guest, go back to nap */
398 /* Clear our vcpu and vcore pointers so we don't come back in early */
400 std r0, HSTATE_KVM_VCPU(r13)
402 * Once we clear HSTATE_KVM_VCORE(r13), the code in
403 * kvmppc_run_core() is going to assume that all our vcpu
404 * state is visible in memory. This lwsync makes sure
408 std r0, HSTATE_KVM_VCORE(r13)
411 * All secondaries exiting guest will fall through this path.
412 * Before proceeding, just check for HMI interrupt and
413 * invoke opal hmi handler. By now we are sure that the
414 * primary thread on this core/subcore has already made partition
415 * switch/TB resync and we are good to call opal hmi handler.
417 cmpwi r12, BOOK3S_INTERRUPT_HMI
420 li r3,0 /* NULL argument */
421 bl hmi_exception_realmode
423 * At this point we have finished executing in the guest.
424 * We need to wait for hwthread_req to become zero, since
425 * we may not turn on the MMU while hwthread_req is non-zero.
426 * While waiting we also need to check if we get given a vcpu to run.
429 lbz r3, HSTATE_HWTHREAD_REQ(r13)
433 li r0, KVM_HWTHREAD_IN_KERNEL
434 stb r0, HSTATE_HWTHREAD_STATE(r13)
435 /* need to recheck hwthread_req after a barrier, to avoid race */
437 lbz r3, HSTATE_HWTHREAD_REQ(r13)
441 * We jump to pnv_wakeup_loss, which will return to the caller
442 * of power7_nap in the powernv cpu offline loop. The value we
443 * put in r3 becomes the return value for power7_nap.
447 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
453 ld r5, HSTATE_KVM_VCORE(r13)
456 ld r3, HSTATE_SPLIT_MODE(r13)
459 lbz r0, KVM_SPLIT_DO_NAP(r3)
465 b kvm_secondary_got_guest
467 54: li r0, KVM_HWTHREAD_IN_KVM
468 stb r0, HSTATE_HWTHREAD_STATE(r13)
472 * Here the primary thread is trying to return the core to
473 * whole-core mode, so we need to nap.
477 * When secondaries are napping in kvm_unsplit_nap() with
478 * hwthread_req = 1, HMI goes ignored even though subcores are
479 * already exited the guest. Hence HMI keeps waking up secondaries
480 * from nap in a loop and secondaries always go back to nap since
481 * no vcore is assigned to them. This makes impossible for primary
482 * thread to get hold of secondary threads resulting into a soft
483 * lockup in KVM path.
485 * Let us check if HMI is pending and handle it before we go to nap.
487 cmpwi r12, BOOK3S_INTERRUPT_HMI
489 li r3, 0 /* NULL argument */
490 bl hmi_exception_realmode
493 * Ensure that secondary doesn't nap when it has
494 * its vcore pointer set.
496 sync /* matches smp_mb() before setting split_info.do_nap */
497 ld r0, HSTATE_KVM_VCORE(r13)
500 /* clear any pending message */
502 lis r6, (PPC_DBELL_SERVER << (63-36))@h
504 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
505 /* Set kvm_split_mode.napped[tid] = 1 */
506 ld r3, HSTATE_SPLIT_MODE(r13)
508 lhz r4, PACAPACAINDEX(r13)
509 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
510 addi r4, r4, KVM_SPLIT_NAPPED
512 /* Check the do_nap flag again after setting napped[] */
514 lbz r0, KVM_SPLIT_DO_NAP(r3)
517 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
519 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
526 /******************************************************************************
530 *****************************************************************************/
532 .global kvmppc_hv_entry
537 * R4 = vcpu pointer (or NULL)
542 * all other volatile GPRS = free
543 * Does not preserve non-volatile GPRs or CR fields
546 std r0, PPC_LR_STKOFF(r1)
549 /* Save R1 in the PACA */
550 std r1, HSTATE_HOST_R1(r13)
552 li r6, KVM_GUEST_MODE_HOST_HV
553 stb r6, HSTATE_IN_GUEST(r13)
555 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
556 /* Store initial timestamp */
559 addi r3, r4, VCPU_TB_RMENTRY
560 bl kvmhv_start_timing
564 /* Use cr7 as an indication of radix mode */
565 ld r5, HSTATE_KVM_VCORE(r13)
566 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
567 lbz r0, KVM_RADIX(r9)
570 /* Clear out SLB if hash */
578 * POWER7/POWER8 host -> guest partition switch code.
579 * We don't have to lock against concurrent tlbies,
580 * but we do have to coordinate across hardware threads.
582 /* Set bit in entry map iff exit map is zero. */
584 lbz r6, HSTATE_PTID(r13)
586 addi r8, r5, VCORE_ENTRY_EXIT
588 cmpwi r3, 0x100 /* any threads starting to exit? */
589 bge secondary_too_late /* if so we're too late to the party */
594 /* Primary thread switches to guest partition. */
600 li r0,LPID_RSVD /* switch to reserved LPID */
603 mtspr SPRN_SDR1,r6 /* switch to partition page table */
604 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
608 /* See if we need to flush the TLB */
609 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
612 * On POWER9, individual threads can come in here, but the
613 * TLB is shared between the 4 threads in a core, hence
614 * invalidating on one thread invalidates for all.
615 * Thus we make all 4 threads use the same bit here.
618 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
619 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
620 srdi r6,r6,6 /* doubleword number */
621 sldi r6,r6,3 /* address offset */
623 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
629 /* Flush the TLB of any entries for this LPID */
630 lwz r0,KVM_TLB_SETS(r9)
632 li r7,0x800 /* IS field = 0b10 */
634 li r0,0 /* RS for P9 version of tlbiel */
636 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
640 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
644 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
649 /* Add timebase offset onto timebase */
650 22: ld r8,VCORE_TB_OFFSET(r5)
653 mftb r6 /* current host timebase */
655 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
656 mftb r7 /* check if lower 24 bits overflowed */
661 addis r8,r8,0x100 /* if so, increment upper 40 bits */
664 /* Load guest PCR value to select appropriate compat mode */
665 37: ld r7, VCORE_PCR(r5)
672 /* DPDES and VTB are shared between threads */
673 ld r8, VCORE_DPDES(r5)
677 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
679 /* Mark the subcore state as inside guest */
680 bl kvmppc_subcore_enter_guest
682 ld r5, HSTATE_KVM_VCORE(r13)
683 ld r4, HSTATE_KVM_VCPU(r13)
685 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
687 /* Do we have a guest vcpu to run? */
689 beq kvmppc_primary_no_guest
692 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
693 lwz r5,VCPU_SLB_MAX(r4)
698 1: ld r8,VCPU_SLB_E(r6)
701 addi r6,r6,VCPU_SLB_SIZE
704 /* Increment yield count if they have a VPA */
708 li r6, LPPACA_YIELDCOUNT
713 stb r6, VCPU_VPA_DIRTY(r4)
716 /* Save purr/spurr */
719 std r5,HSTATE_PURR(r13)
720 std r6,HSTATE_SPURR(r13)
726 /* Save host values of some registers */
732 std r5, STACK_SLOT_TID(r1)
733 std r6, STACK_SLOT_PSSCR(r1)
734 std r7, STACK_SLOT_PID(r1)
735 std r8, STACK_SLOT_IAMR(r1)
737 std r5, STACK_SLOT_HFSCR(r1)
738 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
743 std r5, STACK_SLOT_CIABR(r1)
744 std r6, STACK_SLOT_DAWR(r1)
745 std r7, STACK_SLOT_DAWRX(r1)
746 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
749 /* Set partition DABR */
750 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
751 lwz r5,VCPU_DABRX(r4)
756 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
758 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
761 END_FTR_SECTION_IFSET(CPU_FTR_TM)
764 /* Load guest PMU registers */
765 /* R4 is live here (vcpu pointer) */
767 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
768 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
772 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
775 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
776 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
777 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
778 lwz r6, VCPU_PMC + 8(r4)
779 lwz r7, VCPU_PMC + 12(r4)
780 lwz r8, VCPU_PMC + 16(r4)
781 lwz r9, VCPU_PMC + 20(r4)
789 ld r5, VCPU_MMCR + 8(r4)
790 ld r6, VCPU_MMCR + 16(r4)
798 ld r5, VCPU_MMCR + 24(r4)
802 BEGIN_FTR_SECTION_NESTED(96)
803 lwz r7, VCPU_PMC + 24(r4)
804 lwz r8, VCPU_PMC + 28(r4)
805 ld r9, VCPU_MMCR + 32(r4)
809 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
810 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
814 /* Load up FP, VMX and VSX registers */
817 ld r14, VCPU_GPR(R14)(r4)
818 ld r15, VCPU_GPR(R15)(r4)
819 ld r16, VCPU_GPR(R16)(r4)
820 ld r17, VCPU_GPR(R17)(r4)
821 ld r18, VCPU_GPR(R18)(r4)
822 ld r19, VCPU_GPR(R19)(r4)
823 ld r20, VCPU_GPR(R20)(r4)
824 ld r21, VCPU_GPR(R21)(r4)
825 ld r22, VCPU_GPR(R22)(r4)
826 ld r23, VCPU_GPR(R23)(r4)
827 ld r24, VCPU_GPR(R24)(r4)
828 ld r25, VCPU_GPR(R25)(r4)
829 ld r26, VCPU_GPR(R26)(r4)
830 ld r27, VCPU_GPR(R27)(r4)
831 ld r28, VCPU_GPR(R28)(r4)
832 ld r29, VCPU_GPR(R29)(r4)
833 ld r30, VCPU_GPR(R30)(r4)
834 ld r31, VCPU_GPR(R31)(r4)
836 /* Switch DSCR to guest value */
841 /* Skip next section on POWER7 */
843 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
844 /* Load up POWER8-specific registers */
846 lwz r6, VCPU_PSPB(r4)
852 ld r6, VCPU_DAWRX(r4)
853 ld r7, VCPU_CIABR(r4)
860 ld r8, VCPU_EBBHR(r4)
863 ld r5, VCPU_EBBRR(r4)
864 ld r6, VCPU_BESCR(r4)
865 lwz r7, VCPU_GUEST_PID(r4)
873 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
875 /* POWER8-only registers */
876 ld r5, VCPU_TCSCR(r4)
878 ld r7, VCPU_CSIGR(r4)
885 /* POWER9-only registers */
887 ld r6, VCPU_PSSCR(r4)
888 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
889 ld r7, VCPU_HFSCR(r4)
893 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
897 * Set the decrementer to the guest decrementer.
899 ld r8,VCPU_DEC_EXPIRES(r4)
900 /* r8 is a host timebase value here, convert to guest TB */
901 ld r5,HSTATE_KVM_VCORE(r13)
902 ld r6,VCORE_TB_OFFSET(r5)
909 ld r5, VCPU_SPRG0(r4)
910 ld r6, VCPU_SPRG1(r4)
911 ld r7, VCPU_SPRG2(r4)
912 ld r8, VCPU_SPRG3(r4)
918 /* Load up DAR and DSISR */
920 lwz r6, VCPU_DSISR(r4)
924 /* Restore AMR and UAMOR, set AMOR to all 1s */
932 /* Restore state of CTRL run bit; assume 1 on entry */
940 /* Secondary threads wait for primary to have done partition switch */
941 ld r5, HSTATE_KVM_VCORE(r13)
942 lbz r6, HSTATE_PTID(r13)
945 lbz r0, VCORE_IN_GUEST(r5)
949 20: lwz r3, VCORE_ENTRY_EXIT(r5)
952 lbz r0, VCORE_IN_GUEST(r5)
962 /* Check if HDEC expires soon */
965 cmpdi r3, 512 /* 1 microsecond */
968 #ifdef CONFIG_KVM_XICS
969 /* We are entering the guest on that thread, push VCPU to XIVE */
970 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
973 ld r11, VCPU_XIVE_SAVED_STATE(r4)
977 lwz r11, VCPU_XIVE_CAM_WORD(r4)
978 li r9, TM_QW1_OS + TM_WORD2
981 stw r9, VCPU_XIVE_PUSHED(r4)
983 #endif /* CONFIG_KVM_XICS */
985 deliver_guest_interrupt:
992 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1000 /* r11 = vcpu->arch.msr & ~MSR_HV */
1001 rldicl r11, r11, 63 - MSR_HV_LG, 1
1002 rotldi r11, r11, 1 + MSR_HV_LG
1003 ori r11, r11, MSR_ME
1005 /* Check if we can deliver an external or decrementer interrupt now */
1006 ld r0, VCPU_PENDING_EXC(r4)
1007 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1009 andi. r8, r11, MSR_EE
1011 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1012 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1016 li r0, BOOK3S_INTERRUPT_EXTERNAL
1020 /* On POWER9 check whether the guest has large decrementer enabled */
1021 andis. r8, r8, LPCR_LD@h
1023 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1026 li r0, BOOK3S_INTERRUPT_DECREMENTER
1029 12: mtspr SPRN_SRR0, r10
1031 mtspr SPRN_SRR1, r11
1033 bl kvmppc_msr_interrupt
1037 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1038 /* On POWER9, check for pending doorbell requests */
1039 lbz r0, VCPU_DBELL_REQ(r4)
1041 beq fast_guest_return
1042 ld r5, HSTATE_KVM_VCORE(r13)
1043 /* Set DPDES register so the CPU will take a doorbell interrupt */
1045 mtspr SPRN_DPDES, r0
1046 std r0, VCORE_DPDES(r5)
1047 /* Make sure other cpus see vcore->dpdes set before dbell req clear */
1049 /* Clear the pending doorbell request */
1051 stb r0, VCPU_DBELL_REQ(r4)
1056 * R10: value for HSRR0
1057 * R11: value for HSRR1
1062 stb r0,VCPU_CEDED(r4) /* cancel cede */
1063 mtspr SPRN_HSRR0,r10
1064 mtspr SPRN_HSRR1,r11
1066 /* Activate guest mode, so faults get handled by KVM */
1067 li r9, KVM_GUEST_MODE_GUEST_HV
1068 stb r9, HSTATE_IN_GUEST(r13)
1070 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1071 /* Accumulate timing */
1072 addi r3, r4, VCPU_TB_GUEST
1073 bl kvmhv_accumulate_time
1079 ld r5, VCPU_CFAR(r4)
1081 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1084 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1091 ld r1, VCPU_GPR(R1)(r4)
1092 ld r2, VCPU_GPR(R2)(r4)
1093 ld r3, VCPU_GPR(R3)(r4)
1094 ld r5, VCPU_GPR(R5)(r4)
1095 ld r6, VCPU_GPR(R6)(r4)
1096 ld r7, VCPU_GPR(R7)(r4)
1097 ld r8, VCPU_GPR(R8)(r4)
1098 ld r9, VCPU_GPR(R9)(r4)
1099 ld r10, VCPU_GPR(R10)(r4)
1100 ld r11, VCPU_GPR(R11)(r4)
1101 ld r12, VCPU_GPR(R12)(r4)
1102 ld r13, VCPU_GPR(R13)(r4)
1106 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1107 ld r0, VCPU_GPR(R0)(r4)
1108 ld r4, VCPU_GPR(R4)(r4)
1117 stw r12, VCPU_TRAP(r4)
1118 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1119 addi r3, r4, VCPU_TB_RMEXIT
1120 bl kvmhv_accumulate_time
1122 11: b kvmhv_switch_to_host
1129 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1130 12: stw r12, VCPU_TRAP(r4)
1132 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1133 addi r3, r4, VCPU_TB_RMEXIT
1134 bl kvmhv_accumulate_time
1138 /******************************************************************************
1142 *****************************************************************************/
1145 * We come here from the first-level interrupt handlers.
1147 .globl kvmppc_interrupt_hv
1148 kvmppc_interrupt_hv:
1150 * Register contents:
1151 * R12 = (guest CR << 32) | interrupt vector
1153 * guest R12 saved in shadow VCPU SCRATCH0
1154 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1155 * guest R13 saved in SPRN_SCRATCH0
1157 std r9, HSTATE_SCRATCH2(r13)
1158 lbz r9, HSTATE_IN_GUEST(r13)
1159 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1160 beq kvmppc_bad_host_intr
1161 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1162 cmpwi r9, KVM_GUEST_MODE_GUEST
1163 ld r9, HSTATE_SCRATCH2(r13)
1164 beq kvmppc_interrupt_pr
1166 /* We're now back in the host but in guest MMU context */
1167 li r9, KVM_GUEST_MODE_HOST_HV
1168 stb r9, HSTATE_IN_GUEST(r13)
1170 ld r9, HSTATE_KVM_VCPU(r13)
1172 /* Save registers */
1174 std r0, VCPU_GPR(R0)(r9)
1175 std r1, VCPU_GPR(R1)(r9)
1176 std r2, VCPU_GPR(R2)(r9)
1177 std r3, VCPU_GPR(R3)(r9)
1178 std r4, VCPU_GPR(R4)(r9)
1179 std r5, VCPU_GPR(R5)(r9)
1180 std r6, VCPU_GPR(R6)(r9)
1181 std r7, VCPU_GPR(R7)(r9)
1182 std r8, VCPU_GPR(R8)(r9)
1183 ld r0, HSTATE_SCRATCH2(r13)
1184 std r0, VCPU_GPR(R9)(r9)
1185 std r10, VCPU_GPR(R10)(r9)
1186 std r11, VCPU_GPR(R11)(r9)
1187 ld r3, HSTATE_SCRATCH0(r13)
1188 std r3, VCPU_GPR(R12)(r9)
1189 /* CR is in the high half of r12 */
1193 ld r3, HSTATE_CFAR(r13)
1194 std r3, VCPU_CFAR(r9)
1195 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1197 ld r4, HSTATE_PPR(r13)
1198 std r4, VCPU_PPR(r9)
1199 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1201 /* Restore R1/R2 so we can handle faults */
1202 ld r1, HSTATE_HOST_R1(r13)
1205 mfspr r10, SPRN_SRR0
1206 mfspr r11, SPRN_SRR1
1207 std r10, VCPU_SRR0(r9)
1208 std r11, VCPU_SRR1(r9)
1209 /* trap is in the low half of r12, clear CR from the high half */
1211 andi. r0, r12, 2 /* need to read HSRR0/1? */
1213 mfspr r10, SPRN_HSRR0
1214 mfspr r11, SPRN_HSRR1
1216 1: std r10, VCPU_PC(r9)
1217 std r11, VCPU_MSR(r9)
1221 std r3, VCPU_GPR(R13)(r9)
1224 stw r12,VCPU_TRAP(r9)
1227 * Now that we have saved away SRR0/1 and HSRR0/1,
1228 * interrupts are recoverable in principle, so set MSR_RI.
1229 * This becomes important for relocation-on interrupts from
1230 * the guest, which we can get in radix mode on POWER9.
1235 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1236 addi r3, r9, VCPU_TB_RMINTR
1238 bl kvmhv_accumulate_time
1239 ld r5, VCPU_GPR(R5)(r9)
1240 ld r6, VCPU_GPR(R6)(r9)
1241 ld r7, VCPU_GPR(R7)(r9)
1242 ld r8, VCPU_GPR(R8)(r9)
1245 /* Save HEIR (HV emulation assist reg) in emul_inst
1246 if this is an HEI (HV emulation interrupt, e40) */
1247 li r3,KVM_INST_FETCH_FAILED
1248 stw r3,VCPU_LAST_INST(r9)
1249 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1252 11: stw r3,VCPU_HEIR(r9)
1254 /* these are volatile across C function calls */
1255 #ifdef CONFIG_RELOCATABLE
1256 ld r3, HSTATE_SCRATCH1(r13)
1262 std r3, VCPU_CTR(r9)
1263 std r4, VCPU_XER(r9)
1265 /* If this is a page table miss then see if it's theirs or ours */
1266 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1268 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1271 /* See if this is a leftover HDEC interrupt */
1272 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1277 bge fast_guest_return
1279 /* See if this is an hcall we can handle in real mode */
1280 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1281 beq hcall_try_real_mode
1283 /* Hypervisor doorbell - exit only if host IPI flag set */
1284 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1286 lbz r0, HSTATE_HOST_IPI(r13)
1291 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1292 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1294 mfspr r3, SPRN_HFSCR
1295 std r3, VCPU_HFSCR(r9)
1298 /* External interrupt ? */
1299 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1300 bne+ guest_exit_cont
1302 /* External interrupt, first check for host_ipi. If this is
1303 * set, we know the host wants us out so let's do it now
1308 * Restore the active volatile registers after returning from
1311 ld r9, HSTATE_KVM_VCPU(r13)
1312 li r12, BOOK3S_INTERRUPT_EXTERNAL
1315 * kvmppc_read_intr return codes:
1317 * Exit to host (r3 > 0)
1318 * 1 An interrupt is pending that needs to be handled by the host
1319 * Exit guest and return to host by branching to guest_exit_cont
1321 * 2 Passthrough that needs completion in the host
1322 * Exit guest and return to host by branching to guest_exit_cont
1323 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1324 * to indicate to the host to complete handling the interrupt
1326 * Before returning to guest, we check if any CPU is heading out
1327 * to the host and if so, we head out also. If no CPUs are heading
1328 * check return values <= 0.
1330 * Return to guest (r3 <= 0)
1331 * 0 No external interrupt is pending
1332 * -1 A guest wakeup IPI (which has now been cleared)
1333 * In either case, we return to guest to deliver any pending
1336 * -2 A PCI passthrough external interrupt was handled
1337 * (interrupt was delivered directly to guest)
1338 * Return to guest to deliver any pending guest interrupts.
1344 /* Return code = 2 */
1345 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1346 stw r12, VCPU_TRAP(r9)
1349 1: /* Return code <= 1 */
1353 /* Return code <= 0 */
1354 4: ld r5, HSTATE_KVM_VCORE(r13)
1355 lwz r0, VCORE_ENTRY_EXIT(r5)
1358 blt deliver_guest_interrupt
1360 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1361 #ifdef CONFIG_KVM_XICS
1362 /* We are exiting, pull the VP from the XIVE */
1363 lwz r0, VCPU_XIVE_PUSHED(r9)
1366 li r7, TM_SPC_PULL_OS_CTX
1369 andi. r0, r0, MSR_IR /* in real mode? */
1371 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1374 /* First load to pull the context, we ignore the value */
1377 /* Second load to recover the context state (Words 0 and 1) */
1380 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1383 /* First load to pull the context, we ignore the value */
1386 /* Second load to recover the context state (Words 0 and 1) */
1388 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1389 /* Fixup some of the state for the next load */
1392 stw r10, VCPU_XIVE_PUSHED(r9)
1393 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1394 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1396 #endif /* CONFIG_KVM_XICS */
1397 /* Save more register state */
1400 std r6, VCPU_DAR(r9)
1401 stw r7, VCPU_DSISR(r9)
1402 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1403 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1405 std r6, VCPU_FAULT_DAR(r9)
1406 stw r7, VCPU_FAULT_DSISR(r9)
1408 /* See if it is a machine check */
1409 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1410 beq machine_check_realmode
1412 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1413 addi r3, r9, VCPU_TB_RMEXIT
1415 bl kvmhv_accumulate_time
1419 /* Increment exit count, poke other threads to exit */
1420 bl kvmhv_commence_exit
1422 ld r9, HSTATE_KVM_VCPU(r13)
1423 lwz r12, VCPU_TRAP(r9)
1425 /* Stop others sending VCPU interrupts to this physical CPU */
1427 stw r0, VCPU_CPU(r9)
1428 stw r0, VCPU_THREAD_CPU(r9)
1430 /* Save guest CTRL register, set runlatch to 1 */
1432 stw r6,VCPU_CTRL(r9)
1438 /* Read the guest SLB and save it away */
1440 lbz r0, KVM_RADIX(r5)
1443 bne 3f /* for radix, save 0 entries */
1444 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1449 andis. r0,r8,SLB_ESID_V@h
1451 add r8,r8,r6 /* put index in */
1453 std r8,VCPU_SLB_E(r7)
1454 std r3,VCPU_SLB_V(r7)
1455 addi r7,r7,VCPU_SLB_SIZE
1459 3: stw r5,VCPU_SLB_MAX(r9)
1462 * Save the guest PURR/SPURR
1467 ld r8,VCPU_SPURR(r9)
1468 std r5,VCPU_PURR(r9)
1469 std r6,VCPU_SPURR(r9)
1474 * Restore host PURR/SPURR and add guest times
1475 * so that the time in the guest gets accounted.
1477 ld r3,HSTATE_PURR(r13)
1478 ld r4,HSTATE_SPURR(r13)
1485 ld r3, HSTATE_KVM_VCORE(r13)
1488 /* On P9, if the guest has large decr enabled, don't sign extend */
1490 ld r4, VCORE_LPCR(r3)
1491 andis. r4, r4, LPCR_LD@h
1493 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1496 /* r5 is a guest timebase value here, convert to host TB */
1497 ld r4,VCORE_TB_OFFSET(r3)
1499 std r5,VCPU_DEC_EXPIRES(r9)
1503 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1504 /* Save POWER8-specific registers */
1508 std r5, VCPU_IAMR(r9)
1509 stw r6, VCPU_PSPB(r9)
1510 std r7, VCPU_FSCR(r9)
1514 std r7, VCPU_TAR(r9)
1515 mfspr r8, SPRN_EBBHR
1516 std r8, VCPU_EBBHR(r9)
1517 mfspr r5, SPRN_EBBRR
1518 mfspr r6, SPRN_BESCR
1521 std r5, VCPU_EBBRR(r9)
1522 std r6, VCPU_BESCR(r9)
1523 stw r7, VCPU_GUEST_PID(r9)
1524 std r8, VCPU_WORT(r9)
1526 mfspr r5, SPRN_TCSCR
1528 mfspr r7, SPRN_CSIGR
1530 std r5, VCPU_TCSCR(r9)
1531 std r6, VCPU_ACOP(r9)
1532 std r7, VCPU_CSIGR(r9)
1533 std r8, VCPU_TACR(r9)
1536 mfspr r6, SPRN_PSSCR
1537 std r5, VCPU_TID(r9)
1538 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1540 std r6, VCPU_PSSCR(r9)
1541 /* Restore host HFSCR value */
1542 ld r7, STACK_SLOT_HFSCR(r1)
1543 mtspr SPRN_HFSCR, r7
1544 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1546 * Restore various registers to 0, where non-zero values
1547 * set by the guest could disrupt the host.
1554 mtspr SPRN_TCSCR, r0
1555 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1558 mtspr SPRN_MMCRS, r0
1559 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1562 /* Save and reset AMR and UAMOR before turning on the MMU */
1566 std r6,VCPU_UAMOR(r9)
1569 mtspr SPRN_UAMOR, r6
1571 /* Switch DSCR back to host value */
1573 ld r7, HSTATE_DSCR(r13)
1574 std r8, VCPU_DSCR(r9)
1577 /* Save non-volatile GPRs */
1578 std r14, VCPU_GPR(R14)(r9)
1579 std r15, VCPU_GPR(R15)(r9)
1580 std r16, VCPU_GPR(R16)(r9)
1581 std r17, VCPU_GPR(R17)(r9)
1582 std r18, VCPU_GPR(R18)(r9)
1583 std r19, VCPU_GPR(R19)(r9)
1584 std r20, VCPU_GPR(R20)(r9)
1585 std r21, VCPU_GPR(R21)(r9)
1586 std r22, VCPU_GPR(R22)(r9)
1587 std r23, VCPU_GPR(R23)(r9)
1588 std r24, VCPU_GPR(R24)(r9)
1589 std r25, VCPU_GPR(R25)(r9)
1590 std r26, VCPU_GPR(R26)(r9)
1591 std r27, VCPU_GPR(R27)(r9)
1592 std r28, VCPU_GPR(R28)(r9)
1593 std r29, VCPU_GPR(R29)(r9)
1594 std r30, VCPU_GPR(R30)(r9)
1595 std r31, VCPU_GPR(R31)(r9)
1598 mfspr r3, SPRN_SPRG0
1599 mfspr r4, SPRN_SPRG1
1600 mfspr r5, SPRN_SPRG2
1601 mfspr r6, SPRN_SPRG3
1602 std r3, VCPU_SPRG0(r9)
1603 std r4, VCPU_SPRG1(r9)
1604 std r5, VCPU_SPRG2(r9)
1605 std r6, VCPU_SPRG3(r9)
1611 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1614 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1617 /* Increment yield count if they have a VPA */
1618 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1621 li r4, LPPACA_YIELDCOUNT
1626 stb r3, VCPU_VPA_DIRTY(r9)
1628 /* Save PMU registers if requested */
1629 /* r8 and cr0.eq are live here */
1632 * POWER8 seems to have a hardware bug where setting
1633 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1634 * when some counters are already negative doesn't seem
1635 * to cause a performance monitor alert (and hence interrupt).
1636 * The effect of this is that when saving the PMU state,
1637 * if there is no PMU alert pending when we read MMCR0
1638 * before freezing the counters, but one becomes pending
1639 * before we read the counters, we lose it.
1640 * To work around this, we need a way to freeze the counters
1641 * before reading MMCR0. Normally, freezing the counters
1642 * is done by writing MMCR0 (to set MMCR0[FC]) which
1643 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1644 * we can also freeze the counters using MMCR2, by writing
1645 * 1s to all the counter freeze condition bits (there are
1646 * 9 bits each for 6 counters).
1648 li r3, -1 /* set all freeze bits */
1650 mfspr r10, SPRN_MMCR2
1651 mtspr SPRN_MMCR2, r3
1653 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1655 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1656 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1657 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1658 mfspr r6, SPRN_MMCRA
1659 /* Clear MMCRA in order to disable SDAR updates */
1661 mtspr SPRN_MMCRA, r7
1663 beq 21f /* if no VPA, save PMU stuff anyway */
1664 lbz r7, LPPACA_PMCINUSE(r8)
1665 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1667 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1669 21: mfspr r5, SPRN_MMCR1
1672 std r4, VCPU_MMCR(r9)
1673 std r5, VCPU_MMCR + 8(r9)
1674 std r6, VCPU_MMCR + 16(r9)
1676 std r10, VCPU_MMCR + 24(r9)
1677 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1678 std r7, VCPU_SIAR(r9)
1679 std r8, VCPU_SDAR(r9)
1686 stw r3, VCPU_PMC(r9)
1687 stw r4, VCPU_PMC + 4(r9)
1688 stw r5, VCPU_PMC + 8(r9)
1689 stw r6, VCPU_PMC + 12(r9)
1690 stw r7, VCPU_PMC + 16(r9)
1691 stw r8, VCPU_PMC + 20(r9)
1694 std r5, VCPU_SIER(r9)
1695 BEGIN_FTR_SECTION_NESTED(96)
1696 mfspr r6, SPRN_SPMC1
1697 mfspr r7, SPRN_SPMC2
1698 mfspr r8, SPRN_MMCRS
1699 stw r6, VCPU_PMC + 24(r9)
1700 stw r7, VCPU_PMC + 28(r9)
1701 std r8, VCPU_MMCR + 32(r9)
1703 mtspr SPRN_MMCRS, r4
1704 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1705 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1713 /* Restore host values of some registers */
1715 ld r5, STACK_SLOT_CIABR(r1)
1716 ld r6, STACK_SLOT_DAWR(r1)
1717 ld r7, STACK_SLOT_DAWRX(r1)
1718 mtspr SPRN_CIABR, r5
1720 mtspr SPRN_DAWRX, r7
1721 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1723 ld r5, STACK_SLOT_TID(r1)
1724 ld r6, STACK_SLOT_PSSCR(r1)
1725 ld r7, STACK_SLOT_PID(r1)
1726 ld r8, STACK_SLOT_IAMR(r1)
1728 mtspr SPRN_PSSCR, r6
1731 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1734 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1737 * POWER7/POWER8 guest -> host partition switch code.
1738 * We don't have to lock against tlbies but we do
1739 * have to coordinate the hardware threads.
1741 kvmhv_switch_to_host:
1742 /* Secondary threads wait for primary to do partition switch */
1743 ld r5,HSTATE_KVM_VCORE(r13)
1744 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1745 lbz r3,HSTATE_PTID(r13)
1749 13: lbz r3,VCORE_IN_GUEST(r5)
1755 /* Primary thread waits for all the secondaries to exit guest */
1756 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1757 rlwinm r0,r3,32-8,0xff
1763 /* Did we actually switch to the guest at all? */
1764 lbz r6, VCORE_IN_GUEST(r5)
1768 /* Primary thread switches back to host partition */
1769 lwz r7,KVM_HOST_LPID(r4)
1771 ld r6,KVM_HOST_SDR1(r4)
1772 li r8,LPID_RSVD /* switch to reserved LPID */
1775 mtspr SPRN_SDR1,r6 /* switch to host page table */
1776 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1781 /* DPDES and VTB are shared between threads */
1782 mfspr r7, SPRN_DPDES
1784 std r7, VCORE_DPDES(r5)
1785 std r8, VCORE_VTB(r5)
1786 /* clear DPDES so we don't get guest doorbells in the host */
1788 mtspr SPRN_DPDES, r8
1789 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1791 /* If HMI, call kvmppc_realmode_hmi_handler() */
1792 cmpwi r12, BOOK3S_INTERRUPT_HMI
1794 bl kvmppc_realmode_hmi_handler
1796 li r12, BOOK3S_INTERRUPT_HMI
1798 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1799 * the TB. Hence it is not required to subtract guest timebase
1800 * offset from timebase. So, skip it.
1802 * Also, do not call kvmppc_subcore_exit_guest() because it has
1803 * been invoked as part of kvmppc_realmode_hmi_handler().
1808 /* Subtract timebase offset from timebase */
1809 ld r8,VCORE_TB_OFFSET(r5)
1812 mftb r6 /* current guest timebase */
1814 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1815 mftb r7 /* check if lower 24 bits overflowed */
1820 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1823 17: bl kvmppc_subcore_exit_guest
1825 30: ld r5,HSTATE_KVM_VCORE(r13)
1826 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1829 ld r0, VCORE_PCR(r5)
1835 /* Signal secondary CPUs to continue */
1836 stb r0,VCORE_IN_GUEST(r5)
1837 19: lis r8,0x7fff /* MAX_INT@h */
1840 16: ld r8,KVM_HOST_LPCR(r4)
1844 /* load host SLB entries */
1845 BEGIN_MMU_FTR_SECTION
1847 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1848 ld r8,PACA_SLBSHADOWPTR(r13)
1850 .rept SLB_NUM_BOLTED
1851 li r3, SLBSHADOW_SAVEAREA
1855 andis. r7,r5,SLB_ESID_V@h
1861 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1862 /* Finish timing, if we have a vcpu */
1863 ld r4, HSTATE_KVM_VCPU(r13)
1867 bl kvmhv_accumulate_time
1870 /* Unset guest mode */
1871 li r0, KVM_GUEST_MODE_NONE
1872 stb r0, HSTATE_IN_GUEST(r13)
1874 ld r0, SFS+PPC_LR_STKOFF(r1)
1880 * Check whether an HDSI is an HPTE not found fault or something else.
1881 * If it is an HPTE not found fault that is due to the guest accessing
1882 * a page that they have mapped but which we have paged out, then
1883 * we continue on with the guest exit path. In all other cases,
1884 * reflect the HDSI to the guest as a DSI.
1888 lbz r0, KVM_RADIX(r3)
1891 mfspr r6, SPRN_HDSISR
1892 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
1893 /* HPTE not found fault or protection fault? */
1894 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1895 beq 1f /* if not, send it to the guest */
1896 andi. r0, r11, MSR_DR /* data relocation enabled? */
1899 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1901 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1903 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1904 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1905 bne 7f /* if no SLB entry found */
1906 4: std r4, VCPU_FAULT_DAR(r9)
1907 stw r6, VCPU_FAULT_DSISR(r9)
1909 /* Search the hash table. */
1910 mr r3, r9 /* vcpu pointer */
1911 li r7, 1 /* data fault */
1912 bl kvmppc_hpte_hv_fault
1913 ld r9, HSTATE_KVM_VCPU(r13)
1915 ld r11, VCPU_MSR(r9)
1916 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1917 cmpdi r3, 0 /* retry the instruction */
1919 cmpdi r3, -1 /* handle in kernel mode */
1921 cmpdi r3, -2 /* MMIO emulation; need instr word */
1924 /* Synthesize a DSI (or DSegI) for the guest */
1925 ld r4, VCPU_FAULT_DAR(r9)
1927 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1928 mtspr SPRN_DSISR, r6
1929 7: mtspr SPRN_DAR, r4
1930 mtspr SPRN_SRR0, r10
1931 mtspr SPRN_SRR1, r11
1933 bl kvmppc_msr_interrupt
1934 fast_interrupt_c_return:
1935 6: ld r7, VCPU_CTR(r9)
1942 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1943 ld r5, KVM_VRMA_SLB_V(r5)
1946 /* If this is for emulated MMIO, load the instruction word */
1947 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1949 /* Set guest mode to 'jump over instruction' so if lwz faults
1950 * we'll just continue at the next IP. */
1951 li r0, KVM_GUEST_MODE_SKIP
1952 stb r0, HSTATE_IN_GUEST(r13)
1954 /* Do the access with MSR:DR enabled */
1956 ori r4, r3, MSR_DR /* Enable paging for data */
1961 /* Store the result */
1962 stw r8, VCPU_LAST_INST(r9)
1964 /* Unset guest mode. */
1965 li r0, KVM_GUEST_MODE_HOST_HV
1966 stb r0, HSTATE_IN_GUEST(r13)
1970 std r4, VCPU_FAULT_DAR(r9)
1971 stw r6, VCPU_FAULT_DSISR(r9)
1974 std r5, VCPU_FAULT_GPA(r9)
1978 * Similarly for an HISI, reflect it to the guest as an ISI unless
1979 * it is an HPTE not found fault for a page that we have paged out.
1983 lbz r0, KVM_RADIX(r3)
1985 bne .Lradix_hisi /* for radix, just save ASDR */
1986 andis. r0, r11, SRR1_ISI_NOPT@h
1988 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1991 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1993 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1995 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1996 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1997 bne 7f /* if no SLB entry found */
1999 /* Search the hash table. */
2000 mr r3, r9 /* vcpu pointer */
2003 li r7, 0 /* instruction fault */
2004 bl kvmppc_hpte_hv_fault
2005 ld r9, HSTATE_KVM_VCPU(r13)
2007 ld r11, VCPU_MSR(r9)
2008 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2009 cmpdi r3, 0 /* retry the instruction */
2010 beq fast_interrupt_c_return
2011 cmpdi r3, -1 /* handle in kernel mode */
2014 /* Synthesize an ISI (or ISegI) for the guest */
2016 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2017 7: mtspr SPRN_SRR0, r10
2018 mtspr SPRN_SRR1, r11
2020 bl kvmppc_msr_interrupt
2021 b fast_interrupt_c_return
2023 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2024 ld r5, KVM_VRMA_SLB_V(r6)
2028 * Try to handle an hcall in real mode.
2029 * Returns to the guest if we handle it, or continues on up to
2030 * the kernel if we can't (i.e. if we don't have a handler for
2031 * it, or if the handler returns H_TOO_HARD).
2033 * r5 - r8 contain hcall args,
2034 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2036 hcall_try_real_mode:
2037 ld r3,VCPU_GPR(R3)(r9)
2039 /* sc 1 from userspace - reflect to guest syscall */
2040 bne sc_1_fast_return
2042 cmpldi r3,hcall_real_table_end - hcall_real_table
2044 /* See if this hcall is enabled for in-kernel handling */
2046 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2047 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2049 ld r0, KVM_ENABLED_HCALLS(r4)
2050 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2054 /* Get pointer to handler, if any, and call it */
2055 LOAD_REG_ADDR(r4, hcall_real_table)
2061 mr r3,r9 /* get vcpu pointer */
2062 ld r4,VCPU_GPR(R4)(r9)
2065 beq hcall_real_fallback
2066 ld r4,HSTATE_KVM_VCPU(r13)
2067 std r3,VCPU_GPR(R3)(r4)
2075 li r10, BOOK3S_INTERRUPT_SYSCALL
2076 bl kvmppc_msr_interrupt
2080 /* We've attempted a real mode hcall, but it's punted it back
2081 * to userspace. We need to restore some clobbered volatiles
2082 * before resuming the pass-it-to-qemu path */
2083 hcall_real_fallback:
2084 li r12,BOOK3S_INTERRUPT_SYSCALL
2085 ld r9, HSTATE_KVM_VCPU(r13)
2089 .globl hcall_real_table
2091 .long 0 /* 0 - unused */
2092 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2093 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2094 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2095 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2096 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2097 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2098 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2099 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2100 .long 0 /* 0x24 - H_SET_SPRG0 */
2101 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2116 #ifdef CONFIG_KVM_XICS
2117 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2118 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2119 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2120 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2121 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2123 .long 0 /* 0x64 - H_EOI */
2124 .long 0 /* 0x68 - H_CPPR */
2125 .long 0 /* 0x6c - H_IPI */
2126 .long 0 /* 0x70 - H_IPOLL */
2127 .long 0 /* 0x74 - H_XIRR */
2155 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2156 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2172 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2176 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2177 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2178 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2290 #ifdef CONFIG_KVM_XICS
2291 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2293 .long 0 /* 0x2fc - H_XIRR_X*/
2295 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2296 .globl hcall_real_table_end
2297 hcall_real_table_end:
2299 _GLOBAL(kvmppc_h_set_xdabr)
2300 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2302 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2305 6: li r3, H_PARAMETER
2308 _GLOBAL(kvmppc_h_set_dabr)
2309 li r5, DABRX_USER | DABRX_KERNEL
2313 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2314 std r4,VCPU_DABR(r3)
2315 stw r5, VCPU_DABRX(r3)
2316 mtspr SPRN_DABRX, r5
2317 /* Work around P7 bug where DABR can get corrupted on mtspr */
2318 1: mtspr SPRN_DABR,r4
2326 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2327 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2328 rlwimi r5, r4, 2, DAWRX_WT
2330 std r4, VCPU_DAWR(r3)
2331 std r5, VCPU_DAWRX(r3)
2333 mtspr SPRN_DAWRX, r5
2337 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2339 std r11,VCPU_MSR(r3)
2341 stb r0,VCPU_CEDED(r3)
2342 sync /* order setting ceded vs. testing prodded */
2343 lbz r5,VCPU_PRODDED(r3)
2345 bne kvm_cede_prodded
2346 li r12,0 /* set trap to 0 to say hcall is handled */
2347 stw r12,VCPU_TRAP(r3)
2349 std r0,VCPU_GPR(R3)(r3)
2352 * Set our bit in the bitmask of napping threads unless all the
2353 * other threads are already napping, in which case we send this
2356 ld r5,HSTATE_KVM_VCORE(r13)
2357 lbz r6,HSTATE_PTID(r13)
2358 lwz r8,VCORE_ENTRY_EXIT(r5)
2362 addi r6,r5,VCORE_NAPPING_THREADS
2369 /* order napping_threads update vs testing entry_exit_map */
2372 stb r0,HSTATE_NAPPING(r13)
2373 lwz r7,VCORE_ENTRY_EXIT(r5)
2375 bge 33f /* another thread already exiting */
2378 * Although not specifically required by the architecture, POWER7
2379 * preserves the following registers in nap mode, even if an SMT mode
2380 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2381 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2383 /* Save non-volatile GPRs */
2384 std r14, VCPU_GPR(R14)(r3)
2385 std r15, VCPU_GPR(R15)(r3)
2386 std r16, VCPU_GPR(R16)(r3)
2387 std r17, VCPU_GPR(R17)(r3)
2388 std r18, VCPU_GPR(R18)(r3)
2389 std r19, VCPU_GPR(R19)(r3)
2390 std r20, VCPU_GPR(R20)(r3)
2391 std r21, VCPU_GPR(R21)(r3)
2392 std r22, VCPU_GPR(R22)(r3)
2393 std r23, VCPU_GPR(R23)(r3)
2394 std r24, VCPU_GPR(R24)(r3)
2395 std r25, VCPU_GPR(R25)(r3)
2396 std r26, VCPU_GPR(R26)(r3)
2397 std r27, VCPU_GPR(R27)(r3)
2398 std r28, VCPU_GPR(R28)(r3)
2399 std r29, VCPU_GPR(R29)(r3)
2400 std r30, VCPU_GPR(R30)(r3)
2401 std r31, VCPU_GPR(R31)(r3)
2406 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2408 ld r9, HSTATE_KVM_VCPU(r13)
2410 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2414 * Set DEC to the smaller of DEC and HDEC, so that we wake
2415 * no later than the end of our timeslice (HDEC interrupts
2416 * don't wake us from nap).
2422 /* On P9 check whether the guest has large decrementer mode enabled */
2423 ld r6, HSTATE_KVM_VCORE(r13)
2424 ld r6, VCORE_LPCR(r6)
2425 andis. r6, r6, LPCR_LD@h
2427 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2434 /* save expiry time of guest decrementer */
2436 ld r4, HSTATE_KVM_VCPU(r13)
2437 ld r5, HSTATE_KVM_VCORE(r13)
2438 ld r6, VCORE_TB_OFFSET(r5)
2439 subf r3, r6, r3 /* convert to host TB value */
2440 std r3, VCPU_DEC_EXPIRES(r4)
2442 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2443 ld r4, HSTATE_KVM_VCPU(r13)
2444 addi r3, r4, VCPU_TB_CEDE
2445 bl kvmhv_accumulate_time
2448 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2451 * Take a nap until a decrementer or external or doobell interrupt
2452 * occurs, with PECE1 and PECE0 set in LPCR.
2453 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2454 * Also clear the runlatch bit before napping.
2457 mfspr r0, SPRN_CTRLF
2459 mtspr SPRN_CTRLT, r0
2462 stb r0,HSTATE_HWTHREAD_REQ(r13)
2464 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2466 ori r5, r5, LPCR_PECEDH
2467 rlwimi r5, r3, 0, LPCR_PECEDP
2468 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2470 kvm_nap_sequence: /* desired LPCR value in r5 */
2473 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2474 * enable state loss = 1 (allow SMT mode switch)
2475 * requested level = 0 (just stop dispatching)
2477 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2478 mtspr SPRN_PSSCR, r3
2479 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2480 li r4, LPCR_PECE_HVEE@higher
2483 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2487 std r0, HSTATE_SCRATCH0(r13)
2489 ld r0, HSTATE_SCRATCH0(r13)
2496 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2505 /* get vcpu pointer */
2506 ld r4, HSTATE_KVM_VCPU(r13)
2508 /* Woken by external or decrementer interrupt */
2509 ld r1, HSTATE_HOST_R1(r13)
2511 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2512 addi r3, r4, VCPU_TB_RMINTR
2513 bl kvmhv_accumulate_time
2516 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2518 bl kvmppc_restore_tm
2519 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2522 /* load up FP state */
2525 /* Restore guest decrementer */
2526 ld r3, VCPU_DEC_EXPIRES(r4)
2527 ld r5, HSTATE_KVM_VCORE(r13)
2528 ld r6, VCORE_TB_OFFSET(r5)
2529 add r3, r3, r6 /* convert host TB to guest TB value */
2535 ld r14, VCPU_GPR(R14)(r4)
2536 ld r15, VCPU_GPR(R15)(r4)
2537 ld r16, VCPU_GPR(R16)(r4)
2538 ld r17, VCPU_GPR(R17)(r4)
2539 ld r18, VCPU_GPR(R18)(r4)
2540 ld r19, VCPU_GPR(R19)(r4)
2541 ld r20, VCPU_GPR(R20)(r4)
2542 ld r21, VCPU_GPR(R21)(r4)
2543 ld r22, VCPU_GPR(R22)(r4)
2544 ld r23, VCPU_GPR(R23)(r4)
2545 ld r24, VCPU_GPR(R24)(r4)
2546 ld r25, VCPU_GPR(R25)(r4)
2547 ld r26, VCPU_GPR(R26)(r4)
2548 ld r27, VCPU_GPR(R27)(r4)
2549 ld r28, VCPU_GPR(R28)(r4)
2550 ld r29, VCPU_GPR(R29)(r4)
2551 ld r30, VCPU_GPR(R30)(r4)
2552 ld r31, VCPU_GPR(R31)(r4)
2554 /* Check the wake reason in SRR1 to see why we got here */
2555 bl kvmppc_check_wake_reason
2558 * Restore volatile registers since we could have called a
2559 * C routine in kvmppc_check_wake_reason
2561 * r3 tells us whether we need to return to host or not
2562 * WARNING: it gets checked further down:
2563 * should not modify r3 until this check is done.
2565 ld r4, HSTATE_KVM_VCPU(r13)
2567 /* clear our bit in vcore->napping_threads */
2568 34: ld r5,HSTATE_KVM_VCORE(r13)
2569 lbz r7,HSTATE_PTID(r13)
2572 addi r6,r5,VCORE_NAPPING_THREADS
2578 stb r0,HSTATE_NAPPING(r13)
2580 /* See if the wake reason saved in r3 means we need to exit */
2581 stw r12, VCPU_TRAP(r4)
2586 /* see if any other thread is already exiting */
2587 lwz r0,VCORE_ENTRY_EXIT(r5)
2591 b kvmppc_cede_reentry /* if not go back to guest */
2593 /* cede when already previously prodded case */
2596 stb r0,VCPU_PRODDED(r3)
2597 sync /* order testing prodded vs. clearing ceded */
2598 stb r0,VCPU_CEDED(r3)
2602 /* we've ceded but we want to give control to the host */
2604 ld r9, HSTATE_KVM_VCPU(r13)
2607 /* Try to handle a machine check in real mode */
2608 machine_check_realmode:
2609 mr r3, r9 /* get vcpu pointer */
2610 bl kvmppc_realmode_machine_check
2612 ld r9, HSTATE_KVM_VCPU(r13)
2613 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2615 * For the guest that is FWNMI capable, deliver all the MCE errors
2616 * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit
2617 * reason. This new approach injects machine check errors in guest
2618 * address space to guest with additional information in the form
2619 * of RTAS event, thus enabling guest kernel to suitably handle
2622 * For the guest that is not FWNMI capable (old QEMU) fallback
2623 * to old behaviour for backward compatibility:
2624 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either
2625 * through machine check interrupt (set HSRR0 to 0x200).
2626 * For handled errors (no-fatal), just go back to guest execution
2627 * with current HSRR0.
2628 * if we receive machine check with MSR(RI=0) then deliver it to
2629 * guest as machine check causing guest to crash.
2631 ld r11, VCPU_MSR(r9)
2632 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2633 bne mc_cont /* if so, exit to host */
2634 /* Check if guest is capable of handling NMI exit */
2635 ld r10, VCPU_KVM(r9)
2636 lbz r10, KVM_FWNMI(r10)
2637 cmpdi r10, 1 /* FWNMI capable? */
2638 beq mc_cont /* if so, exit with KVM_EXIT_NMI. */
2640 /* if not, fall through for backward compatibility. */
2641 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2642 beq 1f /* Deliver a machine check to guest */
2644 cmpdi r3, 0 /* Did we handle MCE ? */
2645 bne 2f /* Continue guest execution. */
2646 /* If not, deliver a machine check. SRR0/1 are already set */
2647 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2648 bl kvmppc_msr_interrupt
2649 2: b fast_interrupt_c_return
2652 * Check the reason we woke from nap, and take appropriate action.
2654 * 0 if nothing needs to be done
2655 * 1 if something happened that needs to be handled by the host
2656 * -1 if there was a guest wakeup (IPI or msgsnd)
2657 * -2 if we handled a PCI passthrough interrupt (returned by
2658 * kvmppc_read_intr only)
2660 * Also sets r12 to the interrupt vector for any interrupt that needs
2661 * to be handled now by the host (0x500 for external interrupt), or zero.
2662 * Modifies all volatile registers (since it may call a C function).
2663 * This routine calls kvmppc_read_intr, a C function, if an external
2664 * interrupt is pending.
2666 kvmppc_check_wake_reason:
2669 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2671 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2672 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2673 cmpwi r6, 8 /* was it an external interrupt? */
2674 beq 7f /* if so, see what it was */
2677 cmpwi r6, 6 /* was it the decrementer? */
2680 cmpwi r6, 5 /* privileged doorbell? */
2682 cmpwi r6, 3 /* hypervisor doorbell? */
2684 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2685 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2687 li r3, 1 /* anything else, return 1 */
2690 /* hypervisor doorbell */
2691 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2694 * Clear the doorbell as we will invoke the handler
2695 * explicitly in the guest exit path.
2697 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2699 /* see if it's a host IPI */
2701 lbz r0, HSTATE_HOST_IPI(r13)
2704 /* if not, return -1 */
2708 /* Woken up due to Hypervisor maintenance interrupt */
2709 4: li r12, BOOK3S_INTERRUPT_HMI
2713 /* external interrupt - create a stack frame so we can call C */
2715 std r0, PPC_LR_STKOFF(r1)
2716 stdu r1, -PPC_MIN_STKFRM(r1)
2719 li r12, BOOK3S_INTERRUPT_EXTERNAL
2724 * Return code of 2 means PCI passthrough interrupt, but
2725 * we need to return back to host to complete handling the
2726 * interrupt. Trap reason is expected in r12 by guest
2729 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2731 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2732 addi r1, r1, PPC_MIN_STKFRM
2737 * Save away FP, VMX and VSX registers.
2739 * N.B. r30 and r31 are volatile across this function,
2740 * thus it is not callable from C.
2747 #ifdef CONFIG_ALTIVEC
2749 oris r8,r8,MSR_VEC@h
2750 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2754 oris r8,r8,MSR_VSX@h
2755 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2758 addi r3,r3,VCPU_FPRS
2760 #ifdef CONFIG_ALTIVEC
2762 addi r3,r31,VCPU_VRS
2764 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2766 mfspr r6,SPRN_VRSAVE
2767 stw r6,VCPU_VRSAVE(r31)
2772 * Load up FP, VMX and VSX registers
2774 * N.B. r30 and r31 are volatile across this function,
2775 * thus it is not callable from C.
2782 #ifdef CONFIG_ALTIVEC
2784 oris r8,r8,MSR_VEC@h
2785 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2789 oris r8,r8,MSR_VSX@h
2790 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2793 addi r3,r4,VCPU_FPRS
2795 #ifdef CONFIG_ALTIVEC
2797 addi r3,r31,VCPU_VRS
2799 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2801 lwz r7,VCPU_VRSAVE(r31)
2802 mtspr SPRN_VRSAVE,r7
2807 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2809 * Save transactional state and TM-related registers.
2810 * Called with r9 pointing to the vcpu struct.
2811 * This can modify all checkpointed registers, but
2812 * restores r1, r2 and r9 (vcpu pointer) before exit.
2816 std r0, PPC_LR_STKOFF(r1)
2821 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2825 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2826 beq 1f /* TM not active in guest. */
2828 std r1, HSTATE_HOST_R1(r13)
2829 li r3, TM_CAUSE_KVM_RESCHED
2831 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2835 /* All GPRs are volatile at this point. */
2838 /* Temporarily store r13 and r9 so we have some regs to play with */
2841 std r9, PACATMSCRATCH(r13)
2842 ld r9, HSTATE_KVM_VCPU(r13)
2844 /* Get a few more GPRs free. */
2845 std r29, VCPU_GPRS_TM(29)(r9)
2846 std r30, VCPU_GPRS_TM(30)(r9)
2847 std r31, VCPU_GPRS_TM(31)(r9)
2849 /* Save away PPR and DSCR soon so don't run with user values. */
2852 mfspr r30, SPRN_DSCR
2853 ld r29, HSTATE_DSCR(r13)
2854 mtspr SPRN_DSCR, r29
2856 /* Save all but r9, r13 & r29-r31 */
2859 .if (reg != 9) && (reg != 13)
2860 std reg, VCPU_GPRS_TM(reg)(r9)
2864 /* ... now save r13 */
2866 std r4, VCPU_GPRS_TM(13)(r9)
2867 /* ... and save r9 */
2868 ld r4, PACATMSCRATCH(r13)
2869 std r4, VCPU_GPRS_TM(9)(r9)
2871 /* Reload stack pointer and TOC. */
2872 ld r1, HSTATE_HOST_R1(r13)
2875 /* Set MSR RI now we have r1 and r13 back. */
2879 /* Save away checkpinted SPRs. */
2880 std r31, VCPU_PPR_TM(r9)
2881 std r30, VCPU_DSCR_TM(r9)
2888 std r5, VCPU_LR_TM(r9)
2889 stw r6, VCPU_CR_TM(r9)
2890 std r7, VCPU_CTR_TM(r9)
2891 std r8, VCPU_AMR_TM(r9)
2892 std r10, VCPU_TAR_TM(r9)
2893 std r11, VCPU_XER_TM(r9)
2895 /* Restore r12 as trap number. */
2896 lwz r12, VCPU_TRAP(r9)
2899 addi r3, r9, VCPU_FPRS_TM
2901 addi r3, r9, VCPU_VRS_TM
2903 mfspr r6, SPRN_VRSAVE
2904 stw r6, VCPU_VRSAVE_TM(r9)
2907 * We need to save these SPRs after the treclaim so that the software
2908 * error code is recorded correctly in the TEXASR. Also the user may
2909 * change these outside of a transaction, so they must always be
2912 mfspr r5, SPRN_TFHAR
2913 mfspr r6, SPRN_TFIAR
2914 mfspr r7, SPRN_TEXASR
2915 std r5, VCPU_TFHAR(r9)
2916 std r6, VCPU_TFIAR(r9)
2917 std r7, VCPU_TEXASR(r9)
2919 ld r0, PPC_LR_STKOFF(r1)
2924 * Restore transactional state and TM-related registers.
2925 * Called with r4 pointing to the vcpu struct.
2926 * This potentially modifies all checkpointed registers.
2927 * It restores r1, r2, r4 from the PACA.
2931 std r0, PPC_LR_STKOFF(r1)
2933 /* Turn on TM/FP/VSX/VMX so we can restore them. */
2939 oris r5, r5, (MSR_VEC | MSR_VSX)@h
2943 * The user may change these outside of a transaction, so they must
2944 * always be context switched.
2946 ld r5, VCPU_TFHAR(r4)
2947 ld r6, VCPU_TFIAR(r4)
2948 ld r7, VCPU_TEXASR(r4)
2949 mtspr SPRN_TFHAR, r5
2950 mtspr SPRN_TFIAR, r6
2951 mtspr SPRN_TEXASR, r7
2954 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2955 beqlr /* TM not active in guest */
2956 std r1, HSTATE_HOST_R1(r13)
2958 /* Make sure the failure summary is set, otherwise we'll program check
2959 * when we trechkpt. It's possible that this might have been not set
2960 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
2963 oris r7, r7, (TEXASR_FS)@h
2964 mtspr SPRN_TEXASR, r7
2967 * We need to load up the checkpointed state for the guest.
2968 * We need to do this early as it will blow away any GPRs, VSRs and
2973 addi r3, r31, VCPU_FPRS_TM
2975 addi r3, r31, VCPU_VRS_TM
2978 lwz r7, VCPU_VRSAVE_TM(r4)
2979 mtspr SPRN_VRSAVE, r7
2981 ld r5, VCPU_LR_TM(r4)
2982 lwz r6, VCPU_CR_TM(r4)
2983 ld r7, VCPU_CTR_TM(r4)
2984 ld r8, VCPU_AMR_TM(r4)
2985 ld r9, VCPU_TAR_TM(r4)
2986 ld r10, VCPU_XER_TM(r4)
2995 * Load up PPR and DSCR values but don't put them in the actual SPRs
2996 * till the last moment to avoid running with userspace PPR and DSCR for
2999 ld r29, VCPU_DSCR_TM(r4)
3000 ld r30, VCPU_PPR_TM(r4)
3002 std r2, PACATMSCRATCH(r13) /* Save TOC */
3004 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3008 /* Load GPRs r0-r28 */
3011 ld reg, VCPU_GPRS_TM(reg)(r31)
3015 mtspr SPRN_DSCR, r29
3018 /* Load final GPRs */
3019 ld 29, VCPU_GPRS_TM(29)(r31)
3020 ld 30, VCPU_GPRS_TM(30)(r31)
3021 ld 31, VCPU_GPRS_TM(31)(r31)
3023 /* TM checkpointed state is now setup. All GPRs are now volatile. */
3026 /* Now let's get back the state we need. */
3029 ld r29, HSTATE_DSCR(r13)
3030 mtspr SPRN_DSCR, r29
3031 ld r4, HSTATE_KVM_VCPU(r13)
3032 ld r1, HSTATE_HOST_R1(r13)
3033 ld r2, PACATMSCRATCH(r13)
3035 /* Set the MSR RI since we have our registers back. */
3039 ld r0, PPC_LR_STKOFF(r1)
3045 * We come here if we get any exception or interrupt while we are
3046 * executing host real mode code while in guest MMU context.
3047 * For now just spin, but we should do something better.
3049 kvmppc_bad_host_intr:
3053 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3054 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3055 * r11 has the guest MSR value (in/out)
3056 * r9 has a vcpu pointer (in)
3057 * r0 is used as a scratch register
3059 kvmppc_msr_interrupt:
3060 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3061 cmpwi r0, 2 /* Check if we are in transactional state.. */
3062 ld r11, VCPU_INTR_MSR(r9)
3064 /* ... if transactional, change to suspended */
3066 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3070 * This works around a hardware bug on POWER8E processors, where
3071 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3072 * performance monitor interrupt. Instead, when we need to have
3073 * an interrupt pending, we have to arrange for a counter to overflow.
3077 mtspr SPRN_MMCR2, r3
3078 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3079 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3080 mtspr SPRN_MMCR0, r3
3087 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3089 * Start timing an activity
3090 * r3 = pointer to time accumulation struct, r4 = vcpu
3093 ld r5, HSTATE_KVM_VCORE(r13)
3094 lbz r6, VCORE_IN_GUEST(r5)
3096 beq 5f /* if in guest, need to */
3097 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3100 std r3, VCPU_CUR_ACTIVITY(r4)
3101 std r5, VCPU_ACTIVITY_START(r4)
3105 * Accumulate time to one activity and start another.
3106 * r3 = pointer to new time accumulation struct, r4 = vcpu
3108 kvmhv_accumulate_time:
3109 ld r5, HSTATE_KVM_VCORE(r13)
3110 lbz r8, VCORE_IN_GUEST(r5)
3112 beq 4f /* if in guest, need to */
3113 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3114 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3115 ld r6, VCPU_ACTIVITY_START(r4)
3116 std r3, VCPU_CUR_ACTIVITY(r4)
3119 std r7, VCPU_ACTIVITY_START(r4)
3123 ld r8, TAS_SEQCOUNT(r5)
3126 std r8, TAS_SEQCOUNT(r5)
3128 ld r7, TAS_TOTAL(r5)
3130 std r7, TAS_TOTAL(r5)
3136 3: std r3, TAS_MIN(r5)
3142 std r8, TAS_SEQCOUNT(r5)