2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
31 #include <asm/export.h>
34 #include <asm/xive-regs.h>
35 #include <asm/thread_info.h>
36 #include <asm/asm-compat.h>
37 #include <asm/feature-fixups.h>
38 #include <asm/cpuidle.h>
40 /* Sign-extend HDEC if not on POWER9 */
41 #define EXTEND_HDEC(reg) \
44 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
46 /* Values in HSTATE_NAPPING(r13) */
47 #define NAPPING_CEDE 1
48 #define NAPPING_NOVCPU 2
49 #define NAPPING_UNSPLIT 3
51 /* Stack frame offsets for kvmppc_hv_entry */
53 #define STACK_SLOT_TRAP (SFS-4)
54 #define STACK_SLOT_SHORT_PATH (SFS-8)
55 #define STACK_SLOT_TID (SFS-16)
56 #define STACK_SLOT_PSSCR (SFS-24)
57 #define STACK_SLOT_PID (SFS-32)
58 #define STACK_SLOT_IAMR (SFS-40)
59 #define STACK_SLOT_CIABR (SFS-48)
60 #define STACK_SLOT_DAWR (SFS-56)
61 #define STACK_SLOT_DAWRX (SFS-64)
62 #define STACK_SLOT_HFSCR (SFS-72)
63 #define STACK_SLOT_AMR (SFS-80)
64 #define STACK_SLOT_UAMOR (SFS-88)
65 /* the following is used by the P9 short path */
66 #define STACK_SLOT_NVGPRS (SFS-152) /* 18 gprs */
69 * Call kvmppc_hv_entry in real mode.
70 * Must be called with interrupts hard-disabled.
74 * LR = return address to continue at after eventually re-enabling MMU
76 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
78 std r0, PPC_LR_STKOFF(r1)
81 std r10, HSTATE_HOST_MSR(r13)
82 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
87 mtmsrd r0,1 /* clear RI in MSR */
94 /* On P9, do LPCR setting, if necessary */
95 ld r3, HSTATE_SPLIT_MODE(r13)
98 lwz r4, KVM_SPLIT_DO_SET(r3)
104 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
106 ld r4, HSTATE_KVM_VCPU(r13)
109 /* Back from guest - restore host state and return to caller */
112 /* Restore host DABR and DABRX */
113 ld r5,HSTATE_DABR(r13)
117 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
120 ld r3,PACA_SPRG_VDSO(r13)
121 mtspr SPRN_SPRG_VDSO_WRITE,r3
123 /* Reload the host's PMU registers */
124 bl kvmhv_load_host_pmu
127 * Reload DEC. HDEC interrupts were disabled when
128 * we reloaded the host's LPCR value.
130 ld r3, HSTATE_DECEXP(r13)
135 /* hwthread_req may have got set by cede or no vcpu, so clear it */
137 stb r0, HSTATE_HWTHREAD_REQ(r13)
140 * For external interrupts we need to call the Linux
141 * handler to process the interrupt. We do that by jumping
142 * to absolute address 0x500 for external interrupts.
143 * The [h]rfid at the end of the handler will return to
144 * the book3s_hv_interrupts.S code. For other interrupts
145 * we do the rfid to get back to the book3s_hv_interrupts.S
148 ld r8, 112+PPC_LR_STKOFF(r1)
150 ld r7, HSTATE_HOST_MSR(r13)
152 /* Return the trap number on this thread as the return value */
156 * If we came back from the guest via a relocation-on interrupt,
157 * we will be in virtual mode at this point, which makes it a
158 * little easier to get back to the caller.
161 andi. r0, r0, MSR_IR /* in real mode? */
164 /* RFI into the highmem handler */
168 mtmsrd r6, 1 /* Clear RI in MSR */
173 /* Virtual-mode return */
178 kvmppc_primary_no_guest:
179 /* We handle this much like a ceded vcpu */
180 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
181 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
182 /* HDEC value came from DEC in the first place, it will fit */
186 * Make sure the primary has finished the MMU switch.
187 * We should never get here on a secondary thread, but
188 * check it for robustness' sake.
190 ld r5, HSTATE_KVM_VCORE(r13)
191 65: lbz r0, VCORE_IN_GUEST(r5)
198 /* set our bit in napping_threads */
199 ld r5, HSTATE_KVM_VCORE(r13)
200 lbz r7, HSTATE_PTID(r13)
203 addi r6, r5, VCORE_NAPPING_THREADS
208 /* order napping_threads update vs testing entry_exit_map */
211 lwz r7, VCORE_ENTRY_EXIT(r5)
213 bge kvm_novcpu_exit /* another thread already exiting */
214 li r3, NAPPING_NOVCPU
215 stb r3, HSTATE_NAPPING(r13)
217 li r3, 0 /* Don't wake on privileged (OS) doorbell */
222 * Entered from kvm_start_guest if kvm_hstate.napping is set
228 ld r1, HSTATE_HOST_R1(r13)
229 ld r5, HSTATE_KVM_VCORE(r13)
231 stb r0, HSTATE_NAPPING(r13)
233 /* check the wake reason */
234 bl kvmppc_check_wake_reason
237 * Restore volatile registers since we could have called
238 * a C routine in kvmppc_check_wake_reason.
241 ld r5, HSTATE_KVM_VCORE(r13)
243 /* see if any other thread is already exiting */
244 lwz r0, VCORE_ENTRY_EXIT(r5)
248 /* clear our bit in napping_threads */
249 lbz r7, HSTATE_PTID(r13)
252 addi r6, r5, VCORE_NAPPING_THREADS
258 /* See if the wake reason means we need to exit */
262 /* See if our timeslice has expired (HDEC is negative) */
265 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
269 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
270 ld r4, HSTATE_KVM_VCPU(r13)
272 beq kvmppc_primary_no_guest
274 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
275 addi r3, r4, VCPU_TB_RMENTRY
276 bl kvmhv_start_timing
281 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
282 ld r4, HSTATE_KVM_VCPU(r13)
285 addi r3, r4, VCPU_TB_RMEXIT
286 bl kvmhv_accumulate_time
289 stw r12, STACK_SLOT_TRAP(r1)
290 bl kvmhv_commence_exit
292 b kvmhv_switch_to_host
295 * We come in here when wakened from Linux offline idle code.
297 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
299 _GLOBAL(idle_kvm_start_guest)
300 ld r4,PACAEMERGSP(r13)
306 subi r1,r4,STACK_FRAME_OVERHEAD
310 * Could avoid this and pass it through in r3. For now,
311 * code expects it to be in SRR1.
316 stb r0,PACA_FTRACE_ENABLED(r13)
318 li r0,KVM_HWTHREAD_IN_KVM
319 stb r0,HSTATE_HWTHREAD_STATE(r13)
321 /* kvm cede / napping does not come through here */
322 lbz r0,HSTATE_NAPPING(r13)
329 stb r0, HSTATE_NAPPING(r13)
334 * We weren't napping due to cede, so this must be a secondary
335 * thread being woken up to run a guest, or being woken up due
336 * to a stray IPI. (Or due to some machine check or hypervisor
337 * maintenance interrupt while the core is in KVM.)
340 /* Check the wake reason in SRR1 to see why we got here */
341 bl kvmppc_check_wake_reason
343 * kvmppc_check_wake_reason could invoke a C routine, but we
344 * have no volatile registers to restore when we return.
350 /* get vcore pointer, NULL if we have nothing to run */
351 ld r5,HSTATE_KVM_VCORE(r13)
353 /* if we have no vcore to run, go back to sleep */
356 kvm_secondary_got_guest:
358 /* Set HSTATE_DSCR(r13) to something sensible */
359 ld r6, PACA_DSCR_DEFAULT(r13)
360 std r6, HSTATE_DSCR(r13)
362 /* On thread 0 of a subcore, set HDEC to max */
363 lbz r4, HSTATE_PTID(r13)
366 LOAD_REG_ADDR(r6, decrementer_max)
369 /* and set per-LPAR registers, if doing dynamic micro-threading */
370 ld r6, HSTATE_SPLIT_MODE(r13)
374 ld r0, KVM_SPLIT_RPR(r6)
376 ld r0, KVM_SPLIT_PMMAR(r6)
378 ld r0, KVM_SPLIT_LDBAR(r6)
382 /* On P9 we use the split_info for coordinating LPCR changes */
383 lwz r4, KVM_SPLIT_DO_SET(r6)
390 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
392 /* Order load of vcpu after load of vcore */
394 ld r4, HSTATE_KVM_VCPU(r13)
397 /* Back from the guest, go back to nap */
398 /* Clear our vcpu and vcore pointers so we don't come back in early */
400 std r0, HSTATE_KVM_VCPU(r13)
402 * Once we clear HSTATE_KVM_VCORE(r13), the code in
403 * kvmppc_run_core() is going to assume that all our vcpu
404 * state is visible in memory. This lwsync makes sure
408 std r0, HSTATE_KVM_VCORE(r13)
411 * All secondaries exiting guest will fall through this path.
412 * Before proceeding, just check for HMI interrupt and
413 * invoke opal hmi handler. By now we are sure that the
414 * primary thread on this core/subcore has already made partition
415 * switch/TB resync and we are good to call opal hmi handler.
417 cmpwi r12, BOOK3S_INTERRUPT_HMI
420 li r3,0 /* NULL argument */
421 bl hmi_exception_realmode
423 * At this point we have finished executing in the guest.
424 * We need to wait for hwthread_req to become zero, since
425 * we may not turn on the MMU while hwthread_req is non-zero.
426 * While waiting we also need to check if we get given a vcpu to run.
429 lbz r3, HSTATE_HWTHREAD_REQ(r13)
433 li r0, KVM_HWTHREAD_IN_KERNEL
434 stb r0, HSTATE_HWTHREAD_STATE(r13)
435 /* need to recheck hwthread_req after a barrier, to avoid race */
437 lbz r3, HSTATE_HWTHREAD_REQ(r13)
442 * Jump to idle_return_gpr_loss, which returns to the
443 * idle_kvm_start_guest caller.
447 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
449 /* set up r3 for return */
452 addi r1, r1, STACK_FRAME_OVERHEAD
461 ld r5, HSTATE_KVM_VCORE(r13)
464 ld r3, HSTATE_SPLIT_MODE(r13)
467 lwz r0, KVM_SPLIT_DO_SET(r3)
470 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
473 lbz r0, KVM_SPLIT_DO_NAP(r3)
479 b kvm_secondary_got_guest
481 54: li r0, KVM_HWTHREAD_IN_KVM
482 stb r0, HSTATE_HWTHREAD_STATE(r13)
486 /* Set LPCR, LPIDR etc. on P9 */
494 bl kvmhv_p9_restore_lpcr
499 * Here the primary thread is trying to return the core to
500 * whole-core mode, so we need to nap.
504 * When secondaries are napping in kvm_unsplit_nap() with
505 * hwthread_req = 1, HMI goes ignored even though subcores are
506 * already exited the guest. Hence HMI keeps waking up secondaries
507 * from nap in a loop and secondaries always go back to nap since
508 * no vcore is assigned to them. This makes impossible for primary
509 * thread to get hold of secondary threads resulting into a soft
510 * lockup in KVM path.
512 * Let us check if HMI is pending and handle it before we go to nap.
514 cmpwi r12, BOOK3S_INTERRUPT_HMI
516 li r3, 0 /* NULL argument */
517 bl hmi_exception_realmode
520 * Ensure that secondary doesn't nap when it has
521 * its vcore pointer set.
523 sync /* matches smp_mb() before setting split_info.do_nap */
524 ld r0, HSTATE_KVM_VCORE(r13)
527 /* clear any pending message */
529 lis r6, (PPC_DBELL_SERVER << (63-36))@h
531 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
532 /* Set kvm_split_mode.napped[tid] = 1 */
533 ld r3, HSTATE_SPLIT_MODE(r13)
535 lbz r4, HSTATE_TID(r13)
536 addi r4, r4, KVM_SPLIT_NAPPED
538 /* Check the do_nap flag again after setting napped[] */
540 lbz r0, KVM_SPLIT_DO_NAP(r3)
543 li r3, NAPPING_UNSPLIT
544 stb r3, HSTATE_NAPPING(r13)
545 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
547 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
554 /******************************************************************************
558 *****************************************************************************/
560 .global kvmppc_hv_entry
565 * R4 = vcpu pointer (or NULL)
570 * all other volatile GPRS = free
571 * Does not preserve non-volatile GPRs or CR fields
574 std r0, PPC_LR_STKOFF(r1)
577 /* Save R1 in the PACA */
578 std r1, HSTATE_HOST_R1(r13)
580 li r6, KVM_GUEST_MODE_HOST_HV
581 stb r6, HSTATE_IN_GUEST(r13)
583 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
584 /* Store initial timestamp */
587 addi r3, r4, VCPU_TB_RMENTRY
588 bl kvmhv_start_timing
592 ld r5, HSTATE_KVM_VCORE(r13)
593 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
596 * POWER7/POWER8 host -> guest partition switch code.
597 * We don't have to lock against concurrent tlbies,
598 * but we do have to coordinate across hardware threads.
600 /* Set bit in entry map iff exit map is zero. */
602 lbz r6, HSTATE_PTID(r13)
604 addi r8, r5, VCORE_ENTRY_EXIT
606 cmpwi r3, 0x100 /* any threads starting to exit? */
607 bge secondary_too_late /* if so we're too late to the party */
612 /* Primary thread switches to guest partition. */
619 li r0,LPID_RSVD /* switch to reserved LPID */
622 mtspr SPRN_SDR1,r6 /* switch to partition page table */
623 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
627 /* See if we need to flush the TLB. */
628 mr r3, r9 /* kvm pointer */
629 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
630 li r5, 0 /* nested vcpu pointer */
631 bl kvmppc_check_need_tlb_flush
633 ld r5, HSTATE_KVM_VCORE(r13)
635 /* Add timebase offset onto timebase */
636 22: ld r8,VCORE_TB_OFFSET(r5)
639 std r8, VCORE_TB_OFFSET_APPL(r5)
640 mftb r6 /* current host timebase */
642 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
643 mftb r7 /* check if lower 24 bits overflowed */
648 addis r8,r8,0x100 /* if so, increment upper 40 bits */
651 /* Load guest PCR value to select appropriate compat mode */
652 37: ld r7, VCORE_PCR(r5)
659 /* DPDES and VTB are shared between threads */
660 ld r8, VCORE_DPDES(r5)
664 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
666 /* Mark the subcore state as inside guest */
667 bl kvmppc_subcore_enter_guest
669 ld r5, HSTATE_KVM_VCORE(r13)
670 ld r4, HSTATE_KVM_VCPU(r13)
672 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
674 /* Do we have a guest vcpu to run? */
676 beq kvmppc_primary_no_guest
678 /* Increment yield count if they have a VPA */
682 li r6, LPPACA_YIELDCOUNT
687 stb r6, VCPU_VPA_DIRTY(r4)
690 /* Save purr/spurr */
693 std r5,HSTATE_PURR(r13)
694 std r6,HSTATE_SPURR(r13)
700 /* Save host values of some registers */
705 std r5, STACK_SLOT_TID(r1)
706 std r6, STACK_SLOT_PSSCR(r1)
707 std r7, STACK_SLOT_PID(r1)
709 std r5, STACK_SLOT_HFSCR(r1)
710 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
716 std r5, STACK_SLOT_CIABR(r1)
717 std r6, STACK_SLOT_DAWR(r1)
718 std r7, STACK_SLOT_DAWRX(r1)
719 std r8, STACK_SLOT_IAMR(r1)
720 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
723 std r5, STACK_SLOT_AMR(r1)
725 std r6, STACK_SLOT_UAMOR(r1)
728 /* Set partition DABR */
729 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
730 lwz r5,VCPU_DABRX(r4)
735 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
737 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
739 * Branch around the call if both CPU_FTR_TM and
740 * CPU_FTR_P9_TM_HV_ASSIST are off.
744 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
746 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
750 li r5, 0 /* don't preserve non-vol regs */
751 bl kvmppc_restore_tm_hv
753 ld r4, HSTATE_KVM_VCPU(r13)
757 /* Load guest PMU registers; r4 = vcpu pointer here */
759 bl kvmhv_load_guest_pmu
761 /* Load up FP, VMX and VSX registers */
762 ld r4, HSTATE_KVM_VCPU(r13)
765 ld r14, VCPU_GPR(R14)(r4)
766 ld r15, VCPU_GPR(R15)(r4)
767 ld r16, VCPU_GPR(R16)(r4)
768 ld r17, VCPU_GPR(R17)(r4)
769 ld r18, VCPU_GPR(R18)(r4)
770 ld r19, VCPU_GPR(R19)(r4)
771 ld r20, VCPU_GPR(R20)(r4)
772 ld r21, VCPU_GPR(R21)(r4)
773 ld r22, VCPU_GPR(R22)(r4)
774 ld r23, VCPU_GPR(R23)(r4)
775 ld r24, VCPU_GPR(R24)(r4)
776 ld r25, VCPU_GPR(R25)(r4)
777 ld r26, VCPU_GPR(R26)(r4)
778 ld r27, VCPU_GPR(R27)(r4)
779 ld r28, VCPU_GPR(R28)(r4)
780 ld r29, VCPU_GPR(R29)(r4)
781 ld r30, VCPU_GPR(R30)(r4)
782 ld r31, VCPU_GPR(R31)(r4)
784 /* Switch DSCR to guest value */
789 /* Skip next section on POWER7 */
791 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
792 /* Load up POWER8-specific registers */
794 lwz r6, VCPU_PSPB(r4)
800 * Handle broken DAWR case by not writing it. This means we
801 * can still store the DAWR register for migration.
803 LOAD_REG_ADDR(r5, dawr_force_enable)
808 ld r6, VCPU_DAWRX(r4)
812 ld r7, VCPU_CIABR(r4)
817 ld r8, VCPU_EBBHR(r4)
820 ld r5, VCPU_EBBRR(r4)
821 ld r6, VCPU_BESCR(r4)
822 lwz r7, VCPU_GUEST_PID(r4)
829 /* POWER8-only registers */
830 ld r5, VCPU_TCSCR(r4)
832 ld r7, VCPU_CSIGR(r4)
840 /* POWER9-only registers */
842 ld r6, VCPU_PSSCR(r4)
843 lbz r8, HSTATE_FAKE_SUSPEND(r13)
844 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
845 rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG
846 ld r7, VCPU_HFSCR(r4)
850 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
853 ld r5, VCPU_SPRG0(r4)
854 ld r6, VCPU_SPRG1(r4)
855 ld r7, VCPU_SPRG2(r4)
856 ld r8, VCPU_SPRG3(r4)
862 /* Load up DAR and DSISR */
864 lwz r6, VCPU_DSISR(r4)
868 /* Restore AMR and UAMOR, set AMOR to all 1s */
876 /* Restore state of CTRL run bit; assume 1 on entry */
884 /* Secondary threads wait for primary to have done partition switch */
885 ld r5, HSTATE_KVM_VCORE(r13)
886 lbz r6, HSTATE_PTID(r13)
889 lbz r0, VCORE_IN_GUEST(r5)
893 20: lwz r3, VCORE_ENTRY_EXIT(r5)
896 lbz r0, VCORE_IN_GUEST(r5)
907 * Set the decrementer to the guest decrementer.
909 ld r8,VCPU_DEC_EXPIRES(r4)
910 /* r8 is a host timebase value here, convert to guest TB */
911 ld r5,HSTATE_KVM_VCORE(r13)
912 ld r6,VCORE_TB_OFFSET_APPL(r5)
918 /* Check if HDEC expires soon */
921 cmpdi r3, 512 /* 1 microsecond */
924 /* For hash guest, clear out and reload the SLB */
926 lbz r0, KVM_RADIX(r6)
934 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
935 lwz r5,VCPU_SLB_MAX(r4)
940 1: ld r8,VCPU_SLB_E(r6)
943 addi r6,r6,VCPU_SLB_SIZE
947 #ifdef CONFIG_KVM_XICS
948 /* We are entering the guest on that thread, push VCPU to XIVE */
949 ld r11, VCPU_XIVE_SAVED_STATE(r4)
951 lwz r8, VCPU_XIVE_CAM_WORD(r4)
952 li r7, TM_QW1_OS + TM_WORD2
954 andi. r0, r0, MSR_DR /* in real mode? */
956 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
963 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
970 stb r9, VCPU_XIVE_PUSHED(r4)
974 * We clear the irq_pending flag. There is a small chance of a
975 * race vs. the escalation interrupt happening on another
976 * processor setting it again, but the only consequence is to
977 * cause a spurrious wakeup on the next H_CEDE which is not an
981 stb r0, VCPU_IRQ_PENDING(r4)
984 * In single escalation mode, if the escalation interrupt is
987 lbz r0, VCPU_XIVE_ESC_ON(r4)
990 li r9, XIVE_ESB_SET_PQ_01
991 beq 4f /* in real mode? */
992 ld r10, VCPU_XIVE_ESC_VADDR(r4)
995 4: ld r10, VCPU_XIVE_ESC_RADDR(r4)
999 /* We have a possible subtle race here: The escalation interrupt might
1000 * have fired and be on its way to the host queue while we mask it,
1001 * and if we unmask it early enough (re-cede right away), there is
1002 * a theorical possibility that it fires again, thus landing in the
1003 * target queue more than once which is a big no-no.
1005 * Fortunately, solving this is rather easy. If the above load setting
1006 * PQ to 01 returns a previous value where P is set, then we know the
1007 * escalation interrupt is somewhere on its way to the host. In that
1008 * case we simply don't clear the xive_esc_on flag below. It will be
1009 * eventually cleared by the handler for the escalation interrupt.
1011 * Then, when doing a cede, we check that flag again before re-enabling
1012 * the escalation interrupt, and if set, we abort the cede.
1014 andi. r0, r0, XIVE_ESB_VAL_P
1017 /* Now P is 0, we can clear the flag */
1019 stb r0, VCPU_XIVE_ESC_ON(r4)
1022 #endif /* CONFIG_KVM_XICS */
1025 stw r0, STACK_SLOT_SHORT_PATH(r1)
1027 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
1028 /* Check if we can deliver an external or decrementer interrupt now */
1029 ld r0, VCPU_PENDING_EXC(r4)
1031 /* On POWER9, also check for emulated doorbell interrupt */
1032 lbz r3, VCPU_DBELL_REQ(r4)
1034 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1038 bl kvmppc_guest_entry_inject_int
1039 ld r4, HSTATE_KVM_VCPU(r13)
1041 ld r6, VCPU_SRR0(r4)
1042 ld r7, VCPU_SRR1(r4)
1048 ld r11, VCPU_MSR(r4)
1049 /* r11 = vcpu->arch.msr & ~MSR_HV */
1050 rldicl r11, r11, 63 - MSR_HV_LG, 1
1051 rotldi r11, r11, 1 + MSR_HV_LG
1052 ori r11, r11, MSR_ME
1062 * R10: value for HSRR0
1063 * R11: value for HSRR1
1068 stb r0,VCPU_CEDED(r4) /* cancel cede */
1069 mtspr SPRN_HSRR0,r10
1070 mtspr SPRN_HSRR1,r11
1072 /* Activate guest mode, so faults get handled by KVM */
1073 li r9, KVM_GUEST_MODE_GUEST_HV
1074 stb r9, HSTATE_IN_GUEST(r13)
1076 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1077 /* Accumulate timing */
1078 addi r3, r4, VCPU_TB_GUEST
1079 bl kvmhv_accumulate_time
1085 ld r5, VCPU_CFAR(r4)
1087 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1090 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1097 ld r1, VCPU_GPR(R1)(r4)
1098 ld r2, VCPU_GPR(R2)(r4)
1099 ld r3, VCPU_GPR(R3)(r4)
1100 ld r5, VCPU_GPR(R5)(r4)
1101 ld r6, VCPU_GPR(R6)(r4)
1102 ld r7, VCPU_GPR(R7)(r4)
1103 ld r8, VCPU_GPR(R8)(r4)
1104 ld r9, VCPU_GPR(R9)(r4)
1105 ld r10, VCPU_GPR(R10)(r4)
1106 ld r11, VCPU_GPR(R11)(r4)
1107 ld r12, VCPU_GPR(R12)(r4)
1108 ld r13, VCPU_GPR(R13)(r4)
1112 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1114 /* Move canary into DSISR to check for later */
1117 mtspr SPRN_HDSISR, r0
1118 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1120 ld r0, VCPU_GPR(R0)(r4)
1121 ld r4, VCPU_GPR(R4)(r4)
1126 * Enter the guest on a P9 or later system where we have exactly
1127 * one vcpu per vcore and we don't need to go to real mode
1128 * (which implies that host and guest are both using radix MMU mode).
1130 * Most SPRs and all the VSRs have been loaded already.
1132 _GLOBAL(__kvmhv_vcpu_entry_p9)
1133 EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9)
1135 std r0, PPC_LR_STKOFF(r1)
1139 stw r0, STACK_SLOT_SHORT_PATH(r1)
1141 std r3, HSTATE_KVM_VCPU(r13)
1145 std r1, HSTATE_HOST_R1(r13)
1149 std reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1155 ld reg, __VCPU_GPR(reg)(r3)
1160 std r10, HSTATE_HOST_MSR(r13)
1163 b fast_guest_entry_c
1164 guest_exit_short_path:
1166 li r0, KVM_GUEST_MODE_NONE
1167 stb r0, HSTATE_IN_GUEST(r13)
1171 std reg, __VCPU_GPR(reg)(r9)
1177 ld reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1184 mr r3, r12 /* trap number */
1187 ld r0, PPC_LR_STKOFF(r1)
1190 /* If we are in real mode, do a rfid to get back to the caller */
1192 andi. r5, r4, MSR_IR
1194 rldicl r5, r4, 64 - MSR_TS_S_LG, 62 /* extract TS field */
1196 ld r10, HSTATE_HOST_MSR(r13)
1197 rldimi r10, r5, MSR_TS_S_LG, 63 - MSR_TS_T_LG
1198 mtspr SPRN_SRR1, r10
1204 stw r12, STACK_SLOT_TRAP(r1)
1207 stw r12, VCPU_TRAP(r4)
1208 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1209 addi r3, r4, VCPU_TB_RMEXIT
1210 bl kvmhv_accumulate_time
1212 11: b kvmhv_switch_to_host
1219 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1220 12: stw r12, VCPU_TRAP(r4)
1222 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1223 addi r3, r4, VCPU_TB_RMEXIT
1224 bl kvmhv_accumulate_time
1228 /******************************************************************************
1232 *****************************************************************************/
1235 * We come here from the first-level interrupt handlers.
1237 .globl kvmppc_interrupt_hv
1238 kvmppc_interrupt_hv:
1240 * Register contents:
1241 * R12 = (guest CR << 32) | interrupt vector
1243 * guest R12 saved in shadow VCPU SCRATCH0
1244 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1245 * guest R13 saved in SPRN_SCRATCH0
1247 std r9, HSTATE_SCRATCH2(r13)
1248 lbz r9, HSTATE_IN_GUEST(r13)
1249 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1250 beq kvmppc_bad_host_intr
1251 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1252 cmpwi r9, KVM_GUEST_MODE_GUEST
1253 ld r9, HSTATE_SCRATCH2(r13)
1254 beq kvmppc_interrupt_pr
1256 /* We're now back in the host but in guest MMU context */
1257 li r9, KVM_GUEST_MODE_HOST_HV
1258 stb r9, HSTATE_IN_GUEST(r13)
1260 ld r9, HSTATE_KVM_VCPU(r13)
1262 /* Save registers */
1264 std r0, VCPU_GPR(R0)(r9)
1265 std r1, VCPU_GPR(R1)(r9)
1266 std r2, VCPU_GPR(R2)(r9)
1267 std r3, VCPU_GPR(R3)(r9)
1268 std r4, VCPU_GPR(R4)(r9)
1269 std r5, VCPU_GPR(R5)(r9)
1270 std r6, VCPU_GPR(R6)(r9)
1271 std r7, VCPU_GPR(R7)(r9)
1272 std r8, VCPU_GPR(R8)(r9)
1273 ld r0, HSTATE_SCRATCH2(r13)
1274 std r0, VCPU_GPR(R9)(r9)
1275 std r10, VCPU_GPR(R10)(r9)
1276 std r11, VCPU_GPR(R11)(r9)
1277 ld r3, HSTATE_SCRATCH0(r13)
1278 std r3, VCPU_GPR(R12)(r9)
1279 /* CR is in the high half of r12 */
1283 ld r3, HSTATE_CFAR(r13)
1284 std r3, VCPU_CFAR(r9)
1285 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1287 ld r4, HSTATE_PPR(r13)
1288 std r4, VCPU_PPR(r9)
1289 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1291 /* Restore R1/R2 so we can handle faults */
1292 ld r1, HSTATE_HOST_R1(r13)
1295 mfspr r10, SPRN_SRR0
1296 mfspr r11, SPRN_SRR1
1297 std r10, VCPU_SRR0(r9)
1298 std r11, VCPU_SRR1(r9)
1299 /* trap is in the low half of r12, clear CR from the high half */
1301 andi. r0, r12, 2 /* need to read HSRR0/1? */
1303 mfspr r10, SPRN_HSRR0
1304 mfspr r11, SPRN_HSRR1
1306 1: std r10, VCPU_PC(r9)
1307 std r11, VCPU_MSR(r9)
1311 std r3, VCPU_GPR(R13)(r9)
1314 stw r12,VCPU_TRAP(r9)
1317 * Now that we have saved away SRR0/1 and HSRR0/1,
1318 * interrupts are recoverable in principle, so set MSR_RI.
1319 * This becomes important for relocation-on interrupts from
1320 * the guest, which we can get in radix mode on POWER9.
1325 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1326 addi r3, r9, VCPU_TB_RMINTR
1328 bl kvmhv_accumulate_time
1329 ld r5, VCPU_GPR(R5)(r9)
1330 ld r6, VCPU_GPR(R6)(r9)
1331 ld r7, VCPU_GPR(R7)(r9)
1332 ld r8, VCPU_GPR(R8)(r9)
1335 /* Save HEIR (HV emulation assist reg) in emul_inst
1336 if this is an HEI (HV emulation interrupt, e40) */
1337 li r3,KVM_INST_FETCH_FAILED
1338 stw r3,VCPU_LAST_INST(r9)
1339 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1342 11: stw r3,VCPU_HEIR(r9)
1344 /* these are volatile across C function calls */
1345 #ifdef CONFIG_RELOCATABLE
1346 ld r3, HSTATE_SCRATCH1(r13)
1352 std r3, VCPU_CTR(r9)
1353 std r4, VCPU_XER(r9)
1355 /* Save more register state */
1358 std r3, VCPU_DAR(r9)
1359 stw r4, VCPU_DSISR(r9)
1361 /* If this is a page table miss then see if it's theirs or ours */
1362 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1364 std r3, VCPU_FAULT_DAR(r9)
1365 stw r4, VCPU_FAULT_DSISR(r9)
1366 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1369 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1370 /* For softpatch interrupt, go off and do TM instruction emulation */
1371 cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
1375 /* See if this is a leftover HDEC interrupt */
1376 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1382 bge fast_guest_return
1384 /* See if this is an hcall we can handle in real mode */
1385 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1386 beq hcall_try_real_mode
1388 /* Hypervisor doorbell - exit only if host IPI flag set */
1389 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1394 /* always exit if we're running a nested guest */
1395 ld r0, VCPU_NESTED(r9)
1398 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1399 lbz r0, HSTATE_HOST_IPI(r13)
1401 beq maybe_reenter_guest
1404 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1405 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1407 mfspr r3, SPRN_HFSCR
1408 std r3, VCPU_HFSCR(r9)
1411 /* External interrupt ? */
1412 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1413 beq kvmppc_guest_external
1414 /* See if it is a machine check */
1415 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1416 beq machine_check_realmode
1417 /* Or a hypervisor maintenance interrupt */
1418 cmpwi r12, BOOK3S_INTERRUPT_HMI
1421 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1423 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1424 addi r3, r9, VCPU_TB_RMEXIT
1426 bl kvmhv_accumulate_time
1428 #ifdef CONFIG_KVM_XICS
1429 /* We are exiting, pull the VP from the XIVE */
1430 lbz r0, VCPU_XIVE_PUSHED(r9)
1433 li r7, TM_SPC_PULL_OS_CTX
1436 andi. r0, r0, MSR_DR /* in real mode? */
1438 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1441 /* First load to pull the context, we ignore the value */
1444 /* Second load to recover the context state (Words 0 and 1) */
1447 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1450 /* First load to pull the context, we ignore the value */
1453 /* Second load to recover the context state (Words 0 and 1) */
1455 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1456 /* Fixup some of the state for the next load */
1459 stb r10, VCPU_XIVE_PUSHED(r9)
1460 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1461 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1464 #endif /* CONFIG_KVM_XICS */
1466 /* If we came in through the P9 short path, go back out to C now */
1467 lwz r0, STACK_SLOT_SHORT_PATH(r1)
1469 bne guest_exit_short_path
1471 /* For hash guest, read the guest SLB and save it away */
1473 lbz r0, KVM_RADIX(r5)
1476 bne 3f /* for radix, save 0 entries */
1477 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1482 andis. r0,r8,SLB_ESID_V@h
1484 add r8,r8,r6 /* put index in */
1486 std r8,VCPU_SLB_E(r7)
1487 std r3,VCPU_SLB_V(r7)
1488 addi r7,r7,VCPU_SLB_SIZE
1492 /* Finally clear out the SLB */
1497 3: stw r5,VCPU_SLB_MAX(r9)
1499 /* load host SLB entries */
1500 BEGIN_MMU_FTR_SECTION
1502 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1503 ld r8,PACA_SLBSHADOWPTR(r13)
1505 .rept SLB_NUM_BOLTED
1506 li r3, SLBSHADOW_SAVEAREA
1510 andis. r7,r5,SLB_ESID_V@h
1518 stw r12, STACK_SLOT_TRAP(r1)
1521 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1522 ld r3, HSTATE_KVM_VCORE(r13)
1525 /* On P9, if the guest has large decr enabled, don't sign extend */
1527 ld r4, VCORE_LPCR(r3)
1528 andis. r4, r4, LPCR_LD@h
1530 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1533 /* r5 is a guest timebase value here, convert to host TB */
1534 ld r4,VCORE_TB_OFFSET_APPL(r3)
1536 std r5,VCPU_DEC_EXPIRES(r9)
1538 /* Increment exit count, poke other threads to exit */
1540 bl kvmhv_commence_exit
1542 ld r9, HSTATE_KVM_VCPU(r13)
1544 /* Stop others sending VCPU interrupts to this physical CPU */
1546 stw r0, VCPU_CPU(r9)
1547 stw r0, VCPU_THREAD_CPU(r9)
1549 /* Save guest CTRL register, set runlatch to 1 */
1551 stw r6,VCPU_CTRL(r9)
1558 * Save the guest PURR/SPURR
1563 ld r8,VCPU_SPURR(r9)
1564 std r5,VCPU_PURR(r9)
1565 std r6,VCPU_SPURR(r9)
1570 * Restore host PURR/SPURR and add guest times
1571 * so that the time in the guest gets accounted.
1573 ld r3,HSTATE_PURR(r13)
1574 ld r4,HSTATE_SPURR(r13)
1582 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1583 /* Save POWER8-specific registers */
1587 std r5, VCPU_IAMR(r9)
1588 stw r6, VCPU_PSPB(r9)
1589 std r7, VCPU_FSCR(r9)
1593 std r7, VCPU_TAR(r9)
1594 mfspr r8, SPRN_EBBHR
1595 std r8, VCPU_EBBHR(r9)
1596 mfspr r5, SPRN_EBBRR
1597 mfspr r6, SPRN_BESCR
1600 std r5, VCPU_EBBRR(r9)
1601 std r6, VCPU_BESCR(r9)
1602 stw r7, VCPU_GUEST_PID(r9)
1603 std r8, VCPU_WORT(r9)
1605 mfspr r5, SPRN_TCSCR
1607 mfspr r7, SPRN_CSIGR
1609 std r5, VCPU_TCSCR(r9)
1610 std r6, VCPU_ACOP(r9)
1611 std r7, VCPU_CSIGR(r9)
1612 std r8, VCPU_TACR(r9)
1615 mfspr r6, SPRN_PSSCR
1616 std r5, VCPU_TID(r9)
1617 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1619 std r6, VCPU_PSSCR(r9)
1620 /* Restore host HFSCR value */
1621 ld r7, STACK_SLOT_HFSCR(r1)
1622 mtspr SPRN_HFSCR, r7
1623 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1625 * Restore various registers to 0, where non-zero values
1626 * set by the guest could disrupt the host.
1632 mtspr SPRN_TCSCR, r0
1633 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1636 mtspr SPRN_MMCRS, r0
1637 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1639 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1640 ld r8, STACK_SLOT_IAMR(r1)
1643 8: /* Power7 jumps back in here */
1647 std r6,VCPU_UAMOR(r9)
1648 ld r5,STACK_SLOT_AMR(r1)
1649 ld r6,STACK_SLOT_UAMOR(r1)
1651 mtspr SPRN_UAMOR, r6
1653 /* Switch DSCR back to host value */
1655 ld r7, HSTATE_DSCR(r13)
1656 std r8, VCPU_DSCR(r9)
1659 /* Save non-volatile GPRs */
1660 std r14, VCPU_GPR(R14)(r9)
1661 std r15, VCPU_GPR(R15)(r9)
1662 std r16, VCPU_GPR(R16)(r9)
1663 std r17, VCPU_GPR(R17)(r9)
1664 std r18, VCPU_GPR(R18)(r9)
1665 std r19, VCPU_GPR(R19)(r9)
1666 std r20, VCPU_GPR(R20)(r9)
1667 std r21, VCPU_GPR(R21)(r9)
1668 std r22, VCPU_GPR(R22)(r9)
1669 std r23, VCPU_GPR(R23)(r9)
1670 std r24, VCPU_GPR(R24)(r9)
1671 std r25, VCPU_GPR(R25)(r9)
1672 std r26, VCPU_GPR(R26)(r9)
1673 std r27, VCPU_GPR(R27)(r9)
1674 std r28, VCPU_GPR(R28)(r9)
1675 std r29, VCPU_GPR(R29)(r9)
1676 std r30, VCPU_GPR(R30)(r9)
1677 std r31, VCPU_GPR(R31)(r9)
1680 mfspr r3, SPRN_SPRG0
1681 mfspr r4, SPRN_SPRG1
1682 mfspr r5, SPRN_SPRG2
1683 mfspr r6, SPRN_SPRG3
1684 std r3, VCPU_SPRG0(r9)
1685 std r4, VCPU_SPRG1(r9)
1686 std r5, VCPU_SPRG2(r9)
1687 std r6, VCPU_SPRG3(r9)
1693 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1695 * Branch around the call if both CPU_FTR_TM and
1696 * CPU_FTR_P9_TM_HV_ASSIST are off.
1700 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
1702 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1706 li r5, 0 /* don't preserve non-vol regs */
1707 bl kvmppc_save_tm_hv
1709 ld r9, HSTATE_KVM_VCPU(r13)
1713 /* Increment yield count if they have a VPA */
1714 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1717 li r4, LPPACA_YIELDCOUNT
1722 stb r3, VCPU_VPA_DIRTY(r9)
1724 /* Save PMU registers if requested */
1725 /* r8 and cr0.eq are live here */
1728 beq 21f /* if no VPA, save PMU stuff anyway */
1729 lbz r4, LPPACA_PMCINUSE(r8)
1730 21: bl kvmhv_save_guest_pmu
1731 ld r9, HSTATE_KVM_VCPU(r13)
1733 /* Restore host values of some registers */
1735 ld r5, STACK_SLOT_CIABR(r1)
1736 ld r6, STACK_SLOT_DAWR(r1)
1737 ld r7, STACK_SLOT_DAWRX(r1)
1738 mtspr SPRN_CIABR, r5
1740 * If the DAWR doesn't work, it's ok to write these here as
1741 * this value should always be zero
1744 mtspr SPRN_DAWRX, r7
1745 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1747 ld r5, STACK_SLOT_TID(r1)
1748 ld r6, STACK_SLOT_PSSCR(r1)
1749 ld r7, STACK_SLOT_PID(r1)
1751 mtspr SPRN_PSSCR, r6
1753 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1755 #ifdef CONFIG_PPC_RADIX_MMU
1757 * Are we running hash or radix ?
1760 lbz r0, KVM_RADIX(r5)
1765 * Radix: do eieio; tlbsync; ptesync sequence in case we
1766 * interrupted the guest between a tlbie and a ptesync.
1772 /* Radix: Handle the case where the guest used an illegal PID */
1773 LOAD_REG_ADDR(r4, mmu_base_pid)
1774 lwz r3, VCPU_GUEST_PID(r9)
1780 * Illegal PID, the HW might have prefetched and cached in the TLB
1781 * some translations for the LPID 0 / guest PID combination which
1782 * Linux doesn't know about, so we need to flush that PID out of
1783 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1784 * the right context.
1790 /* Then do a congruence class local flush */
1792 lwz r0,KVM_TLB_SETS(r6)
1794 li r7,0x400 /* IS field = 0b01 */
1796 sldi r0,r3,32 /* RS has PID */
1797 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1803 #endif /* CONFIG_PPC_RADIX_MMU */
1806 * POWER7/POWER8 guest -> host partition switch code.
1807 * We don't have to lock against tlbies but we do
1808 * have to coordinate the hardware threads.
1809 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1811 kvmhv_switch_to_host:
1812 /* Secondary threads wait for primary to do partition switch */
1813 ld r5,HSTATE_KVM_VCORE(r13)
1814 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1815 lbz r3,HSTATE_PTID(r13)
1819 13: lbz r3,VCORE_IN_GUEST(r5)
1825 /* Primary thread waits for all the secondaries to exit guest */
1826 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1827 rlwinm r0,r3,32-8,0xff
1833 /* Did we actually switch to the guest at all? */
1834 lbz r6, VCORE_IN_GUEST(r5)
1838 /* Primary thread switches back to host partition */
1839 lwz r7,KVM_HOST_LPID(r4)
1841 ld r6,KVM_HOST_SDR1(r4)
1842 li r8,LPID_RSVD /* switch to reserved LPID */
1845 mtspr SPRN_SDR1,r6 /* switch to host page table */
1846 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1851 /* DPDES and VTB are shared between threads */
1852 mfspr r7, SPRN_DPDES
1854 std r7, VCORE_DPDES(r5)
1855 std r8, VCORE_VTB(r5)
1856 /* clear DPDES so we don't get guest doorbells in the host */
1858 mtspr SPRN_DPDES, r8
1859 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1861 /* Subtract timebase offset from timebase */
1862 ld r8, VCORE_TB_OFFSET_APPL(r5)
1866 std r0, VCORE_TB_OFFSET_APPL(r5)
1867 mftb r6 /* current guest timebase */
1869 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1870 mftb r7 /* check if lower 24 bits overflowed */
1875 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1880 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1881 * above, which may or may not have already called
1882 * kvmppc_subcore_exit_guest. Fortunately, all that
1883 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1884 * it again here is benign even if kvmppc_realmode_hmi_handler
1885 * has already called it.
1887 bl kvmppc_subcore_exit_guest
1889 30: ld r5,HSTATE_KVM_VCORE(r13)
1890 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1893 ld r0, VCORE_PCR(r5)
1899 /* Signal secondary CPUs to continue */
1900 stb r0,VCORE_IN_GUEST(r5)
1901 19: lis r8,0x7fff /* MAX_INT@h */
1906 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
1907 ld r3, HSTATE_SPLIT_MODE(r13)
1910 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
1913 bl kvmhv_p9_restore_lpcr
1917 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1918 ld r8,KVM_HOST_LPCR(r4)
1922 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1923 /* Finish timing, if we have a vcpu */
1924 ld r4, HSTATE_KVM_VCPU(r13)
1928 bl kvmhv_accumulate_time
1931 /* Unset guest mode */
1932 li r0, KVM_GUEST_MODE_NONE
1933 stb r0, HSTATE_IN_GUEST(r13)
1935 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1936 ld r0, SFS+PPC_LR_STKOFF(r1)
1941 kvmppc_guest_external:
1942 /* External interrupt, first check for host_ipi. If this is
1943 * set, we know the host wants us out so let's do it now
1948 * Restore the active volatile registers after returning from
1951 ld r9, HSTATE_KVM_VCPU(r13)
1952 li r12, BOOK3S_INTERRUPT_EXTERNAL
1955 * kvmppc_read_intr return codes:
1957 * Exit to host (r3 > 0)
1958 * 1 An interrupt is pending that needs to be handled by the host
1959 * Exit guest and return to host by branching to guest_exit_cont
1961 * 2 Passthrough that needs completion in the host
1962 * Exit guest and return to host by branching to guest_exit_cont
1963 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1964 * to indicate to the host to complete handling the interrupt
1966 * Before returning to guest, we check if any CPU is heading out
1967 * to the host and if so, we head out also. If no CPUs are heading
1968 * check return values <= 0.
1970 * Return to guest (r3 <= 0)
1971 * 0 No external interrupt is pending
1972 * -1 A guest wakeup IPI (which has now been cleared)
1973 * In either case, we return to guest to deliver any pending
1976 * -2 A PCI passthrough external interrupt was handled
1977 * (interrupt was delivered directly to guest)
1978 * Return to guest to deliver any pending guest interrupts.
1984 /* Return code = 2 */
1985 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1986 stw r12, VCPU_TRAP(r9)
1989 1: /* Return code <= 1 */
1993 /* Return code <= 0 */
1994 maybe_reenter_guest:
1995 ld r5, HSTATE_KVM_VCORE(r13)
1996 lwz r0, VCORE_ENTRY_EXIT(r5)
1999 blt deliver_guest_interrupt
2002 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2004 * Softpatch interrupt for transactional memory emulation cases
2005 * on POWER9 DD2.2. This is early in the guest exit path - we
2006 * haven't saved registers or done a treclaim yet.
2009 /* Save instruction image in HEIR */
2011 stw r3, VCPU_HEIR(r9)
2014 * The cases we want to handle here are those where the guest
2015 * is in real suspend mode and is trying to transition to
2016 * transactional mode.
2018 lbz r0, HSTATE_FAKE_SUSPEND(r13)
2019 cmpwi r0, 0 /* keep exiting guest if in fake suspend */
2021 rldicl r3, r11, 64 - MSR_TS_S_LG, 62
2022 cmpwi r3, 1 /* or if not in suspend state */
2025 /* Call C code to do the emulation */
2027 bl kvmhv_p9_tm_emulation_early
2029 ld r9, HSTATE_KVM_VCPU(r13)
2030 li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
2032 beq guest_exit_cont /* continue exiting if not handled */
2034 ld r11, VCPU_MSR(r9)
2035 b fast_interrupt_c_return /* go back to guest if handled */
2036 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2039 * Check whether an HDSI is an HPTE not found fault or something else.
2040 * If it is an HPTE not found fault that is due to the guest accessing
2041 * a page that they have mapped but which we have paged out, then
2042 * we continue on with the guest exit path. In all other cases,
2043 * reflect the HDSI to the guest as a DSI.
2047 lbz r0, KVM_RADIX(r3)
2049 mfspr r6, SPRN_HDSISR
2051 /* Look for DSISR canary. If we find it, retry instruction */
2054 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2056 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2057 /* HPTE not found fault or protection fault? */
2058 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2059 beq 1f /* if not, send it to the guest */
2060 andi. r0, r11, MSR_DR /* data relocation enabled? */
2063 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2065 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2067 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2068 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2069 bne 7f /* if no SLB entry found */
2070 4: std r4, VCPU_FAULT_DAR(r9)
2071 stw r6, VCPU_FAULT_DSISR(r9)
2073 /* Search the hash table. */
2074 mr r3, r9 /* vcpu pointer */
2075 li r7, 1 /* data fault */
2076 bl kvmppc_hpte_hv_fault
2077 ld r9, HSTATE_KVM_VCPU(r13)
2079 ld r11, VCPU_MSR(r9)
2080 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2081 cmpdi r3, 0 /* retry the instruction */
2083 cmpdi r3, -1 /* handle in kernel mode */
2085 cmpdi r3, -2 /* MMIO emulation; need instr word */
2088 /* Synthesize a DSI (or DSegI) for the guest */
2089 ld r4, VCPU_FAULT_DAR(r9)
2091 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2092 mtspr SPRN_DSISR, r6
2093 7: mtspr SPRN_DAR, r4
2094 mtspr SPRN_SRR0, r10
2095 mtspr SPRN_SRR1, r11
2097 bl kvmppc_msr_interrupt
2098 fast_interrupt_c_return:
2099 6: ld r7, VCPU_CTR(r9)
2106 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2107 ld r5, KVM_VRMA_SLB_V(r5)
2110 /* If this is for emulated MMIO, load the instruction word */
2111 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2113 /* Set guest mode to 'jump over instruction' so if lwz faults
2114 * we'll just continue at the next IP. */
2115 li r0, KVM_GUEST_MODE_SKIP
2116 stb r0, HSTATE_IN_GUEST(r13)
2118 /* Do the access with MSR:DR enabled */
2120 ori r4, r3, MSR_DR /* Enable paging for data */
2125 /* Store the result */
2126 stw r8, VCPU_LAST_INST(r9)
2128 /* Unset guest mode. */
2129 li r0, KVM_GUEST_MODE_HOST_HV
2130 stb r0, HSTATE_IN_GUEST(r13)
2134 std r4, VCPU_FAULT_DAR(r9)
2135 stw r6, VCPU_FAULT_DSISR(r9)
2138 std r5, VCPU_FAULT_GPA(r9)
2142 * Similarly for an HISI, reflect it to the guest as an ISI unless
2143 * it is an HPTE not found fault for a page that we have paged out.
2147 lbz r0, KVM_RADIX(r3)
2149 bne .Lradix_hisi /* for radix, just save ASDR */
2150 andis. r0, r11, SRR1_ISI_NOPT@h
2152 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2155 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2157 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2159 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2160 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2161 bne 7f /* if no SLB entry found */
2163 /* Search the hash table. */
2164 mr r3, r9 /* vcpu pointer */
2167 li r7, 0 /* instruction fault */
2168 bl kvmppc_hpte_hv_fault
2169 ld r9, HSTATE_KVM_VCPU(r13)
2171 ld r11, VCPU_MSR(r9)
2172 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2173 cmpdi r3, 0 /* retry the instruction */
2174 beq fast_interrupt_c_return
2175 cmpdi r3, -1 /* handle in kernel mode */
2178 /* Synthesize an ISI (or ISegI) for the guest */
2180 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2181 7: mtspr SPRN_SRR0, r10
2182 mtspr SPRN_SRR1, r11
2184 bl kvmppc_msr_interrupt
2185 b fast_interrupt_c_return
2187 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2188 ld r5, KVM_VRMA_SLB_V(r6)
2192 * Try to handle an hcall in real mode.
2193 * Returns to the guest if we handle it, or continues on up to
2194 * the kernel if we can't (i.e. if we don't have a handler for
2195 * it, or if the handler returns H_TOO_HARD).
2197 * r5 - r8 contain hcall args,
2198 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2200 hcall_try_real_mode:
2201 ld r3,VCPU_GPR(R3)(r9)
2203 /* sc 1 from userspace - reflect to guest syscall */
2204 bne sc_1_fast_return
2205 /* sc 1 from nested guest - give it to L1 to handle */
2206 ld r0, VCPU_NESTED(r9)
2210 cmpldi r3,hcall_real_table_end - hcall_real_table
2212 /* See if this hcall is enabled for in-kernel handling */
2214 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2215 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2217 ld r0, KVM_ENABLED_HCALLS(r4)
2218 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2222 /* Get pointer to handler, if any, and call it */
2223 LOAD_REG_ADDR(r4, hcall_real_table)
2229 mr r3,r9 /* get vcpu pointer */
2230 ld r4,VCPU_GPR(R4)(r9)
2233 beq hcall_real_fallback
2234 ld r4,HSTATE_KVM_VCPU(r13)
2235 std r3,VCPU_GPR(R3)(r4)
2243 li r10, BOOK3S_INTERRUPT_SYSCALL
2244 bl kvmppc_msr_interrupt
2248 /* We've attempted a real mode hcall, but it's punted it back
2249 * to userspace. We need to restore some clobbered volatiles
2250 * before resuming the pass-it-to-qemu path */
2251 hcall_real_fallback:
2252 li r12,BOOK3S_INTERRUPT_SYSCALL
2253 ld r9, HSTATE_KVM_VCPU(r13)
2257 .globl hcall_real_table
2259 .long 0 /* 0 - unused */
2260 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2261 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2262 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2263 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2264 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2265 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2266 #ifdef CONFIG_SPAPR_TCE_IOMMU
2267 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2268 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2273 .long 0 /* 0x24 - H_SET_SPRG0 */
2274 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2275 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
2289 #ifdef CONFIG_KVM_XICS
2290 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2291 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2292 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2293 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2294 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2296 .long 0 /* 0x64 - H_EOI */
2297 .long 0 /* 0x68 - H_CPPR */
2298 .long 0 /* 0x6c - H_IPI */
2299 .long 0 /* 0x70 - H_IPOLL */
2300 .long 0 /* 0x74 - H_XIRR */
2328 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2329 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2345 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2349 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2350 #ifdef CONFIG_SPAPR_TCE_IOMMU
2351 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2352 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2468 #ifdef CONFIG_KVM_XICS
2469 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2471 .long 0 /* 0x2fc - H_XIRR_X*/
2473 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2474 .globl hcall_real_table_end
2475 hcall_real_table_end:
2477 _GLOBAL(kvmppc_h_set_xdabr)
2478 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2479 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2481 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2484 6: li r3, H_PARAMETER
2487 _GLOBAL(kvmppc_h_set_dabr)
2488 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2489 li r5, DABRX_USER | DABRX_KERNEL
2493 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2494 std r4,VCPU_DABR(r3)
2495 stw r5, VCPU_DABRX(r3)
2496 mtspr SPRN_DABRX, r5
2497 /* Work around P7 bug where DABR can get corrupted on mtspr */
2498 1: mtspr SPRN_DABR,r4
2507 LOAD_REG_ADDR(r11, dawr_force_enable)
2512 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2513 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2514 rlwimi r5, r4, 2, DAWRX_WT
2516 std r4, VCPU_DAWR(r3)
2517 std r5, VCPU_DAWRX(r3)
2519 mtspr SPRN_DAWRX, r5
2523 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2525 std r11,VCPU_MSR(r3)
2527 stb r0,VCPU_CEDED(r3)
2528 sync /* order setting ceded vs. testing prodded */
2529 lbz r5,VCPU_PRODDED(r3)
2531 bne kvm_cede_prodded
2532 li r12,0 /* set trap to 0 to say hcall is handled */
2533 stw r12,VCPU_TRAP(r3)
2535 std r0,VCPU_GPR(R3)(r3)
2538 * Set our bit in the bitmask of napping threads unless all the
2539 * other threads are already napping, in which case we send this
2542 ld r5,HSTATE_KVM_VCORE(r13)
2543 lbz r6,HSTATE_PTID(r13)
2544 lwz r8,VCORE_ENTRY_EXIT(r5)
2548 addi r6,r5,VCORE_NAPPING_THREADS
2555 /* order napping_threads update vs testing entry_exit_map */
2558 stb r0,HSTATE_NAPPING(r13)
2559 lwz r7,VCORE_ENTRY_EXIT(r5)
2561 bge 33f /* another thread already exiting */
2564 * Although not specifically required by the architecture, POWER7
2565 * preserves the following registers in nap mode, even if an SMT mode
2566 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2567 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2569 /* Save non-volatile GPRs */
2570 std r14, VCPU_GPR(R14)(r3)
2571 std r15, VCPU_GPR(R15)(r3)
2572 std r16, VCPU_GPR(R16)(r3)
2573 std r17, VCPU_GPR(R17)(r3)
2574 std r18, VCPU_GPR(R18)(r3)
2575 std r19, VCPU_GPR(R19)(r3)
2576 std r20, VCPU_GPR(R20)(r3)
2577 std r21, VCPU_GPR(R21)(r3)
2578 std r22, VCPU_GPR(R22)(r3)
2579 std r23, VCPU_GPR(R23)(r3)
2580 std r24, VCPU_GPR(R24)(r3)
2581 std r25, VCPU_GPR(R25)(r3)
2582 std r26, VCPU_GPR(R26)(r3)
2583 std r27, VCPU_GPR(R27)(r3)
2584 std r28, VCPU_GPR(R28)(r3)
2585 std r29, VCPU_GPR(R29)(r3)
2586 std r30, VCPU_GPR(R30)(r3)
2587 std r31, VCPU_GPR(R31)(r3)
2592 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2594 * Branch around the call if both CPU_FTR_TM and
2595 * CPU_FTR_P9_TM_HV_ASSIST are off.
2599 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2601 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2603 ld r3, HSTATE_KVM_VCPU(r13)
2605 li r5, 0 /* don't preserve non-vol regs */
2606 bl kvmppc_save_tm_hv
2612 * Set DEC to the smaller of DEC and HDEC, so that we wake
2613 * no later than the end of our timeslice (HDEC interrupts
2614 * don't wake us from nap).
2620 /* On P9 check whether the guest has large decrementer mode enabled */
2621 ld r6, HSTATE_KVM_VCORE(r13)
2622 ld r6, VCORE_LPCR(r6)
2623 andis. r6, r6, LPCR_LD@h
2625 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2632 /* save expiry time of guest decrementer */
2634 ld r4, HSTATE_KVM_VCPU(r13)
2635 ld r5, HSTATE_KVM_VCORE(r13)
2636 ld r6, VCORE_TB_OFFSET_APPL(r5)
2637 subf r3, r6, r3 /* convert to host TB value */
2638 std r3, VCPU_DEC_EXPIRES(r4)
2640 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2641 ld r4, HSTATE_KVM_VCPU(r13)
2642 addi r3, r4, VCPU_TB_CEDE
2643 bl kvmhv_accumulate_time
2646 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2648 /* Go back to host stack */
2649 ld r1, HSTATE_HOST_R1(r13)
2652 * Take a nap until a decrementer or external or doobell interrupt
2653 * occurs, with PECE1 and PECE0 set in LPCR.
2654 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2655 * Also clear the runlatch bit before napping.
2658 mfspr r0, SPRN_CTRLF
2660 mtspr SPRN_CTRLT, r0
2663 stb r0,HSTATE_HWTHREAD_REQ(r13)
2665 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2667 ori r5, r5, LPCR_PECEDH
2668 rlwimi r5, r3, 0, LPCR_PECEDP
2669 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2671 kvm_nap_sequence: /* desired LPCR value in r5 */
2674 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2675 * enable state loss = 1 (allow SMT mode switch)
2676 * requested level = 0 (just stop dispatching)
2678 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2679 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2680 li r4, LPCR_PECE_HVEE@higher
2684 li r3, PNV_THREAD_NAP
2685 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2690 bl isa300_idle_stop_mayloss
2692 bl isa206_idle_insn_mayloss
2693 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2695 mfspr r0, SPRN_CTRLF
2697 mtspr SPRN_CTRLT, r0
2702 stb r0, PACA_FTRACE_ENABLED(r13)
2704 li r0, KVM_HWTHREAD_IN_KVM
2705 stb r0, HSTATE_HWTHREAD_STATE(r13)
2707 lbz r0, HSTATE_NAPPING(r13)
2708 cmpwi r0, NAPPING_CEDE
2710 cmpwi r0, NAPPING_NOVCPU
2711 beq kvm_novcpu_wakeup
2712 cmpwi r0, NAPPING_UNSPLIT
2713 beq kvm_unsplit_wakeup
2714 twi 31,0,0 /* Nap state must not be zero */
2722 /* Woken by external or decrementer interrupt */
2724 /* get vcpu pointer */
2725 ld r4, HSTATE_KVM_VCPU(r13)
2727 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2728 addi r3, r4, VCPU_TB_RMINTR
2729 bl kvmhv_accumulate_time
2732 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2734 * Branch around the call if both CPU_FTR_TM and
2735 * CPU_FTR_P9_TM_HV_ASSIST are off.
2739 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2741 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2745 li r5, 0 /* don't preserve non-vol regs */
2746 bl kvmppc_restore_tm_hv
2748 ld r4, HSTATE_KVM_VCPU(r13)
2752 /* load up FP state */
2755 /* Restore guest decrementer */
2756 ld r3, VCPU_DEC_EXPIRES(r4)
2757 ld r5, HSTATE_KVM_VCORE(r13)
2758 ld r6, VCORE_TB_OFFSET_APPL(r5)
2759 add r3, r3, r6 /* convert host TB to guest TB value */
2765 ld r14, VCPU_GPR(R14)(r4)
2766 ld r15, VCPU_GPR(R15)(r4)
2767 ld r16, VCPU_GPR(R16)(r4)
2768 ld r17, VCPU_GPR(R17)(r4)
2769 ld r18, VCPU_GPR(R18)(r4)
2770 ld r19, VCPU_GPR(R19)(r4)
2771 ld r20, VCPU_GPR(R20)(r4)
2772 ld r21, VCPU_GPR(R21)(r4)
2773 ld r22, VCPU_GPR(R22)(r4)
2774 ld r23, VCPU_GPR(R23)(r4)
2775 ld r24, VCPU_GPR(R24)(r4)
2776 ld r25, VCPU_GPR(R25)(r4)
2777 ld r26, VCPU_GPR(R26)(r4)
2778 ld r27, VCPU_GPR(R27)(r4)
2779 ld r28, VCPU_GPR(R28)(r4)
2780 ld r29, VCPU_GPR(R29)(r4)
2781 ld r30, VCPU_GPR(R30)(r4)
2782 ld r31, VCPU_GPR(R31)(r4)
2784 /* Check the wake reason in SRR1 to see why we got here */
2785 bl kvmppc_check_wake_reason
2788 * Restore volatile registers since we could have called a
2789 * C routine in kvmppc_check_wake_reason
2791 * r3 tells us whether we need to return to host or not
2792 * WARNING: it gets checked further down:
2793 * should not modify r3 until this check is done.
2795 ld r4, HSTATE_KVM_VCPU(r13)
2797 /* clear our bit in vcore->napping_threads */
2798 34: ld r5,HSTATE_KVM_VCORE(r13)
2799 lbz r7,HSTATE_PTID(r13)
2802 addi r6,r5,VCORE_NAPPING_THREADS
2808 stb r0,HSTATE_NAPPING(r13)
2810 /* See if the wake reason saved in r3 means we need to exit */
2811 stw r12, VCPU_TRAP(r4)
2815 b maybe_reenter_guest
2817 /* cede when already previously prodded case */
2820 stb r0,VCPU_PRODDED(r3)
2821 sync /* order testing prodded vs. clearing ceded */
2822 stb r0,VCPU_CEDED(r3)
2826 /* we've ceded but we want to give control to the host */
2828 ld r9, HSTATE_KVM_VCPU(r13)
2829 #ifdef CONFIG_KVM_XICS
2830 /* Abort if we still have a pending escalation */
2831 lbz r5, VCPU_XIVE_ESC_ON(r9)
2835 stb r0, VCPU_CEDED(r9)
2836 1: /* Enable XIVE escalation */
2837 li r5, XIVE_ESB_SET_PQ_00
2839 andi. r0, r0, MSR_DR /* in real mode? */
2841 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2846 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2852 stb r0, VCPU_XIVE_ESC_ON(r9)
2853 #endif /* CONFIG_KVM_XICS */
2854 3: b guest_exit_cont
2856 /* Try to do machine check recovery in real mode */
2857 machine_check_realmode:
2858 mr r3, r9 /* get vcpu pointer */
2859 bl kvmppc_realmode_machine_check
2861 /* all machine checks go to virtual mode for further handling */
2862 ld r9, HSTATE_KVM_VCPU(r13)
2863 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2867 * Call C code to handle a HMI in real mode.
2868 * Only the primary thread does the call, secondary threads are handled
2869 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2870 * r9 points to the vcpu on entry
2873 lbz r0, HSTATE_PTID(r13)
2876 bl kvmppc_realmode_hmi_handler
2877 ld r9, HSTATE_KVM_VCPU(r13)
2878 li r12, BOOK3S_INTERRUPT_HMI
2882 * Check the reason we woke from nap, and take appropriate action.
2884 * 0 if nothing needs to be done
2885 * 1 if something happened that needs to be handled by the host
2886 * -1 if there was a guest wakeup (IPI or msgsnd)
2887 * -2 if we handled a PCI passthrough interrupt (returned by
2888 * kvmppc_read_intr only)
2890 * Also sets r12 to the interrupt vector for any interrupt that needs
2891 * to be handled now by the host (0x500 for external interrupt), or zero.
2892 * Modifies all volatile registers (since it may call a C function).
2893 * This routine calls kvmppc_read_intr, a C function, if an external
2894 * interrupt is pending.
2896 kvmppc_check_wake_reason:
2899 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2901 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2902 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2903 cmpwi r6, 8 /* was it an external interrupt? */
2904 beq 7f /* if so, see what it was */
2907 cmpwi r6, 6 /* was it the decrementer? */
2910 cmpwi r6, 5 /* privileged doorbell? */
2912 cmpwi r6, 3 /* hypervisor doorbell? */
2914 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2915 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2917 li r3, 1 /* anything else, return 1 */
2920 /* hypervisor doorbell */
2921 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2924 * Clear the doorbell as we will invoke the handler
2925 * explicitly in the guest exit path.
2927 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2929 /* see if it's a host IPI */
2934 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2935 lbz r0, HSTATE_HOST_IPI(r13)
2938 /* if not, return -1 */
2942 /* Woken up due to Hypervisor maintenance interrupt */
2943 4: li r12, BOOK3S_INTERRUPT_HMI
2947 /* external interrupt - create a stack frame so we can call C */
2949 std r0, PPC_LR_STKOFF(r1)
2950 stdu r1, -PPC_MIN_STKFRM(r1)
2953 li r12, BOOK3S_INTERRUPT_EXTERNAL
2958 * Return code of 2 means PCI passthrough interrupt, but
2959 * we need to return back to host to complete handling the
2960 * interrupt. Trap reason is expected in r12 by guest
2963 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2965 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2966 addi r1, r1, PPC_MIN_STKFRM
2971 * Save away FP, VMX and VSX registers.
2973 * N.B. r30 and r31 are volatile across this function,
2974 * thus it is not callable from C.
2981 #ifdef CONFIG_ALTIVEC
2983 oris r8,r8,MSR_VEC@h
2984 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2988 oris r8,r8,MSR_VSX@h
2989 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2992 addi r3,r3,VCPU_FPRS
2994 #ifdef CONFIG_ALTIVEC
2996 addi r3,r31,VCPU_VRS
2998 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3000 mfspr r6,SPRN_VRSAVE
3001 stw r6,VCPU_VRSAVE(r31)
3006 * Load up FP, VMX and VSX registers
3008 * N.B. r30 and r31 are volatile across this function,
3009 * thus it is not callable from C.
3016 #ifdef CONFIG_ALTIVEC
3018 oris r8,r8,MSR_VEC@h
3019 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3023 oris r8,r8,MSR_VSX@h
3024 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3027 addi r3,r4,VCPU_FPRS
3029 #ifdef CONFIG_ALTIVEC
3031 addi r3,r31,VCPU_VRS
3033 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3035 lwz r7,VCPU_VRSAVE(r31)
3036 mtspr SPRN_VRSAVE,r7
3041 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3043 * Save transactional state and TM-related registers.
3044 * Called with r3 pointing to the vcpu struct and r4 containing
3045 * the guest MSR value.
3046 * r5 is non-zero iff non-volatile register state needs to be maintained.
3047 * If r5 == 0, this can modify all checkpointed registers, but
3048 * restores r1 and r2 before exit.
3050 _GLOBAL_TOC(kvmppc_save_tm_hv)
3051 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
3052 /* See if we need to handle fake suspend mode */
3055 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3057 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3059 beq __kvmppc_save_tm
3061 /* The following code handles the fake_suspend = 1 case */
3063 std r0, PPC_LR_STKOFF(r1)
3064 stdu r1, -PPC_MIN_STKFRM(r1)
3069 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3072 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3075 bl pnv_power9_force_smt4_catch
3076 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3079 /* We have to treclaim here because that's the only way to do S->N */
3080 li r3, TM_CAUSE_KVM_RESCHED
3084 * We were in fake suspend, so we are not going to save the
3085 * register state as the guest checkpointed state (since
3086 * we already have it), therefore we can now use any volatile GPR.
3087 * In fact treclaim in fake suspend state doesn't modify
3092 bl pnv_power9_force_smt4_release
3093 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3097 mfspr r3, SPRN_PSSCR
3098 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
3099 li r0, PSSCR_FAKE_SUSPEND
3101 mtspr SPRN_PSSCR, r3
3103 /* Don't save TEXASR, use value from last exit in real suspend state */
3104 ld r9, HSTATE_KVM_VCPU(r13)
3105 mfspr r5, SPRN_TFHAR
3106 mfspr r6, SPRN_TFIAR
3107 std r5, VCPU_TFHAR(r9)
3108 std r6, VCPU_TFIAR(r9)
3110 addi r1, r1, PPC_MIN_STKFRM
3111 ld r0, PPC_LR_STKOFF(r1)
3116 * Restore transactional state and TM-related registers.
3117 * Called with r3 pointing to the vcpu struct
3118 * and r4 containing the guest MSR value.
3119 * r5 is non-zero iff non-volatile register state needs to be maintained.
3120 * This potentially modifies all checkpointed registers.
3121 * It restores r1 and r2 from the PACA.
3123 _GLOBAL_TOC(kvmppc_restore_tm_hv)
3124 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
3126 * If we are doing TM emulation for the guest on a POWER9 DD2,
3127 * then we don't actually do a trechkpt -- we either set up
3128 * fake-suspend mode, or emulate a TM rollback.
3131 b __kvmppc_restore_tm
3132 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3134 std r0, PPC_LR_STKOFF(r1)
3137 stb r0, HSTATE_FAKE_SUSPEND(r13)
3139 /* Turn on TM so we can restore TM SPRs */
3142 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
3146 * The user may change these outside of a transaction, so they must
3147 * always be context switched.
3149 ld r5, VCPU_TFHAR(r3)
3150 ld r6, VCPU_TFIAR(r3)
3151 ld r7, VCPU_TEXASR(r3)
3152 mtspr SPRN_TFHAR, r5
3153 mtspr SPRN_TFIAR, r6
3154 mtspr SPRN_TEXASR, r7
3156 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
3157 beqlr /* TM not active in guest */
3159 /* Make sure the failure summary is set */
3160 oris r7, r7, (TEXASR_FS)@h
3161 mtspr SPRN_TEXASR, r7
3163 cmpwi r5, 1 /* check for suspended state */
3165 stb r5, HSTATE_FAKE_SUSPEND(r13)
3166 b 9f /* and return */
3167 10: stdu r1, -PPC_MIN_STKFRM(r1)
3168 /* guest is in transactional state, so simulate rollback */
3169 bl kvmhv_emulate_tm_rollback
3171 addi r1, r1, PPC_MIN_STKFRM
3172 9: ld r0, PPC_LR_STKOFF(r1)
3175 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
3178 * We come here if we get any exception or interrupt while we are
3179 * executing host real mode code while in guest MMU context.
3180 * r12 is (CR << 32) | vector
3181 * r13 points to our PACA
3182 * r12 is saved in HSTATE_SCRATCH0(r13)
3183 * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE
3184 * r9 is saved in HSTATE_SCRATCH2(r13)
3185 * r13 is saved in HSPRG1
3186 * cfar is saved in HSTATE_CFAR(r13)
3187 * ppr is saved in HSTATE_PPR(r13)
3189 kvmppc_bad_host_intr:
3191 * Switch to the emergency stack, but start half-way down in
3192 * case we were already on it.
3196 ld r1, PACAEMERGSP(r13)
3197 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3210 mfspr r3, SPRN_HSRR0
3211 mfspr r4, SPRN_HSRR1
3213 mfspr r6, SPRN_HDSISR
3215 1: mfspr r3, SPRN_SRR0
3218 mfspr r6, SPRN_DSISR
3223 ld r9, HSTATE_SCRATCH2(r13)
3224 ld r12, HSTATE_SCRATCH0(r13)
3229 ld r5, HSTATE_CFAR(r13)
3230 std r5, ORIG_GPR3(r1)
3232 #ifdef CONFIG_RELOCATABLE
3233 ld r4, HSTATE_SCRATCH1(r13)
3238 lbz r6, PACAIRQSOFTMASK(r13)
3244 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3245 std r3, STACK_FRAME_OVERHEAD-16(r1)
3248 * On POWER9 do a minimal restore of the MMU and call C code,
3249 * which will print a message and panic.
3250 * XXX On POWER7 and POWER8, we just spin here since we don't
3251 * know what the other threads are doing (and we don't want to
3252 * coordinate with them) - but at least we now have register state
3253 * in memory that we might be able to look at from another CPU.
3257 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3258 ld r9, HSTATE_KVM_VCPU(r13)
3259 ld r10, VCPU_KVM(r9)
3264 mtspr SPRN_CIABR, r0
3265 mtspr SPRN_DAWRX, r0
3267 BEGIN_MMU_FTR_SECTION
3269 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3274 ld r8, PACA_SLBSHADOWPTR(r13)
3275 .rept SLB_NUM_BOLTED
3276 li r3, SLBSHADOW_SAVEAREA
3280 andis. r7, r5, SLB_ESID_V@h
3286 4: lwz r7, KVM_HOST_LPID(r10)
3289 ld r8, KVM_HOST_LPCR(r10)
3292 li r0, KVM_GUEST_MODE_NONE
3293 stb r0, HSTATE_IN_GUEST(r13)
3296 * Turn on the MMU and jump to C code
3300 addi r3, r3, 9f - 5b
3302 rldimi r3, r4, 62, 0 /* ensure 0xc000000000000000 bits are set */
3303 ld r4, PACAKMSR(r13)
3307 9: addi r3, r1, STACK_FRAME_OVERHEAD
3308 bl kvmppc_bad_interrupt
3312 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3313 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3314 * r11 has the guest MSR value (in/out)
3315 * r9 has a vcpu pointer (in)
3316 * r0 is used as a scratch register
3318 kvmppc_msr_interrupt:
3319 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3320 cmpwi r0, 2 /* Check if we are in transactional state.. */
3321 ld r11, VCPU_INTR_MSR(r9)
3323 /* ... if transactional, change to suspended */
3325 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3329 * Load up guest PMU state. R3 points to the vcpu struct.
3331 _GLOBAL(kvmhv_load_guest_pmu)
3332 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
3336 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3337 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3340 ld r3, VCPU_MMCR(r4)
3341 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3342 cmpwi r5, MMCR0_PMAO
3343 beql kvmppc_fix_pmao
3344 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3345 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
3346 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
3347 lwz r6, VCPU_PMC + 8(r4)
3348 lwz r7, VCPU_PMC + 12(r4)
3349 lwz r8, VCPU_PMC + 16(r4)
3350 lwz r9, VCPU_PMC + 20(r4)
3357 ld r3, VCPU_MMCR(r4)
3358 ld r5, VCPU_MMCR + 8(r4)
3359 ld r6, VCPU_MMCR + 16(r4)
3360 ld r7, VCPU_SIAR(r4)
3361 ld r8, VCPU_SDAR(r4)
3362 mtspr SPRN_MMCR1, r5
3363 mtspr SPRN_MMCRA, r6
3367 ld r5, VCPU_MMCR + 24(r4)
3368 ld r6, VCPU_SIER(r4)
3369 mtspr SPRN_MMCR2, r5
3371 BEGIN_FTR_SECTION_NESTED(96)
3372 lwz r7, VCPU_PMC + 24(r4)
3373 lwz r8, VCPU_PMC + 28(r4)
3374 ld r9, VCPU_MMCR + 32(r4)
3375 mtspr SPRN_SPMC1, r7
3376 mtspr SPRN_SPMC2, r8
3377 mtspr SPRN_MMCRS, r9
3378 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3379 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3380 mtspr SPRN_MMCR0, r3
3386 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
3388 _GLOBAL(kvmhv_load_host_pmu)
3389 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
3391 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
3393 beq 23f /* skip if not */
3395 ld r3, HSTATE_MMCR0(r13)
3396 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3397 cmpwi r4, MMCR0_PMAO
3398 beql kvmppc_fix_pmao
3399 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3400 lwz r3, HSTATE_PMC1(r13)
3401 lwz r4, HSTATE_PMC2(r13)
3402 lwz r5, HSTATE_PMC3(r13)
3403 lwz r6, HSTATE_PMC4(r13)
3404 lwz r8, HSTATE_PMC5(r13)
3405 lwz r9, HSTATE_PMC6(r13)
3412 ld r3, HSTATE_MMCR0(r13)
3413 ld r4, HSTATE_MMCR1(r13)
3414 ld r5, HSTATE_MMCRA(r13)
3415 ld r6, HSTATE_SIAR(r13)
3416 ld r7, HSTATE_SDAR(r13)
3417 mtspr SPRN_MMCR1, r4
3418 mtspr SPRN_MMCRA, r5
3422 ld r8, HSTATE_MMCR2(r13)
3423 ld r9, HSTATE_SIER(r13)
3424 mtspr SPRN_MMCR2, r8
3426 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3427 mtspr SPRN_MMCR0, r3
3433 * Save guest PMU state into the vcpu struct.
3434 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
3436 _GLOBAL(kvmhv_save_guest_pmu)
3437 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
3442 * POWER8 seems to have a hardware bug where setting
3443 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
3444 * when some counters are already negative doesn't seem
3445 * to cause a performance monitor alert (and hence interrupt).
3446 * The effect of this is that when saving the PMU state,
3447 * if there is no PMU alert pending when we read MMCR0
3448 * before freezing the counters, but one becomes pending
3449 * before we read the counters, we lose it.
3450 * To work around this, we need a way to freeze the counters
3451 * before reading MMCR0. Normally, freezing the counters
3452 * is done by writing MMCR0 (to set MMCR0[FC]) which
3453 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
3454 * we can also freeze the counters using MMCR2, by writing
3455 * 1s to all the counter freeze condition bits (there are
3456 * 9 bits each for 6 counters).
3458 li r3, -1 /* set all freeze bits */
3460 mfspr r10, SPRN_MMCR2
3461 mtspr SPRN_MMCR2, r3
3463 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3465 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3466 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
3467 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3468 mfspr r6, SPRN_MMCRA
3469 /* Clear MMCRA in order to disable SDAR updates */
3471 mtspr SPRN_MMCRA, r7
3473 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
3475 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
3477 21: mfspr r5, SPRN_MMCR1
3480 std r4, VCPU_MMCR(r9)
3481 std r5, VCPU_MMCR + 8(r9)
3482 std r6, VCPU_MMCR + 16(r9)
3484 std r10, VCPU_MMCR + 24(r9)
3485 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3486 std r7, VCPU_SIAR(r9)
3487 std r8, VCPU_SDAR(r9)
3494 stw r3, VCPU_PMC(r9)
3495 stw r4, VCPU_PMC + 4(r9)
3496 stw r5, VCPU_PMC + 8(r9)
3497 stw r6, VCPU_PMC + 12(r9)
3498 stw r7, VCPU_PMC + 16(r9)
3499 stw r8, VCPU_PMC + 20(r9)
3502 std r5, VCPU_SIER(r9)
3503 BEGIN_FTR_SECTION_NESTED(96)
3504 mfspr r6, SPRN_SPMC1
3505 mfspr r7, SPRN_SPMC2
3506 mfspr r8, SPRN_MMCRS
3507 stw r6, VCPU_PMC + 24(r9)
3508 stw r7, VCPU_PMC + 28(r9)
3509 std r8, VCPU_MMCR + 32(r9)
3511 mtspr SPRN_MMCRS, r4
3512 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3513 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3517 * This works around a hardware bug on POWER8E processors, where
3518 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3519 * performance monitor interrupt. Instead, when we need to have
3520 * an interrupt pending, we have to arrange for a counter to overflow.
3524 mtspr SPRN_MMCR2, r3
3525 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3526 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3527 mtspr SPRN_MMCR0, r3
3534 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3536 * Start timing an activity
3537 * r3 = pointer to time accumulation struct, r4 = vcpu
3540 ld r5, HSTATE_KVM_VCORE(r13)
3541 ld r6, VCORE_TB_OFFSET_APPL(r5)
3543 subf r5, r6, r5 /* subtract current timebase offset */
3544 std r3, VCPU_CUR_ACTIVITY(r4)
3545 std r5, VCPU_ACTIVITY_START(r4)
3549 * Accumulate time to one activity and start another.
3550 * r3 = pointer to new time accumulation struct, r4 = vcpu
3552 kvmhv_accumulate_time:
3553 ld r5, HSTATE_KVM_VCORE(r13)
3554 ld r8, VCORE_TB_OFFSET_APPL(r5)
3555 ld r5, VCPU_CUR_ACTIVITY(r4)
3556 ld r6, VCPU_ACTIVITY_START(r4)
3557 std r3, VCPU_CUR_ACTIVITY(r4)
3559 subf r7, r8, r7 /* subtract current timebase offset */
3560 std r7, VCPU_ACTIVITY_START(r4)
3564 ld r8, TAS_SEQCOUNT(r5)
3567 std r8, TAS_SEQCOUNT(r5)
3569 ld r7, TAS_TOTAL(r5)
3571 std r7, TAS_TOTAL(r5)
3577 3: std r3, TAS_MIN(r5)
3583 std r8, TAS_SEQCOUNT(r5)