2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
34 #include <asm/thread_info.h>
36 /* Sign-extend HDEC if not on POWER9 */
37 #define EXTEND_HDEC(reg) \
40 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
42 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
44 /* Values in HSTATE_NAPPING(r13) */
45 #define NAPPING_CEDE 1
46 #define NAPPING_NOVCPU 2
48 /* Stack frame offsets for kvmppc_hv_entry */
50 #define STACK_SLOT_TRAP (SFS-4)
51 #define STACK_SLOT_TID (SFS-16)
52 #define STACK_SLOT_PSSCR (SFS-24)
53 #define STACK_SLOT_PID (SFS-32)
54 #define STACK_SLOT_IAMR (SFS-40)
55 #define STACK_SLOT_CIABR (SFS-48)
56 #define STACK_SLOT_DAWR (SFS-56)
57 #define STACK_SLOT_DAWRX (SFS-64)
58 #define STACK_SLOT_HFSCR (SFS-72)
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
66 * LR = return address to continue at after eventually re-enabling MMU
68 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
70 std r0, PPC_LR_STKOFF(r1)
73 std r10, HSTATE_HOST_MSR(r13)
74 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
79 mtmsrd r0,1 /* clear RI in MSR */
86 /* On P9, do LPCR setting, if necessary */
87 ld r3, HSTATE_SPLIT_MODE(r13)
90 lwz r4, KVM_SPLIT_DO_SET(r3)
96 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
98 ld r4, HSTATE_KVM_VCPU(r13)
101 /* Back from guest - restore host state and return to caller */
104 /* Restore host DABR and DABRX */
105 ld r5,HSTATE_DABR(r13)
109 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
112 ld r3,PACA_SPRG_VDSO(r13)
113 mtspr SPRN_SPRG_VDSO_WRITE,r3
115 /* Reload the host's PMU registers */
116 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
117 lbz r4, LPPACA_PMCINUSE(r3)
119 beq 23f /* skip if not */
121 ld r3, HSTATE_MMCR0(r13)
122 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
125 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
126 lwz r3, HSTATE_PMC1(r13)
127 lwz r4, HSTATE_PMC2(r13)
128 lwz r5, HSTATE_PMC3(r13)
129 lwz r6, HSTATE_PMC4(r13)
130 lwz r8, HSTATE_PMC5(r13)
131 lwz r9, HSTATE_PMC6(r13)
138 ld r3, HSTATE_MMCR0(r13)
139 ld r4, HSTATE_MMCR1(r13)
140 ld r5, HSTATE_MMCRA(r13)
141 ld r6, HSTATE_SIAR(r13)
142 ld r7, HSTATE_SDAR(r13)
148 ld r8, HSTATE_MMCR2(r13)
149 ld r9, HSTATE_SIER(r13)
152 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
158 * Reload DEC. HDEC interrupts were disabled when
159 * we reloaded the host's LPCR value.
161 ld r3, HSTATE_DECEXP(r13)
166 /* hwthread_req may have got set by cede or no vcpu, so clear it */
168 stb r0, HSTATE_HWTHREAD_REQ(r13)
171 * For external interrupts we need to call the Linux
172 * handler to process the interrupt. We do that by jumping
173 * to absolute address 0x500 for external interrupts.
174 * The [h]rfid at the end of the handler will return to
175 * the book3s_hv_interrupts.S code. For other interrupts
176 * we do the rfid to get back to the book3s_hv_interrupts.S
179 ld r8, 112+PPC_LR_STKOFF(r1)
181 ld r7, HSTATE_HOST_MSR(r13)
183 /* Return the trap number on this thread as the return value */
187 * If we came back from the guest via a relocation-on interrupt,
188 * we will be in virtual mode at this point, which makes it a
189 * little easier to get back to the caller.
192 andi. r0, r0, MSR_IR /* in real mode? */
195 /* RFI into the highmem handler */
199 mtmsrd r6, 1 /* Clear RI in MSR */
204 /* Virtual-mode return */
209 kvmppc_primary_no_guest:
210 /* We handle this much like a ceded vcpu */
211 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
212 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
213 /* HDEC value came from DEC in the first place, it will fit */
217 * Make sure the primary has finished the MMU switch.
218 * We should never get here on a secondary thread, but
219 * check it for robustness' sake.
221 ld r5, HSTATE_KVM_VCORE(r13)
222 65: lbz r0, VCORE_IN_GUEST(r5)
229 /* set our bit in napping_threads */
230 ld r5, HSTATE_KVM_VCORE(r13)
231 lbz r7, HSTATE_PTID(r13)
234 addi r6, r5, VCORE_NAPPING_THREADS
239 /* order napping_threads update vs testing entry_exit_map */
242 lwz r7, VCORE_ENTRY_EXIT(r5)
244 bge kvm_novcpu_exit /* another thread already exiting */
245 li r3, NAPPING_NOVCPU
246 stb r3, HSTATE_NAPPING(r13)
248 li r3, 0 /* Don't wake on privileged (OS) doorbell */
253 * Entered from kvm_start_guest if kvm_hstate.napping is set
259 ld r1, HSTATE_HOST_R1(r13)
260 ld r5, HSTATE_KVM_VCORE(r13)
262 stb r0, HSTATE_NAPPING(r13)
264 /* check the wake reason */
265 bl kvmppc_check_wake_reason
268 * Restore volatile registers since we could have called
269 * a C routine in kvmppc_check_wake_reason.
272 ld r5, HSTATE_KVM_VCORE(r13)
274 /* see if any other thread is already exiting */
275 lwz r0, VCORE_ENTRY_EXIT(r5)
279 /* clear our bit in napping_threads */
280 lbz r7, HSTATE_PTID(r13)
283 addi r6, r5, VCORE_NAPPING_THREADS
289 /* See if the wake reason means we need to exit */
293 /* See if our timeslice has expired (HDEC is negative) */
296 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
300 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
301 ld r4, HSTATE_KVM_VCPU(r13)
303 beq kvmppc_primary_no_guest
305 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
306 addi r3, r4, VCPU_TB_RMENTRY
307 bl kvmhv_start_timing
312 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
313 ld r4, HSTATE_KVM_VCPU(r13)
316 addi r3, r4, VCPU_TB_RMEXIT
317 bl kvmhv_accumulate_time
320 stw r12, STACK_SLOT_TRAP(r1)
321 bl kvmhv_commence_exit
323 lwz r12, STACK_SLOT_TRAP(r1)
324 b kvmhv_switch_to_host
327 * We come in here when wakened from nap mode.
328 * Relocation is off and most register values are lost.
329 * r13 points to the PACA.
330 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
332 .globl kvm_start_guest
334 /* Set runlatch bit the minute you wake up from nap */
340 * Could avoid this and pass it through in r3. For now,
341 * code expects it to be in SRR1.
347 li r0,KVM_HWTHREAD_IN_KVM
348 stb r0,HSTATE_HWTHREAD_STATE(r13)
350 /* NV GPR values from power7_idle() will no longer be valid */
352 stb r0,PACA_NAPSTATELOST(r13)
354 /* were we napping due to cede? */
355 lbz r0,HSTATE_NAPPING(r13)
356 cmpwi r0,NAPPING_CEDE
358 cmpwi r0,NAPPING_NOVCPU
359 beq kvm_novcpu_wakeup
361 ld r1,PACAEMERGSP(r13)
362 subi r1,r1,STACK_FRAME_OVERHEAD
365 * We weren't napping due to cede, so this must be a secondary
366 * thread being woken up to run a guest, or being woken up due
367 * to a stray IPI. (Or due to some machine check or hypervisor
368 * maintenance interrupt while the core is in KVM.)
371 /* Check the wake reason in SRR1 to see why we got here */
372 bl kvmppc_check_wake_reason
374 * kvmppc_check_wake_reason could invoke a C routine, but we
375 * have no volatile registers to restore when we return.
381 /* get vcore pointer, NULL if we have nothing to run */
382 ld r5,HSTATE_KVM_VCORE(r13)
384 /* if we have no vcore to run, go back to sleep */
387 kvm_secondary_got_guest:
389 /* Set HSTATE_DSCR(r13) to something sensible */
390 ld r6, PACA_DSCR_DEFAULT(r13)
391 std r6, HSTATE_DSCR(r13)
393 /* On thread 0 of a subcore, set HDEC to max */
394 lbz r4, HSTATE_PTID(r13)
397 LOAD_REG_ADDR(r6, decrementer_max)
400 /* and set per-LPAR registers, if doing dynamic micro-threading */
401 ld r6, HSTATE_SPLIT_MODE(r13)
405 ld r0, KVM_SPLIT_RPR(r6)
407 ld r0, KVM_SPLIT_PMMAR(r6)
409 ld r0, KVM_SPLIT_LDBAR(r6)
413 /* On P9 we use the split_info for coordinating LPCR changes */
414 lwz r4, KVM_SPLIT_DO_SET(r6)
421 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
423 /* Order load of vcpu after load of vcore */
425 ld r4, HSTATE_KVM_VCPU(r13)
428 /* Back from the guest, go back to nap */
429 /* Clear our vcpu and vcore pointers so we don't come back in early */
431 std r0, HSTATE_KVM_VCPU(r13)
433 * Once we clear HSTATE_KVM_VCORE(r13), the code in
434 * kvmppc_run_core() is going to assume that all our vcpu
435 * state is visible in memory. This lwsync makes sure
439 std r0, HSTATE_KVM_VCORE(r13)
442 * All secondaries exiting guest will fall through this path.
443 * Before proceeding, just check for HMI interrupt and
444 * invoke opal hmi handler. By now we are sure that the
445 * primary thread on this core/subcore has already made partition
446 * switch/TB resync and we are good to call opal hmi handler.
448 cmpwi r12, BOOK3S_INTERRUPT_HMI
451 li r3,0 /* NULL argument */
452 bl hmi_exception_realmode
454 * At this point we have finished executing in the guest.
455 * We need to wait for hwthread_req to become zero, since
456 * we may not turn on the MMU while hwthread_req is non-zero.
457 * While waiting we also need to check if we get given a vcpu to run.
460 lbz r3, HSTATE_HWTHREAD_REQ(r13)
464 li r0, KVM_HWTHREAD_IN_KERNEL
465 stb r0, HSTATE_HWTHREAD_STATE(r13)
466 /* need to recheck hwthread_req after a barrier, to avoid race */
468 lbz r3, HSTATE_HWTHREAD_REQ(r13)
472 * We jump to pnv_wakeup_loss, which will return to the caller
473 * of power7_nap in the powernv cpu offline loop. The value we
474 * put in r3 becomes the return value for power7_nap. pnv_wakeup_loss
475 * requires SRR1 in r12.
479 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
486 ld r5, HSTATE_KVM_VCORE(r13)
489 ld r3, HSTATE_SPLIT_MODE(r13)
492 lwz r0, KVM_SPLIT_DO_SET(r3)
495 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
498 lbz r0, KVM_SPLIT_DO_NAP(r3)
504 b kvm_secondary_got_guest
506 54: li r0, KVM_HWTHREAD_IN_KVM
507 stb r0, HSTATE_HWTHREAD_STATE(r13)
511 /* Set LPCR, LPIDR etc. on P9 */
519 bl kvmhv_p9_restore_lpcr
524 * Here the primary thread is trying to return the core to
525 * whole-core mode, so we need to nap.
529 * When secondaries are napping in kvm_unsplit_nap() with
530 * hwthread_req = 1, HMI goes ignored even though subcores are
531 * already exited the guest. Hence HMI keeps waking up secondaries
532 * from nap in a loop and secondaries always go back to nap since
533 * no vcore is assigned to them. This makes impossible for primary
534 * thread to get hold of secondary threads resulting into a soft
535 * lockup in KVM path.
537 * Let us check if HMI is pending and handle it before we go to nap.
539 cmpwi r12, BOOK3S_INTERRUPT_HMI
541 li r3, 0 /* NULL argument */
542 bl hmi_exception_realmode
545 * Ensure that secondary doesn't nap when it has
546 * its vcore pointer set.
548 sync /* matches smp_mb() before setting split_info.do_nap */
549 ld r0, HSTATE_KVM_VCORE(r13)
552 /* clear any pending message */
554 lis r6, (PPC_DBELL_SERVER << (63-36))@h
556 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
557 /* Set kvm_split_mode.napped[tid] = 1 */
558 ld r3, HSTATE_SPLIT_MODE(r13)
560 lbz r4, HSTATE_TID(r13)
561 addi r4, r4, KVM_SPLIT_NAPPED
563 /* Check the do_nap flag again after setting napped[] */
565 lbz r0, KVM_SPLIT_DO_NAP(r3)
568 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
570 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
577 /******************************************************************************
581 *****************************************************************************/
583 .global kvmppc_hv_entry
588 * R4 = vcpu pointer (or NULL)
593 * all other volatile GPRS = free
594 * Does not preserve non-volatile GPRs or CR fields
597 std r0, PPC_LR_STKOFF(r1)
600 /* Save R1 in the PACA */
601 std r1, HSTATE_HOST_R1(r13)
603 li r6, KVM_GUEST_MODE_HOST_HV
604 stb r6, HSTATE_IN_GUEST(r13)
606 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
607 /* Store initial timestamp */
610 addi r3, r4, VCPU_TB_RMENTRY
611 bl kvmhv_start_timing
615 /* Use cr7 as an indication of radix mode */
616 ld r5, HSTATE_KVM_VCORE(r13)
617 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
618 lbz r0, KVM_RADIX(r9)
622 * POWER7/POWER8 host -> guest partition switch code.
623 * We don't have to lock against concurrent tlbies,
624 * but we do have to coordinate across hardware threads.
626 /* Set bit in entry map iff exit map is zero. */
628 lbz r6, HSTATE_PTID(r13)
630 addi r8, r5, VCORE_ENTRY_EXIT
632 cmpwi r3, 0x100 /* any threads starting to exit? */
633 bge secondary_too_late /* if so we're too late to the party */
638 /* Primary thread switches to guest partition. */
644 li r0,LPID_RSVD /* switch to reserved LPID */
647 mtspr SPRN_SDR1,r6 /* switch to partition page table */
648 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
652 /* See if we need to flush the TLB */
653 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
656 * On POWER9, individual threads can come in here, but the
657 * TLB is shared between the 4 threads in a core, hence
658 * invalidating on one thread invalidates for all.
659 * Thus we make all 4 threads use the same bit here.
662 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
663 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
664 srdi r6,r6,6 /* doubleword number */
665 sldi r6,r6,3 /* address offset */
667 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
673 /* Flush the TLB of any entries for this LPID */
674 lwz r0,KVM_TLB_SETS(r9)
676 li r7,0x800 /* IS field = 0b10 */
678 li r0,0 /* RS for P9 version of tlbiel */
680 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
684 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
688 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
693 /* Add timebase offset onto timebase */
694 22: ld r8,VCORE_TB_OFFSET(r5)
697 mftb r6 /* current host timebase */
699 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
700 mftb r7 /* check if lower 24 bits overflowed */
705 addis r8,r8,0x100 /* if so, increment upper 40 bits */
708 /* Load guest PCR value to select appropriate compat mode */
709 37: ld r7, VCORE_PCR(r5)
716 /* DPDES and VTB are shared between threads */
717 ld r8, VCORE_DPDES(r5)
721 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
723 /* Mark the subcore state as inside guest */
724 bl kvmppc_subcore_enter_guest
726 ld r5, HSTATE_KVM_VCORE(r13)
727 ld r4, HSTATE_KVM_VCPU(r13)
729 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
731 /* Do we have a guest vcpu to run? */
733 beq kvmppc_primary_no_guest
735 /* Increment yield count if they have a VPA */
739 li r6, LPPACA_YIELDCOUNT
744 stb r6, VCPU_VPA_DIRTY(r4)
747 /* Save purr/spurr */
750 std r5,HSTATE_PURR(r13)
751 std r6,HSTATE_SPURR(r13)
757 /* Save host values of some registers */
763 std r5, STACK_SLOT_TID(r1)
764 std r6, STACK_SLOT_PSSCR(r1)
765 std r7, STACK_SLOT_PID(r1)
766 std r8, STACK_SLOT_IAMR(r1)
768 std r5, STACK_SLOT_HFSCR(r1)
769 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
774 std r5, STACK_SLOT_CIABR(r1)
775 std r6, STACK_SLOT_DAWR(r1)
776 std r7, STACK_SLOT_DAWRX(r1)
777 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
780 /* Set partition DABR */
781 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
782 lwz r5,VCPU_DABRX(r4)
787 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
789 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
792 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
795 END_FTR_SECTION_IFSET(CPU_FTR_TM)
798 /* Load guest PMU registers */
799 /* R4 is live here (vcpu pointer) */
801 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
802 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
806 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
809 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
810 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
811 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
812 lwz r6, VCPU_PMC + 8(r4)
813 lwz r7, VCPU_PMC + 12(r4)
814 lwz r8, VCPU_PMC + 16(r4)
815 lwz r9, VCPU_PMC + 20(r4)
823 ld r5, VCPU_MMCR + 8(r4)
824 ld r6, VCPU_MMCR + 16(r4)
832 ld r5, VCPU_MMCR + 24(r4)
836 BEGIN_FTR_SECTION_NESTED(96)
837 lwz r7, VCPU_PMC + 24(r4)
838 lwz r8, VCPU_PMC + 28(r4)
839 ld r9, VCPU_MMCR + 32(r4)
843 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
844 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
848 /* Load up FP, VMX and VSX registers */
851 ld r14, VCPU_GPR(R14)(r4)
852 ld r15, VCPU_GPR(R15)(r4)
853 ld r16, VCPU_GPR(R16)(r4)
854 ld r17, VCPU_GPR(R17)(r4)
855 ld r18, VCPU_GPR(R18)(r4)
856 ld r19, VCPU_GPR(R19)(r4)
857 ld r20, VCPU_GPR(R20)(r4)
858 ld r21, VCPU_GPR(R21)(r4)
859 ld r22, VCPU_GPR(R22)(r4)
860 ld r23, VCPU_GPR(R23)(r4)
861 ld r24, VCPU_GPR(R24)(r4)
862 ld r25, VCPU_GPR(R25)(r4)
863 ld r26, VCPU_GPR(R26)(r4)
864 ld r27, VCPU_GPR(R27)(r4)
865 ld r28, VCPU_GPR(R28)(r4)
866 ld r29, VCPU_GPR(R29)(r4)
867 ld r30, VCPU_GPR(R30)(r4)
868 ld r31, VCPU_GPR(R31)(r4)
870 /* Switch DSCR to guest value */
875 /* Skip next section on POWER7 */
877 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
878 /* Load up POWER8-specific registers */
880 lwz r6, VCPU_PSPB(r4)
886 ld r6, VCPU_DAWRX(r4)
887 ld r7, VCPU_CIABR(r4)
894 ld r8, VCPU_EBBHR(r4)
897 ld r5, VCPU_EBBRR(r4)
898 ld r6, VCPU_BESCR(r4)
899 lwz r7, VCPU_GUEST_PID(r4)
907 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
909 /* POWER8-only registers */
910 ld r5, VCPU_TCSCR(r4)
912 ld r7, VCPU_CSIGR(r4)
919 /* POWER9-only registers */
921 ld r6, VCPU_PSSCR(r4)
922 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
923 ld r7, VCPU_HFSCR(r4)
927 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
931 * Set the decrementer to the guest decrementer.
933 ld r8,VCPU_DEC_EXPIRES(r4)
934 /* r8 is a host timebase value here, convert to guest TB */
935 ld r5,HSTATE_KVM_VCORE(r13)
936 ld r6,VCORE_TB_OFFSET(r5)
942 ld r5, VCPU_SPRG0(r4)
943 ld r6, VCPU_SPRG1(r4)
944 ld r7, VCPU_SPRG2(r4)
945 ld r8, VCPU_SPRG3(r4)
951 /* Load up DAR and DSISR */
953 lwz r6, VCPU_DSISR(r4)
957 /* Restore AMR and UAMOR, set AMOR to all 1s */
965 /* Restore state of CTRL run bit; assume 1 on entry */
973 /* Secondary threads wait for primary to have done partition switch */
974 ld r5, HSTATE_KVM_VCORE(r13)
975 lbz r6, HSTATE_PTID(r13)
978 lbz r0, VCORE_IN_GUEST(r5)
982 20: lwz r3, VCORE_ENTRY_EXIT(r5)
985 lbz r0, VCORE_IN_GUEST(r5)
995 /* Check if HDEC expires soon */
998 cmpdi r3, 512 /* 1 microsecond */
1001 /* For hash guest, clear out and reload the SLB */
1003 lbz r0, KVM_RADIX(r6)
1011 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
1012 lwz r5,VCPU_SLB_MAX(r4)
1017 1: ld r8,VCPU_SLB_E(r6)
1018 ld r9,VCPU_SLB_V(r6)
1020 addi r6,r6,VCPU_SLB_SIZE
1024 #ifdef CONFIG_KVM_XICS
1025 /* We are entering the guest on that thread, push VCPU to XIVE */
1026 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1029 ld r11, VCPU_XIVE_SAVED_STATE(r4)
1033 lwz r11, VCPU_XIVE_CAM_WORD(r4)
1034 li r9, TM_QW1_OS + TM_WORD2
1037 stb r9, VCPU_XIVE_PUSHED(r4)
1041 * We clear the irq_pending flag. There is a small chance of a
1042 * race vs. the escalation interrupt happening on another
1043 * processor setting it again, but the only consequence is to
1044 * cause a spurrious wakeup on the next H_CEDE which is not an
1048 stb r0, VCPU_IRQ_PENDING(r4)
1051 * In single escalation mode, if the escalation interrupt is
1054 lbz r0, VCPU_XIVE_ESC_ON(r4)
1057 ld r10, VCPU_XIVE_ESC_RADDR(r4)
1058 li r9, XIVE_ESB_SET_PQ_01
1062 /* We have a possible subtle race here: The escalation interrupt might
1063 * have fired and be on its way to the host queue while we mask it,
1064 * and if we unmask it early enough (re-cede right away), there is
1065 * a theorical possibility that it fires again, thus landing in the
1066 * target queue more than once which is a big no-no.
1068 * Fortunately, solving this is rather easy. If the above load setting
1069 * PQ to 01 returns a previous value where P is set, then we know the
1070 * escalation interrupt is somewhere on its way to the host. In that
1071 * case we simply don't clear the xive_esc_on flag below. It will be
1072 * eventually cleared by the handler for the escalation interrupt.
1074 * Then, when doing a cede, we check that flag again before re-enabling
1075 * the escalation interrupt, and if set, we abort the cede.
1077 andi. r0, r0, XIVE_ESB_VAL_P
1080 /* Now P is 0, we can clear the flag */
1082 stb r0, VCPU_XIVE_ESC_ON(r4)
1085 #endif /* CONFIG_KVM_XICS */
1087 deliver_guest_interrupt:
1094 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1096 ld r11, VCPU_MSR(r4)
1097 ld r6, VCPU_SRR0(r4)
1098 ld r7, VCPU_SRR1(r4)
1102 /* r11 = vcpu->arch.msr & ~MSR_HV */
1103 rldicl r11, r11, 63 - MSR_HV_LG, 1
1104 rotldi r11, r11, 1 + MSR_HV_LG
1105 ori r11, r11, MSR_ME
1107 /* Check if we can deliver an external or decrementer interrupt now */
1108 ld r0, VCPU_PENDING_EXC(r4)
1109 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1111 andi. r8, r11, MSR_EE
1113 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1114 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1118 li r0, BOOK3S_INTERRUPT_EXTERNAL
1122 /* On POWER9 check whether the guest has large decrementer enabled */
1123 andis. r8, r8, LPCR_LD@h
1125 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1128 li r0, BOOK3S_INTERRUPT_DECREMENTER
1131 12: mtspr SPRN_SRR0, r10
1133 mtspr SPRN_SRR1, r11
1135 bl kvmppc_msr_interrupt
1139 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1140 /* On POWER9, check for pending doorbell requests */
1141 lbz r0, VCPU_DBELL_REQ(r4)
1143 beq fast_guest_return
1144 ld r5, HSTATE_KVM_VCORE(r13)
1145 /* Set DPDES register so the CPU will take a doorbell interrupt */
1147 mtspr SPRN_DPDES, r0
1148 std r0, VCORE_DPDES(r5)
1149 /* Make sure other cpus see vcore->dpdes set before dbell req clear */
1151 /* Clear the pending doorbell request */
1153 stb r0, VCPU_DBELL_REQ(r4)
1158 * R10: value for HSRR0
1159 * R11: value for HSRR1
1164 stb r0,VCPU_CEDED(r4) /* cancel cede */
1165 mtspr SPRN_HSRR0,r10
1166 mtspr SPRN_HSRR1,r11
1168 /* Activate guest mode, so faults get handled by KVM */
1169 li r9, KVM_GUEST_MODE_GUEST_HV
1170 stb r9, HSTATE_IN_GUEST(r13)
1172 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1173 /* Accumulate timing */
1174 addi r3, r4, VCPU_TB_GUEST
1175 bl kvmhv_accumulate_time
1181 ld r5, VCPU_CFAR(r4)
1183 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1186 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1193 ld r1, VCPU_GPR(R1)(r4)
1194 ld r2, VCPU_GPR(R2)(r4)
1195 ld r3, VCPU_GPR(R3)(r4)
1196 ld r5, VCPU_GPR(R5)(r4)
1197 ld r6, VCPU_GPR(R6)(r4)
1198 ld r7, VCPU_GPR(R7)(r4)
1199 ld r8, VCPU_GPR(R8)(r4)
1200 ld r9, VCPU_GPR(R9)(r4)
1201 ld r10, VCPU_GPR(R10)(r4)
1202 ld r11, VCPU_GPR(R11)(r4)
1203 ld r12, VCPU_GPR(R12)(r4)
1204 ld r13, VCPU_GPR(R13)(r4)
1208 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1210 /* Move canary into DSISR to check for later */
1213 mtspr SPRN_HDSISR, r0
1214 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1216 ld r0, VCPU_GPR(R0)(r4)
1217 ld r4, VCPU_GPR(R4)(r4)
1225 stw r12, VCPU_TRAP(r4)
1226 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1227 addi r3, r4, VCPU_TB_RMEXIT
1228 bl kvmhv_accumulate_time
1230 11: b kvmhv_switch_to_host
1237 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1238 12: stw r12, VCPU_TRAP(r4)
1240 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1241 addi r3, r4, VCPU_TB_RMEXIT
1242 bl kvmhv_accumulate_time
1246 /******************************************************************************
1250 *****************************************************************************/
1253 * We come here from the first-level interrupt handlers.
1255 .globl kvmppc_interrupt_hv
1256 kvmppc_interrupt_hv:
1258 * Register contents:
1259 * R12 = (guest CR << 32) | interrupt vector
1261 * guest R12 saved in shadow VCPU SCRATCH0
1262 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1263 * guest R13 saved in SPRN_SCRATCH0
1265 std r9, HSTATE_SCRATCH2(r13)
1266 lbz r9, HSTATE_IN_GUEST(r13)
1267 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1268 beq kvmppc_bad_host_intr
1269 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1270 cmpwi r9, KVM_GUEST_MODE_GUEST
1271 ld r9, HSTATE_SCRATCH2(r13)
1272 beq kvmppc_interrupt_pr
1274 /* We're now back in the host but in guest MMU context */
1275 li r9, KVM_GUEST_MODE_HOST_HV
1276 stb r9, HSTATE_IN_GUEST(r13)
1278 ld r9, HSTATE_KVM_VCPU(r13)
1280 /* Save registers */
1282 std r0, VCPU_GPR(R0)(r9)
1283 std r1, VCPU_GPR(R1)(r9)
1284 std r2, VCPU_GPR(R2)(r9)
1285 std r3, VCPU_GPR(R3)(r9)
1286 std r4, VCPU_GPR(R4)(r9)
1287 std r5, VCPU_GPR(R5)(r9)
1288 std r6, VCPU_GPR(R6)(r9)
1289 std r7, VCPU_GPR(R7)(r9)
1290 std r8, VCPU_GPR(R8)(r9)
1291 ld r0, HSTATE_SCRATCH2(r13)
1292 std r0, VCPU_GPR(R9)(r9)
1293 std r10, VCPU_GPR(R10)(r9)
1294 std r11, VCPU_GPR(R11)(r9)
1295 ld r3, HSTATE_SCRATCH0(r13)
1296 std r3, VCPU_GPR(R12)(r9)
1297 /* CR is in the high half of r12 */
1301 ld r3, HSTATE_CFAR(r13)
1302 std r3, VCPU_CFAR(r9)
1303 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1305 ld r4, HSTATE_PPR(r13)
1306 std r4, VCPU_PPR(r9)
1307 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1309 /* Restore R1/R2 so we can handle faults */
1310 ld r1, HSTATE_HOST_R1(r13)
1313 mfspr r10, SPRN_SRR0
1314 mfspr r11, SPRN_SRR1
1315 std r10, VCPU_SRR0(r9)
1316 std r11, VCPU_SRR1(r9)
1317 /* trap is in the low half of r12, clear CR from the high half */
1319 andi. r0, r12, 2 /* need to read HSRR0/1? */
1321 mfspr r10, SPRN_HSRR0
1322 mfspr r11, SPRN_HSRR1
1324 1: std r10, VCPU_PC(r9)
1325 std r11, VCPU_MSR(r9)
1329 std r3, VCPU_GPR(R13)(r9)
1332 stw r12,VCPU_TRAP(r9)
1335 * Now that we have saved away SRR0/1 and HSRR0/1,
1336 * interrupts are recoverable in principle, so set MSR_RI.
1337 * This becomes important for relocation-on interrupts from
1338 * the guest, which we can get in radix mode on POWER9.
1343 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1344 addi r3, r9, VCPU_TB_RMINTR
1346 bl kvmhv_accumulate_time
1347 ld r5, VCPU_GPR(R5)(r9)
1348 ld r6, VCPU_GPR(R6)(r9)
1349 ld r7, VCPU_GPR(R7)(r9)
1350 ld r8, VCPU_GPR(R8)(r9)
1353 /* Save HEIR (HV emulation assist reg) in emul_inst
1354 if this is an HEI (HV emulation interrupt, e40) */
1355 li r3,KVM_INST_FETCH_FAILED
1356 stw r3,VCPU_LAST_INST(r9)
1357 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1360 11: stw r3,VCPU_HEIR(r9)
1362 /* these are volatile across C function calls */
1363 #ifdef CONFIG_RELOCATABLE
1364 ld r3, HSTATE_SCRATCH1(r13)
1370 std r3, VCPU_CTR(r9)
1371 std r4, VCPU_XER(r9)
1373 /* If this is a page table miss then see if it's theirs or ours */
1374 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1376 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1379 /* See if this is a leftover HDEC interrupt */
1380 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1386 bge fast_guest_return
1388 /* See if this is an hcall we can handle in real mode */
1389 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1390 beq hcall_try_real_mode
1392 /* Hypervisor doorbell - exit only if host IPI flag set */
1393 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1398 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1399 lbz r0, HSTATE_HOST_IPI(r13)
1404 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1405 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1407 mfspr r3, SPRN_HFSCR
1408 std r3, VCPU_HFSCR(r9)
1411 /* External interrupt ? */
1412 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1413 bne+ guest_exit_cont
1415 /* External interrupt, first check for host_ipi. If this is
1416 * set, we know the host wants us out so let's do it now
1421 * Restore the active volatile registers after returning from
1424 ld r9, HSTATE_KVM_VCPU(r13)
1425 li r12, BOOK3S_INTERRUPT_EXTERNAL
1428 * kvmppc_read_intr return codes:
1430 * Exit to host (r3 > 0)
1431 * 1 An interrupt is pending that needs to be handled by the host
1432 * Exit guest and return to host by branching to guest_exit_cont
1434 * 2 Passthrough that needs completion in the host
1435 * Exit guest and return to host by branching to guest_exit_cont
1436 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1437 * to indicate to the host to complete handling the interrupt
1439 * Before returning to guest, we check if any CPU is heading out
1440 * to the host and if so, we head out also. If no CPUs are heading
1441 * check return values <= 0.
1443 * Return to guest (r3 <= 0)
1444 * 0 No external interrupt is pending
1445 * -1 A guest wakeup IPI (which has now been cleared)
1446 * In either case, we return to guest to deliver any pending
1449 * -2 A PCI passthrough external interrupt was handled
1450 * (interrupt was delivered directly to guest)
1451 * Return to guest to deliver any pending guest interrupts.
1457 /* Return code = 2 */
1458 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1459 stw r12, VCPU_TRAP(r9)
1462 1: /* Return code <= 1 */
1466 /* Return code <= 0 */
1467 4: ld r5, HSTATE_KVM_VCORE(r13)
1468 lwz r0, VCORE_ENTRY_EXIT(r5)
1471 blt deliver_guest_interrupt
1473 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1474 /* Save more register state */
1477 std r6, VCPU_DAR(r9)
1478 stw r7, VCPU_DSISR(r9)
1479 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1480 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1482 std r6, VCPU_FAULT_DAR(r9)
1483 stw r7, VCPU_FAULT_DSISR(r9)
1485 /* See if it is a machine check */
1486 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1487 beq machine_check_realmode
1489 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1490 addi r3, r9, VCPU_TB_RMEXIT
1492 bl kvmhv_accumulate_time
1494 #ifdef CONFIG_KVM_XICS
1495 /* We are exiting, pull the VP from the XIVE */
1496 lbz r0, VCPU_XIVE_PUSHED(r9)
1499 li r7, TM_SPC_PULL_OS_CTX
1502 andi. r0, r0, MSR_DR /* in real mode? */
1504 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1507 /* First load to pull the context, we ignore the value */
1510 /* Second load to recover the context state (Words 0 and 1) */
1513 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1516 /* First load to pull the context, we ignore the value */
1519 /* Second load to recover the context state (Words 0 and 1) */
1521 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1522 /* Fixup some of the state for the next load */
1525 stb r10, VCPU_XIVE_PUSHED(r9)
1526 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1527 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1530 #endif /* CONFIG_KVM_XICS */
1532 /* For hash guest, read the guest SLB and save it away */
1534 lbz r0, KVM_RADIX(r5)
1537 bne 3f /* for radix, save 0 entries */
1538 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1543 andis. r0,r8,SLB_ESID_V@h
1545 add r8,r8,r6 /* put index in */
1547 std r8,VCPU_SLB_E(r7)
1548 std r3,VCPU_SLB_V(r7)
1549 addi r7,r7,VCPU_SLB_SIZE
1553 /* Finally clear out the SLB */
1558 3: stw r5,VCPU_SLB_MAX(r9)
1562 /* Increment exit count, poke other threads to exit */
1563 bl kvmhv_commence_exit
1565 ld r9, HSTATE_KVM_VCPU(r13)
1566 lwz r12, VCPU_TRAP(r9)
1568 /* Stop others sending VCPU interrupts to this physical CPU */
1570 stw r0, VCPU_CPU(r9)
1571 stw r0, VCPU_THREAD_CPU(r9)
1573 /* Save guest CTRL register, set runlatch to 1 */
1575 stw r6,VCPU_CTRL(r9)
1582 * Save the guest PURR/SPURR
1587 ld r8,VCPU_SPURR(r9)
1588 std r5,VCPU_PURR(r9)
1589 std r6,VCPU_SPURR(r9)
1594 * Restore host PURR/SPURR and add guest times
1595 * so that the time in the guest gets accounted.
1597 ld r3,HSTATE_PURR(r13)
1598 ld r4,HSTATE_SPURR(r13)
1605 ld r3, HSTATE_KVM_VCORE(r13)
1608 /* On P9, if the guest has large decr enabled, don't sign extend */
1610 ld r4, VCORE_LPCR(r3)
1611 andis. r4, r4, LPCR_LD@h
1613 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1616 /* r5 is a guest timebase value here, convert to host TB */
1617 ld r4,VCORE_TB_OFFSET(r3)
1619 std r5,VCPU_DEC_EXPIRES(r9)
1623 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1624 /* Save POWER8-specific registers */
1628 std r5, VCPU_IAMR(r9)
1629 stw r6, VCPU_PSPB(r9)
1630 std r7, VCPU_FSCR(r9)
1634 std r7, VCPU_TAR(r9)
1635 mfspr r8, SPRN_EBBHR
1636 std r8, VCPU_EBBHR(r9)
1637 mfspr r5, SPRN_EBBRR
1638 mfspr r6, SPRN_BESCR
1641 std r5, VCPU_EBBRR(r9)
1642 std r6, VCPU_BESCR(r9)
1643 stw r7, VCPU_GUEST_PID(r9)
1644 std r8, VCPU_WORT(r9)
1646 mfspr r5, SPRN_TCSCR
1648 mfspr r7, SPRN_CSIGR
1650 std r5, VCPU_TCSCR(r9)
1651 std r6, VCPU_ACOP(r9)
1652 std r7, VCPU_CSIGR(r9)
1653 std r8, VCPU_TACR(r9)
1656 mfspr r6, SPRN_PSSCR
1657 std r5, VCPU_TID(r9)
1658 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1660 std r6, VCPU_PSSCR(r9)
1661 /* Restore host HFSCR value */
1662 ld r7, STACK_SLOT_HFSCR(r1)
1663 mtspr SPRN_HFSCR, r7
1664 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1666 * Restore various registers to 0, where non-zero values
1667 * set by the guest could disrupt the host.
1674 mtspr SPRN_TCSCR, r0
1675 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1678 mtspr SPRN_MMCRS, r0
1679 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1682 /* Save and reset AMR and UAMOR before turning on the MMU */
1686 std r6,VCPU_UAMOR(r9)
1689 mtspr SPRN_UAMOR, r6
1691 /* Switch DSCR back to host value */
1693 ld r7, HSTATE_DSCR(r13)
1694 std r8, VCPU_DSCR(r9)
1697 /* Save non-volatile GPRs */
1698 std r14, VCPU_GPR(R14)(r9)
1699 std r15, VCPU_GPR(R15)(r9)
1700 std r16, VCPU_GPR(R16)(r9)
1701 std r17, VCPU_GPR(R17)(r9)
1702 std r18, VCPU_GPR(R18)(r9)
1703 std r19, VCPU_GPR(R19)(r9)
1704 std r20, VCPU_GPR(R20)(r9)
1705 std r21, VCPU_GPR(R21)(r9)
1706 std r22, VCPU_GPR(R22)(r9)
1707 std r23, VCPU_GPR(R23)(r9)
1708 std r24, VCPU_GPR(R24)(r9)
1709 std r25, VCPU_GPR(R25)(r9)
1710 std r26, VCPU_GPR(R26)(r9)
1711 std r27, VCPU_GPR(R27)(r9)
1712 std r28, VCPU_GPR(R28)(r9)
1713 std r29, VCPU_GPR(R29)(r9)
1714 std r30, VCPU_GPR(R30)(r9)
1715 std r31, VCPU_GPR(R31)(r9)
1718 mfspr r3, SPRN_SPRG0
1719 mfspr r4, SPRN_SPRG1
1720 mfspr r5, SPRN_SPRG2
1721 mfspr r6, SPRN_SPRG3
1722 std r3, VCPU_SPRG0(r9)
1723 std r4, VCPU_SPRG1(r9)
1724 std r5, VCPU_SPRG2(r9)
1725 std r6, VCPU_SPRG3(r9)
1731 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1734 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
1737 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1740 /* Increment yield count if they have a VPA */
1741 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1744 li r4, LPPACA_YIELDCOUNT
1749 stb r3, VCPU_VPA_DIRTY(r9)
1751 /* Save PMU registers if requested */
1752 /* r8 and cr0.eq are live here */
1755 * POWER8 seems to have a hardware bug where setting
1756 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1757 * when some counters are already negative doesn't seem
1758 * to cause a performance monitor alert (and hence interrupt).
1759 * The effect of this is that when saving the PMU state,
1760 * if there is no PMU alert pending when we read MMCR0
1761 * before freezing the counters, but one becomes pending
1762 * before we read the counters, we lose it.
1763 * To work around this, we need a way to freeze the counters
1764 * before reading MMCR0. Normally, freezing the counters
1765 * is done by writing MMCR0 (to set MMCR0[FC]) which
1766 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1767 * we can also freeze the counters using MMCR2, by writing
1768 * 1s to all the counter freeze condition bits (there are
1769 * 9 bits each for 6 counters).
1771 li r3, -1 /* set all freeze bits */
1773 mfspr r10, SPRN_MMCR2
1774 mtspr SPRN_MMCR2, r3
1776 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1778 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1779 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1780 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1781 mfspr r6, SPRN_MMCRA
1782 /* Clear MMCRA in order to disable SDAR updates */
1784 mtspr SPRN_MMCRA, r7
1786 beq 21f /* if no VPA, save PMU stuff anyway */
1787 lbz r7, LPPACA_PMCINUSE(r8)
1788 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1790 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1792 21: mfspr r5, SPRN_MMCR1
1795 std r4, VCPU_MMCR(r9)
1796 std r5, VCPU_MMCR + 8(r9)
1797 std r6, VCPU_MMCR + 16(r9)
1799 std r10, VCPU_MMCR + 24(r9)
1800 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1801 std r7, VCPU_SIAR(r9)
1802 std r8, VCPU_SDAR(r9)
1809 stw r3, VCPU_PMC(r9)
1810 stw r4, VCPU_PMC + 4(r9)
1811 stw r5, VCPU_PMC + 8(r9)
1812 stw r6, VCPU_PMC + 12(r9)
1813 stw r7, VCPU_PMC + 16(r9)
1814 stw r8, VCPU_PMC + 20(r9)
1817 std r5, VCPU_SIER(r9)
1818 BEGIN_FTR_SECTION_NESTED(96)
1819 mfspr r6, SPRN_SPMC1
1820 mfspr r7, SPRN_SPMC2
1821 mfspr r8, SPRN_MMCRS
1822 stw r6, VCPU_PMC + 24(r9)
1823 stw r7, VCPU_PMC + 28(r9)
1824 std r8, VCPU_MMCR + 32(r9)
1826 mtspr SPRN_MMCRS, r4
1827 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1828 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1831 /* Restore host values of some registers */
1833 ld r5, STACK_SLOT_CIABR(r1)
1834 ld r6, STACK_SLOT_DAWR(r1)
1835 ld r7, STACK_SLOT_DAWRX(r1)
1836 mtspr SPRN_CIABR, r5
1838 mtspr SPRN_DAWRX, r7
1839 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1841 ld r5, STACK_SLOT_TID(r1)
1842 ld r6, STACK_SLOT_PSSCR(r1)
1843 ld r7, STACK_SLOT_PID(r1)
1844 ld r8, STACK_SLOT_IAMR(r1)
1846 mtspr SPRN_PSSCR, r6
1849 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1851 #ifdef CONFIG_PPC_RADIX_MMU
1853 * Are we running hash or radix ?
1856 lbz r0, KVM_RADIX(r5)
1860 /* Radix: Handle the case where the guest used an illegal PID */
1861 LOAD_REG_ADDR(r4, mmu_base_pid)
1862 lwz r3, VCPU_GUEST_PID(r9)
1868 * Illegal PID, the HW might have prefetched and cached in the TLB
1869 * some translations for the LPID 0 / guest PID combination which
1870 * Linux doesn't know about, so we need to flush that PID out of
1871 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1872 * the right context.
1878 /* Then do a congruence class local flush */
1880 lwz r0,KVM_TLB_SETS(r6)
1882 li r7,0x400 /* IS field = 0b01 */
1884 sldi r0,r3,32 /* RS has PID */
1885 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1890 2: /* Flush the ERAT on radix P9 DD1 guest exit */
1893 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1895 #endif /* CONFIG_PPC_RADIX_MMU */
1898 * POWER7/POWER8 guest -> host partition switch code.
1899 * We don't have to lock against tlbies but we do
1900 * have to coordinate the hardware threads.
1902 kvmhv_switch_to_host:
1903 /* Secondary threads wait for primary to do partition switch */
1904 ld r5,HSTATE_KVM_VCORE(r13)
1905 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1906 lbz r3,HSTATE_PTID(r13)
1910 13: lbz r3,VCORE_IN_GUEST(r5)
1916 /* Primary thread waits for all the secondaries to exit guest */
1917 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1918 rlwinm r0,r3,32-8,0xff
1924 /* Did we actually switch to the guest at all? */
1925 lbz r6, VCORE_IN_GUEST(r5)
1929 /* Primary thread switches back to host partition */
1930 lwz r7,KVM_HOST_LPID(r4)
1932 ld r6,KVM_HOST_SDR1(r4)
1933 li r8,LPID_RSVD /* switch to reserved LPID */
1936 mtspr SPRN_SDR1,r6 /* switch to host page table */
1937 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1942 /* DPDES and VTB are shared between threads */
1943 mfspr r7, SPRN_DPDES
1945 std r7, VCORE_DPDES(r5)
1946 std r8, VCORE_VTB(r5)
1947 /* clear DPDES so we don't get guest doorbells in the host */
1949 mtspr SPRN_DPDES, r8
1950 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1952 /* If HMI, call kvmppc_realmode_hmi_handler() */
1953 cmpwi r12, BOOK3S_INTERRUPT_HMI
1955 bl kvmppc_realmode_hmi_handler
1958 li r12, BOOK3S_INTERRUPT_HMI
1960 * At this point kvmppc_realmode_hmi_handler may have resync-ed
1961 * the TB, and if it has, we must not subtract the guest timebase
1962 * offset from the timebase. So, skip it.
1964 * Also, do not call kvmppc_subcore_exit_guest() because it has
1965 * been invoked as part of kvmppc_realmode_hmi_handler().
1970 /* Subtract timebase offset from timebase */
1971 ld r8,VCORE_TB_OFFSET(r5)
1974 mftb r6 /* current guest timebase */
1976 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1977 mftb r7 /* check if lower 24 bits overflowed */
1982 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1985 17: bl kvmppc_subcore_exit_guest
1987 30: ld r5,HSTATE_KVM_VCORE(r13)
1988 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1991 ld r0, VCORE_PCR(r5)
1997 /* Signal secondary CPUs to continue */
1998 stb r0,VCORE_IN_GUEST(r5)
1999 19: lis r8,0x7fff /* MAX_INT@h */
2004 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
2005 ld r3, HSTATE_SPLIT_MODE(r13)
2008 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
2011 stw r12, STACK_SLOT_TRAP(r1)
2012 bl kvmhv_p9_restore_lpcr
2014 lwz r12, STACK_SLOT_TRAP(r1)
2017 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2018 ld r8,KVM_HOST_LPCR(r4)
2022 /* load host SLB entries */
2023 BEGIN_MMU_FTR_SECTION
2025 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
2026 ld r8,PACA_SLBSHADOWPTR(r13)
2028 .rept SLB_NUM_BOLTED
2029 li r3, SLBSHADOW_SAVEAREA
2033 andis. r7,r5,SLB_ESID_V@h
2039 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2040 /* Finish timing, if we have a vcpu */
2041 ld r4, HSTATE_KVM_VCPU(r13)
2045 bl kvmhv_accumulate_time
2048 /* Unset guest mode */
2049 li r0, KVM_GUEST_MODE_NONE
2050 stb r0, HSTATE_IN_GUEST(r13)
2052 ld r0, SFS+PPC_LR_STKOFF(r1)
2058 * Check whether an HDSI is an HPTE not found fault or something else.
2059 * If it is an HPTE not found fault that is due to the guest accessing
2060 * a page that they have mapped but which we have paged out, then
2061 * we continue on with the guest exit path. In all other cases,
2062 * reflect the HDSI to the guest as a DSI.
2066 lbz r0, KVM_RADIX(r3)
2068 mfspr r6, SPRN_HDSISR
2070 /* Look for DSISR canary. If we find it, retry instruction */
2073 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2075 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2076 /* HPTE not found fault or protection fault? */
2077 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2078 beq 1f /* if not, send it to the guest */
2079 andi. r0, r11, MSR_DR /* data relocation enabled? */
2082 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2084 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2086 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2087 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2088 bne 7f /* if no SLB entry found */
2089 4: std r4, VCPU_FAULT_DAR(r9)
2090 stw r6, VCPU_FAULT_DSISR(r9)
2092 /* Search the hash table. */
2093 mr r3, r9 /* vcpu pointer */
2094 li r7, 1 /* data fault */
2095 bl kvmppc_hpte_hv_fault
2096 ld r9, HSTATE_KVM_VCPU(r13)
2098 ld r11, VCPU_MSR(r9)
2099 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2100 cmpdi r3, 0 /* retry the instruction */
2102 cmpdi r3, -1 /* handle in kernel mode */
2104 cmpdi r3, -2 /* MMIO emulation; need instr word */
2107 /* Synthesize a DSI (or DSegI) for the guest */
2108 ld r4, VCPU_FAULT_DAR(r9)
2110 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2111 mtspr SPRN_DSISR, r6
2112 7: mtspr SPRN_DAR, r4
2113 mtspr SPRN_SRR0, r10
2114 mtspr SPRN_SRR1, r11
2116 bl kvmppc_msr_interrupt
2117 fast_interrupt_c_return:
2118 6: ld r7, VCPU_CTR(r9)
2125 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2126 ld r5, KVM_VRMA_SLB_V(r5)
2129 /* If this is for emulated MMIO, load the instruction word */
2130 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2132 /* Set guest mode to 'jump over instruction' so if lwz faults
2133 * we'll just continue at the next IP. */
2134 li r0, KVM_GUEST_MODE_SKIP
2135 stb r0, HSTATE_IN_GUEST(r13)
2137 /* Do the access with MSR:DR enabled */
2139 ori r4, r3, MSR_DR /* Enable paging for data */
2144 /* Store the result */
2145 stw r8, VCPU_LAST_INST(r9)
2147 /* Unset guest mode. */
2148 li r0, KVM_GUEST_MODE_HOST_HV
2149 stb r0, HSTATE_IN_GUEST(r13)
2153 std r4, VCPU_FAULT_DAR(r9)
2154 stw r6, VCPU_FAULT_DSISR(r9)
2157 std r5, VCPU_FAULT_GPA(r9)
2161 * Similarly for an HISI, reflect it to the guest as an ISI unless
2162 * it is an HPTE not found fault for a page that we have paged out.
2166 lbz r0, KVM_RADIX(r3)
2168 bne .Lradix_hisi /* for radix, just save ASDR */
2169 andis. r0, r11, SRR1_ISI_NOPT@h
2171 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2174 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2176 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2178 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2179 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2180 bne 7f /* if no SLB entry found */
2182 /* Search the hash table. */
2183 mr r3, r9 /* vcpu pointer */
2186 li r7, 0 /* instruction fault */
2187 bl kvmppc_hpte_hv_fault
2188 ld r9, HSTATE_KVM_VCPU(r13)
2190 ld r11, VCPU_MSR(r9)
2191 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2192 cmpdi r3, 0 /* retry the instruction */
2193 beq fast_interrupt_c_return
2194 cmpdi r3, -1 /* handle in kernel mode */
2197 /* Synthesize an ISI (or ISegI) for the guest */
2199 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2200 7: mtspr SPRN_SRR0, r10
2201 mtspr SPRN_SRR1, r11
2203 bl kvmppc_msr_interrupt
2204 b fast_interrupt_c_return
2206 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2207 ld r5, KVM_VRMA_SLB_V(r6)
2211 * Try to handle an hcall in real mode.
2212 * Returns to the guest if we handle it, or continues on up to
2213 * the kernel if we can't (i.e. if we don't have a handler for
2214 * it, or if the handler returns H_TOO_HARD).
2216 * r5 - r8 contain hcall args,
2217 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2219 hcall_try_real_mode:
2220 ld r3,VCPU_GPR(R3)(r9)
2222 /* sc 1 from userspace - reflect to guest syscall */
2223 bne sc_1_fast_return
2225 cmpldi r3,hcall_real_table_end - hcall_real_table
2227 /* See if this hcall is enabled for in-kernel handling */
2229 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2230 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2232 ld r0, KVM_ENABLED_HCALLS(r4)
2233 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2237 /* Get pointer to handler, if any, and call it */
2238 LOAD_REG_ADDR(r4, hcall_real_table)
2244 mr r3,r9 /* get vcpu pointer */
2245 ld r4,VCPU_GPR(R4)(r9)
2248 beq hcall_real_fallback
2249 ld r4,HSTATE_KVM_VCPU(r13)
2250 std r3,VCPU_GPR(R3)(r4)
2258 li r10, BOOK3S_INTERRUPT_SYSCALL
2259 bl kvmppc_msr_interrupt
2263 /* We've attempted a real mode hcall, but it's punted it back
2264 * to userspace. We need to restore some clobbered volatiles
2265 * before resuming the pass-it-to-qemu path */
2266 hcall_real_fallback:
2267 li r12,BOOK3S_INTERRUPT_SYSCALL
2268 ld r9, HSTATE_KVM_VCPU(r13)
2272 .globl hcall_real_table
2274 .long 0 /* 0 - unused */
2275 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2276 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2277 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2278 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2279 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2280 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2281 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2282 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2283 .long 0 /* 0x24 - H_SET_SPRG0 */
2284 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2299 #ifdef CONFIG_KVM_XICS
2300 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2301 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2302 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2303 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2304 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2306 .long 0 /* 0x64 - H_EOI */
2307 .long 0 /* 0x68 - H_CPPR */
2308 .long 0 /* 0x6c - H_IPI */
2309 .long 0 /* 0x70 - H_IPOLL */
2310 .long 0 /* 0x74 - H_XIRR */
2338 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2339 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2355 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2359 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2360 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2361 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2473 #ifdef CONFIG_KVM_XICS
2474 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2476 .long 0 /* 0x2fc - H_XIRR_X*/
2478 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2479 .globl hcall_real_table_end
2480 hcall_real_table_end:
2482 _GLOBAL(kvmppc_h_set_xdabr)
2483 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2485 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2488 6: li r3, H_PARAMETER
2491 _GLOBAL(kvmppc_h_set_dabr)
2492 li r5, DABRX_USER | DABRX_KERNEL
2496 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2497 std r4,VCPU_DABR(r3)
2498 stw r5, VCPU_DABRX(r3)
2499 mtspr SPRN_DABRX, r5
2500 /* Work around P7 bug where DABR can get corrupted on mtspr */
2501 1: mtspr SPRN_DABR,r4
2509 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2510 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2511 rlwimi r5, r4, 2, DAWRX_WT
2513 std r4, VCPU_DAWR(r3)
2514 std r5, VCPU_DAWRX(r3)
2516 mtspr SPRN_DAWRX, r5
2520 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2522 std r11,VCPU_MSR(r3)
2524 stb r0,VCPU_CEDED(r3)
2525 sync /* order setting ceded vs. testing prodded */
2526 lbz r5,VCPU_PRODDED(r3)
2528 bne kvm_cede_prodded
2529 li r12,0 /* set trap to 0 to say hcall is handled */
2530 stw r12,VCPU_TRAP(r3)
2532 std r0,VCPU_GPR(R3)(r3)
2535 * Set our bit in the bitmask of napping threads unless all the
2536 * other threads are already napping, in which case we send this
2539 ld r5,HSTATE_KVM_VCORE(r13)
2540 lbz r6,HSTATE_PTID(r13)
2541 lwz r8,VCORE_ENTRY_EXIT(r5)
2545 addi r6,r5,VCORE_NAPPING_THREADS
2552 /* order napping_threads update vs testing entry_exit_map */
2555 stb r0,HSTATE_NAPPING(r13)
2556 lwz r7,VCORE_ENTRY_EXIT(r5)
2558 bge 33f /* another thread already exiting */
2561 * Although not specifically required by the architecture, POWER7
2562 * preserves the following registers in nap mode, even if an SMT mode
2563 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2564 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2566 /* Save non-volatile GPRs */
2567 std r14, VCPU_GPR(R14)(r3)
2568 std r15, VCPU_GPR(R15)(r3)
2569 std r16, VCPU_GPR(R16)(r3)
2570 std r17, VCPU_GPR(R17)(r3)
2571 std r18, VCPU_GPR(R18)(r3)
2572 std r19, VCPU_GPR(R19)(r3)
2573 std r20, VCPU_GPR(R20)(r3)
2574 std r21, VCPU_GPR(R21)(r3)
2575 std r22, VCPU_GPR(R22)(r3)
2576 std r23, VCPU_GPR(R23)(r3)
2577 std r24, VCPU_GPR(R24)(r3)
2578 std r25, VCPU_GPR(R25)(r3)
2579 std r26, VCPU_GPR(R26)(r3)
2580 std r27, VCPU_GPR(R27)(r3)
2581 std r28, VCPU_GPR(R28)(r3)
2582 std r29, VCPU_GPR(R29)(r3)
2583 std r30, VCPU_GPR(R30)(r3)
2584 std r31, VCPU_GPR(R31)(r3)
2589 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2592 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2594 ld r9, HSTATE_KVM_VCPU(r13)
2596 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2600 * Set DEC to the smaller of DEC and HDEC, so that we wake
2601 * no later than the end of our timeslice (HDEC interrupts
2602 * don't wake us from nap).
2608 /* On P9 check whether the guest has large decrementer mode enabled */
2609 ld r6, HSTATE_KVM_VCORE(r13)
2610 ld r6, VCORE_LPCR(r6)
2611 andis. r6, r6, LPCR_LD@h
2613 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2620 /* save expiry time of guest decrementer */
2622 ld r4, HSTATE_KVM_VCPU(r13)
2623 ld r5, HSTATE_KVM_VCORE(r13)
2624 ld r6, VCORE_TB_OFFSET(r5)
2625 subf r3, r6, r3 /* convert to host TB value */
2626 std r3, VCPU_DEC_EXPIRES(r4)
2628 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2629 ld r4, HSTATE_KVM_VCPU(r13)
2630 addi r3, r4, VCPU_TB_CEDE
2631 bl kvmhv_accumulate_time
2634 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2637 * Take a nap until a decrementer or external or doobell interrupt
2638 * occurs, with PECE1 and PECE0 set in LPCR.
2639 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2640 * Also clear the runlatch bit before napping.
2643 mfspr r0, SPRN_CTRLF
2645 mtspr SPRN_CTRLT, r0
2648 stb r0,HSTATE_HWTHREAD_REQ(r13)
2650 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2652 ori r5, r5, LPCR_PECEDH
2653 rlwimi r5, r3, 0, LPCR_PECEDP
2654 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2656 kvm_nap_sequence: /* desired LPCR value in r5 */
2659 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2660 * enable state loss = 1 (allow SMT mode switch)
2661 * requested level = 0 (just stop dispatching)
2663 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2664 mtspr SPRN_PSSCR, r3
2665 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2666 li r4, LPCR_PECE_HVEE@higher
2669 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2673 std r0, HSTATE_SCRATCH0(r13)
2675 ld r0, HSTATE_SCRATCH0(r13)
2682 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2691 /* get vcpu pointer */
2692 ld r4, HSTATE_KVM_VCPU(r13)
2694 /* Woken by external or decrementer interrupt */
2695 ld r1, HSTATE_HOST_R1(r13)
2697 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2698 addi r3, r4, VCPU_TB_RMINTR
2699 bl kvmhv_accumulate_time
2702 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2705 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2707 bl kvmppc_restore_tm
2708 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2711 /* load up FP state */
2714 /* Restore guest decrementer */
2715 ld r3, VCPU_DEC_EXPIRES(r4)
2716 ld r5, HSTATE_KVM_VCORE(r13)
2717 ld r6, VCORE_TB_OFFSET(r5)
2718 add r3, r3, r6 /* convert host TB to guest TB value */
2724 ld r14, VCPU_GPR(R14)(r4)
2725 ld r15, VCPU_GPR(R15)(r4)
2726 ld r16, VCPU_GPR(R16)(r4)
2727 ld r17, VCPU_GPR(R17)(r4)
2728 ld r18, VCPU_GPR(R18)(r4)
2729 ld r19, VCPU_GPR(R19)(r4)
2730 ld r20, VCPU_GPR(R20)(r4)
2731 ld r21, VCPU_GPR(R21)(r4)
2732 ld r22, VCPU_GPR(R22)(r4)
2733 ld r23, VCPU_GPR(R23)(r4)
2734 ld r24, VCPU_GPR(R24)(r4)
2735 ld r25, VCPU_GPR(R25)(r4)
2736 ld r26, VCPU_GPR(R26)(r4)
2737 ld r27, VCPU_GPR(R27)(r4)
2738 ld r28, VCPU_GPR(R28)(r4)
2739 ld r29, VCPU_GPR(R29)(r4)
2740 ld r30, VCPU_GPR(R30)(r4)
2741 ld r31, VCPU_GPR(R31)(r4)
2743 /* Check the wake reason in SRR1 to see why we got here */
2744 bl kvmppc_check_wake_reason
2747 * Restore volatile registers since we could have called a
2748 * C routine in kvmppc_check_wake_reason
2750 * r3 tells us whether we need to return to host or not
2751 * WARNING: it gets checked further down:
2752 * should not modify r3 until this check is done.
2754 ld r4, HSTATE_KVM_VCPU(r13)
2756 /* clear our bit in vcore->napping_threads */
2757 34: ld r5,HSTATE_KVM_VCORE(r13)
2758 lbz r7,HSTATE_PTID(r13)
2761 addi r6,r5,VCORE_NAPPING_THREADS
2767 stb r0,HSTATE_NAPPING(r13)
2769 /* See if the wake reason saved in r3 means we need to exit */
2770 stw r12, VCPU_TRAP(r4)
2775 /* see if any other thread is already exiting */
2776 lwz r0,VCORE_ENTRY_EXIT(r5)
2780 b kvmppc_cede_reentry /* if not go back to guest */
2782 /* cede when already previously prodded case */
2785 stb r0,VCPU_PRODDED(r3)
2786 sync /* order testing prodded vs. clearing ceded */
2787 stb r0,VCPU_CEDED(r3)
2791 /* we've ceded but we want to give control to the host */
2793 ld r9, HSTATE_KVM_VCPU(r13)
2794 #ifdef CONFIG_KVM_XICS
2795 /* Abort if we still have a pending escalation */
2796 lbz r5, VCPU_XIVE_ESC_ON(r9)
2800 stb r0, VCPU_CEDED(r9)
2801 1: /* Enable XIVE escalation */
2802 li r5, XIVE_ESB_SET_PQ_00
2804 andi. r0, r0, MSR_DR /* in real mode? */
2806 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2811 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2817 stb r0, VCPU_XIVE_ESC_ON(r9)
2818 #endif /* CONFIG_KVM_XICS */
2819 3: b guest_exit_cont
2821 /* Try to handle a machine check in real mode */
2822 machine_check_realmode:
2823 mr r3, r9 /* get vcpu pointer */
2824 bl kvmppc_realmode_machine_check
2826 ld r9, HSTATE_KVM_VCPU(r13)
2827 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2829 * For the guest that is FWNMI capable, deliver all the MCE errors
2830 * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit
2831 * reason. This new approach injects machine check errors in guest
2832 * address space to guest with additional information in the form
2833 * of RTAS event, thus enabling guest kernel to suitably handle
2836 * For the guest that is not FWNMI capable (old QEMU) fallback
2837 * to old behaviour for backward compatibility:
2838 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either
2839 * through machine check interrupt (set HSRR0 to 0x200).
2840 * For handled errors (no-fatal), just go back to guest execution
2841 * with current HSRR0.
2842 * if we receive machine check with MSR(RI=0) then deliver it to
2843 * guest as machine check causing guest to crash.
2845 ld r11, VCPU_MSR(r9)
2846 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2847 bne mc_cont /* if so, exit to host */
2848 /* Check if guest is capable of handling NMI exit */
2849 ld r10, VCPU_KVM(r9)
2850 lbz r10, KVM_FWNMI(r10)
2851 cmpdi r10, 1 /* FWNMI capable? */
2852 beq mc_cont /* if so, exit with KVM_EXIT_NMI. */
2854 /* if not, fall through for backward compatibility. */
2855 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2856 beq 1f /* Deliver a machine check to guest */
2858 cmpdi r3, 0 /* Did we handle MCE ? */
2859 bne 2f /* Continue guest execution. */
2860 /* If not, deliver a machine check. SRR0/1 are already set */
2861 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2862 bl kvmppc_msr_interrupt
2863 2: b fast_interrupt_c_return
2866 * Check the reason we woke from nap, and take appropriate action.
2868 * 0 if nothing needs to be done
2869 * 1 if something happened that needs to be handled by the host
2870 * -1 if there was a guest wakeup (IPI or msgsnd)
2871 * -2 if we handled a PCI passthrough interrupt (returned by
2872 * kvmppc_read_intr only)
2874 * Also sets r12 to the interrupt vector for any interrupt that needs
2875 * to be handled now by the host (0x500 for external interrupt), or zero.
2876 * Modifies all volatile registers (since it may call a C function).
2877 * This routine calls kvmppc_read_intr, a C function, if an external
2878 * interrupt is pending.
2880 kvmppc_check_wake_reason:
2883 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2885 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2886 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2887 cmpwi r6, 8 /* was it an external interrupt? */
2888 beq 7f /* if so, see what it was */
2891 cmpwi r6, 6 /* was it the decrementer? */
2894 cmpwi r6, 5 /* privileged doorbell? */
2896 cmpwi r6, 3 /* hypervisor doorbell? */
2898 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2899 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2901 li r3, 1 /* anything else, return 1 */
2904 /* hypervisor doorbell */
2905 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2908 * Clear the doorbell as we will invoke the handler
2909 * explicitly in the guest exit path.
2911 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2913 /* see if it's a host IPI */
2918 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2919 lbz r0, HSTATE_HOST_IPI(r13)
2922 /* if not, return -1 */
2926 /* Woken up due to Hypervisor maintenance interrupt */
2927 4: li r12, BOOK3S_INTERRUPT_HMI
2931 /* external interrupt - create a stack frame so we can call C */
2933 std r0, PPC_LR_STKOFF(r1)
2934 stdu r1, -PPC_MIN_STKFRM(r1)
2937 li r12, BOOK3S_INTERRUPT_EXTERNAL
2942 * Return code of 2 means PCI passthrough interrupt, but
2943 * we need to return back to host to complete handling the
2944 * interrupt. Trap reason is expected in r12 by guest
2947 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2949 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2950 addi r1, r1, PPC_MIN_STKFRM
2955 * Save away FP, VMX and VSX registers.
2957 * N.B. r30 and r31 are volatile across this function,
2958 * thus it is not callable from C.
2965 #ifdef CONFIG_ALTIVEC
2967 oris r8,r8,MSR_VEC@h
2968 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2972 oris r8,r8,MSR_VSX@h
2973 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2976 addi r3,r3,VCPU_FPRS
2978 #ifdef CONFIG_ALTIVEC
2980 addi r3,r31,VCPU_VRS
2982 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2984 mfspr r6,SPRN_VRSAVE
2985 stw r6,VCPU_VRSAVE(r31)
2990 * Load up FP, VMX and VSX registers
2992 * N.B. r30 and r31 are volatile across this function,
2993 * thus it is not callable from C.
3000 #ifdef CONFIG_ALTIVEC
3002 oris r8,r8,MSR_VEC@h
3003 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3007 oris r8,r8,MSR_VSX@h
3008 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3011 addi r3,r4,VCPU_FPRS
3013 #ifdef CONFIG_ALTIVEC
3015 addi r3,r31,VCPU_VRS
3017 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3019 lwz r7,VCPU_VRSAVE(r31)
3020 mtspr SPRN_VRSAVE,r7
3025 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3027 * Save transactional state and TM-related registers.
3028 * Called with r9 pointing to the vcpu struct.
3029 * This can modify all checkpointed registers, but
3030 * restores r1, r2 and r9 (vcpu pointer) before exit.
3034 std r0, PPC_LR_STKOFF(r1)
3039 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3043 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3044 beq 1f /* TM not active in guest. */
3046 std r1, HSTATE_HOST_R1(r13)
3047 li r3, TM_CAUSE_KVM_RESCHED
3049 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3053 /* All GPRs are volatile at this point. */
3056 /* Temporarily store r13 and r9 so we have some regs to play with */
3059 std r9, PACATMSCRATCH(r13)
3060 ld r9, HSTATE_KVM_VCPU(r13)
3062 /* Get a few more GPRs free. */
3063 std r29, VCPU_GPRS_TM(29)(r9)
3064 std r30, VCPU_GPRS_TM(30)(r9)
3065 std r31, VCPU_GPRS_TM(31)(r9)
3067 /* Save away PPR and DSCR soon so don't run with user values. */
3070 mfspr r30, SPRN_DSCR
3071 ld r29, HSTATE_DSCR(r13)
3072 mtspr SPRN_DSCR, r29
3074 /* Save all but r9, r13 & r29-r31 */
3077 .if (reg != 9) && (reg != 13)
3078 std reg, VCPU_GPRS_TM(reg)(r9)
3082 /* ... now save r13 */
3084 std r4, VCPU_GPRS_TM(13)(r9)
3085 /* ... and save r9 */
3086 ld r4, PACATMSCRATCH(r13)
3087 std r4, VCPU_GPRS_TM(9)(r9)
3089 /* Reload stack pointer and TOC. */
3090 ld r1, HSTATE_HOST_R1(r13)
3093 /* Set MSR RI now we have r1 and r13 back. */
3097 /* Save away checkpinted SPRs. */
3098 std r31, VCPU_PPR_TM(r9)
3099 std r30, VCPU_DSCR_TM(r9)
3106 std r5, VCPU_LR_TM(r9)
3107 stw r6, VCPU_CR_TM(r9)
3108 std r7, VCPU_CTR_TM(r9)
3109 std r8, VCPU_AMR_TM(r9)
3110 std r10, VCPU_TAR_TM(r9)
3111 std r11, VCPU_XER_TM(r9)
3113 /* Restore r12 as trap number. */
3114 lwz r12, VCPU_TRAP(r9)
3117 addi r3, r9, VCPU_FPRS_TM
3119 addi r3, r9, VCPU_VRS_TM
3121 mfspr r6, SPRN_VRSAVE
3122 stw r6, VCPU_VRSAVE_TM(r9)
3125 * We need to save these SPRs after the treclaim so that the software
3126 * error code is recorded correctly in the TEXASR. Also the user may
3127 * change these outside of a transaction, so they must always be
3130 mfspr r5, SPRN_TFHAR
3131 mfspr r6, SPRN_TFIAR
3132 mfspr r7, SPRN_TEXASR
3133 std r5, VCPU_TFHAR(r9)
3134 std r6, VCPU_TFIAR(r9)
3135 std r7, VCPU_TEXASR(r9)
3137 ld r0, PPC_LR_STKOFF(r1)
3142 * Restore transactional state and TM-related registers.
3143 * Called with r4 pointing to the vcpu struct.
3144 * This potentially modifies all checkpointed registers.
3145 * It restores r1, r2, r4 from the PACA.
3149 std r0, PPC_LR_STKOFF(r1)
3151 /* Turn on TM/FP/VSX/VMX so we can restore them. */
3157 oris r5, r5, (MSR_VEC | MSR_VSX)@h
3161 * The user may change these outside of a transaction, so they must
3162 * always be context switched.
3164 ld r5, VCPU_TFHAR(r4)
3165 ld r6, VCPU_TFIAR(r4)
3166 ld r7, VCPU_TEXASR(r4)
3167 mtspr SPRN_TFHAR, r5
3168 mtspr SPRN_TFIAR, r6
3169 mtspr SPRN_TEXASR, r7
3172 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3173 beqlr /* TM not active in guest */
3174 std r1, HSTATE_HOST_R1(r13)
3176 /* Make sure the failure summary is set, otherwise we'll program check
3177 * when we trechkpt. It's possible that this might have been not set
3178 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
3181 oris r7, r7, (TEXASR_FS)@h
3182 mtspr SPRN_TEXASR, r7
3185 * We need to load up the checkpointed state for the guest.
3186 * We need to do this early as it will blow away any GPRs, VSRs and
3191 addi r3, r31, VCPU_FPRS_TM
3193 addi r3, r31, VCPU_VRS_TM
3196 lwz r7, VCPU_VRSAVE_TM(r4)
3197 mtspr SPRN_VRSAVE, r7
3199 ld r5, VCPU_LR_TM(r4)
3200 lwz r6, VCPU_CR_TM(r4)
3201 ld r7, VCPU_CTR_TM(r4)
3202 ld r8, VCPU_AMR_TM(r4)
3203 ld r9, VCPU_TAR_TM(r4)
3204 ld r10, VCPU_XER_TM(r4)
3213 * Load up PPR and DSCR values but don't put them in the actual SPRs
3214 * till the last moment to avoid running with userspace PPR and DSCR for
3217 ld r29, VCPU_DSCR_TM(r4)
3218 ld r30, VCPU_PPR_TM(r4)
3220 std r2, PACATMSCRATCH(r13) /* Save TOC */
3222 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3226 /* Load GPRs r0-r28 */
3229 ld reg, VCPU_GPRS_TM(reg)(r31)
3233 mtspr SPRN_DSCR, r29
3236 /* Load final GPRs */
3237 ld 29, VCPU_GPRS_TM(29)(r31)
3238 ld 30, VCPU_GPRS_TM(30)(r31)
3239 ld 31, VCPU_GPRS_TM(31)(r31)
3241 /* TM checkpointed state is now setup. All GPRs are now volatile. */
3244 /* Now let's get back the state we need. */
3247 ld r29, HSTATE_DSCR(r13)
3248 mtspr SPRN_DSCR, r29
3249 ld r4, HSTATE_KVM_VCPU(r13)
3250 ld r1, HSTATE_HOST_R1(r13)
3251 ld r2, PACATMSCRATCH(r13)
3253 /* Set the MSR RI since we have our registers back. */
3257 ld r0, PPC_LR_STKOFF(r1)
3263 * We come here if we get any exception or interrupt while we are
3264 * executing host real mode code while in guest MMU context.
3265 * r12 is (CR << 32) | vector
3266 * r13 points to our PACA
3267 * r12 is saved in HSTATE_SCRATCH0(r13)
3268 * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE
3269 * r9 is saved in HSTATE_SCRATCH2(r13)
3270 * r13 is saved in HSPRG1
3271 * cfar is saved in HSTATE_CFAR(r13)
3272 * ppr is saved in HSTATE_PPR(r13)
3274 kvmppc_bad_host_intr:
3276 * Switch to the emergency stack, but start half-way down in
3277 * case we were already on it.
3281 ld r1, PACAEMERGSP(r13)
3282 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3295 mfspr r3, SPRN_HSRR0
3296 mfspr r4, SPRN_HSRR1
3298 mfspr r6, SPRN_HDSISR
3300 1: mfspr r3, SPRN_SRR0
3303 mfspr r6, SPRN_DSISR
3308 ld r9, HSTATE_SCRATCH2(r13)
3309 ld r12, HSTATE_SCRATCH0(r13)
3314 ld r5, HSTATE_CFAR(r13)
3315 std r5, ORIG_GPR3(r1)
3317 #ifdef CONFIG_RELOCATABLE
3318 ld r4, HSTATE_SCRATCH1(r13)
3323 lbz r6, PACASOFTIRQEN(r13)
3329 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3330 std r3, STACK_FRAME_OVERHEAD-16(r1)
3333 * On POWER9 do a minimal restore of the MMU and call C code,
3334 * which will print a message and panic.
3335 * XXX On POWER7 and POWER8, we just spin here since we don't
3336 * know what the other threads are doing (and we don't want to
3337 * coordinate with them) - but at least we now have register state
3338 * in memory that we might be able to look at from another CPU.
3342 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3343 ld r9, HSTATE_KVM_VCPU(r13)
3344 ld r10, VCPU_KVM(r9)
3349 mtspr SPRN_CIABR, r0
3350 mtspr SPRN_DAWRX, r0
3352 /* Flush the ERAT on radix P9 DD1 guest exit */
3355 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
3357 BEGIN_MMU_FTR_SECTION
3359 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3364 ld r8, PACA_SLBSHADOWPTR(r13)
3365 .rept SLB_NUM_BOLTED
3366 li r3, SLBSHADOW_SAVEAREA
3370 andis. r7, r5, SLB_ESID_V@h
3376 4: lwz r7, KVM_HOST_LPID(r10)
3379 ld r8, KVM_HOST_LPCR(r10)
3382 li r0, KVM_GUEST_MODE_NONE
3383 stb r0, HSTATE_IN_GUEST(r13)
3386 * Turn on the MMU and jump to C code
3390 addi r3, r3, 9f - 5b
3391 ld r4, PACAKMSR(r13)
3395 9: addi r3, r1, STACK_FRAME_OVERHEAD
3396 bl kvmppc_bad_interrupt
3400 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3401 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3402 * r11 has the guest MSR value (in/out)
3403 * r9 has a vcpu pointer (in)
3404 * r0 is used as a scratch register
3406 kvmppc_msr_interrupt:
3407 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3408 cmpwi r0, 2 /* Check if we are in transactional state.. */
3409 ld r11, VCPU_INTR_MSR(r9)
3411 /* ... if transactional, change to suspended */
3413 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3417 * This works around a hardware bug on POWER8E processors, where
3418 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3419 * performance monitor interrupt. Instead, when we need to have
3420 * an interrupt pending, we have to arrange for a counter to overflow.
3424 mtspr SPRN_MMCR2, r3
3425 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3426 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3427 mtspr SPRN_MMCR0, r3
3434 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3436 * Start timing an activity
3437 * r3 = pointer to time accumulation struct, r4 = vcpu
3440 ld r5, HSTATE_KVM_VCORE(r13)
3441 lbz r6, VCORE_IN_GUEST(r5)
3443 beq 5f /* if in guest, need to */
3444 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3447 std r3, VCPU_CUR_ACTIVITY(r4)
3448 std r5, VCPU_ACTIVITY_START(r4)
3452 * Accumulate time to one activity and start another.
3453 * r3 = pointer to new time accumulation struct, r4 = vcpu
3455 kvmhv_accumulate_time:
3456 ld r5, HSTATE_KVM_VCORE(r13)
3457 lbz r8, VCORE_IN_GUEST(r5)
3459 beq 4f /* if in guest, need to */
3460 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3461 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3462 ld r6, VCPU_ACTIVITY_START(r4)
3463 std r3, VCPU_CUR_ACTIVITY(r4)
3466 std r7, VCPU_ACTIVITY_START(r4)
3470 ld r8, TAS_SEQCOUNT(r5)
3473 std r8, TAS_SEQCOUNT(r5)
3475 ld r7, TAS_TOTAL(r5)
3477 std r7, TAS_TOTAL(r5)
3483 3: std r3, TAS_MIN(r5)
3489 std r8, TAS_SEQCOUNT(r5)
projects / linux-2.6-microblaze.git / blob