1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@samba.org)
11 * This file handles the architecture-dependent parts of hardware exceptions
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/kernel.h>
19 #include <linux/pkeys.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/module.h> /* print_modules */
28 #include <linux/prctl.h>
29 #include <linux/delay.h>
30 #include <linux/kprobes.h>
31 #include <linux/kexec.h>
32 #include <linux/backlight.h>
33 #include <linux/bug.h>
34 #include <linux/kdebug.h>
35 #include <linux/ratelimit.h>
36 #include <linux/context_tracking.h>
37 #include <linux/smp.h>
38 #include <linux/console.h>
39 #include <linux/kmsg_dump.h>
41 #include <asm/emulated_ops.h>
42 #include <linux/uaccess.h>
43 #include <asm/debugfs.h>
44 #include <asm/interrupt.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
69 #include <asm/stacktrace.h>
72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
73 int (*__debugger)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
81 EXPORT_SYMBOL(__debugger);
82 EXPORT_SYMBOL(__debugger_ipi);
83 EXPORT_SYMBOL(__debugger_bpt);
84 EXPORT_SYMBOL(__debugger_sstep);
85 EXPORT_SYMBOL(__debugger_iabr_match);
86 EXPORT_SYMBOL(__debugger_break_match);
87 EXPORT_SYMBOL(__debugger_fault_handler);
90 /* Transactional Memory trap debug */
92 #define TM_DEBUG(x...) printk(KERN_INFO x)
94 #define TM_DEBUG(x...) do { } while(0)
97 static const char *signame(int signr)
100 case SIGBUS: return "bus error";
101 case SIGFPE: return "floating point exception";
102 case SIGILL: return "illegal instruction";
103 case SIGSEGV: return "segfault";
104 case SIGTRAP: return "unhandled trap";
107 return "unknown signal";
111 * Trap & Exception support
114 #ifdef CONFIG_PMAC_BACKLIGHT
115 static void pmac_backlight_unblank(void)
117 mutex_lock(&pmac_backlight_mutex);
118 if (pmac_backlight) {
119 struct backlight_properties *props;
121 props = &pmac_backlight->props;
122 props->brightness = props->max_brightness;
123 props->power = FB_BLANK_UNBLANK;
124 backlight_update_status(pmac_backlight);
126 mutex_unlock(&pmac_backlight_mutex);
129 static inline void pmac_backlight_unblank(void) { }
133 * If oops/die is expected to crash the machine, return true here.
135 * This should not be expected to be 100% accurate, there may be
136 * notifiers registered or other unexpected conditions that may bring
137 * down the kernel. Or if the current process in the kernel is holding
138 * locks or has other critical state, the kernel may become effectively
141 bool die_will_crash(void)
143 if (should_fadump_crash())
145 if (kexec_should_crash(current))
147 if (in_interrupt() || panic_on_oops ||
148 !current->pid || is_global_init(current))
154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
155 static int die_owner = -1;
156 static unsigned int die_nest_count;
157 static int die_counter;
159 extern void panic_flush_kmsg_start(void)
162 * These are mostly taken from kernel/panic.c, but tries to do
163 * relatively minimal work. Don't use delay functions (TB may
164 * be broken), don't crash dump (need to set a firmware log),
165 * don't run notifiers. We do want to get some information to
172 extern void panic_flush_kmsg_end(void)
174 printk_safe_flush_on_panic();
175 kmsg_dump(KMSG_DUMP_PANIC);
178 console_flush_on_panic(CONSOLE_FLUSH_PENDING);
181 static unsigned long oops_begin(struct pt_regs *regs)
188 /* racy, but better than risking deadlock. */
189 raw_local_irq_save(flags);
190 cpu = smp_processor_id();
191 if (!arch_spin_trylock(&die_lock)) {
192 if (cpu == die_owner)
193 /* nested oops. should stop eventually */;
195 arch_spin_lock(&die_lock);
201 if (machine_is(powermac))
202 pmac_backlight_unblank();
205 NOKPROBE_SYMBOL(oops_begin);
207 static void oops_end(unsigned long flags, struct pt_regs *regs,
211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
215 if (!die_nest_count) {
216 /* Nest count reaches zero, release the lock. */
218 arch_spin_unlock(&die_lock);
220 raw_local_irq_restore(flags);
223 * system_reset_excption handles debugger, crash dump, panic, for 0x100
225 if (TRAP(regs) == 0x100)
228 crash_fadump(regs, "die oops");
230 if (kexec_should_crash(current))
237 * While our oops output is serialised by a spinlock, output
238 * from panic() called below can race and corrupt it. If we
239 * know we are going to panic, delay for 1 second so we have a
240 * chance to get clean backtraces from all CPUs that are oopsing.
242 if (in_interrupt() || panic_on_oops || !current->pid ||
243 is_global_init(current)) {
244 mdelay(MSEC_PER_SEC);
248 panic("Fatal exception");
251 NOKPROBE_SYMBOL(oops_end);
253 static char *get_mmu_str(void)
255 if (early_radix_enabled())
257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE))
262 static int __die(const char *str, struct pt_regs *regs, long err)
264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
268 PAGE_SIZE / 1024, get_mmu_str(),
269 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
270 IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
271 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
273 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "",
274 ppc_md.name ? ppc_md.name : "");
276 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
284 NOKPROBE_SYMBOL(__die);
286 void die(const char *str, struct pt_regs *regs, long err)
291 * system_reset_excption handles debugger, crash dump, panic, for 0x100
293 if (TRAP(regs) != 0x100) {
298 flags = oops_begin(regs);
299 if (__die(str, regs, err))
301 oops_end(flags, regs, err);
303 NOKPROBE_SYMBOL(die);
305 void user_single_step_report(struct pt_regs *regs)
307 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip);
310 static void show_signal_msg(int signr, struct pt_regs *regs, int code,
313 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
314 DEFAULT_RATELIMIT_BURST);
316 if (!show_unhandled_signals)
319 if (!unhandled_signal(current, signr))
322 if (!__ratelimit(&rs))
325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
326 current->comm, current->pid, signame(signr), signr,
327 addr, regs->nip, regs->link, code);
329 print_vma_addr(KERN_CONT " in ", regs->nip);
333 show_user_instructions(regs);
336 static bool exception_common(int signr, struct pt_regs *regs, int code,
339 if (!user_mode(regs)) {
340 die("Exception in kernel mode", regs, signr);
344 show_signal_msg(signr, regs, code, addr);
346 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
349 current->thread.trap_nr = code;
354 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key)
356 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr))
359 force_sig_pkuerr((void __user *) addr, key);
362 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
364 if (!exception_common(signr, regs, code, addr))
367 force_sig_fault(signr, code, (void __user *)addr);
371 * The interrupt architecture has a quirk in that the HV interrupts excluding
372 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
373 * that an interrupt handler must do is save off a GPR into a scratch register,
374 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
375 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
376 * that it is non-reentrant, which leads to random data corruption.
378 * The solution is for NMI interrupts in HV mode to check if they originated
379 * from these critical HV interrupt regions. If so, then mark them not
382 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
383 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
384 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
385 * that would work. However any other guest OS that may have the SPRG live
386 * and MSR[RI]=1 could encounter silent corruption.
388 * Builds that do not support KVM could take this second option to increase
389 * the recoverability of NMIs.
391 void hv_nmi_check_nonrecoverable(struct pt_regs *regs)
393 #ifdef CONFIG_PPC_POWERNV
394 unsigned long kbase = (unsigned long)_stext;
395 unsigned long nip = regs->nip;
397 if (!(regs->msr & MSR_RI))
399 if (!(regs->msr & MSR_HV))
401 if (regs->msr & MSR_PR)
405 * Now test if the interrupt has hit a range that may be using
406 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
407 * problem ranges all run un-relocated. Test real and virt modes
408 * at the same time by droping the high bit of the nip (virt mode
409 * entry points still have the +0x4000 offset).
411 nip &= ~0xc000000000000000ULL;
412 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600))
414 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00))
416 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0))
418 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0))
421 /* Trampoline code runs un-relocated so subtract kbase. */
422 if (nip >= (unsigned long)(start_real_trampolines - kbase) &&
423 nip < (unsigned long)(end_real_trampolines - kbase))
425 if (nip >= (unsigned long)(start_virt_trampolines - kbase) &&
426 nip < (unsigned long)(end_virt_trampolines - kbase))
431 regs->msr &= ~MSR_RI;
434 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception)
436 unsigned long hsrr0, hsrr1;
437 bool saved_hsrrs = false;
438 u8 ftrace_enabled = this_cpu_get_ftrace_enabled();
440 this_cpu_set_ftrace_enabled(0);
445 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
446 * The system reset interrupt itself may clobber HSRRs (e.g., to call
447 * OPAL), so save them here and restore them before returning.
449 * Machine checks don't need to save HSRRs, as the real mode handler
450 * is careful to avoid them, and the regular handler is not delivered
453 if (cpu_has_feature(CPU_FTR_HVMODE)) {
454 hsrr0 = mfspr(SPRN_HSRR0);
455 hsrr1 = mfspr(SPRN_HSRR1);
459 hv_nmi_check_nonrecoverable(regs);
461 __this_cpu_inc(irq_stat.sreset_irqs);
463 /* See if any machine dependent calls */
464 if (ppc_md.system_reset_exception) {
465 if (ppc_md.system_reset_exception(regs))
472 kmsg_dump(KMSG_DUMP_OOPS);
474 * A system reset is a request to dump, so we always send
475 * it through the crashdump code (if fadump or kdump are
478 crash_fadump(regs, "System Reset");
483 * We aren't the primary crash CPU. We need to send it
484 * to a holding pattern to avoid it ending up in the panic
487 crash_kexec_secondary(regs);
490 * No debugger or crash dump registered, print logs then
493 die("System Reset", regs, SIGABRT);
495 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
496 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
497 nmi_panic(regs, "System Reset");
500 #ifdef CONFIG_PPC_BOOK3S_64
501 BUG_ON(get_paca()->in_nmi == 0);
502 if (get_paca()->in_nmi > 1)
503 die("Unrecoverable nested System Reset", regs, SIGABRT);
505 /* Must die if the interrupt is not recoverable */
506 if (!(regs->msr & MSR_RI)) {
507 /* For the reason explained in die_mce, nmi_exit before die */
509 die("Unrecoverable System Reset", regs, SIGABRT);
513 mtspr(SPRN_HSRR0, hsrr0);
514 mtspr(SPRN_HSRR1, hsrr1);
519 this_cpu_set_ftrace_enabled(ftrace_enabled);
521 /* What should we do here? We could issue a shutdown or hard reset. */
525 NOKPROBE_SYMBOL(system_reset_exception);
528 * I/O accesses can cause machine checks on powermacs.
529 * Check if the NIP corresponds to the address of a sync
530 * instruction for which there is an entry in the exception
534 static inline int check_io_access(struct pt_regs *regs)
537 unsigned long msr = regs->msr;
538 const struct exception_table_entry *entry;
539 unsigned int *nip = (unsigned int *)regs->nip;
541 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
542 && (entry = search_exception_tables(regs->nip)) != NULL) {
544 * Check that it's a sync instruction, or somewhere
545 * in the twi; isync; nop sequence that inb/inw/inl uses.
546 * As the address is in the exception table
547 * we should be able to read the instr there.
548 * For the debug message, we look at the preceding
551 if (*nip == PPC_INST_NOP)
553 else if (*nip == PPC_INST_ISYNC)
555 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
559 rb = (*nip >> 11) & 0x1f;
560 printk(KERN_DEBUG "%s bad port %lx at %p\n",
561 (*nip & 0x100)? "OUT to": "IN from",
562 regs->gpr[rb] - _IO_BASE, nip);
564 regs->nip = extable_fixup(entry);
568 #endif /* CONFIG_PPC32 */
572 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
573 /* On 4xx, the reason for the machine check or program exception
575 #define get_reason(regs) ((regs)->dsisr)
576 #define REASON_FP ESR_FP
577 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
578 #define REASON_PRIVILEGED ESR_PPR
579 #define REASON_TRAP ESR_PTR
580 #define REASON_PREFIXED 0
581 #define REASON_BOUNDARY 0
583 /* single-step stuff */
584 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
585 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
586 #define clear_br_trace(regs) do {} while(0)
588 /* On non-4xx, the reason for the machine check or program
589 exception is in the MSR. */
590 #define get_reason(regs) ((regs)->msr)
591 #define REASON_TM SRR1_PROGTM
592 #define REASON_FP SRR1_PROGFPE
593 #define REASON_ILLEGAL SRR1_PROGILL
594 #define REASON_PRIVILEGED SRR1_PROGPRIV
595 #define REASON_TRAP SRR1_PROGTRAP
596 #define REASON_PREFIXED SRR1_PREFIXED
597 #define REASON_BOUNDARY SRR1_BOUNDARY
599 #define single_stepping(regs) ((regs)->msr & MSR_SE)
600 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
601 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
604 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
606 #if defined(CONFIG_E500)
607 int machine_check_e500mc(struct pt_regs *regs)
609 unsigned long mcsr = mfspr(SPRN_MCSR);
610 unsigned long pvr = mfspr(SPRN_PVR);
611 unsigned long reason = mcsr;
614 if (reason & MCSR_LD) {
615 recoverable = fsl_rio_mcheck_exception(regs);
616 if (recoverable == 1)
620 printk("Machine check in kernel mode.\n");
621 printk("Caused by (from MCSR=%lx): ", reason);
623 if (reason & MCSR_MCP)
624 pr_cont("Machine Check Signal\n");
626 if (reason & MCSR_ICPERR) {
627 pr_cont("Instruction Cache Parity Error\n");
630 * This is recoverable by invalidating the i-cache.
632 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
633 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
637 * This will generally be accompanied by an instruction
638 * fetch error report -- only treat MCSR_IF as fatal
639 * if it wasn't due to an L1 parity error.
644 if (reason & MCSR_DCPERR_MC) {
645 pr_cont("Data Cache Parity Error\n");
648 * In write shadow mode we auto-recover from the error, but it
649 * may still get logged and cause a machine check. We should
650 * only treat the non-write shadow case as non-recoverable.
652 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
653 * is not implemented but L1 data cache always runs in write
654 * shadow mode. Hence on data cache parity errors HW will
655 * automatically invalidate the L1 Data Cache.
657 if (PVR_VER(pvr) != PVR_VER_E6500) {
658 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
663 if (reason & MCSR_L2MMU_MHIT) {
664 pr_cont("Hit on multiple TLB entries\n");
668 if (reason & MCSR_NMI)
669 pr_cont("Non-maskable interrupt\n");
671 if (reason & MCSR_IF) {
672 pr_cont("Instruction Fetch Error Report\n");
676 if (reason & MCSR_LD) {
677 pr_cont("Load Error Report\n");
681 if (reason & MCSR_ST) {
682 pr_cont("Store Error Report\n");
686 if (reason & MCSR_LDG) {
687 pr_cont("Guarded Load Error Report\n");
691 if (reason & MCSR_TLBSYNC)
692 pr_cont("Simultaneous tlbsync operations\n");
694 if (reason & MCSR_BSL2_ERR) {
695 pr_cont("Level 2 Cache Error\n");
699 if (reason & MCSR_MAV) {
702 addr = mfspr(SPRN_MCAR);
703 addr |= (u64)mfspr(SPRN_MCARU) << 32;
705 pr_cont("Machine Check %s Address: %#llx\n",
706 reason & MCSR_MEA ? "Effective" : "Physical", addr);
710 mtspr(SPRN_MCSR, mcsr);
711 return mfspr(SPRN_MCSR) == 0 && recoverable;
714 int machine_check_e500(struct pt_regs *regs)
716 unsigned long reason = mfspr(SPRN_MCSR);
718 if (reason & MCSR_BUS_RBERR) {
719 if (fsl_rio_mcheck_exception(regs))
721 if (fsl_pci_mcheck_exception(regs))
725 printk("Machine check in kernel mode.\n");
726 printk("Caused by (from MCSR=%lx): ", reason);
728 if (reason & MCSR_MCP)
729 pr_cont("Machine Check Signal\n");
730 if (reason & MCSR_ICPERR)
731 pr_cont("Instruction Cache Parity Error\n");
732 if (reason & MCSR_DCP_PERR)
733 pr_cont("Data Cache Push Parity Error\n");
734 if (reason & MCSR_DCPERR)
735 pr_cont("Data Cache Parity Error\n");
736 if (reason & MCSR_BUS_IAERR)
737 pr_cont("Bus - Instruction Address Error\n");
738 if (reason & MCSR_BUS_RAERR)
739 pr_cont("Bus - Read Address Error\n");
740 if (reason & MCSR_BUS_WAERR)
741 pr_cont("Bus - Write Address Error\n");
742 if (reason & MCSR_BUS_IBERR)
743 pr_cont("Bus - Instruction Data Error\n");
744 if (reason & MCSR_BUS_RBERR)
745 pr_cont("Bus - Read Data Bus Error\n");
746 if (reason & MCSR_BUS_WBERR)
747 pr_cont("Bus - Write Data Bus Error\n");
748 if (reason & MCSR_BUS_IPERR)
749 pr_cont("Bus - Instruction Parity Error\n");
750 if (reason & MCSR_BUS_RPERR)
751 pr_cont("Bus - Read Parity Error\n");
756 int machine_check_generic(struct pt_regs *regs)
760 #elif defined(CONFIG_PPC32)
761 int machine_check_generic(struct pt_regs *regs)
763 unsigned long reason = regs->msr;
765 printk("Machine check in kernel mode.\n");
766 printk("Caused by (from SRR1=%lx): ", reason);
767 switch (reason & 0x601F0000) {
769 pr_cont("Machine check signal\n");
772 case 0x140000: /* 7450 MSS error and TEA */
773 pr_cont("Transfer error ack signal\n");
776 pr_cont("Data parity error signal\n");
779 pr_cont("Address parity error signal\n");
782 pr_cont("L1 Data Cache error\n");
785 pr_cont("L1 Instruction Cache error\n");
788 pr_cont("L2 data cache parity error\n");
791 pr_cont("Unknown values in msr\n");
795 #endif /* everything else */
797 void die_mce(const char *str, struct pt_regs *regs, long err)
800 * The machine check wants to kill the interrupted context, but
801 * do_exit() checks for in_interrupt() and panics in that case, so
802 * exit the irq/nmi before calling die.
804 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
808 NOKPROBE_SYMBOL(die_mce);
810 #ifdef CONFIG_PPC_BOOK3S_64
811 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception)
813 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception)
819 * BOOK3S_64 does not call this handler as a non-maskable interrupt
820 * (it uses its own early real-mode handler to handle the MCE proper
821 * and then raises irq_work to call this handler when interrupts are
824 * This is silly. The BOOK3S_64 should just call a different function
825 * rather than expecting semantics to magically change. Something
826 * like 'non_nmi_machine_check_exception()', perhaps?
828 const bool nmi = !IS_ENABLED(CONFIG_PPC_BOOK3S_64);
830 if (nmi) nmi_enter();
832 __this_cpu_inc(irq_stat.mce_exceptions);
834 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
836 /* See if any machine dependent calls. In theory, we would want
837 * to call the CPU first, and call the ppc_md. one if the CPU
838 * one returns a positive number. However there is existing code
839 * that assumes the board gets a first chance, so let's keep it
840 * that way for now and fix things later. --BenH.
842 if (ppc_md.machine_check_exception)
843 recover = ppc_md.machine_check_exception(regs);
844 else if (cur_cpu_spec->machine_check)
845 recover = cur_cpu_spec->machine_check(regs);
850 if (debugger_fault_handler(regs))
853 if (check_io_access(regs))
856 die_mce("Machine check", regs, SIGBUS);
859 /* Must die if the interrupt is not recoverable */
860 if (!(regs->msr & MSR_RI))
861 die_mce("Unrecoverable Machine check", regs, SIGBUS);
865 #ifdef CONFIG_PPC_BOOK3S_64
871 NOKPROBE_SYMBOL(machine_check_exception);
873 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */
875 die("System Management Interrupt", regs, SIGABRT);
879 static void p9_hmi_special_emu(struct pt_regs *regs)
881 unsigned int ra, rb, t, i, sel, instr, rc;
882 const void __user *addr;
883 u8 vbuf[16] __aligned(16), *vdst;
884 unsigned long ea, msr, msr_mask;
887 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
891 * lxvb16x opcode: 0x7c0006d8
892 * lxvd2x opcode: 0x7c000698
893 * lxvh8x opcode: 0x7c000658
894 * lxvw4x opcode: 0x7c000618
896 if ((instr & 0xfc00073e) != 0x7c000618) {
897 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
899 smp_processor_id(), current->comm, current->pid,
904 /* Grab vector registers into the task struct */
905 msr = regs->msr; /* Grab msr before we flush the bits */
906 flush_vsx_to_thread(current);
907 enable_kernel_altivec();
910 * Is userspace running with a different endian (this is rare but
913 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
915 /* Decode the instruction */
916 ra = (instr >> 16) & 0x1f;
917 rb = (instr >> 11) & 0x1f;
918 t = (instr >> 21) & 0x1f;
920 vdst = (u8 *)¤t->thread.vr_state.vr[t];
922 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
924 /* Grab the vector address */
925 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
928 addr = (__force const void __user *)ea;
931 if (!access_ok(addr, 16)) {
932 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
933 " instr=%08x addr=%016lx\n",
934 smp_processor_id(), current->comm, current->pid,
935 regs->nip, instr, (unsigned long)addr);
939 /* Read the vector */
941 if ((unsigned long)addr & 0xfUL)
943 rc = __copy_from_user_inatomic(vbuf, addr, 16);
945 __get_user_atomic_128_aligned(vbuf, addr, rc);
947 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
948 " instr=%08x addr=%016lx\n",
949 smp_processor_id(), current->comm, current->pid,
950 regs->nip, instr, (unsigned long)addr);
954 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
955 " instr=%08x addr=%016lx\n",
956 smp_processor_id(), current->comm, current->pid, regs->nip,
957 instr, (unsigned long) addr);
959 /* Grab instruction "selector" */
960 sel = (instr >> 6) & 3;
963 * Check to make sure the facility is actually enabled. This
964 * could happen if we get a false positive hit.
966 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
967 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
970 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
972 if (!(msr & msr_mask)) {
973 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
974 " instr=%08x msr:%016lx\n",
975 smp_processor_id(), current->comm, current->pid,
976 regs->nip, instr, msr);
980 /* Do logging here before we modify sel based on endian */
983 PPC_WARN_EMULATED(lxvw4x, regs);
986 PPC_WARN_EMULATED(lxvh8x, regs);
989 PPC_WARN_EMULATED(lxvd2x, regs);
991 case 3: /* lxvb16x */
992 PPC_WARN_EMULATED(lxvb16x, regs);
996 #ifdef __LITTLE_ENDIAN__
998 * An LE kernel stores the vector in the task struct as an LE
999 * byte array (effectively swapping both the components and
1000 * the content of the components). Those instructions expect
1001 * the components to remain in ascending address order, so we
1004 * If we are running a BE user space, the expectation is that
1005 * of a simple memcpy, so forcing the emulation to look like
1006 * a lxvb16x should do the trick.
1012 case 0: /* lxvw4x */
1013 for (i = 0; i < 4; i++)
1014 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
1016 case 1: /* lxvh8x */
1017 for (i = 0; i < 8; i++)
1018 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
1020 case 2: /* lxvd2x */
1021 for (i = 0; i < 2; i++)
1022 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
1024 case 3: /* lxvb16x */
1025 for (i = 0; i < 16; i++)
1026 vdst[i] = vbuf[15-i];
1029 #else /* __LITTLE_ENDIAN__ */
1030 /* On a big endian kernel, a BE userspace only needs a memcpy */
1034 /* Otherwise, we need to swap the content of the components */
1036 case 0: /* lxvw4x */
1037 for (i = 0; i < 4; i++)
1038 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
1040 case 1: /* lxvh8x */
1041 for (i = 0; i < 8; i++)
1042 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
1044 case 2: /* lxvd2x */
1045 for (i = 0; i < 2; i++)
1046 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
1048 case 3: /* lxvb16x */
1049 memcpy(vdst, vbuf, 16);
1052 #endif /* !__LITTLE_ENDIAN__ */
1054 /* Go to next instruction */
1057 #endif /* CONFIG_VSX */
1059 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception)
1061 struct pt_regs *old_regs;
1063 old_regs = set_irq_regs(regs);
1067 /* Real mode flagged P9 special emu is needed */
1068 if (local_paca->hmi_p9_special_emu) {
1069 local_paca->hmi_p9_special_emu = 0;
1072 * We don't want to take page faults while doing the
1073 * emulation, we just replay the instruction if necessary.
1075 pagefault_disable();
1076 p9_hmi_special_emu(regs);
1079 #endif /* CONFIG_VSX */
1081 if (ppc_md.handle_hmi_exception)
1082 ppc_md.handle_hmi_exception(regs);
1085 set_irq_regs(old_regs);
1088 DEFINE_INTERRUPT_HANDLER(unknown_exception)
1090 enum ctx_state prev_state = exception_enter();
1092 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1093 regs->nip, regs->msr, regs->trap);
1095 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1097 exception_exit(prev_state);
1100 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception)
1102 enum ctx_state prev_state = exception_enter();
1104 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1105 regs->nip, regs->msr, regs->trap);
1107 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1109 exception_exit(prev_state);
1112 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception)
1114 enum ctx_state prev_state = exception_enter();
1116 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
1117 5, SIGTRAP) == NOTIFY_STOP)
1119 if (debugger_iabr_match(regs))
1121 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1124 exception_exit(prev_state);
1127 DEFINE_INTERRUPT_HANDLER(RunModeException)
1129 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1132 DEFINE_INTERRUPT_HANDLER(single_step_exception)
1134 enum ctx_state prev_state = exception_enter();
1136 clear_single_step(regs);
1137 clear_br_trace(regs);
1139 if (kprobe_post_handler(regs))
1142 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1143 5, SIGTRAP) == NOTIFY_STOP)
1145 if (debugger_sstep(regs))
1148 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1151 exception_exit(prev_state);
1153 NOKPROBE_SYMBOL(single_step_exception);
1156 * After we have successfully emulated an instruction, we have to
1157 * check if the instruction was being single-stepped, and if so,
1158 * pretend we got a single-step exception. This was pointed out
1159 * by Kumar Gala. -- paulus
1161 static void emulate_single_step(struct pt_regs *regs)
1163 if (single_stepping(regs))
1164 single_step_exception(regs);
1167 static inline int __parse_fpscr(unsigned long fpscr)
1169 int ret = FPE_FLTUNK;
1171 /* Invalid operation */
1172 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1176 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1180 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1183 /* Divide by zero */
1184 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1187 /* Inexact result */
1188 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1194 static void parse_fpe(struct pt_regs *regs)
1198 flush_fp_to_thread(current);
1200 #ifdef CONFIG_PPC_FPU_REGS
1201 code = __parse_fpscr(current->thread.fp_state.fpscr);
1204 _exception(SIGFPE, regs, code, regs->nip);
1208 * Illegal instruction emulation support. Originally written to
1209 * provide the PVR to user applications using the mfspr rd, PVR.
1210 * Return non-zero if we can't emulate, or -EFAULT if the associated
1211 * memory access caused an access fault. Return zero on success.
1213 * There are a couple of ways to do this, either "decode" the instruction
1214 * or directly match lots of bits. In this case, matching lots of
1215 * bits is faster and easier.
1218 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1220 u8 rT = (instword >> 21) & 0x1f;
1221 u8 rA = (instword >> 16) & 0x1f;
1222 u8 NB_RB = (instword >> 11) & 0x1f;
1227 /* Early out if we are an invalid form of lswx */
1228 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1229 if ((rT == rA) || (rT == NB_RB))
1232 EA = (rA == 0) ? 0 : regs->gpr[rA];
1234 switch (instword & PPC_INST_STRING_MASK) {
1236 case PPC_INST_STSWX:
1238 num_bytes = regs->xer & 0x7f;
1241 case PPC_INST_STSWI:
1242 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1248 while (num_bytes != 0)
1251 u32 shift = 8 * (3 - (pos & 0x3));
1253 /* if process is 32-bit, clear upper 32 bits of EA */
1254 if ((regs->msr & MSR_64BIT) == 0)
1257 switch ((instword & PPC_INST_STRING_MASK)) {
1260 if (get_user(val, (u8 __user *)EA))
1262 /* first time updating this reg,
1266 regs->gpr[rT] |= val << shift;
1268 case PPC_INST_STSWI:
1269 case PPC_INST_STSWX:
1270 val = regs->gpr[rT] >> shift;
1271 if (put_user(val, (u8 __user *)EA))
1275 /* move EA to next address */
1279 /* manage our position within the register */
1290 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1295 ra = (instword >> 16) & 0x1f;
1296 rs = (instword >> 21) & 0x1f;
1298 tmp = regs->gpr[rs];
1299 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1300 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1301 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1302 regs->gpr[ra] = tmp;
1307 static int emulate_isel(struct pt_regs *regs, u32 instword)
1309 u8 rT = (instword >> 21) & 0x1f;
1310 u8 rA = (instword >> 16) & 0x1f;
1311 u8 rB = (instword >> 11) & 0x1f;
1312 u8 BC = (instword >> 6) & 0x1f;
1316 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1317 bit = (regs->ccr >> (31 - BC)) & 0x1;
1319 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1324 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1325 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1327 /* If we're emulating a load/store in an active transaction, we cannot
1328 * emulate it as the kernel operates in transaction suspended context.
1329 * We need to abort the transaction. This creates a persistent TM
1330 * abort so tell the user what caused it with a new code.
1332 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1340 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1346 static int emulate_instruction(struct pt_regs *regs)
1351 if (!user_mode(regs))
1353 CHECK_FULL_REGS(regs);
1355 if (get_user(instword, (u32 __user *)(regs->nip)))
1358 /* Emulate the mfspr rD, PVR. */
1359 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1360 PPC_WARN_EMULATED(mfpvr, regs);
1361 rd = (instword >> 21) & 0x1f;
1362 regs->gpr[rd] = mfspr(SPRN_PVR);
1366 /* Emulating the dcba insn is just a no-op. */
1367 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1368 PPC_WARN_EMULATED(dcba, regs);
1372 /* Emulate the mcrxr insn. */
1373 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1374 int shift = (instword >> 21) & 0x1c;
1375 unsigned long msk = 0xf0000000UL >> shift;
1377 PPC_WARN_EMULATED(mcrxr, regs);
1378 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1379 regs->xer &= ~0xf0000000UL;
1383 /* Emulate load/store string insn. */
1384 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1385 if (tm_abort_check(regs,
1386 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1388 PPC_WARN_EMULATED(string, regs);
1389 return emulate_string_inst(regs, instword);
1392 /* Emulate the popcntb (Population Count Bytes) instruction. */
1393 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1394 PPC_WARN_EMULATED(popcntb, regs);
1395 return emulate_popcntb_inst(regs, instword);
1398 /* Emulate isel (Integer Select) instruction */
1399 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1400 PPC_WARN_EMULATED(isel, regs);
1401 return emulate_isel(regs, instword);
1404 /* Emulate sync instruction variants */
1405 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1406 PPC_WARN_EMULATED(sync, regs);
1407 asm volatile("sync");
1412 /* Emulate the mfspr rD, DSCR. */
1413 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1414 PPC_INST_MFSPR_DSCR_USER) ||
1415 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1416 PPC_INST_MFSPR_DSCR)) &&
1417 cpu_has_feature(CPU_FTR_DSCR)) {
1418 PPC_WARN_EMULATED(mfdscr, regs);
1419 rd = (instword >> 21) & 0x1f;
1420 regs->gpr[rd] = mfspr(SPRN_DSCR);
1423 /* Emulate the mtspr DSCR, rD. */
1424 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1425 PPC_INST_MTSPR_DSCR_USER) ||
1426 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1427 PPC_INST_MTSPR_DSCR)) &&
1428 cpu_has_feature(CPU_FTR_DSCR)) {
1429 PPC_WARN_EMULATED(mtdscr, regs);
1430 rd = (instword >> 21) & 0x1f;
1431 current->thread.dscr = regs->gpr[rd];
1432 current->thread.dscr_inherit = 1;
1433 mtspr(SPRN_DSCR, current->thread.dscr);
1441 int is_valid_bugaddr(unsigned long addr)
1443 return is_kernel_addr(addr);
1446 #ifdef CONFIG_MATH_EMULATION
1447 static int emulate_math(struct pt_regs *regs)
1450 extern int do_mathemu(struct pt_regs *regs);
1452 ret = do_mathemu(regs);
1454 PPC_WARN_EMULATED(math, regs);
1458 emulate_single_step(regs);
1462 code = __parse_fpscr(current->thread.fp_state.fpscr);
1463 _exception(SIGFPE, regs, code, regs->nip);
1467 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1474 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1477 static void do_program_check(struct pt_regs *regs)
1479 unsigned int reason = get_reason(regs);
1481 /* We can now get here via a FP Unavailable exception if the core
1482 * has no FPU, in that case the reason flags will be 0 */
1484 if (reason & REASON_FP) {
1485 /* IEEE FP exception */
1489 if (reason & REASON_TRAP) {
1490 unsigned long bugaddr;
1491 /* Debugger is first in line to stop recursive faults in
1492 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1493 if (debugger_bpt(regs))
1496 if (kprobe_handler(regs))
1499 /* trap exception */
1500 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1504 bugaddr = regs->nip;
1506 * Fixup bugaddr for BUG_ON() in real mode
1508 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1509 bugaddr += PAGE_OFFSET;
1511 if (!(regs->msr & MSR_PR) && /* not user-mode */
1512 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1516 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1519 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1520 if (reason & REASON_TM) {
1521 /* This is a TM "Bad Thing Exception" program check.
1523 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1524 * transition in TM states.
1525 * - A trechkpt is attempted when transactional.
1526 * - A treclaim is attempted when non transactional.
1527 * - A tend is illegally attempted.
1528 * - writing a TM SPR when transactional.
1530 * If usermode caused this, it's done something illegal and
1531 * gets a SIGILL slap on the wrist. We call it an illegal
1532 * operand to distinguish from the instruction just being bad
1533 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1534 * illegal /placement/ of a valid instruction.
1536 if (user_mode(regs)) {
1537 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1540 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1541 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1542 regs->nip, regs->msr, get_paca()->tm_scratch);
1543 die("Unrecoverable exception", regs, SIGABRT);
1549 * If we took the program check in the kernel skip down to sending a
1550 * SIGILL. The subsequent cases all relate to emulating instructions
1551 * which we should only do for userspace. We also do not want to enable
1552 * interrupts for kernel faults because that might lead to further
1553 * faults, and loose the context of the original exception.
1555 if (!user_mode(regs))
1558 /* We restore the interrupt state now */
1559 if (!arch_irq_disabled_regs(regs))
1562 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1563 * but there seems to be a hardware bug on the 405GP (RevD)
1564 * that means ESR is sometimes set incorrectly - either to
1565 * ESR_DST (!?) or 0. In the process of chasing this with the
1566 * hardware people - not sure if it can happen on any illegal
1567 * instruction or only on FP instructions, whether there is a
1568 * pattern to occurrences etc. -dgibson 31/Mar/2003
1570 if (!emulate_math(regs))
1573 /* Try to emulate it if we should. */
1574 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1575 switch (emulate_instruction(regs)) {
1578 emulate_single_step(regs);
1581 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1587 if (reason & REASON_PRIVILEGED)
1588 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1590 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1594 DEFINE_INTERRUPT_HANDLER(program_check_exception)
1596 enum ctx_state prev_state = exception_enter();
1598 do_program_check(regs);
1600 exception_exit(prev_state);
1602 NOKPROBE_SYMBOL(program_check_exception);
1605 * This occurs when running in hypervisor mode on POWER6 or later
1606 * and an illegal instruction is encountered.
1608 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt)
1610 enum ctx_state prev_state = exception_enter();
1612 regs->msr |= REASON_ILLEGAL;
1613 do_program_check(regs);
1615 exception_exit(prev_state);
1617 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1619 DEFINE_INTERRUPT_HANDLER(alignment_exception)
1621 enum ctx_state prev_state = exception_enter();
1622 int sig, code, fixed = 0;
1623 unsigned long reason;
1625 /* We restore the interrupt state now */
1626 if (!arch_irq_disabled_regs(regs))
1629 reason = get_reason(regs);
1631 if (reason & REASON_BOUNDARY) {
1637 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1640 /* we don't implement logging of alignment exceptions */
1641 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1642 fixed = fix_alignment(regs);
1645 /* skip over emulated instruction */
1646 regs->nip += inst_length(reason);
1647 emulate_single_step(regs);
1651 /* Operand address was bad */
1652 if (fixed == -EFAULT) {
1660 if (user_mode(regs))
1661 _exception(sig, regs, code, regs->dar);
1663 bad_page_fault(regs, sig);
1666 exception_exit(prev_state);
1669 DEFINE_INTERRUPT_HANDLER(StackOverflow)
1671 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1672 current->comm, task_pid_nr(current), regs->gpr[1]);
1675 panic("kernel stack overflow");
1678 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception)
1680 enum ctx_state prev_state = exception_enter();
1682 die("Kernel stack overflow", regs, SIGSEGV);
1684 exception_exit(prev_state);
1687 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception)
1689 enum ctx_state prev_state = exception_enter();
1691 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1692 "%lx at %lx\n", regs->trap, regs->nip);
1693 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1695 exception_exit(prev_state);
1698 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception)
1700 enum ctx_state prev_state = exception_enter();
1702 if (user_mode(regs)) {
1703 /* A user program has executed an altivec instruction,
1704 but this kernel doesn't support altivec. */
1705 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1709 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1710 "%lx at %lx\n", regs->trap, regs->nip);
1711 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1714 exception_exit(prev_state);
1717 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception)
1719 if (user_mode(regs)) {
1720 /* A user program has executed an vsx instruction,
1721 but this kernel doesn't support vsx. */
1722 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1726 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1727 "%lx at %lx\n", regs->trap, regs->nip);
1728 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1732 static void tm_unavailable(struct pt_regs *regs)
1734 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1735 if (user_mode(regs)) {
1736 current->thread.load_tm++;
1737 regs->msr |= MSR_TM;
1739 tm_restore_sprs(¤t->thread);
1743 pr_emerg("Unrecoverable TM Unavailable Exception "
1744 "%lx at %lx\n", regs->trap, regs->nip);
1745 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1748 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception)
1750 static char *facility_strings[] = {
1751 [FSCR_FP_LG] = "FPU",
1752 [FSCR_VECVSX_LG] = "VMX/VSX",
1753 [FSCR_DSCR_LG] = "DSCR",
1754 [FSCR_PM_LG] = "PMU SPRs",
1755 [FSCR_BHRB_LG] = "BHRB",
1756 [FSCR_TM_LG] = "TM",
1757 [FSCR_EBB_LG] = "EBB",
1758 [FSCR_TAR_LG] = "TAR",
1759 [FSCR_MSGP_LG] = "MSGP",
1760 [FSCR_SCV_LG] = "SCV",
1761 [FSCR_PREFIX_LG] = "PREFIX",
1763 char *facility = "unknown";
1769 hv = (TRAP(regs) == 0xf80);
1771 value = mfspr(SPRN_HFSCR);
1773 value = mfspr(SPRN_FSCR);
1775 status = value >> 56;
1776 if ((hv || status >= 2) &&
1777 (status < ARRAY_SIZE(facility_strings)) &&
1778 facility_strings[status])
1779 facility = facility_strings[status];
1781 /* We should not have taken this interrupt in kernel */
1782 if (!user_mode(regs)) {
1783 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1784 facility, status, regs->nip);
1785 die("Unexpected facility unavailable exception", regs, SIGABRT);
1788 /* We restore the interrupt state now */
1789 if (!arch_irq_disabled_regs(regs))
1792 if (status == FSCR_DSCR_LG) {
1794 * User is accessing the DSCR register using the problem
1795 * state only SPR number (0x03) either through a mfspr or
1796 * a mtspr instruction. If it is a write attempt through
1797 * a mtspr, then we set the inherit bit. This also allows
1798 * the user to write or read the register directly in the
1799 * future by setting via the FSCR DSCR bit. But in case it
1800 * is a read DSCR attempt through a mfspr instruction, we
1801 * just emulate the instruction instead. This code path will
1802 * always emulate all the mfspr instructions till the user
1803 * has attempted at least one mtspr instruction. This way it
1804 * preserves the same behaviour when the user is accessing
1805 * the DSCR through privilege level only SPR number (0x11)
1806 * which is emulated through illegal instruction exception.
1807 * We always leave HFSCR DSCR set.
1809 if (get_user(instword, (u32 __user *)(regs->nip))) {
1810 pr_err("Failed to fetch the user instruction\n");
1814 /* Write into DSCR (mtspr 0x03, RS) */
1815 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1816 == PPC_INST_MTSPR_DSCR_USER) {
1817 rd = (instword >> 21) & 0x1f;
1818 current->thread.dscr = regs->gpr[rd];
1819 current->thread.dscr_inherit = 1;
1820 current->thread.fscr |= FSCR_DSCR;
1821 mtspr(SPRN_FSCR, current->thread.fscr);
1824 /* Read from DSCR (mfspr RT, 0x03) */
1825 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1826 == PPC_INST_MFSPR_DSCR_USER) {
1827 if (emulate_instruction(regs)) {
1828 pr_err("DSCR based mfspr emulation failed\n");
1832 emulate_single_step(regs);
1837 if (status == FSCR_TM_LG) {
1839 * If we're here then the hardware is TM aware because it
1840 * generated an exception with FSRM_TM set.
1842 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1843 * told us not to do TM, or the kernel is not built with TM
1846 * If both of those things are true, then userspace can spam the
1847 * console by triggering the printk() below just by continually
1848 * doing tbegin (or any TM instruction). So in that case just
1849 * send the process a SIGILL immediately.
1851 if (!cpu_has_feature(CPU_FTR_TM))
1854 tm_unavailable(regs);
1858 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1859 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1862 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1866 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1868 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm)
1870 /* Note: This does not handle any kind of FP laziness. */
1872 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1873 regs->nip, regs->msr);
1875 /* We can only have got here if the task started using FP after
1876 * beginning the transaction. So, the transactional regs are just a
1877 * copy of the checkpointed ones. But, we still need to recheckpoint
1878 * as we're enabling FP for the process; it will return, abort the
1879 * transaction, and probably retry but now with FP enabled. So the
1880 * checkpointed FP registers need to be loaded.
1882 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1885 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1886 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1888 * At this point, ck{fp,vr}_state contains the exact values we want to
1892 /* Enable FP for the task: */
1893 current->thread.load_fp = 1;
1896 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1898 tm_recheckpoint(¤t->thread);
1901 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm)
1903 /* See the comments in fp_unavailable_tm(). This function operates
1907 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1909 regs->nip, regs->msr);
1910 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1911 current->thread.load_vec = 1;
1912 tm_recheckpoint(¤t->thread);
1913 current->thread.used_vr = 1;
1916 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm)
1918 /* See the comments in fp_unavailable_tm(). This works similarly,
1919 * though we're loading both FP and VEC registers in here.
1921 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1922 * regs. Either way, set MSR_VSX.
1925 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1927 regs->nip, regs->msr);
1929 current->thread.used_vsr = 1;
1931 /* This reclaims FP and/or VR regs if they're already enabled */
1932 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1934 current->thread.load_vec = 1;
1935 current->thread.load_fp = 1;
1937 tm_recheckpoint(¤t->thread);
1939 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1942 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi);
1943 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi)
1947 __this_cpu_inc(irq_stat.pmu_irqs);
1957 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async);
1958 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async)
1962 __this_cpu_inc(irq_stat.pmu_irqs);
1969 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception)
1972 * On 64-bit, if perf interrupts hit in a local_irq_disable
1973 * (soft-masked) region, we consider them as NMIs. This is required to
1974 * prevent hash faults on user addresses when reading callchains (and
1975 * looks better from an irq tracing perspective).
1977 if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs)))
1978 performance_monitor_exception_nmi(regs);
1980 performance_monitor_exception_async(regs);
1985 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1986 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1990 * Determine the cause of the debug event, clear the
1991 * event flags and send a trap to the handler. Torez
1993 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1994 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1995 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1996 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1998 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
2001 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
2002 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
2003 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
2006 } else if (debug_status & DBSR_IAC1) {
2007 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
2008 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
2009 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
2012 } else if (debug_status & DBSR_IAC2) {
2013 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
2014 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
2017 } else if (debug_status & DBSR_IAC3) {
2018 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
2019 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
2020 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
2023 } else if (debug_status & DBSR_IAC4) {
2024 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
2025 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
2030 * At the point this routine was called, the MSR(DE) was turned off.
2031 * Check all other debug flags and see if that bit needs to be turned
2034 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
2035 current->thread.debug.dbcr1))
2036 regs->msr |= MSR_DE;
2038 /* Make sure the IDM flag is off */
2039 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
2042 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
2045 DEFINE_INTERRUPT_HANDLER(DebugException)
2047 unsigned long debug_status = regs->dsisr;
2049 current->thread.debug.dbsr = debug_status;
2051 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
2052 * on server, it stops on the target of the branch. In order to simulate
2053 * the server behaviour, we thus restart right away with a single step
2054 * instead of stopping here when hitting a BT
2056 if (debug_status & DBSR_BT) {
2057 regs->msr &= ~MSR_DE;
2060 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
2061 /* Clear the BT event */
2062 mtspr(SPRN_DBSR, DBSR_BT);
2064 /* Do the single step trick only when coming from userspace */
2065 if (user_mode(regs)) {
2066 current->thread.debug.dbcr0 &= ~DBCR0_BT;
2067 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2068 regs->msr |= MSR_DE;
2072 if (kprobe_post_handler(regs))
2075 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
2076 5, SIGTRAP) == NOTIFY_STOP) {
2079 if (debugger_sstep(regs))
2081 } else if (debug_status & DBSR_IC) { /* Instruction complete */
2082 regs->msr &= ~MSR_DE;
2084 /* Disable instruction completion */
2085 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
2086 /* Clear the instruction completion event */
2087 mtspr(SPRN_DBSR, DBSR_IC);
2089 if (kprobe_post_handler(regs))
2092 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
2093 5, SIGTRAP) == NOTIFY_STOP) {
2097 if (debugger_sstep(regs))
2100 if (user_mode(regs)) {
2101 current->thread.debug.dbcr0 &= ~DBCR0_IC;
2102 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
2103 current->thread.debug.dbcr1))
2104 regs->msr |= MSR_DE;
2106 /* Make sure the IDM bit is off */
2107 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
2110 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
2112 handle_debug(regs, debug_status);
2114 NOKPROBE_SYMBOL(DebugException);
2115 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2117 #ifdef CONFIG_ALTIVEC
2118 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception)
2122 if (!user_mode(regs)) {
2123 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
2124 " at %lx\n", regs->nip);
2125 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
2128 flush_altivec_to_thread(current);
2130 PPC_WARN_EMULATED(altivec, regs);
2131 err = emulate_altivec(regs);
2133 regs->nip += 4; /* skip emulated instruction */
2134 emulate_single_step(regs);
2138 if (err == -EFAULT) {
2139 /* got an error reading the instruction */
2140 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2142 /* didn't recognize the instruction */
2143 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2144 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
2145 "in %s at %lx\n", current->comm, regs->nip);
2146 current->thread.vr_state.vscr.u[3] |= 0x10000;
2149 #endif /* CONFIG_ALTIVEC */
2151 #ifdef CONFIG_FSL_BOOKE
2152 DEFINE_INTERRUPT_HANDLER(CacheLockingException)
2154 unsigned long error_code = regs->dsisr;
2156 /* We treat cache locking instructions from the user
2157 * as priv ops, in the future we could try to do
2160 if (error_code & (ESR_DLK|ESR_ILK))
2161 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
2164 #endif /* CONFIG_FSL_BOOKE */
2167 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException)
2169 extern int do_spe_mathemu(struct pt_regs *regs);
2170 unsigned long spefscr;
2172 int code = FPE_FLTUNK;
2175 /* We restore the interrupt state now */
2176 if (!arch_irq_disabled_regs(regs))
2179 flush_spe_to_thread(current);
2181 spefscr = current->thread.spefscr;
2182 fpexc_mode = current->thread.fpexc_mode;
2184 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
2187 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
2190 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
2192 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
2195 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
2198 err = do_spe_mathemu(regs);
2200 regs->nip += 4; /* skip emulated instruction */
2201 emulate_single_step(regs);
2205 if (err == -EFAULT) {
2206 /* got an error reading the instruction */
2207 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2208 } else if (err == -EINVAL) {
2209 /* didn't recognize the instruction */
2210 printk(KERN_ERR "unrecognized spe instruction "
2211 "in %s at %lx\n", current->comm, regs->nip);
2213 _exception(SIGFPE, regs, code, regs->nip);
2219 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException)
2221 extern int speround_handler(struct pt_regs *regs);
2224 /* We restore the interrupt state now */
2225 if (!arch_irq_disabled_regs(regs))
2229 if (regs->msr & MSR_SPE)
2230 giveup_spe(current);
2234 err = speround_handler(regs);
2236 regs->nip += 4; /* skip emulated instruction */
2237 emulate_single_step(regs);
2241 if (err == -EFAULT) {
2242 /* got an error reading the instruction */
2243 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2244 } else if (err == -EINVAL) {
2245 /* didn't recognize the instruction */
2246 printk(KERN_ERR "unrecognized spe instruction "
2247 "in %s at %lx\n", current->comm, regs->nip);
2249 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip);
2256 * We enter here if we get an unrecoverable exception, that is, one
2257 * that happened at a point where the RI (recoverable interrupt) bit
2258 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2259 * we therefore lost state by taking this exception.
2261 DEFINE_INTERRUPT_HANDLER(unrecoverable_exception)
2263 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2264 regs->trap, regs->nip, regs->msr);
2265 die("Unrecoverable exception", regs, SIGABRT);
2267 NOKPROBE_SYMBOL(unrecoverable_exception);
2269 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2271 * Default handler for a Watchdog exception,
2272 * spins until a reboot occurs
2274 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2276 /* Generic WatchdogHandler, implement your own */
2277 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2281 DEFINE_INTERRUPT_HANDLER(WatchdogException) /* XXX NMI? async? */
2283 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2284 WatchdogHandler(regs);
2289 * We enter here if we discover during exception entry that we are
2290 * running in supervisor mode with a userspace value in the stack pointer.
2292 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack)
2294 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2295 regs->gpr[1], regs->nip);
2296 die("Bad kernel stack pointer", regs, SIGABRT);
2298 NOKPROBE_SYMBOL(kernel_bad_stack);
2300 void __init trap_init(void)
2305 #ifdef CONFIG_PPC_EMULATED_STATS
2307 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2309 struct ppc_emulated ppc_emulated = {
2310 #ifdef CONFIG_ALTIVEC
2311 WARN_EMULATED_SETUP(altivec),
2313 WARN_EMULATED_SETUP(dcba),
2314 WARN_EMULATED_SETUP(dcbz),
2315 WARN_EMULATED_SETUP(fp_pair),
2316 WARN_EMULATED_SETUP(isel),
2317 WARN_EMULATED_SETUP(mcrxr),
2318 WARN_EMULATED_SETUP(mfpvr),
2319 WARN_EMULATED_SETUP(multiple),
2320 WARN_EMULATED_SETUP(popcntb),
2321 WARN_EMULATED_SETUP(spe),
2322 WARN_EMULATED_SETUP(string),
2323 WARN_EMULATED_SETUP(sync),
2324 WARN_EMULATED_SETUP(unaligned),
2325 #ifdef CONFIG_MATH_EMULATION
2326 WARN_EMULATED_SETUP(math),
2329 WARN_EMULATED_SETUP(vsx),
2332 WARN_EMULATED_SETUP(mfdscr),
2333 WARN_EMULATED_SETUP(mtdscr),
2334 WARN_EMULATED_SETUP(lq_stq),
2335 WARN_EMULATED_SETUP(lxvw4x),
2336 WARN_EMULATED_SETUP(lxvh8x),
2337 WARN_EMULATED_SETUP(lxvd2x),
2338 WARN_EMULATED_SETUP(lxvb16x),
2342 u32 ppc_warn_emulated;
2344 void ppc_warn_emulated_print(const char *type)
2346 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2350 static int __init ppc_warn_emulated_init(void)
2354 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2356 dir = debugfs_create_dir("emulated_instructions",
2357 powerpc_debugfs_root);
2359 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated);
2361 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++)
2362 debugfs_create_u32(entries[i].name, 0644, dir,
2363 (u32 *)&entries[i].val.counter);
2368 device_initcall(ppc_warn_emulated_init);
2370 #endif /* CONFIG_PPC_EMULATED_STATS */