2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
48 #ifdef CONFIG_PMAC_BACKLIGHT
49 #include <asm/backlight.h>
52 #include <asm/firmware.h>
53 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
62 #include <asm/debug.h>
63 #include <sysdev/fsl_pci.h>
65 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
66 int (*__debugger)(struct pt_regs *regs) __read_mostly;
67 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
71 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
74 EXPORT_SYMBOL(__debugger);
75 EXPORT_SYMBOL(__debugger_ipi);
76 EXPORT_SYMBOL(__debugger_bpt);
77 EXPORT_SYMBOL(__debugger_sstep);
78 EXPORT_SYMBOL(__debugger_iabr_match);
79 EXPORT_SYMBOL(__debugger_break_match);
80 EXPORT_SYMBOL(__debugger_fault_handler);
83 /* Transactional Memory trap debug */
85 #define TM_DEBUG(x...) printk(KERN_INFO x)
87 #define TM_DEBUG(x...) do { } while(0)
91 * Trap & Exception support
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 static void pmac_backlight_unblank(void)
97 mutex_lock(&pmac_backlight_mutex);
99 struct backlight_properties *props;
101 props = &pmac_backlight->props;
102 props->brightness = props->max_brightness;
103 props->power = FB_BLANK_UNBLANK;
104 backlight_update_status(pmac_backlight);
106 mutex_unlock(&pmac_backlight_mutex);
109 static inline void pmac_backlight_unblank(void) { }
112 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
113 static int die_owner = -1;
114 static unsigned int die_nest_count;
115 static int die_counter;
117 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
127 /* racy, but better than risking deadlock. */
128 raw_local_irq_save(flags);
129 cpu = smp_processor_id();
130 if (!arch_spin_trylock(&die_lock)) {
131 if (cpu == die_owner)
132 /* nested oops. should stop eventually */;
134 arch_spin_lock(&die_lock);
140 if (machine_is(powermac))
141 pmac_backlight_unblank();
145 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
150 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
155 /* Nest count reaches zero, release the lock. */
156 arch_spin_unlock(&die_lock);
157 raw_local_irq_restore(flags);
159 crash_fadump(regs, "die oops");
162 * A system reset (0x100) is a request to dump, so we always send
163 * it through the crashdump code.
165 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
169 * We aren't the primary crash CPU. We need to send it
170 * to a holding pattern to avoid it ending up in the panic
173 crash_kexec_secondary(regs);
180 * While our oops output is serialised by a spinlock, output
181 * from panic() called below can race and corrupt it. If we
182 * know we are going to panic, delay for 1 second so we have a
183 * chance to get clean backtraces from all CPUs that are oopsing.
185 if (in_interrupt() || panic_on_oops || !current->pid ||
186 is_global_init(current)) {
187 mdelay(MSEC_PER_SEC);
191 panic("Fatal exception in interrupt");
193 panic("Fatal exception");
197 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
199 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
200 #ifdef CONFIG_PREEMPT
204 printk("SMP NR_CPUS=%d ", NR_CPUS);
206 #ifdef CONFIG_DEBUG_PAGEALLOC
207 printk("DEBUG_PAGEALLOC ");
212 printk("%s\n", ppc_md.name ? ppc_md.name : "");
214 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
223 void die(const char *str, struct pt_regs *regs, long err)
225 unsigned long flags = oops_begin(regs);
227 if (__die(str, regs, err))
229 oops_end(flags, regs, err);
232 void user_single_step_siginfo(struct task_struct *tsk,
233 struct pt_regs *regs, siginfo_t *info)
235 memset(info, 0, sizeof(*info));
236 info->si_signo = SIGTRAP;
237 info->si_code = TRAP_TRACE;
238 info->si_addr = (void __user *)regs->nip;
241 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
244 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
245 "at %08lx nip %08lx lr %08lx code %x\n";
246 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
247 "at %016lx nip %016lx lr %016lx code %x\n";
249 if (!user_mode(regs)) {
250 die("Exception in kernel mode", regs, signr);
254 if (show_unhandled_signals && unhandled_signal(current, signr)) {
255 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
256 current->comm, current->pid, signr,
257 addr, regs->nip, regs->link, code);
260 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
263 current->thread.trap_nr = code;
264 memset(&info, 0, sizeof(info));
265 info.si_signo = signr;
267 info.si_addr = (void __user *) addr;
268 force_sig_info(signr, &info, current);
272 void system_reset_exception(struct pt_regs *regs)
274 /* See if any machine dependent calls */
275 if (ppc_md.system_reset_exception) {
276 if (ppc_md.system_reset_exception(regs))
280 die("System Reset", regs, SIGABRT);
282 /* Must die if the interrupt is not recoverable */
283 if (!(regs->msr & MSR_RI))
284 panic("Unrecoverable System Reset");
286 /* What should we do here? We could issue a shutdown or hard reset. */
290 * This function is called in real mode. Strictly no printk's please.
292 * regs->nip and regs->msr contains srr0 and ssr1.
294 long machine_check_early(struct pt_regs *regs)
298 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
299 handled = cur_cpu_spec->machine_check_early(regs);
306 * I/O accesses can cause machine checks on powermacs.
307 * Check if the NIP corresponds to the address of a sync
308 * instruction for which there is an entry in the exception
310 * Note that the 601 only takes a machine check on TEA
311 * (transfer error ack) signal assertion, and does not
312 * set any of the top 16 bits of SRR1.
315 static inline int check_io_access(struct pt_regs *regs)
318 unsigned long msr = regs->msr;
319 const struct exception_table_entry *entry;
320 unsigned int *nip = (unsigned int *)regs->nip;
322 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
323 && (entry = search_exception_tables(regs->nip)) != NULL) {
325 * Check that it's a sync instruction, or somewhere
326 * in the twi; isync; nop sequence that inb/inw/inl uses.
327 * As the address is in the exception table
328 * we should be able to read the instr there.
329 * For the debug message, we look at the preceding
332 if (*nip == 0x60000000) /* nop */
334 else if (*nip == 0x4c00012c) /* isync */
336 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
341 rb = (*nip >> 11) & 0x1f;
342 printk(KERN_DEBUG "%s bad port %lx at %p\n",
343 (*nip & 0x100)? "OUT to": "IN from",
344 regs->gpr[rb] - _IO_BASE, nip);
346 regs->nip = entry->fixup;
350 #endif /* CONFIG_PPC32 */
354 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
355 /* On 4xx, the reason for the machine check or program exception
357 #define get_reason(regs) ((regs)->dsisr)
358 #ifndef CONFIG_FSL_BOOKE
359 #define get_mc_reason(regs) ((regs)->dsisr)
361 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
363 #define REASON_FP ESR_FP
364 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
365 #define REASON_PRIVILEGED ESR_PPR
366 #define REASON_TRAP ESR_PTR
368 /* single-step stuff */
369 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
370 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
373 /* On non-4xx, the reason for the machine check or program
374 exception is in the MSR. */
375 #define get_reason(regs) ((regs)->msr)
376 #define get_mc_reason(regs) ((regs)->msr)
377 #define REASON_TM 0x200000
378 #define REASON_FP 0x100000
379 #define REASON_ILLEGAL 0x80000
380 #define REASON_PRIVILEGED 0x40000
381 #define REASON_TRAP 0x20000
383 #define single_stepping(regs) ((regs)->msr & MSR_SE)
384 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
387 #if defined(CONFIG_4xx)
388 int machine_check_4xx(struct pt_regs *regs)
390 unsigned long reason = get_mc_reason(regs);
392 if (reason & ESR_IMCP) {
393 printk("Instruction");
394 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
397 printk(" machine check in kernel mode.\n");
402 int machine_check_440A(struct pt_regs *regs)
404 unsigned long reason = get_mc_reason(regs);
406 printk("Machine check in kernel mode.\n");
407 if (reason & ESR_IMCP){
408 printk("Instruction Synchronous Machine Check exception\n");
409 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
412 u32 mcsr = mfspr(SPRN_MCSR);
414 printk("Instruction Read PLB Error\n");
416 printk("Data Read PLB Error\n");
418 printk("Data Write PLB Error\n");
419 if (mcsr & MCSR_TLBP)
420 printk("TLB Parity Error\n");
421 if (mcsr & MCSR_ICP){
422 flush_instruction_cache();
423 printk("I-Cache Parity Error\n");
425 if (mcsr & MCSR_DCSP)
426 printk("D-Cache Search Parity Error\n");
427 if (mcsr & MCSR_DCFP)
428 printk("D-Cache Flush Parity Error\n");
429 if (mcsr & MCSR_IMPE)
430 printk("Machine Check exception is imprecise\n");
433 mtspr(SPRN_MCSR, mcsr);
438 int machine_check_47x(struct pt_regs *regs)
440 unsigned long reason = get_mc_reason(regs);
443 printk(KERN_ERR "Machine check in kernel mode.\n");
444 if (reason & ESR_IMCP) {
446 "Instruction Synchronous Machine Check exception\n");
447 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
450 mcsr = mfspr(SPRN_MCSR);
452 printk(KERN_ERR "Instruction Read PLB Error\n");
454 printk(KERN_ERR "Data Read PLB Error\n");
456 printk(KERN_ERR "Data Write PLB Error\n");
457 if (mcsr & MCSR_TLBP)
458 printk(KERN_ERR "TLB Parity Error\n");
459 if (mcsr & MCSR_ICP) {
460 flush_instruction_cache();
461 printk(KERN_ERR "I-Cache Parity Error\n");
463 if (mcsr & MCSR_DCSP)
464 printk(KERN_ERR "D-Cache Search Parity Error\n");
465 if (mcsr & PPC47x_MCSR_GPR)
466 printk(KERN_ERR "GPR Parity Error\n");
467 if (mcsr & PPC47x_MCSR_FPR)
468 printk(KERN_ERR "FPR Parity Error\n");
469 if (mcsr & PPC47x_MCSR_IPR)
470 printk(KERN_ERR "Machine Check exception is imprecise\n");
473 mtspr(SPRN_MCSR, mcsr);
477 #elif defined(CONFIG_E500)
478 int machine_check_e500mc(struct pt_regs *regs)
480 unsigned long mcsr = mfspr(SPRN_MCSR);
481 unsigned long reason = mcsr;
484 if (reason & MCSR_LD) {
485 recoverable = fsl_rio_mcheck_exception(regs);
486 if (recoverable == 1)
490 printk("Machine check in kernel mode.\n");
491 printk("Caused by (from MCSR=%lx): ", reason);
493 if (reason & MCSR_MCP)
494 printk("Machine Check Signal\n");
496 if (reason & MCSR_ICPERR) {
497 printk("Instruction Cache Parity Error\n");
500 * This is recoverable by invalidating the i-cache.
502 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
503 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
507 * This will generally be accompanied by an instruction
508 * fetch error report -- only treat MCSR_IF as fatal
509 * if it wasn't due to an L1 parity error.
514 if (reason & MCSR_DCPERR_MC) {
515 printk("Data Cache Parity Error\n");
518 * In write shadow mode we auto-recover from the error, but it
519 * may still get logged and cause a machine check. We should
520 * only treat the non-write shadow case as non-recoverable.
522 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
526 if (reason & MCSR_L2MMU_MHIT) {
527 printk("Hit on multiple TLB entries\n");
531 if (reason & MCSR_NMI)
532 printk("Non-maskable interrupt\n");
534 if (reason & MCSR_IF) {
535 printk("Instruction Fetch Error Report\n");
539 if (reason & MCSR_LD) {
540 printk("Load Error Report\n");
544 if (reason & MCSR_ST) {
545 printk("Store Error Report\n");
549 if (reason & MCSR_LDG) {
550 printk("Guarded Load Error Report\n");
554 if (reason & MCSR_TLBSYNC)
555 printk("Simultaneous tlbsync operations\n");
557 if (reason & MCSR_BSL2_ERR) {
558 printk("Level 2 Cache Error\n");
562 if (reason & MCSR_MAV) {
565 addr = mfspr(SPRN_MCAR);
566 addr |= (u64)mfspr(SPRN_MCARU) << 32;
568 printk("Machine Check %s Address: %#llx\n",
569 reason & MCSR_MEA ? "Effective" : "Physical", addr);
573 mtspr(SPRN_MCSR, mcsr);
574 return mfspr(SPRN_MCSR) == 0 && recoverable;
577 int machine_check_e500(struct pt_regs *regs)
579 unsigned long reason = get_mc_reason(regs);
581 if (reason & MCSR_BUS_RBERR) {
582 if (fsl_rio_mcheck_exception(regs))
584 if (fsl_pci_mcheck_exception(regs))
588 printk("Machine check in kernel mode.\n");
589 printk("Caused by (from MCSR=%lx): ", reason);
591 if (reason & MCSR_MCP)
592 printk("Machine Check Signal\n");
593 if (reason & MCSR_ICPERR)
594 printk("Instruction Cache Parity Error\n");
595 if (reason & MCSR_DCP_PERR)
596 printk("Data Cache Push Parity Error\n");
597 if (reason & MCSR_DCPERR)
598 printk("Data Cache Parity Error\n");
599 if (reason & MCSR_BUS_IAERR)
600 printk("Bus - Instruction Address Error\n");
601 if (reason & MCSR_BUS_RAERR)
602 printk("Bus - Read Address Error\n");
603 if (reason & MCSR_BUS_WAERR)
604 printk("Bus - Write Address Error\n");
605 if (reason & MCSR_BUS_IBERR)
606 printk("Bus - Instruction Data Error\n");
607 if (reason & MCSR_BUS_RBERR)
608 printk("Bus - Read Data Bus Error\n");
609 if (reason & MCSR_BUS_WBERR)
610 printk("Bus - Read Data Bus Error\n");
611 if (reason & MCSR_BUS_IPERR)
612 printk("Bus - Instruction Parity Error\n");
613 if (reason & MCSR_BUS_RPERR)
614 printk("Bus - Read Parity Error\n");
619 int machine_check_generic(struct pt_regs *regs)
623 #elif defined(CONFIG_E200)
624 int machine_check_e200(struct pt_regs *regs)
626 unsigned long reason = get_mc_reason(regs);
628 printk("Machine check in kernel mode.\n");
629 printk("Caused by (from MCSR=%lx): ", reason);
631 if (reason & MCSR_MCP)
632 printk("Machine Check Signal\n");
633 if (reason & MCSR_CP_PERR)
634 printk("Cache Push Parity Error\n");
635 if (reason & MCSR_CPERR)
636 printk("Cache Parity Error\n");
637 if (reason & MCSR_EXCP_ERR)
638 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
639 if (reason & MCSR_BUS_IRERR)
640 printk("Bus - Read Bus Error on instruction fetch\n");
641 if (reason & MCSR_BUS_DRERR)
642 printk("Bus - Read Bus Error on data load\n");
643 if (reason & MCSR_BUS_WRERR)
644 printk("Bus - Write Bus Error on buffered store or cache line push\n");
649 int machine_check_generic(struct pt_regs *regs)
651 unsigned long reason = get_mc_reason(regs);
653 printk("Machine check in kernel mode.\n");
654 printk("Caused by (from SRR1=%lx): ", reason);
655 switch (reason & 0x601F0000) {
657 printk("Machine check signal\n");
659 case 0: /* for 601 */
661 case 0x140000: /* 7450 MSS error and TEA */
662 printk("Transfer error ack signal\n");
665 printk("Data parity error signal\n");
668 printk("Address parity error signal\n");
671 printk("L1 Data Cache error\n");
674 printk("L1 Instruction Cache error\n");
677 printk("L2 data cache parity error\n");
680 printk("Unknown values in msr\n");
684 #endif /* everything else */
686 void machine_check_exception(struct pt_regs *regs)
688 enum ctx_state prev_state = exception_enter();
691 __get_cpu_var(irq_stat).mce_exceptions++;
693 /* See if any machine dependent calls. In theory, we would want
694 * to call the CPU first, and call the ppc_md. one if the CPU
695 * one returns a positive number. However there is existing code
696 * that assumes the board gets a first chance, so let's keep it
697 * that way for now and fix things later. --BenH.
699 if (ppc_md.machine_check_exception)
700 recover = ppc_md.machine_check_exception(regs);
701 else if (cur_cpu_spec->machine_check)
702 recover = cur_cpu_spec->machine_check(regs);
707 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
708 /* the qspan pci read routines can cause machine checks -- Cort
710 * yuck !!! that totally needs to go away ! There are better ways
711 * to deal with that than having a wart in the mcheck handler.
714 bad_page_fault(regs, regs->dar, SIGBUS);
718 if (debugger_fault_handler(regs))
721 if (check_io_access(regs))
724 die("Machine check", regs, SIGBUS);
726 /* Must die if the interrupt is not recoverable */
727 if (!(regs->msr & MSR_RI))
728 panic("Unrecoverable Machine check");
731 exception_exit(prev_state);
734 void SMIException(struct pt_regs *regs)
736 die("System Management Interrupt", regs, SIGABRT);
739 void unknown_exception(struct pt_regs *regs)
741 enum ctx_state prev_state = exception_enter();
743 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
744 regs->nip, regs->msr, regs->trap);
746 _exception(SIGTRAP, regs, 0, 0);
748 exception_exit(prev_state);
751 void instruction_breakpoint_exception(struct pt_regs *regs)
753 enum ctx_state prev_state = exception_enter();
755 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
756 5, SIGTRAP) == NOTIFY_STOP)
758 if (debugger_iabr_match(regs))
760 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
763 exception_exit(prev_state);
766 void RunModeException(struct pt_regs *regs)
768 _exception(SIGTRAP, regs, 0, 0);
771 void __kprobes single_step_exception(struct pt_regs *regs)
773 enum ctx_state prev_state = exception_enter();
775 clear_single_step(regs);
777 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
778 5, SIGTRAP) == NOTIFY_STOP)
780 if (debugger_sstep(regs))
783 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
786 exception_exit(prev_state);
790 * After we have successfully emulated an instruction, we have to
791 * check if the instruction was being single-stepped, and if so,
792 * pretend we got a single-step exception. This was pointed out
793 * by Kumar Gala. -- paulus
795 static void emulate_single_step(struct pt_regs *regs)
797 if (single_stepping(regs))
798 single_step_exception(regs);
801 static inline int __parse_fpscr(unsigned long fpscr)
805 /* Invalid operation */
806 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
810 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
814 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
818 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
822 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
828 static void parse_fpe(struct pt_regs *regs)
832 flush_fp_to_thread(current);
834 code = __parse_fpscr(current->thread.fp_state.fpscr);
836 _exception(SIGFPE, regs, code, regs->nip);
840 * Illegal instruction emulation support. Originally written to
841 * provide the PVR to user applications using the mfspr rd, PVR.
842 * Return non-zero if we can't emulate, or -EFAULT if the associated
843 * memory access caused an access fault. Return zero on success.
845 * There are a couple of ways to do this, either "decode" the instruction
846 * or directly match lots of bits. In this case, matching lots of
847 * bits is faster and easier.
850 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
852 u8 rT = (instword >> 21) & 0x1f;
853 u8 rA = (instword >> 16) & 0x1f;
854 u8 NB_RB = (instword >> 11) & 0x1f;
859 /* Early out if we are an invalid form of lswx */
860 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
861 if ((rT == rA) || (rT == NB_RB))
864 EA = (rA == 0) ? 0 : regs->gpr[rA];
866 switch (instword & PPC_INST_STRING_MASK) {
870 num_bytes = regs->xer & 0x7f;
874 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
880 while (num_bytes != 0)
883 u32 shift = 8 * (3 - (pos & 0x3));
885 /* if process is 32-bit, clear upper 32 bits of EA */
886 if ((regs->msr & MSR_64BIT) == 0)
889 switch ((instword & PPC_INST_STRING_MASK)) {
892 if (get_user(val, (u8 __user *)EA))
894 /* first time updating this reg,
898 regs->gpr[rT] |= val << shift;
902 val = regs->gpr[rT] >> shift;
903 if (put_user(val, (u8 __user *)EA))
907 /* move EA to next address */
911 /* manage our position within the register */
922 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
927 ra = (instword >> 16) & 0x1f;
928 rs = (instword >> 21) & 0x1f;
931 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
932 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
933 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
939 static int emulate_isel(struct pt_regs *regs, u32 instword)
941 u8 rT = (instword >> 21) & 0x1f;
942 u8 rA = (instword >> 16) & 0x1f;
943 u8 rB = (instword >> 11) & 0x1f;
944 u8 BC = (instword >> 6) & 0x1f;
948 tmp = (rA == 0) ? 0 : regs->gpr[rA];
949 bit = (regs->ccr >> (31 - BC)) & 0x1;
951 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
956 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
957 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
959 /* If we're emulating a load/store in an active transaction, we cannot
960 * emulate it as the kernel operates in transaction suspended context.
961 * We need to abort the transaction. This creates a persistent TM
962 * abort so tell the user what caused it with a new code.
964 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
972 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
978 static int emulate_instruction(struct pt_regs *regs)
983 if (!user_mode(regs))
985 CHECK_FULL_REGS(regs);
987 if (get_user(instword, (u32 __user *)(regs->nip)))
990 /* Emulate the mfspr rD, PVR. */
991 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
992 PPC_WARN_EMULATED(mfpvr, regs);
993 rd = (instword >> 21) & 0x1f;
994 regs->gpr[rd] = mfspr(SPRN_PVR);
998 /* Emulating the dcba insn is just a no-op. */
999 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1000 PPC_WARN_EMULATED(dcba, regs);
1004 /* Emulate the mcrxr insn. */
1005 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1006 int shift = (instword >> 21) & 0x1c;
1007 unsigned long msk = 0xf0000000UL >> shift;
1009 PPC_WARN_EMULATED(mcrxr, regs);
1010 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1011 regs->xer &= ~0xf0000000UL;
1015 /* Emulate load/store string insn. */
1016 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1017 if (tm_abort_check(regs,
1018 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1020 PPC_WARN_EMULATED(string, regs);
1021 return emulate_string_inst(regs, instword);
1024 /* Emulate the popcntb (Population Count Bytes) instruction. */
1025 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1026 PPC_WARN_EMULATED(popcntb, regs);
1027 return emulate_popcntb_inst(regs, instword);
1030 /* Emulate isel (Integer Select) instruction */
1031 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1032 PPC_WARN_EMULATED(isel, regs);
1033 return emulate_isel(regs, instword);
1036 /* Emulate sync instruction variants */
1037 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1038 PPC_WARN_EMULATED(sync, regs);
1039 asm volatile("sync");
1044 /* Emulate the mfspr rD, DSCR. */
1045 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1046 PPC_INST_MFSPR_DSCR_USER) ||
1047 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1048 PPC_INST_MFSPR_DSCR)) &&
1049 cpu_has_feature(CPU_FTR_DSCR)) {
1050 PPC_WARN_EMULATED(mfdscr, regs);
1051 rd = (instword >> 21) & 0x1f;
1052 regs->gpr[rd] = mfspr(SPRN_DSCR);
1055 /* Emulate the mtspr DSCR, rD. */
1056 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1057 PPC_INST_MTSPR_DSCR_USER) ||
1058 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1059 PPC_INST_MTSPR_DSCR)) &&
1060 cpu_has_feature(CPU_FTR_DSCR)) {
1061 PPC_WARN_EMULATED(mtdscr, regs);
1062 rd = (instword >> 21) & 0x1f;
1063 current->thread.dscr = regs->gpr[rd];
1064 current->thread.dscr_inherit = 1;
1065 mtspr(SPRN_DSCR, current->thread.dscr);
1073 int is_valid_bugaddr(unsigned long addr)
1075 return is_kernel_addr(addr);
1078 #ifdef CONFIG_MATH_EMULATION
1079 static int emulate_math(struct pt_regs *regs)
1082 extern int do_mathemu(struct pt_regs *regs);
1084 ret = do_mathemu(regs);
1086 PPC_WARN_EMULATED(math, regs);
1090 emulate_single_step(regs);
1094 code = __parse_fpscr(current->thread.fp_state.fpscr);
1095 _exception(SIGFPE, regs, code, regs->nip);
1099 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1106 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1109 void __kprobes program_check_exception(struct pt_regs *regs)
1111 enum ctx_state prev_state = exception_enter();
1112 unsigned int reason = get_reason(regs);
1114 /* We can now get here via a FP Unavailable exception if the core
1115 * has no FPU, in that case the reason flags will be 0 */
1117 if (reason & REASON_FP) {
1118 /* IEEE FP exception */
1122 if (reason & REASON_TRAP) {
1123 /* Debugger is first in line to stop recursive faults in
1124 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1125 if (debugger_bpt(regs))
1128 /* trap exception */
1129 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1133 if (!(regs->msr & MSR_PR) && /* not user-mode */
1134 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1138 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1141 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1142 if (reason & REASON_TM) {
1143 /* This is a TM "Bad Thing Exception" program check.
1145 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1146 * transition in TM states.
1147 * - A trechkpt is attempted when transactional.
1148 * - A treclaim is attempted when non transactional.
1149 * - A tend is illegally attempted.
1150 * - writing a TM SPR when transactional.
1152 if (!user_mode(regs) &&
1153 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1157 /* If usermode caused this, it's done something illegal and
1158 * gets a SIGILL slap on the wrist. We call it an illegal
1159 * operand to distinguish from the instruction just being bad
1160 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1161 * illegal /placement/ of a valid instruction.
1163 if (user_mode(regs)) {
1164 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1167 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1168 "at %lx (msr 0x%x)\n", regs->nip, reason);
1169 die("Unrecoverable exception", regs, SIGABRT);
1175 * If we took the program check in the kernel skip down to sending a
1176 * SIGILL. The subsequent cases all relate to emulating instructions
1177 * which we should only do for userspace. We also do not want to enable
1178 * interrupts for kernel faults because that might lead to further
1179 * faults, and loose the context of the original exception.
1181 if (!user_mode(regs))
1184 /* We restore the interrupt state now */
1185 if (!arch_irq_disabled_regs(regs))
1188 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1189 * but there seems to be a hardware bug on the 405GP (RevD)
1190 * that means ESR is sometimes set incorrectly - either to
1191 * ESR_DST (!?) or 0. In the process of chasing this with the
1192 * hardware people - not sure if it can happen on any illegal
1193 * instruction or only on FP instructions, whether there is a
1194 * pattern to occurrences etc. -dgibson 31/Mar/2003
1196 if (!emulate_math(regs))
1199 /* Try to emulate it if we should. */
1200 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1201 switch (emulate_instruction(regs)) {
1204 emulate_single_step(regs);
1207 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1213 if (reason & REASON_PRIVILEGED)
1214 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1216 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1219 exception_exit(prev_state);
1223 * This occurs when running in hypervisor mode on POWER6 or later
1224 * and an illegal instruction is encountered.
1226 void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1228 regs->msr |= REASON_ILLEGAL;
1229 program_check_exception(regs);
1232 void alignment_exception(struct pt_regs *regs)
1234 enum ctx_state prev_state = exception_enter();
1235 int sig, code, fixed = 0;
1237 /* We restore the interrupt state now */
1238 if (!arch_irq_disabled_regs(regs))
1241 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1244 /* we don't implement logging of alignment exceptions */
1245 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1246 fixed = fix_alignment(regs);
1249 regs->nip += 4; /* skip over emulated instruction */
1250 emulate_single_step(regs);
1254 /* Operand address was bad */
1255 if (fixed == -EFAULT) {
1262 if (user_mode(regs))
1263 _exception(sig, regs, code, regs->dar);
1265 bad_page_fault(regs, regs->dar, sig);
1268 exception_exit(prev_state);
1271 void StackOverflow(struct pt_regs *regs)
1273 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1274 current, regs->gpr[1]);
1277 panic("kernel stack overflow");
1280 void nonrecoverable_exception(struct pt_regs *regs)
1282 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1283 regs->nip, regs->msr);
1285 die("nonrecoverable exception", regs, SIGKILL);
1288 void trace_syscall(struct pt_regs *regs)
1290 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1291 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1292 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1295 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1297 enum ctx_state prev_state = exception_enter();
1299 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1300 "%lx at %lx\n", regs->trap, regs->nip);
1301 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1303 exception_exit(prev_state);
1306 void altivec_unavailable_exception(struct pt_regs *regs)
1308 enum ctx_state prev_state = exception_enter();
1310 if (user_mode(regs)) {
1311 /* A user program has executed an altivec instruction,
1312 but this kernel doesn't support altivec. */
1313 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1317 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1318 "%lx at %lx\n", regs->trap, regs->nip);
1319 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1322 exception_exit(prev_state);
1325 void vsx_unavailable_exception(struct pt_regs *regs)
1327 if (user_mode(regs)) {
1328 /* A user program has executed an vsx instruction,
1329 but this kernel doesn't support vsx. */
1330 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1334 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1335 "%lx at %lx\n", regs->trap, regs->nip);
1336 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1340 void facility_unavailable_exception(struct pt_regs *regs)
1342 static char *facility_strings[] = {
1343 [FSCR_FP_LG] = "FPU",
1344 [FSCR_VECVSX_LG] = "VMX/VSX",
1345 [FSCR_DSCR_LG] = "DSCR",
1346 [FSCR_PM_LG] = "PMU SPRs",
1347 [FSCR_BHRB_LG] = "BHRB",
1348 [FSCR_TM_LG] = "TM",
1349 [FSCR_EBB_LG] = "EBB",
1350 [FSCR_TAR_LG] = "TAR",
1352 char *facility = "unknown";
1357 hv = (regs->trap == 0xf80);
1359 value = mfspr(SPRN_HFSCR);
1361 value = mfspr(SPRN_FSCR);
1363 status = value >> 56;
1364 if (status == FSCR_DSCR_LG) {
1365 /* User is acessing the DSCR. Set the inherit bit and allow
1366 * the user to set it directly in future by setting via the
1367 * FSCR DSCR bit. We always leave HFSCR DSCR set.
1369 current->thread.dscr_inherit = 1;
1370 mtspr(SPRN_FSCR, value | FSCR_DSCR);
1374 if ((status < ARRAY_SIZE(facility_strings)) &&
1375 facility_strings[status])
1376 facility = facility_strings[status];
1378 /* We restore the interrupt state now */
1379 if (!arch_irq_disabled_regs(regs))
1382 pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1383 hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
1385 if (user_mode(regs)) {
1386 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1390 die("Unexpected facility unavailable exception", regs, SIGABRT);
1394 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1396 void fp_unavailable_tm(struct pt_regs *regs)
1398 /* Note: This does not handle any kind of FP laziness. */
1400 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1401 regs->nip, regs->msr);
1403 /* We can only have got here if the task started using FP after
1404 * beginning the transaction. So, the transactional regs are just a
1405 * copy of the checkpointed ones. But, we still need to recheckpoint
1406 * as we're enabling FP for the process; it will return, abort the
1407 * transaction, and probably retry but now with FP enabled. So the
1408 * checkpointed FP registers need to be loaded.
1410 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1411 /* Reclaim didn't save out any FPRs to transact_fprs. */
1413 /* Enable FP for the task: */
1414 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1416 /* This loads and recheckpoints the FP registers from
1417 * thread.fpr[]. They will remain in registers after the
1418 * checkpoint so we don't need to reload them after.
1420 tm_recheckpoint(¤t->thread, regs->msr);
1423 #ifdef CONFIG_ALTIVEC
1424 void altivec_unavailable_tm(struct pt_regs *regs)
1426 /* See the comments in fp_unavailable_tm(). This function operates
1430 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1432 regs->nip, regs->msr);
1433 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1434 regs->msr |= MSR_VEC;
1435 tm_recheckpoint(¤t->thread, regs->msr);
1436 current->thread.used_vr = 1;
1441 void vsx_unavailable_tm(struct pt_regs *regs)
1443 /* See the comments in fp_unavailable_tm(). This works similarly,
1444 * though we're loading both FP and VEC registers in here.
1446 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1447 * regs. Either way, set MSR_VSX.
1450 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1452 regs->nip, regs->msr);
1454 /* This reclaims FP and/or VR regs if they're already enabled */
1455 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1457 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1459 /* This loads & recheckpoints FP and VRs. */
1460 tm_recheckpoint(¤t->thread, regs->msr);
1461 current->thread.used_vsr = 1;
1464 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1466 void performance_monitor_exception(struct pt_regs *regs)
1468 __get_cpu_var(irq_stat).pmu_irqs++;
1474 void SoftwareEmulation(struct pt_regs *regs)
1476 CHECK_FULL_REGS(regs);
1478 if (!user_mode(regs)) {
1480 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1484 if (!emulate_math(regs))
1487 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1489 #endif /* CONFIG_8xx */
1491 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1492 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1496 * Determine the cause of the debug event, clear the
1497 * event flags and send a trap to the handler. Torez
1499 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1500 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1501 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1502 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1504 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1507 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1508 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1509 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1512 } else if (debug_status & DBSR_IAC1) {
1513 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1514 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1515 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1518 } else if (debug_status & DBSR_IAC2) {
1519 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1520 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1523 } else if (debug_status & DBSR_IAC3) {
1524 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1525 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1526 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1529 } else if (debug_status & DBSR_IAC4) {
1530 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1531 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1536 * At the point this routine was called, the MSR(DE) was turned off.
1537 * Check all other debug flags and see if that bit needs to be turned
1540 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1541 current->thread.debug.dbcr1))
1542 regs->msr |= MSR_DE;
1544 /* Make sure the IDM flag is off */
1545 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1548 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1551 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1553 current->thread.debug.dbsr = debug_status;
1555 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1556 * on server, it stops on the target of the branch. In order to simulate
1557 * the server behaviour, we thus restart right away with a single step
1558 * instead of stopping here when hitting a BT
1560 if (debug_status & DBSR_BT) {
1561 regs->msr &= ~MSR_DE;
1564 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1565 /* Clear the BT event */
1566 mtspr(SPRN_DBSR, DBSR_BT);
1568 /* Do the single step trick only when coming from userspace */
1569 if (user_mode(regs)) {
1570 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1571 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1572 regs->msr |= MSR_DE;
1576 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1577 5, SIGTRAP) == NOTIFY_STOP) {
1580 if (debugger_sstep(regs))
1582 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1583 regs->msr &= ~MSR_DE;
1585 /* Disable instruction completion */
1586 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1587 /* Clear the instruction completion event */
1588 mtspr(SPRN_DBSR, DBSR_IC);
1590 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1591 5, SIGTRAP) == NOTIFY_STOP) {
1595 if (debugger_sstep(regs))
1598 if (user_mode(regs)) {
1599 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1600 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1601 current->thread.debug.dbcr1))
1602 regs->msr |= MSR_DE;
1604 /* Make sure the IDM bit is off */
1605 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1608 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1610 handle_debug(regs, debug_status);
1612 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1614 #if !defined(CONFIG_TAU_INT)
1615 void TAUException(struct pt_regs *regs)
1617 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1618 regs->nip, regs->msr, regs->trap, print_tainted());
1620 #endif /* CONFIG_INT_TAU */
1622 #ifdef CONFIG_ALTIVEC
1623 void altivec_assist_exception(struct pt_regs *regs)
1627 if (!user_mode(regs)) {
1628 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1629 " at %lx\n", regs->nip);
1630 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1633 flush_altivec_to_thread(current);
1635 PPC_WARN_EMULATED(altivec, regs);
1636 err = emulate_altivec(regs);
1638 regs->nip += 4; /* skip emulated instruction */
1639 emulate_single_step(regs);
1643 if (err == -EFAULT) {
1644 /* got an error reading the instruction */
1645 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1647 /* didn't recognize the instruction */
1648 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1649 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1650 "in %s at %lx\n", current->comm, regs->nip);
1651 current->thread.vr_state.vscr.u[3] |= 0x10000;
1654 #endif /* CONFIG_ALTIVEC */
1657 void vsx_assist_exception(struct pt_regs *regs)
1659 if (!user_mode(regs)) {
1660 printk(KERN_EMERG "VSX assist exception in kernel mode"
1661 " at %lx\n", regs->nip);
1662 die("Kernel VSX assist exception", regs, SIGILL);
1665 flush_vsx_to_thread(current);
1666 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1667 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1669 #endif /* CONFIG_VSX */
1671 #ifdef CONFIG_FSL_BOOKE
1672 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1673 unsigned long error_code)
1675 /* We treat cache locking instructions from the user
1676 * as priv ops, in the future we could try to do
1679 if (error_code & (ESR_DLK|ESR_ILK))
1680 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1683 #endif /* CONFIG_FSL_BOOKE */
1686 void SPEFloatingPointException(struct pt_regs *regs)
1688 extern int do_spe_mathemu(struct pt_regs *regs);
1689 unsigned long spefscr;
1694 flush_spe_to_thread(current);
1696 spefscr = current->thread.spefscr;
1697 fpexc_mode = current->thread.fpexc_mode;
1699 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1702 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1705 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1707 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1710 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1713 err = do_spe_mathemu(regs);
1715 regs->nip += 4; /* skip emulated instruction */
1716 emulate_single_step(regs);
1720 if (err == -EFAULT) {
1721 /* got an error reading the instruction */
1722 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1723 } else if (err == -EINVAL) {
1724 /* didn't recognize the instruction */
1725 printk(KERN_ERR "unrecognized spe instruction "
1726 "in %s at %lx\n", current->comm, regs->nip);
1728 _exception(SIGFPE, regs, code, regs->nip);
1734 void SPEFloatingPointRoundException(struct pt_regs *regs)
1736 extern int speround_handler(struct pt_regs *regs);
1740 if (regs->msr & MSR_SPE)
1741 giveup_spe(current);
1745 err = speround_handler(regs);
1747 regs->nip += 4; /* skip emulated instruction */
1748 emulate_single_step(regs);
1752 if (err == -EFAULT) {
1753 /* got an error reading the instruction */
1754 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1755 } else if (err == -EINVAL) {
1756 /* didn't recognize the instruction */
1757 printk(KERN_ERR "unrecognized spe instruction "
1758 "in %s at %lx\n", current->comm, regs->nip);
1760 _exception(SIGFPE, regs, 0, regs->nip);
1767 * We enter here if we get an unrecoverable exception, that is, one
1768 * that happened at a point where the RI (recoverable interrupt) bit
1769 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1770 * we therefore lost state by taking this exception.
1772 void unrecoverable_exception(struct pt_regs *regs)
1774 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1775 regs->trap, regs->nip);
1776 die("Unrecoverable exception", regs, SIGABRT);
1779 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1781 * Default handler for a Watchdog exception,
1782 * spins until a reboot occurs
1784 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1786 /* Generic WatchdogHandler, implement your own */
1787 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1791 void WatchdogException(struct pt_regs *regs)
1793 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1794 WatchdogHandler(regs);
1799 * We enter here if we discover during exception entry that we are
1800 * running in supervisor mode with a userspace value in the stack pointer.
1802 void kernel_bad_stack(struct pt_regs *regs)
1804 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1805 regs->gpr[1], regs->nip);
1806 die("Bad kernel stack pointer", regs, SIGABRT);
1809 void __init trap_init(void)
1814 #ifdef CONFIG_PPC_EMULATED_STATS
1816 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1818 struct ppc_emulated ppc_emulated = {
1819 #ifdef CONFIG_ALTIVEC
1820 WARN_EMULATED_SETUP(altivec),
1822 WARN_EMULATED_SETUP(dcba),
1823 WARN_EMULATED_SETUP(dcbz),
1824 WARN_EMULATED_SETUP(fp_pair),
1825 WARN_EMULATED_SETUP(isel),
1826 WARN_EMULATED_SETUP(mcrxr),
1827 WARN_EMULATED_SETUP(mfpvr),
1828 WARN_EMULATED_SETUP(multiple),
1829 WARN_EMULATED_SETUP(popcntb),
1830 WARN_EMULATED_SETUP(spe),
1831 WARN_EMULATED_SETUP(string),
1832 WARN_EMULATED_SETUP(sync),
1833 WARN_EMULATED_SETUP(unaligned),
1834 #ifdef CONFIG_MATH_EMULATION
1835 WARN_EMULATED_SETUP(math),
1838 WARN_EMULATED_SETUP(vsx),
1841 WARN_EMULATED_SETUP(mfdscr),
1842 WARN_EMULATED_SETUP(mtdscr),
1846 u32 ppc_warn_emulated;
1848 void ppc_warn_emulated_print(const char *type)
1850 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1854 static int __init ppc_warn_emulated_init(void)
1856 struct dentry *dir, *d;
1858 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1860 if (!powerpc_debugfs_root)
1863 dir = debugfs_create_dir("emulated_instructions",
1864 powerpc_debugfs_root);
1868 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1869 &ppc_warn_emulated);
1873 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1874 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1875 (u32 *)&entries[i].val.counter);
1883 debugfs_remove_recursive(dir);
1887 device_initcall(ppc_warn_emulated_init);
1889 #endif /* CONFIG_PPC_EMULATED_STATS */