2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/extable.h>
30 #include <linux/module.h> /* print_modules */
31 #include <linux/prctl.h>
32 #include <linux/delay.h>
33 #include <linux/kprobes.h>
34 #include <linux/kexec.h>
35 #include <linux/backlight.h>
36 #include <linux/bug.h>
37 #include <linux/kdebug.h>
38 #include <linux/ratelimit.h>
39 #include <linux/context_tracking.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
70 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
71 int (*__debugger)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
79 EXPORT_SYMBOL(__debugger);
80 EXPORT_SYMBOL(__debugger_ipi);
81 EXPORT_SYMBOL(__debugger_bpt);
82 EXPORT_SYMBOL(__debugger_sstep);
83 EXPORT_SYMBOL(__debugger_iabr_match);
84 EXPORT_SYMBOL(__debugger_break_match);
85 EXPORT_SYMBOL(__debugger_fault_handler);
88 /* Transactional Memory trap debug */
90 #define TM_DEBUG(x...) printk(KERN_INFO x)
92 #define TM_DEBUG(x...) do { } while(0)
96 * Trap & Exception support
99 #ifdef CONFIG_PMAC_BACKLIGHT
100 static void pmac_backlight_unblank(void)
102 mutex_lock(&pmac_backlight_mutex);
103 if (pmac_backlight) {
104 struct backlight_properties *props;
106 props = &pmac_backlight->props;
107 props->brightness = props->max_brightness;
108 props->power = FB_BLANK_UNBLANK;
109 backlight_update_status(pmac_backlight);
111 mutex_unlock(&pmac_backlight_mutex);
114 static inline void pmac_backlight_unblank(void) { }
117 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
118 static int die_owner = -1;
119 static unsigned int die_nest_count;
120 static int die_counter;
122 static unsigned long oops_begin(struct pt_regs *regs)
129 /* racy, but better than risking deadlock. */
130 raw_local_irq_save(flags);
131 cpu = smp_processor_id();
132 if (!arch_spin_trylock(&die_lock)) {
133 if (cpu == die_owner)
134 /* nested oops. should stop eventually */;
136 arch_spin_lock(&die_lock);
142 if (machine_is(powermac))
143 pmac_backlight_unblank();
146 NOKPROBE_SYMBOL(oops_begin);
148 static void oops_end(unsigned long flags, struct pt_regs *regs,
152 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
156 if (!die_nest_count) {
157 /* Nest count reaches zero, release the lock. */
159 arch_spin_unlock(&die_lock);
161 raw_local_irq_restore(flags);
163 crash_fadump(regs, "die oops");
166 * A system reset (0x100) is a request to dump, so we always send
167 * it through the crashdump code.
169 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
173 * We aren't the primary crash CPU. We need to send it
174 * to a holding pattern to avoid it ending up in the panic
177 crash_kexec_secondary(regs);
184 * While our oops output is serialised by a spinlock, output
185 * from panic() called below can race and corrupt it. If we
186 * know we are going to panic, delay for 1 second so we have a
187 * chance to get clean backtraces from all CPUs that are oopsing.
189 if (in_interrupt() || panic_on_oops || !current->pid ||
190 is_global_init(current)) {
191 mdelay(MSEC_PER_SEC);
195 panic("Fatal exception in interrupt");
197 panic("Fatal exception");
200 NOKPROBE_SYMBOL(oops_end);
202 static int __die(const char *str, struct pt_regs *regs, long err)
204 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
205 #ifdef CONFIG_PREEMPT
209 printk("SMP NR_CPUS=%d ", NR_CPUS);
211 if (debug_pagealloc_enabled())
212 printk("DEBUG_PAGEALLOC ");
216 printk("%s\n", ppc_md.name ? ppc_md.name : "");
218 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
226 NOKPROBE_SYMBOL(__die);
228 void die(const char *str, struct pt_regs *regs, long err)
235 flags = oops_begin(regs);
236 if (__die(str, regs, err))
238 oops_end(flags, regs, err);
240 NOKPROBE_SYMBOL(die);
242 void user_single_step_siginfo(struct task_struct *tsk,
243 struct pt_regs *regs, siginfo_t *info)
245 memset(info, 0, sizeof(*info));
246 info->si_signo = SIGTRAP;
247 info->si_code = TRAP_TRACE;
248 info->si_addr = (void __user *)regs->nip;
251 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
254 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
255 "at %08lx nip %08lx lr %08lx code %x\n";
256 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
257 "at %016lx nip %016lx lr %016lx code %x\n";
259 if (!user_mode(regs)) {
260 die("Exception in kernel mode", regs, signr);
264 if (show_unhandled_signals && unhandled_signal(current, signr)) {
265 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
266 current->comm, current->pid, signr,
267 addr, regs->nip, regs->link, code);
270 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
273 current->thread.trap_nr = code;
274 memset(&info, 0, sizeof(info));
275 info.si_signo = signr;
277 info.si_addr = (void __user *) addr;
278 force_sig_info(signr, &info, current);
281 void system_reset_exception(struct pt_regs *regs)
284 * Avoid crashes in case of nested NMI exceptions. Recoverability
285 * is determined by RI and in_nmi
287 bool nested = in_nmi();
291 __this_cpu_inc(irq_stat.sreset_irqs);
293 /* See if any machine dependent calls */
294 if (ppc_md.system_reset_exception) {
295 if (ppc_md.system_reset_exception(regs))
299 die("System Reset", regs, SIGABRT);
302 #ifdef CONFIG_PPC_BOOK3S_64
303 BUG_ON(get_paca()->in_nmi == 0);
304 if (get_paca()->in_nmi > 1)
305 panic("Unrecoverable nested System Reset");
307 /* Must die if the interrupt is not recoverable */
308 if (!(regs->msr & MSR_RI))
309 panic("Unrecoverable System Reset");
314 /* What should we do here? We could issue a shutdown or hard reset. */
319 * This function is called in real mode. Strictly no printk's please.
321 * regs->nip and regs->msr contains srr0 and ssr1.
323 long machine_check_early(struct pt_regs *regs)
327 __this_cpu_inc(irq_stat.mce_exceptions);
329 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
330 handled = cur_cpu_spec->machine_check_early(regs);
334 long hmi_exception_realmode(struct pt_regs *regs)
336 __this_cpu_inc(irq_stat.hmi_exceptions);
338 wait_for_subcore_guest_exit();
340 if (ppc_md.hmi_exception_early)
341 ppc_md.hmi_exception_early(regs);
343 wait_for_tb_resync();
351 * I/O accesses can cause machine checks on powermacs.
352 * Check if the NIP corresponds to the address of a sync
353 * instruction for which there is an entry in the exception
355 * Note that the 601 only takes a machine check on TEA
356 * (transfer error ack) signal assertion, and does not
357 * set any of the top 16 bits of SRR1.
360 static inline int check_io_access(struct pt_regs *regs)
363 unsigned long msr = regs->msr;
364 const struct exception_table_entry *entry;
365 unsigned int *nip = (unsigned int *)regs->nip;
367 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
368 && (entry = search_exception_tables(regs->nip)) != NULL) {
370 * Check that it's a sync instruction, or somewhere
371 * in the twi; isync; nop sequence that inb/inw/inl uses.
372 * As the address is in the exception table
373 * we should be able to read the instr there.
374 * For the debug message, we look at the preceding
377 if (*nip == PPC_INST_NOP)
379 else if (*nip == PPC_INST_ISYNC)
381 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
385 rb = (*nip >> 11) & 0x1f;
386 printk(KERN_DEBUG "%s bad port %lx at %p\n",
387 (*nip & 0x100)? "OUT to": "IN from",
388 regs->gpr[rb] - _IO_BASE, nip);
390 regs->nip = extable_fixup(entry);
394 #endif /* CONFIG_PPC32 */
398 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
399 /* On 4xx, the reason for the machine check or program exception
401 #define get_reason(regs) ((regs)->dsisr)
402 #define REASON_FP ESR_FP
403 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
404 #define REASON_PRIVILEGED ESR_PPR
405 #define REASON_TRAP ESR_PTR
407 /* single-step stuff */
408 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
409 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
412 /* On non-4xx, the reason for the machine check or program
413 exception is in the MSR. */
414 #define get_reason(regs) ((regs)->msr)
415 #define REASON_TM 0x200000
416 #define REASON_FP 0x100000
417 #define REASON_ILLEGAL 0x80000
418 #define REASON_PRIVILEGED 0x40000
419 #define REASON_TRAP 0x20000
421 #define single_stepping(regs) ((regs)->msr & MSR_SE)
422 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
425 #if defined(CONFIG_E500)
426 int machine_check_e500mc(struct pt_regs *regs)
428 unsigned long mcsr = mfspr(SPRN_MCSR);
429 unsigned long reason = mcsr;
432 if (reason & MCSR_LD) {
433 recoverable = fsl_rio_mcheck_exception(regs);
434 if (recoverable == 1)
438 printk("Machine check in kernel mode.\n");
439 printk("Caused by (from MCSR=%lx): ", reason);
441 if (reason & MCSR_MCP)
442 printk("Machine Check Signal\n");
444 if (reason & MCSR_ICPERR) {
445 printk("Instruction Cache Parity Error\n");
448 * This is recoverable by invalidating the i-cache.
450 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
451 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
455 * This will generally be accompanied by an instruction
456 * fetch error report -- only treat MCSR_IF as fatal
457 * if it wasn't due to an L1 parity error.
462 if (reason & MCSR_DCPERR_MC) {
463 printk("Data Cache Parity Error\n");
466 * In write shadow mode we auto-recover from the error, but it
467 * may still get logged and cause a machine check. We should
468 * only treat the non-write shadow case as non-recoverable.
470 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
474 if (reason & MCSR_L2MMU_MHIT) {
475 printk("Hit on multiple TLB entries\n");
479 if (reason & MCSR_NMI)
480 printk("Non-maskable interrupt\n");
482 if (reason & MCSR_IF) {
483 printk("Instruction Fetch Error Report\n");
487 if (reason & MCSR_LD) {
488 printk("Load Error Report\n");
492 if (reason & MCSR_ST) {
493 printk("Store Error Report\n");
497 if (reason & MCSR_LDG) {
498 printk("Guarded Load Error Report\n");
502 if (reason & MCSR_TLBSYNC)
503 printk("Simultaneous tlbsync operations\n");
505 if (reason & MCSR_BSL2_ERR) {
506 printk("Level 2 Cache Error\n");
510 if (reason & MCSR_MAV) {
513 addr = mfspr(SPRN_MCAR);
514 addr |= (u64)mfspr(SPRN_MCARU) << 32;
516 printk("Machine Check %s Address: %#llx\n",
517 reason & MCSR_MEA ? "Effective" : "Physical", addr);
521 mtspr(SPRN_MCSR, mcsr);
522 return mfspr(SPRN_MCSR) == 0 && recoverable;
525 int machine_check_e500(struct pt_regs *regs)
527 unsigned long reason = mfspr(SPRN_MCSR);
529 if (reason & MCSR_BUS_RBERR) {
530 if (fsl_rio_mcheck_exception(regs))
532 if (fsl_pci_mcheck_exception(regs))
536 printk("Machine check in kernel mode.\n");
537 printk("Caused by (from MCSR=%lx): ", reason);
539 if (reason & MCSR_MCP)
540 printk("Machine Check Signal\n");
541 if (reason & MCSR_ICPERR)
542 printk("Instruction Cache Parity Error\n");
543 if (reason & MCSR_DCP_PERR)
544 printk("Data Cache Push Parity Error\n");
545 if (reason & MCSR_DCPERR)
546 printk("Data Cache Parity Error\n");
547 if (reason & MCSR_BUS_IAERR)
548 printk("Bus - Instruction Address Error\n");
549 if (reason & MCSR_BUS_RAERR)
550 printk("Bus - Read Address Error\n");
551 if (reason & MCSR_BUS_WAERR)
552 printk("Bus - Write Address Error\n");
553 if (reason & MCSR_BUS_IBERR)
554 printk("Bus - Instruction Data Error\n");
555 if (reason & MCSR_BUS_RBERR)
556 printk("Bus - Read Data Bus Error\n");
557 if (reason & MCSR_BUS_WBERR)
558 printk("Bus - Write Data Bus Error\n");
559 if (reason & MCSR_BUS_IPERR)
560 printk("Bus - Instruction Parity Error\n");
561 if (reason & MCSR_BUS_RPERR)
562 printk("Bus - Read Parity Error\n");
567 int machine_check_generic(struct pt_regs *regs)
571 #elif defined(CONFIG_E200)
572 int machine_check_e200(struct pt_regs *regs)
574 unsigned long reason = mfspr(SPRN_MCSR);
576 printk("Machine check in kernel mode.\n");
577 printk("Caused by (from MCSR=%lx): ", reason);
579 if (reason & MCSR_MCP)
580 printk("Machine Check Signal\n");
581 if (reason & MCSR_CP_PERR)
582 printk("Cache Push Parity Error\n");
583 if (reason & MCSR_CPERR)
584 printk("Cache Parity Error\n");
585 if (reason & MCSR_EXCP_ERR)
586 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
587 if (reason & MCSR_BUS_IRERR)
588 printk("Bus - Read Bus Error on instruction fetch\n");
589 if (reason & MCSR_BUS_DRERR)
590 printk("Bus - Read Bus Error on data load\n");
591 if (reason & MCSR_BUS_WRERR)
592 printk("Bus - Write Bus Error on buffered store or cache line push\n");
596 #elif defined(CONFIG_PPC_8xx)
597 int machine_check_8xx(struct pt_regs *regs)
599 unsigned long reason = regs->msr;
601 pr_err("Machine check in kernel mode.\n");
602 pr_err("Caused by (from SRR1=%lx): ", reason);
603 if (reason & 0x40000000)
604 pr_err("Fetch error at address %lx\n", regs->nip);
606 pr_err("Data access error at address %lx\n", regs->dar);
609 /* the qspan pci read routines can cause machine checks -- Cort
611 * yuck !!! that totally needs to go away ! There are better ways
612 * to deal with that than having a wart in the mcheck handler.
615 bad_page_fault(regs, regs->dar, SIGBUS);
622 int machine_check_generic(struct pt_regs *regs)
624 unsigned long reason = regs->msr;
626 printk("Machine check in kernel mode.\n");
627 printk("Caused by (from SRR1=%lx): ", reason);
628 switch (reason & 0x601F0000) {
630 printk("Machine check signal\n");
632 case 0: /* for 601 */
634 case 0x140000: /* 7450 MSS error and TEA */
635 printk("Transfer error ack signal\n");
638 printk("Data parity error signal\n");
641 printk("Address parity error signal\n");
644 printk("L1 Data Cache error\n");
647 printk("L1 Instruction Cache error\n");
650 printk("L2 data cache parity error\n");
653 printk("Unknown values in msr\n");
657 #endif /* everything else */
659 void machine_check_exception(struct pt_regs *regs)
661 enum ctx_state prev_state = exception_enter();
664 /* 64s accounts the mce in machine_check_early when in HVMODE */
665 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
666 __this_cpu_inc(irq_stat.mce_exceptions);
668 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
670 /* See if any machine dependent calls. In theory, we would want
671 * to call the CPU first, and call the ppc_md. one if the CPU
672 * one returns a positive number. However there is existing code
673 * that assumes the board gets a first chance, so let's keep it
674 * that way for now and fix things later. --BenH.
676 if (ppc_md.machine_check_exception)
677 recover = ppc_md.machine_check_exception(regs);
678 else if (cur_cpu_spec->machine_check)
679 recover = cur_cpu_spec->machine_check(regs);
684 if (debugger_fault_handler(regs))
687 if (check_io_access(regs))
690 die("Machine check", regs, SIGBUS);
692 /* Must die if the interrupt is not recoverable */
693 if (!(regs->msr & MSR_RI))
694 panic("Unrecoverable Machine check");
697 exception_exit(prev_state);
700 void SMIException(struct pt_regs *regs)
702 die("System Management Interrupt", regs, SIGABRT);
705 void handle_hmi_exception(struct pt_regs *regs)
707 struct pt_regs *old_regs;
709 old_regs = set_irq_regs(regs);
712 if (ppc_md.handle_hmi_exception)
713 ppc_md.handle_hmi_exception(regs);
716 set_irq_regs(old_regs);
719 void unknown_exception(struct pt_regs *regs)
721 enum ctx_state prev_state = exception_enter();
723 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
724 regs->nip, regs->msr, regs->trap);
726 _exception(SIGTRAP, regs, 0, 0);
728 exception_exit(prev_state);
731 void instruction_breakpoint_exception(struct pt_regs *regs)
733 enum ctx_state prev_state = exception_enter();
735 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
736 5, SIGTRAP) == NOTIFY_STOP)
738 if (debugger_iabr_match(regs))
740 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
743 exception_exit(prev_state);
746 void RunModeException(struct pt_regs *regs)
748 _exception(SIGTRAP, regs, 0, 0);
751 void single_step_exception(struct pt_regs *regs)
753 enum ctx_state prev_state = exception_enter();
755 clear_single_step(regs);
757 if (kprobe_post_handler(regs))
760 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
761 5, SIGTRAP) == NOTIFY_STOP)
763 if (debugger_sstep(regs))
766 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
769 exception_exit(prev_state);
771 NOKPROBE_SYMBOL(single_step_exception);
774 * After we have successfully emulated an instruction, we have to
775 * check if the instruction was being single-stepped, and if so,
776 * pretend we got a single-step exception. This was pointed out
777 * by Kumar Gala. -- paulus
779 static void emulate_single_step(struct pt_regs *regs)
781 if (single_stepping(regs))
782 single_step_exception(regs);
785 static inline int __parse_fpscr(unsigned long fpscr)
789 /* Invalid operation */
790 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
794 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
798 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
802 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
806 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
812 static void parse_fpe(struct pt_regs *regs)
816 flush_fp_to_thread(current);
818 code = __parse_fpscr(current->thread.fp_state.fpscr);
820 _exception(SIGFPE, regs, code, regs->nip);
824 * Illegal instruction emulation support. Originally written to
825 * provide the PVR to user applications using the mfspr rd, PVR.
826 * Return non-zero if we can't emulate, or -EFAULT if the associated
827 * memory access caused an access fault. Return zero on success.
829 * There are a couple of ways to do this, either "decode" the instruction
830 * or directly match lots of bits. In this case, matching lots of
831 * bits is faster and easier.
834 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
836 u8 rT = (instword >> 21) & 0x1f;
837 u8 rA = (instword >> 16) & 0x1f;
838 u8 NB_RB = (instword >> 11) & 0x1f;
843 /* Early out if we are an invalid form of lswx */
844 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
845 if ((rT == rA) || (rT == NB_RB))
848 EA = (rA == 0) ? 0 : regs->gpr[rA];
850 switch (instword & PPC_INST_STRING_MASK) {
854 num_bytes = regs->xer & 0x7f;
858 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
864 while (num_bytes != 0)
867 u32 shift = 8 * (3 - (pos & 0x3));
869 /* if process is 32-bit, clear upper 32 bits of EA */
870 if ((regs->msr & MSR_64BIT) == 0)
873 switch ((instword & PPC_INST_STRING_MASK)) {
876 if (get_user(val, (u8 __user *)EA))
878 /* first time updating this reg,
882 regs->gpr[rT] |= val << shift;
886 val = regs->gpr[rT] >> shift;
887 if (put_user(val, (u8 __user *)EA))
891 /* move EA to next address */
895 /* manage our position within the register */
906 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
911 ra = (instword >> 16) & 0x1f;
912 rs = (instword >> 21) & 0x1f;
915 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
916 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
917 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
923 static int emulate_isel(struct pt_regs *regs, u32 instword)
925 u8 rT = (instword >> 21) & 0x1f;
926 u8 rA = (instword >> 16) & 0x1f;
927 u8 rB = (instword >> 11) & 0x1f;
928 u8 BC = (instword >> 6) & 0x1f;
932 tmp = (rA == 0) ? 0 : regs->gpr[rA];
933 bit = (regs->ccr >> (31 - BC)) & 0x1;
935 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
940 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
941 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
943 /* If we're emulating a load/store in an active transaction, we cannot
944 * emulate it as the kernel operates in transaction suspended context.
945 * We need to abort the transaction. This creates a persistent TM
946 * abort so tell the user what caused it with a new code.
948 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
956 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
962 static int emulate_instruction(struct pt_regs *regs)
967 if (!user_mode(regs))
969 CHECK_FULL_REGS(regs);
971 if (get_user(instword, (u32 __user *)(regs->nip)))
974 /* Emulate the mfspr rD, PVR. */
975 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
976 PPC_WARN_EMULATED(mfpvr, regs);
977 rd = (instword >> 21) & 0x1f;
978 regs->gpr[rd] = mfspr(SPRN_PVR);
982 /* Emulating the dcba insn is just a no-op. */
983 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
984 PPC_WARN_EMULATED(dcba, regs);
988 /* Emulate the mcrxr insn. */
989 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
990 int shift = (instword >> 21) & 0x1c;
991 unsigned long msk = 0xf0000000UL >> shift;
993 PPC_WARN_EMULATED(mcrxr, regs);
994 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
995 regs->xer &= ~0xf0000000UL;
999 /* Emulate load/store string insn. */
1000 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1001 if (tm_abort_check(regs,
1002 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1004 PPC_WARN_EMULATED(string, regs);
1005 return emulate_string_inst(regs, instword);
1008 /* Emulate the popcntb (Population Count Bytes) instruction. */
1009 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1010 PPC_WARN_EMULATED(popcntb, regs);
1011 return emulate_popcntb_inst(regs, instword);
1014 /* Emulate isel (Integer Select) instruction */
1015 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1016 PPC_WARN_EMULATED(isel, regs);
1017 return emulate_isel(regs, instword);
1020 /* Emulate sync instruction variants */
1021 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1022 PPC_WARN_EMULATED(sync, regs);
1023 asm volatile("sync");
1028 /* Emulate the mfspr rD, DSCR. */
1029 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1030 PPC_INST_MFSPR_DSCR_USER) ||
1031 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1032 PPC_INST_MFSPR_DSCR)) &&
1033 cpu_has_feature(CPU_FTR_DSCR)) {
1034 PPC_WARN_EMULATED(mfdscr, regs);
1035 rd = (instword >> 21) & 0x1f;
1036 regs->gpr[rd] = mfspr(SPRN_DSCR);
1039 /* Emulate the mtspr DSCR, rD. */
1040 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1041 PPC_INST_MTSPR_DSCR_USER) ||
1042 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1043 PPC_INST_MTSPR_DSCR)) &&
1044 cpu_has_feature(CPU_FTR_DSCR)) {
1045 PPC_WARN_EMULATED(mtdscr, regs);
1046 rd = (instword >> 21) & 0x1f;
1047 current->thread.dscr = regs->gpr[rd];
1048 current->thread.dscr_inherit = 1;
1049 mtspr(SPRN_DSCR, current->thread.dscr);
1057 int is_valid_bugaddr(unsigned long addr)
1059 return is_kernel_addr(addr);
1062 #ifdef CONFIG_MATH_EMULATION
1063 static int emulate_math(struct pt_regs *regs)
1066 extern int do_mathemu(struct pt_regs *regs);
1068 ret = do_mathemu(regs);
1070 PPC_WARN_EMULATED(math, regs);
1074 emulate_single_step(regs);
1078 code = __parse_fpscr(current->thread.fp_state.fpscr);
1079 _exception(SIGFPE, regs, code, regs->nip);
1083 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1090 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1093 void program_check_exception(struct pt_regs *regs)
1095 enum ctx_state prev_state = exception_enter();
1096 unsigned int reason = get_reason(regs);
1098 /* We can now get here via a FP Unavailable exception if the core
1099 * has no FPU, in that case the reason flags will be 0 */
1101 if (reason & REASON_FP) {
1102 /* IEEE FP exception */
1106 if (reason & REASON_TRAP) {
1107 unsigned long bugaddr;
1108 /* Debugger is first in line to stop recursive faults in
1109 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1110 if (debugger_bpt(regs))
1113 if (kprobe_handler(regs))
1116 /* trap exception */
1117 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1121 bugaddr = regs->nip;
1123 * Fixup bugaddr for BUG_ON() in real mode
1125 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1126 bugaddr += PAGE_OFFSET;
1128 if (!(regs->msr & MSR_PR) && /* not user-mode */
1129 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1133 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1136 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1137 if (reason & REASON_TM) {
1138 /* This is a TM "Bad Thing Exception" program check.
1140 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1141 * transition in TM states.
1142 * - A trechkpt is attempted when transactional.
1143 * - A treclaim is attempted when non transactional.
1144 * - A tend is illegally attempted.
1145 * - writing a TM SPR when transactional.
1147 if (!user_mode(regs) &&
1148 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1152 /* If usermode caused this, it's done something illegal and
1153 * gets a SIGILL slap on the wrist. We call it an illegal
1154 * operand to distinguish from the instruction just being bad
1155 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1156 * illegal /placement/ of a valid instruction.
1158 if (user_mode(regs)) {
1159 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1162 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1163 "at %lx (msr 0x%x)\n", regs->nip, reason);
1164 die("Unrecoverable exception", regs, SIGABRT);
1170 * If we took the program check in the kernel skip down to sending a
1171 * SIGILL. The subsequent cases all relate to emulating instructions
1172 * which we should only do for userspace. We also do not want to enable
1173 * interrupts for kernel faults because that might lead to further
1174 * faults, and loose the context of the original exception.
1176 if (!user_mode(regs))
1179 /* We restore the interrupt state now */
1180 if (!arch_irq_disabled_regs(regs))
1183 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1184 * but there seems to be a hardware bug on the 405GP (RevD)
1185 * that means ESR is sometimes set incorrectly - either to
1186 * ESR_DST (!?) or 0. In the process of chasing this with the
1187 * hardware people - not sure if it can happen on any illegal
1188 * instruction or only on FP instructions, whether there is a
1189 * pattern to occurrences etc. -dgibson 31/Mar/2003
1191 if (!emulate_math(regs))
1194 /* Try to emulate it if we should. */
1195 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1196 switch (emulate_instruction(regs)) {
1199 emulate_single_step(regs);
1202 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1208 if (reason & REASON_PRIVILEGED)
1209 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1211 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1214 exception_exit(prev_state);
1216 NOKPROBE_SYMBOL(program_check_exception);
1219 * This occurs when running in hypervisor mode on POWER6 or later
1220 * and an illegal instruction is encountered.
1222 void emulation_assist_interrupt(struct pt_regs *regs)
1224 regs->msr |= REASON_ILLEGAL;
1225 program_check_exception(regs);
1227 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1229 void alignment_exception(struct pt_regs *regs)
1231 enum ctx_state prev_state = exception_enter();
1232 int sig, code, fixed = 0;
1234 /* We restore the interrupt state now */
1235 if (!arch_irq_disabled_regs(regs))
1238 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1241 /* we don't implement logging of alignment exceptions */
1242 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1243 fixed = fix_alignment(regs);
1246 regs->nip += 4; /* skip over emulated instruction */
1247 emulate_single_step(regs);
1251 /* Operand address was bad */
1252 if (fixed == -EFAULT) {
1259 if (user_mode(regs))
1260 _exception(sig, regs, code, regs->dar);
1262 bad_page_fault(regs, regs->dar, sig);
1265 exception_exit(prev_state);
1268 void slb_miss_bad_addr(struct pt_regs *regs)
1270 enum ctx_state prev_state = exception_enter();
1272 if (user_mode(regs))
1273 _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar);
1275 bad_page_fault(regs, regs->dar, SIGSEGV);
1277 exception_exit(prev_state);
1280 void StackOverflow(struct pt_regs *regs)
1282 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1283 current, regs->gpr[1]);
1286 panic("kernel stack overflow");
1289 void nonrecoverable_exception(struct pt_regs *regs)
1291 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1292 regs->nip, regs->msr);
1294 die("nonrecoverable exception", regs, SIGKILL);
1297 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1299 enum ctx_state prev_state = exception_enter();
1301 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1302 "%lx at %lx\n", regs->trap, regs->nip);
1303 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1305 exception_exit(prev_state);
1308 void altivec_unavailable_exception(struct pt_regs *regs)
1310 enum ctx_state prev_state = exception_enter();
1312 if (user_mode(regs)) {
1313 /* A user program has executed an altivec instruction,
1314 but this kernel doesn't support altivec. */
1315 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1319 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1320 "%lx at %lx\n", regs->trap, regs->nip);
1321 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1324 exception_exit(prev_state);
1327 void vsx_unavailable_exception(struct pt_regs *regs)
1329 if (user_mode(regs)) {
1330 /* A user program has executed an vsx instruction,
1331 but this kernel doesn't support vsx. */
1332 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1336 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1337 "%lx at %lx\n", regs->trap, regs->nip);
1338 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1342 static void tm_unavailable(struct pt_regs *regs)
1344 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1345 if (user_mode(regs)) {
1346 current->thread.load_tm++;
1347 regs->msr |= MSR_TM;
1349 tm_restore_sprs(¤t->thread);
1353 pr_emerg("Unrecoverable TM Unavailable Exception "
1354 "%lx at %lx\n", regs->trap, regs->nip);
1355 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1358 void facility_unavailable_exception(struct pt_regs *regs)
1360 static char *facility_strings[] = {
1361 [FSCR_FP_LG] = "FPU",
1362 [FSCR_VECVSX_LG] = "VMX/VSX",
1363 [FSCR_DSCR_LG] = "DSCR",
1364 [FSCR_PM_LG] = "PMU SPRs",
1365 [FSCR_BHRB_LG] = "BHRB",
1366 [FSCR_TM_LG] = "TM",
1367 [FSCR_EBB_LG] = "EBB",
1368 [FSCR_TAR_LG] = "TAR",
1369 [FSCR_MSGP_LG] = "MSGP",
1370 [FSCR_SCV_LG] = "SCV",
1372 char *facility = "unknown";
1378 hv = (regs->trap == 0xf80);
1380 value = mfspr(SPRN_HFSCR);
1382 value = mfspr(SPRN_FSCR);
1384 status = value >> 56;
1385 if (status == FSCR_DSCR_LG) {
1387 * User is accessing the DSCR register using the problem
1388 * state only SPR number (0x03) either through a mfspr or
1389 * a mtspr instruction. If it is a write attempt through
1390 * a mtspr, then we set the inherit bit. This also allows
1391 * the user to write or read the register directly in the
1392 * future by setting via the FSCR DSCR bit. But in case it
1393 * is a read DSCR attempt through a mfspr instruction, we
1394 * just emulate the instruction instead. This code path will
1395 * always emulate all the mfspr instructions till the user
1396 * has attempted at least one mtspr instruction. This way it
1397 * preserves the same behaviour when the user is accessing
1398 * the DSCR through privilege level only SPR number (0x11)
1399 * which is emulated through illegal instruction exception.
1400 * We always leave HFSCR DSCR set.
1402 if (get_user(instword, (u32 __user *)(regs->nip))) {
1403 pr_err("Failed to fetch the user instruction\n");
1407 /* Write into DSCR (mtspr 0x03, RS) */
1408 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1409 == PPC_INST_MTSPR_DSCR_USER) {
1410 rd = (instword >> 21) & 0x1f;
1411 current->thread.dscr = regs->gpr[rd];
1412 current->thread.dscr_inherit = 1;
1413 current->thread.fscr |= FSCR_DSCR;
1414 mtspr(SPRN_FSCR, current->thread.fscr);
1417 /* Read from DSCR (mfspr RT, 0x03) */
1418 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1419 == PPC_INST_MFSPR_DSCR_USER) {
1420 if (emulate_instruction(regs)) {
1421 pr_err("DSCR based mfspr emulation failed\n");
1425 emulate_single_step(regs);
1430 if (status == FSCR_TM_LG) {
1432 * If we're here then the hardware is TM aware because it
1433 * generated an exception with FSRM_TM set.
1435 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1436 * told us not to do TM, or the kernel is not built with TM
1439 * If both of those things are true, then userspace can spam the
1440 * console by triggering the printk() below just by continually
1441 * doing tbegin (or any TM instruction). So in that case just
1442 * send the process a SIGILL immediately.
1444 if (!cpu_has_feature(CPU_FTR_TM))
1447 tm_unavailable(regs);
1451 if ((hv || status >= 2) &&
1452 (status < ARRAY_SIZE(facility_strings)) &&
1453 facility_strings[status])
1454 facility = facility_strings[status];
1456 /* We restore the interrupt state now */
1457 if (!arch_irq_disabled_regs(regs))
1460 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1461 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1464 if (user_mode(regs)) {
1465 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1469 die("Unexpected facility unavailable exception", regs, SIGABRT);
1473 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1475 void fp_unavailable_tm(struct pt_regs *regs)
1477 /* Note: This does not handle any kind of FP laziness. */
1479 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1480 regs->nip, regs->msr);
1482 /* We can only have got here if the task started using FP after
1483 * beginning the transaction. So, the transactional regs are just a
1484 * copy of the checkpointed ones. But, we still need to recheckpoint
1485 * as we're enabling FP for the process; it will return, abort the
1486 * transaction, and probably retry but now with FP enabled. So the
1487 * checkpointed FP registers need to be loaded.
1489 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1490 /* Reclaim didn't save out any FPRs to transact_fprs. */
1492 /* Enable FP for the task: */
1493 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1495 /* This loads and recheckpoints the FP registers from
1496 * thread.fpr[]. They will remain in registers after the
1497 * checkpoint so we don't need to reload them after.
1498 * If VMX is in use, the VRs now hold checkpointed values,
1499 * so we don't want to load the VRs from the thread_struct.
1501 tm_recheckpoint(¤t->thread, MSR_FP);
1503 /* If VMX is in use, get the transactional values back */
1504 if (regs->msr & MSR_VEC) {
1505 msr_check_and_set(MSR_VEC);
1506 load_vr_state(¤t->thread.vr_state);
1507 /* At this point all the VSX state is loaded, so enable it */
1508 regs->msr |= MSR_VSX;
1512 void altivec_unavailable_tm(struct pt_regs *regs)
1514 /* See the comments in fp_unavailable_tm(). This function operates
1518 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1520 regs->nip, regs->msr);
1521 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1522 regs->msr |= MSR_VEC;
1523 tm_recheckpoint(¤t->thread, MSR_VEC);
1524 current->thread.used_vr = 1;
1526 if (regs->msr & MSR_FP) {
1527 msr_check_and_set(MSR_FP);
1528 load_fp_state(¤t->thread.fp_state);
1529 regs->msr |= MSR_VSX;
1533 void vsx_unavailable_tm(struct pt_regs *regs)
1535 unsigned long orig_msr = regs->msr;
1537 /* See the comments in fp_unavailable_tm(). This works similarly,
1538 * though we're loading both FP and VEC registers in here.
1540 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1541 * regs. Either way, set MSR_VSX.
1544 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1546 regs->nip, regs->msr);
1548 current->thread.used_vsr = 1;
1550 /* If FP and VMX are already loaded, we have all the state we need */
1551 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
1552 regs->msr |= MSR_VSX;
1556 /* This reclaims FP and/or VR regs if they're already enabled */
1557 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1559 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1562 /* This loads & recheckpoints FP and VRs; but we have
1563 * to be sure not to overwrite previously-valid state.
1565 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr);
1567 msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC));
1569 if (orig_msr & MSR_FP)
1570 load_fp_state(¤t->thread.fp_state);
1571 if (orig_msr & MSR_VEC)
1572 load_vr_state(¤t->thread.vr_state);
1574 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1576 void performance_monitor_exception(struct pt_regs *regs)
1578 __this_cpu_inc(irq_stat.pmu_irqs);
1584 void SoftwareEmulation(struct pt_regs *regs)
1586 CHECK_FULL_REGS(regs);
1588 if (!user_mode(regs)) {
1590 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1594 if (!emulate_math(regs))
1597 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1599 #endif /* CONFIG_8xx */
1601 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1602 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1606 * Determine the cause of the debug event, clear the
1607 * event flags and send a trap to the handler. Torez
1609 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1610 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1611 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1612 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1614 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1617 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1618 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1619 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1622 } else if (debug_status & DBSR_IAC1) {
1623 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1624 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1625 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1628 } else if (debug_status & DBSR_IAC2) {
1629 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1630 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1633 } else if (debug_status & DBSR_IAC3) {
1634 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1635 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1636 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1639 } else if (debug_status & DBSR_IAC4) {
1640 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1641 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1646 * At the point this routine was called, the MSR(DE) was turned off.
1647 * Check all other debug flags and see if that bit needs to be turned
1650 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1651 current->thread.debug.dbcr1))
1652 regs->msr |= MSR_DE;
1654 /* Make sure the IDM flag is off */
1655 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1658 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1661 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1663 current->thread.debug.dbsr = debug_status;
1665 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1666 * on server, it stops on the target of the branch. In order to simulate
1667 * the server behaviour, we thus restart right away with a single step
1668 * instead of stopping here when hitting a BT
1670 if (debug_status & DBSR_BT) {
1671 regs->msr &= ~MSR_DE;
1674 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1675 /* Clear the BT event */
1676 mtspr(SPRN_DBSR, DBSR_BT);
1678 /* Do the single step trick only when coming from userspace */
1679 if (user_mode(regs)) {
1680 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1681 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1682 regs->msr |= MSR_DE;
1686 if (kprobe_post_handler(regs))
1689 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1690 5, SIGTRAP) == NOTIFY_STOP) {
1693 if (debugger_sstep(regs))
1695 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1696 regs->msr &= ~MSR_DE;
1698 /* Disable instruction completion */
1699 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1700 /* Clear the instruction completion event */
1701 mtspr(SPRN_DBSR, DBSR_IC);
1703 if (kprobe_post_handler(regs))
1706 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1707 5, SIGTRAP) == NOTIFY_STOP) {
1711 if (debugger_sstep(regs))
1714 if (user_mode(regs)) {
1715 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1716 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1717 current->thread.debug.dbcr1))
1718 regs->msr |= MSR_DE;
1720 /* Make sure the IDM bit is off */
1721 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1724 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1726 handle_debug(regs, debug_status);
1728 NOKPROBE_SYMBOL(DebugException);
1729 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1731 #if !defined(CONFIG_TAU_INT)
1732 void TAUException(struct pt_regs *regs)
1734 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1735 regs->nip, regs->msr, regs->trap, print_tainted());
1737 #endif /* CONFIG_INT_TAU */
1739 #ifdef CONFIG_ALTIVEC
1740 void altivec_assist_exception(struct pt_regs *regs)
1744 if (!user_mode(regs)) {
1745 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1746 " at %lx\n", regs->nip);
1747 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1750 flush_altivec_to_thread(current);
1752 PPC_WARN_EMULATED(altivec, regs);
1753 err = emulate_altivec(regs);
1755 regs->nip += 4; /* skip emulated instruction */
1756 emulate_single_step(regs);
1760 if (err == -EFAULT) {
1761 /* got an error reading the instruction */
1762 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1764 /* didn't recognize the instruction */
1765 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1766 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1767 "in %s at %lx\n", current->comm, regs->nip);
1768 current->thread.vr_state.vscr.u[3] |= 0x10000;
1771 #endif /* CONFIG_ALTIVEC */
1773 #ifdef CONFIG_FSL_BOOKE
1774 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1775 unsigned long error_code)
1777 /* We treat cache locking instructions from the user
1778 * as priv ops, in the future we could try to do
1781 if (error_code & (ESR_DLK|ESR_ILK))
1782 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1785 #endif /* CONFIG_FSL_BOOKE */
1788 void SPEFloatingPointException(struct pt_regs *regs)
1790 extern int do_spe_mathemu(struct pt_regs *regs);
1791 unsigned long spefscr;
1796 flush_spe_to_thread(current);
1798 spefscr = current->thread.spefscr;
1799 fpexc_mode = current->thread.fpexc_mode;
1801 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1804 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1807 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1809 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1812 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1815 err = do_spe_mathemu(regs);
1817 regs->nip += 4; /* skip emulated instruction */
1818 emulate_single_step(regs);
1822 if (err == -EFAULT) {
1823 /* got an error reading the instruction */
1824 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1825 } else if (err == -EINVAL) {
1826 /* didn't recognize the instruction */
1827 printk(KERN_ERR "unrecognized spe instruction "
1828 "in %s at %lx\n", current->comm, regs->nip);
1830 _exception(SIGFPE, regs, code, regs->nip);
1836 void SPEFloatingPointRoundException(struct pt_regs *regs)
1838 extern int speround_handler(struct pt_regs *regs);
1842 if (regs->msr & MSR_SPE)
1843 giveup_spe(current);
1847 err = speround_handler(regs);
1849 regs->nip += 4; /* skip emulated instruction */
1850 emulate_single_step(regs);
1854 if (err == -EFAULT) {
1855 /* got an error reading the instruction */
1856 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1857 } else if (err == -EINVAL) {
1858 /* didn't recognize the instruction */
1859 printk(KERN_ERR "unrecognized spe instruction "
1860 "in %s at %lx\n", current->comm, regs->nip);
1862 _exception(SIGFPE, regs, 0, regs->nip);
1869 * We enter here if we get an unrecoverable exception, that is, one
1870 * that happened at a point where the RI (recoverable interrupt) bit
1871 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1872 * we therefore lost state by taking this exception.
1874 void unrecoverable_exception(struct pt_regs *regs)
1876 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1877 regs->trap, regs->nip);
1878 die("Unrecoverable exception", regs, SIGABRT);
1880 NOKPROBE_SYMBOL(unrecoverable_exception);
1882 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1884 * Default handler for a Watchdog exception,
1885 * spins until a reboot occurs
1887 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1889 /* Generic WatchdogHandler, implement your own */
1890 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1894 void WatchdogException(struct pt_regs *regs)
1896 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1897 WatchdogHandler(regs);
1902 * We enter here if we discover during exception entry that we are
1903 * running in supervisor mode with a userspace value in the stack pointer.
1905 void kernel_bad_stack(struct pt_regs *regs)
1907 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1908 regs->gpr[1], regs->nip);
1909 die("Bad kernel stack pointer", regs, SIGABRT);
1911 NOKPROBE_SYMBOL(kernel_bad_stack);
1913 void __init trap_init(void)
1918 #ifdef CONFIG_PPC_EMULATED_STATS
1920 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1922 struct ppc_emulated ppc_emulated = {
1923 #ifdef CONFIG_ALTIVEC
1924 WARN_EMULATED_SETUP(altivec),
1926 WARN_EMULATED_SETUP(dcba),
1927 WARN_EMULATED_SETUP(dcbz),
1928 WARN_EMULATED_SETUP(fp_pair),
1929 WARN_EMULATED_SETUP(isel),
1930 WARN_EMULATED_SETUP(mcrxr),
1931 WARN_EMULATED_SETUP(mfpvr),
1932 WARN_EMULATED_SETUP(multiple),
1933 WARN_EMULATED_SETUP(popcntb),
1934 WARN_EMULATED_SETUP(spe),
1935 WARN_EMULATED_SETUP(string),
1936 WARN_EMULATED_SETUP(sync),
1937 WARN_EMULATED_SETUP(unaligned),
1938 #ifdef CONFIG_MATH_EMULATION
1939 WARN_EMULATED_SETUP(math),
1942 WARN_EMULATED_SETUP(vsx),
1945 WARN_EMULATED_SETUP(mfdscr),
1946 WARN_EMULATED_SETUP(mtdscr),
1947 WARN_EMULATED_SETUP(lq_stq),
1951 u32 ppc_warn_emulated;
1953 void ppc_warn_emulated_print(const char *type)
1955 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1959 static int __init ppc_warn_emulated_init(void)
1961 struct dentry *dir, *d;
1963 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1965 if (!powerpc_debugfs_root)
1968 dir = debugfs_create_dir("emulated_instructions",
1969 powerpc_debugfs_root);
1973 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1974 &ppc_warn_emulated);
1978 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1979 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1980 (u32 *)&entries[i].val.counter);
1988 debugfs_remove_recursive(dir);
1992 device_initcall(ppc_warn_emulated_init);
1994 #endif /* CONFIG_PPC_EMULATED_STATS */