1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@samba.org)
11 * This file handles the architecture-dependent parts of hardware exceptions
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/kernel.h>
19 #include <linux/pkeys.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/module.h> /* print_modules */
28 #include <linux/prctl.h>
29 #include <linux/delay.h>
30 #include <linux/kprobes.h>
31 #include <linux/kexec.h>
32 #include <linux/backlight.h>
33 #include <linux/bug.h>
34 #include <linux/kdebug.h>
35 #include <linux/ratelimit.h>
36 #include <linux/context_tracking.h>
37 #include <linux/smp.h>
38 #include <linux/console.h>
39 #include <linux/kmsg_dump.h>
41 #include <asm/emulated_ops.h>
42 #include <linux/uaccess.h>
43 #include <asm/debugfs.h>
44 #include <asm/interrupt.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
69 #include <asm/stacktrace.h>
72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
73 int (*__debugger)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
81 EXPORT_SYMBOL(__debugger);
82 EXPORT_SYMBOL(__debugger_ipi);
83 EXPORT_SYMBOL(__debugger_bpt);
84 EXPORT_SYMBOL(__debugger_sstep);
85 EXPORT_SYMBOL(__debugger_iabr_match);
86 EXPORT_SYMBOL(__debugger_break_match);
87 EXPORT_SYMBOL(__debugger_fault_handler);
90 /* Transactional Memory trap debug */
92 #define TM_DEBUG(x...) printk(KERN_INFO x)
94 #define TM_DEBUG(x...) do { } while(0)
97 static const char *signame(int signr)
100 case SIGBUS: return "bus error";
101 case SIGFPE: return "floating point exception";
102 case SIGILL: return "illegal instruction";
103 case SIGSEGV: return "segfault";
104 case SIGTRAP: return "unhandled trap";
107 return "unknown signal";
111 * Trap & Exception support
114 #ifdef CONFIG_PMAC_BACKLIGHT
115 static void pmac_backlight_unblank(void)
117 mutex_lock(&pmac_backlight_mutex);
118 if (pmac_backlight) {
119 struct backlight_properties *props;
121 props = &pmac_backlight->props;
122 props->brightness = props->max_brightness;
123 props->power = FB_BLANK_UNBLANK;
124 backlight_update_status(pmac_backlight);
126 mutex_unlock(&pmac_backlight_mutex);
129 static inline void pmac_backlight_unblank(void) { }
133 * If oops/die is expected to crash the machine, return true here.
135 * This should not be expected to be 100% accurate, there may be
136 * notifiers registered or other unexpected conditions that may bring
137 * down the kernel. Or if the current process in the kernel is holding
138 * locks or has other critical state, the kernel may become effectively
141 bool die_will_crash(void)
143 if (should_fadump_crash())
145 if (kexec_should_crash(current))
147 if (in_interrupt() || panic_on_oops ||
148 !current->pid || is_global_init(current))
154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
155 static int die_owner = -1;
156 static unsigned int die_nest_count;
157 static int die_counter;
159 extern void panic_flush_kmsg_start(void)
162 * These are mostly taken from kernel/panic.c, but tries to do
163 * relatively minimal work. Don't use delay functions (TB may
164 * be broken), don't crash dump (need to set a firmware log),
165 * don't run notifiers. We do want to get some information to
172 extern void panic_flush_kmsg_end(void)
174 printk_safe_flush_on_panic();
175 kmsg_dump(KMSG_DUMP_PANIC);
178 console_flush_on_panic(CONSOLE_FLUSH_PENDING);
181 static unsigned long oops_begin(struct pt_regs *regs)
188 /* racy, but better than risking deadlock. */
189 raw_local_irq_save(flags);
190 cpu = smp_processor_id();
191 if (!arch_spin_trylock(&die_lock)) {
192 if (cpu == die_owner)
193 /* nested oops. should stop eventually */;
195 arch_spin_lock(&die_lock);
201 if (machine_is(powermac))
202 pmac_backlight_unblank();
205 NOKPROBE_SYMBOL(oops_begin);
207 static void oops_end(unsigned long flags, struct pt_regs *regs,
211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
215 if (!die_nest_count) {
216 /* Nest count reaches zero, release the lock. */
218 arch_spin_unlock(&die_lock);
220 raw_local_irq_restore(flags);
223 * system_reset_excption handles debugger, crash dump, panic, for 0x100
225 if (TRAP(regs) == 0x100)
228 crash_fadump(regs, "die oops");
230 if (kexec_should_crash(current))
237 * While our oops output is serialised by a spinlock, output
238 * from panic() called below can race and corrupt it. If we
239 * know we are going to panic, delay for 1 second so we have a
240 * chance to get clean backtraces from all CPUs that are oopsing.
242 if (in_interrupt() || panic_on_oops || !current->pid ||
243 is_global_init(current)) {
244 mdelay(MSEC_PER_SEC);
248 panic("Fatal exception");
251 NOKPROBE_SYMBOL(oops_end);
253 static char *get_mmu_str(void)
255 if (early_radix_enabled())
257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE))
262 static int __die(const char *str, struct pt_regs *regs, long err)
264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
268 PAGE_SIZE / 1024, get_mmu_str(),
269 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
270 IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
271 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
273 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "",
274 ppc_md.name ? ppc_md.name : "");
276 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
284 NOKPROBE_SYMBOL(__die);
286 void die(const char *str, struct pt_regs *regs, long err)
291 * system_reset_excption handles debugger, crash dump, panic, for 0x100
293 if (TRAP(regs) != 0x100) {
298 flags = oops_begin(regs);
299 if (__die(str, regs, err))
301 oops_end(flags, regs, err);
303 NOKPROBE_SYMBOL(die);
305 void user_single_step_report(struct pt_regs *regs)
307 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip);
310 static void show_signal_msg(int signr, struct pt_regs *regs, int code,
313 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
314 DEFAULT_RATELIMIT_BURST);
316 if (!show_unhandled_signals)
319 if (!unhandled_signal(current, signr))
322 if (!__ratelimit(&rs))
325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
326 current->comm, current->pid, signame(signr), signr,
327 addr, regs->nip, regs->link, code);
329 print_vma_addr(KERN_CONT " in ", regs->nip);
333 show_user_instructions(regs);
336 static bool exception_common(int signr, struct pt_regs *regs, int code,
339 if (!user_mode(regs)) {
340 die("Exception in kernel mode", regs, signr);
344 show_signal_msg(signr, regs, code, addr);
346 if (arch_irqs_disabled())
347 interrupt_cond_local_irq_enable(regs);
349 current->thread.trap_nr = code;
354 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key)
356 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr))
359 force_sig_pkuerr((void __user *) addr, key);
362 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
364 if (!exception_common(signr, regs, code, addr))
367 force_sig_fault(signr, code, (void __user *)addr);
371 * The interrupt architecture has a quirk in that the HV interrupts excluding
372 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
373 * that an interrupt handler must do is save off a GPR into a scratch register,
374 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
375 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
376 * that it is non-reentrant, which leads to random data corruption.
378 * The solution is for NMI interrupts in HV mode to check if they originated
379 * from these critical HV interrupt regions. If so, then mark them not
382 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
383 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
384 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
385 * that would work. However any other guest OS that may have the SPRG live
386 * and MSR[RI]=1 could encounter silent corruption.
388 * Builds that do not support KVM could take this second option to increase
389 * the recoverability of NMIs.
391 void hv_nmi_check_nonrecoverable(struct pt_regs *regs)
393 #ifdef CONFIG_PPC_POWERNV
394 unsigned long kbase = (unsigned long)_stext;
395 unsigned long nip = regs->nip;
397 if (!(regs->msr & MSR_RI))
399 if (!(regs->msr & MSR_HV))
401 if (regs->msr & MSR_PR)
405 * Now test if the interrupt has hit a range that may be using
406 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
407 * problem ranges all run un-relocated. Test real and virt modes
408 * at the same time by droping the high bit of the nip (virt mode
409 * entry points still have the +0x4000 offset).
411 nip &= ~0xc000000000000000ULL;
412 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600))
414 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00))
416 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0))
418 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0))
421 /* Trampoline code runs un-relocated so subtract kbase. */
422 if (nip >= (unsigned long)(start_real_trampolines - kbase) &&
423 nip < (unsigned long)(end_real_trampolines - kbase))
425 if (nip >= (unsigned long)(start_virt_trampolines - kbase) &&
426 nip < (unsigned long)(end_virt_trampolines - kbase))
431 regs->msr &= ~MSR_RI;
434 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception)
436 unsigned long hsrr0, hsrr1;
437 bool saved_hsrrs = false;
440 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
441 * The system reset interrupt itself may clobber HSRRs (e.g., to call
442 * OPAL), so save them here and restore them before returning.
444 * Machine checks don't need to save HSRRs, as the real mode handler
445 * is careful to avoid them, and the regular handler is not delivered
448 if (cpu_has_feature(CPU_FTR_HVMODE)) {
449 hsrr0 = mfspr(SPRN_HSRR0);
450 hsrr1 = mfspr(SPRN_HSRR1);
454 hv_nmi_check_nonrecoverable(regs);
456 __this_cpu_inc(irq_stat.sreset_irqs);
458 /* See if any machine dependent calls */
459 if (ppc_md.system_reset_exception) {
460 if (ppc_md.system_reset_exception(regs))
467 kmsg_dump(KMSG_DUMP_OOPS);
469 * A system reset is a request to dump, so we always send
470 * it through the crashdump code (if fadump or kdump are
473 crash_fadump(regs, "System Reset");
478 * We aren't the primary crash CPU. We need to send it
479 * to a holding pattern to avoid it ending up in the panic
482 crash_kexec_secondary(regs);
485 * No debugger or crash dump registered, print logs then
488 die("System Reset", regs, SIGABRT);
490 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
491 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
492 nmi_panic(regs, "System Reset");
495 #ifdef CONFIG_PPC_BOOK3S_64
496 BUG_ON(get_paca()->in_nmi == 0);
497 if (get_paca()->in_nmi > 1)
498 die("Unrecoverable nested System Reset", regs, SIGABRT);
500 /* Must die if the interrupt is not recoverable */
501 if (!(regs->msr & MSR_RI)) {
502 /* For the reason explained in die_mce, nmi_exit before die */
504 die("Unrecoverable System Reset", regs, SIGABRT);
508 mtspr(SPRN_HSRR0, hsrr0);
509 mtspr(SPRN_HSRR1, hsrr1);
512 /* What should we do here? We could issue a shutdown or hard reset. */
518 * I/O accesses can cause machine checks on powermacs.
519 * Check if the NIP corresponds to the address of a sync
520 * instruction for which there is an entry in the exception
524 static inline int check_io_access(struct pt_regs *regs)
527 unsigned long msr = regs->msr;
528 const struct exception_table_entry *entry;
529 unsigned int *nip = (unsigned int *)regs->nip;
531 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
532 && (entry = search_exception_tables(regs->nip)) != NULL) {
534 * Check that it's a sync instruction, or somewhere
535 * in the twi; isync; nop sequence that inb/inw/inl uses.
536 * As the address is in the exception table
537 * we should be able to read the instr there.
538 * For the debug message, we look at the preceding
541 if (*nip == PPC_INST_NOP)
543 else if (*nip == PPC_INST_ISYNC)
545 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
549 rb = (*nip >> 11) & 0x1f;
550 printk(KERN_DEBUG "%s bad port %lx at %p\n",
551 (*nip & 0x100)? "OUT to": "IN from",
552 regs->gpr[rb] - _IO_BASE, nip);
554 regs->nip = extable_fixup(entry);
558 #endif /* CONFIG_PPC32 */
562 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
563 /* On 4xx, the reason for the machine check or program exception
565 #define get_reason(regs) ((regs)->dsisr)
566 #define REASON_FP ESR_FP
567 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
568 #define REASON_PRIVILEGED ESR_PPR
569 #define REASON_TRAP ESR_PTR
570 #define REASON_PREFIXED 0
571 #define REASON_BOUNDARY 0
573 /* single-step stuff */
574 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
575 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
576 #define clear_br_trace(regs) do {} while(0)
578 /* On non-4xx, the reason for the machine check or program
579 exception is in the MSR. */
580 #define get_reason(regs) ((regs)->msr)
581 #define REASON_TM SRR1_PROGTM
582 #define REASON_FP SRR1_PROGFPE
583 #define REASON_ILLEGAL SRR1_PROGILL
584 #define REASON_PRIVILEGED SRR1_PROGPRIV
585 #define REASON_TRAP SRR1_PROGTRAP
586 #define REASON_PREFIXED SRR1_PREFIXED
587 #define REASON_BOUNDARY SRR1_BOUNDARY
589 #define single_stepping(regs) ((regs)->msr & MSR_SE)
590 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
591 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
594 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
596 #if defined(CONFIG_E500)
597 int machine_check_e500mc(struct pt_regs *regs)
599 unsigned long mcsr = mfspr(SPRN_MCSR);
600 unsigned long pvr = mfspr(SPRN_PVR);
601 unsigned long reason = mcsr;
604 if (reason & MCSR_LD) {
605 recoverable = fsl_rio_mcheck_exception(regs);
606 if (recoverable == 1)
610 printk("Machine check in kernel mode.\n");
611 printk("Caused by (from MCSR=%lx): ", reason);
613 if (reason & MCSR_MCP)
614 pr_cont("Machine Check Signal\n");
616 if (reason & MCSR_ICPERR) {
617 pr_cont("Instruction Cache Parity Error\n");
620 * This is recoverable by invalidating the i-cache.
622 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
623 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
627 * This will generally be accompanied by an instruction
628 * fetch error report -- only treat MCSR_IF as fatal
629 * if it wasn't due to an L1 parity error.
634 if (reason & MCSR_DCPERR_MC) {
635 pr_cont("Data Cache Parity Error\n");
638 * In write shadow mode we auto-recover from the error, but it
639 * may still get logged and cause a machine check. We should
640 * only treat the non-write shadow case as non-recoverable.
642 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
643 * is not implemented but L1 data cache always runs in write
644 * shadow mode. Hence on data cache parity errors HW will
645 * automatically invalidate the L1 Data Cache.
647 if (PVR_VER(pvr) != PVR_VER_E6500) {
648 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
653 if (reason & MCSR_L2MMU_MHIT) {
654 pr_cont("Hit on multiple TLB entries\n");
658 if (reason & MCSR_NMI)
659 pr_cont("Non-maskable interrupt\n");
661 if (reason & MCSR_IF) {
662 pr_cont("Instruction Fetch Error Report\n");
666 if (reason & MCSR_LD) {
667 pr_cont("Load Error Report\n");
671 if (reason & MCSR_ST) {
672 pr_cont("Store Error Report\n");
676 if (reason & MCSR_LDG) {
677 pr_cont("Guarded Load Error Report\n");
681 if (reason & MCSR_TLBSYNC)
682 pr_cont("Simultaneous tlbsync operations\n");
684 if (reason & MCSR_BSL2_ERR) {
685 pr_cont("Level 2 Cache Error\n");
689 if (reason & MCSR_MAV) {
692 addr = mfspr(SPRN_MCAR);
693 addr |= (u64)mfspr(SPRN_MCARU) << 32;
695 pr_cont("Machine Check %s Address: %#llx\n",
696 reason & MCSR_MEA ? "Effective" : "Physical", addr);
700 mtspr(SPRN_MCSR, mcsr);
701 return mfspr(SPRN_MCSR) == 0 && recoverable;
704 int machine_check_e500(struct pt_regs *regs)
706 unsigned long reason = mfspr(SPRN_MCSR);
708 if (reason & MCSR_BUS_RBERR) {
709 if (fsl_rio_mcheck_exception(regs))
711 if (fsl_pci_mcheck_exception(regs))
715 printk("Machine check in kernel mode.\n");
716 printk("Caused by (from MCSR=%lx): ", reason);
718 if (reason & MCSR_MCP)
719 pr_cont("Machine Check Signal\n");
720 if (reason & MCSR_ICPERR)
721 pr_cont("Instruction Cache Parity Error\n");
722 if (reason & MCSR_DCP_PERR)
723 pr_cont("Data Cache Push Parity Error\n");
724 if (reason & MCSR_DCPERR)
725 pr_cont("Data Cache Parity Error\n");
726 if (reason & MCSR_BUS_IAERR)
727 pr_cont("Bus - Instruction Address Error\n");
728 if (reason & MCSR_BUS_RAERR)
729 pr_cont("Bus - Read Address Error\n");
730 if (reason & MCSR_BUS_WAERR)
731 pr_cont("Bus - Write Address Error\n");
732 if (reason & MCSR_BUS_IBERR)
733 pr_cont("Bus - Instruction Data Error\n");
734 if (reason & MCSR_BUS_RBERR)
735 pr_cont("Bus - Read Data Bus Error\n");
736 if (reason & MCSR_BUS_WBERR)
737 pr_cont("Bus - Write Data Bus Error\n");
738 if (reason & MCSR_BUS_IPERR)
739 pr_cont("Bus - Instruction Parity Error\n");
740 if (reason & MCSR_BUS_RPERR)
741 pr_cont("Bus - Read Parity Error\n");
746 int machine_check_generic(struct pt_regs *regs)
750 #elif defined(CONFIG_PPC32)
751 int machine_check_generic(struct pt_regs *regs)
753 unsigned long reason = regs->msr;
755 printk("Machine check in kernel mode.\n");
756 printk("Caused by (from SRR1=%lx): ", reason);
757 switch (reason & 0x601F0000) {
759 pr_cont("Machine check signal\n");
762 case 0x140000: /* 7450 MSS error and TEA */
763 pr_cont("Transfer error ack signal\n");
766 pr_cont("Data parity error signal\n");
769 pr_cont("Address parity error signal\n");
772 pr_cont("L1 Data Cache error\n");
775 pr_cont("L1 Instruction Cache error\n");
778 pr_cont("L2 data cache parity error\n");
781 pr_cont("Unknown values in msr\n");
785 #endif /* everything else */
787 void die_mce(const char *str, struct pt_regs *regs, long err)
790 * The machine check wants to kill the interrupted context, but
791 * do_exit() checks for in_interrupt() and panics in that case, so
792 * exit the irq/nmi before calling die.
794 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
802 * BOOK3S_64 does not call this handler as a non-maskable interrupt
803 * (it uses its own early real-mode handler to handle the MCE proper
804 * and then raises irq_work to call this handler when interrupts are
807 #ifdef CONFIG_PPC_BOOK3S_64
808 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception)
810 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception)
815 __this_cpu_inc(irq_stat.mce_exceptions);
817 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
819 /* See if any machine dependent calls. In theory, we would want
820 * to call the CPU first, and call the ppc_md. one if the CPU
821 * one returns a positive number. However there is existing code
822 * that assumes the board gets a first chance, so let's keep it
823 * that way for now and fix things later. --BenH.
825 if (ppc_md.machine_check_exception)
826 recover = ppc_md.machine_check_exception(regs);
827 else if (cur_cpu_spec->machine_check)
828 recover = cur_cpu_spec->machine_check(regs);
833 if (debugger_fault_handler(regs))
836 if (check_io_access(regs))
839 die_mce("Machine check", regs, SIGBUS);
842 /* Must die if the interrupt is not recoverable */
843 if (!(regs->msr & MSR_RI))
844 die_mce("Unrecoverable Machine check", regs, SIGBUS);
846 #ifdef CONFIG_PPC_BOOK3S_64
853 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */
855 die("System Management Interrupt", regs, SIGABRT);
859 static void p9_hmi_special_emu(struct pt_regs *regs)
861 unsigned int ra, rb, t, i, sel, instr, rc;
862 const void __user *addr;
863 u8 vbuf[16] __aligned(16), *vdst;
864 unsigned long ea, msr, msr_mask;
867 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
871 * lxvb16x opcode: 0x7c0006d8
872 * lxvd2x opcode: 0x7c000698
873 * lxvh8x opcode: 0x7c000658
874 * lxvw4x opcode: 0x7c000618
876 if ((instr & 0xfc00073e) != 0x7c000618) {
877 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
879 smp_processor_id(), current->comm, current->pid,
884 /* Grab vector registers into the task struct */
885 msr = regs->msr; /* Grab msr before we flush the bits */
886 flush_vsx_to_thread(current);
887 enable_kernel_altivec();
890 * Is userspace running with a different endian (this is rare but
893 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
895 /* Decode the instruction */
896 ra = (instr >> 16) & 0x1f;
897 rb = (instr >> 11) & 0x1f;
898 t = (instr >> 21) & 0x1f;
900 vdst = (u8 *)¤t->thread.vr_state.vr[t];
902 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
904 /* Grab the vector address */
905 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
908 addr = (__force const void __user *)ea;
911 if (!access_ok(addr, 16)) {
912 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
913 " instr=%08x addr=%016lx\n",
914 smp_processor_id(), current->comm, current->pid,
915 regs->nip, instr, (unsigned long)addr);
919 /* Read the vector */
921 if ((unsigned long)addr & 0xfUL)
923 rc = __copy_from_user_inatomic(vbuf, addr, 16);
925 __get_user_atomic_128_aligned(vbuf, addr, rc);
927 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
928 " instr=%08x addr=%016lx\n",
929 smp_processor_id(), current->comm, current->pid,
930 regs->nip, instr, (unsigned long)addr);
934 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
935 " instr=%08x addr=%016lx\n",
936 smp_processor_id(), current->comm, current->pid, regs->nip,
937 instr, (unsigned long) addr);
939 /* Grab instruction "selector" */
940 sel = (instr >> 6) & 3;
943 * Check to make sure the facility is actually enabled. This
944 * could happen if we get a false positive hit.
946 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
947 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
950 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
952 if (!(msr & msr_mask)) {
953 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
954 " instr=%08x msr:%016lx\n",
955 smp_processor_id(), current->comm, current->pid,
956 regs->nip, instr, msr);
960 /* Do logging here before we modify sel based on endian */
963 PPC_WARN_EMULATED(lxvw4x, regs);
966 PPC_WARN_EMULATED(lxvh8x, regs);
969 PPC_WARN_EMULATED(lxvd2x, regs);
971 case 3: /* lxvb16x */
972 PPC_WARN_EMULATED(lxvb16x, regs);
976 #ifdef __LITTLE_ENDIAN__
978 * An LE kernel stores the vector in the task struct as an LE
979 * byte array (effectively swapping both the components and
980 * the content of the components). Those instructions expect
981 * the components to remain in ascending address order, so we
984 * If we are running a BE user space, the expectation is that
985 * of a simple memcpy, so forcing the emulation to look like
986 * a lxvb16x should do the trick.
993 for (i = 0; i < 4; i++)
994 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
997 for (i = 0; i < 8; i++)
998 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
1000 case 2: /* lxvd2x */
1001 for (i = 0; i < 2; i++)
1002 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
1004 case 3: /* lxvb16x */
1005 for (i = 0; i < 16; i++)
1006 vdst[i] = vbuf[15-i];
1009 #else /* __LITTLE_ENDIAN__ */
1010 /* On a big endian kernel, a BE userspace only needs a memcpy */
1014 /* Otherwise, we need to swap the content of the components */
1016 case 0: /* lxvw4x */
1017 for (i = 0; i < 4; i++)
1018 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
1020 case 1: /* lxvh8x */
1021 for (i = 0; i < 8; i++)
1022 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
1024 case 2: /* lxvd2x */
1025 for (i = 0; i < 2; i++)
1026 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
1028 case 3: /* lxvb16x */
1029 memcpy(vdst, vbuf, 16);
1032 #endif /* !__LITTLE_ENDIAN__ */
1034 /* Go to next instruction */
1037 #endif /* CONFIG_VSX */
1039 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception)
1041 struct pt_regs *old_regs;
1043 old_regs = set_irq_regs(regs);
1046 /* Real mode flagged P9 special emu is needed */
1047 if (local_paca->hmi_p9_special_emu) {
1048 local_paca->hmi_p9_special_emu = 0;
1051 * We don't want to take page faults while doing the
1052 * emulation, we just replay the instruction if necessary.
1054 pagefault_disable();
1055 p9_hmi_special_emu(regs);
1058 #endif /* CONFIG_VSX */
1060 if (ppc_md.handle_hmi_exception)
1061 ppc_md.handle_hmi_exception(regs);
1063 set_irq_regs(old_regs);
1066 DEFINE_INTERRUPT_HANDLER(unknown_exception)
1068 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1069 regs->nip, regs->msr, regs->trap);
1071 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1074 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception)
1076 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1077 regs->nip, regs->msr, regs->trap);
1079 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1082 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception)
1084 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
1085 5, SIGTRAP) == NOTIFY_STOP)
1087 if (debugger_iabr_match(regs))
1089 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1092 DEFINE_INTERRUPT_HANDLER(RunModeException)
1094 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1097 DEFINE_INTERRUPT_HANDLER(single_step_exception)
1099 clear_single_step(regs);
1100 clear_br_trace(regs);
1102 if (kprobe_post_handler(regs))
1105 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1106 5, SIGTRAP) == NOTIFY_STOP)
1108 if (debugger_sstep(regs))
1111 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1115 * After we have successfully emulated an instruction, we have to
1116 * check if the instruction was being single-stepped, and if so,
1117 * pretend we got a single-step exception. This was pointed out
1118 * by Kumar Gala. -- paulus
1120 static void emulate_single_step(struct pt_regs *regs)
1122 if (single_stepping(regs))
1123 single_step_exception(regs);
1126 static inline int __parse_fpscr(unsigned long fpscr)
1128 int ret = FPE_FLTUNK;
1130 /* Invalid operation */
1131 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1135 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1139 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1142 /* Divide by zero */
1143 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1146 /* Inexact result */
1147 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1153 static void parse_fpe(struct pt_regs *regs)
1157 flush_fp_to_thread(current);
1159 #ifdef CONFIG_PPC_FPU_REGS
1160 code = __parse_fpscr(current->thread.fp_state.fpscr);
1163 _exception(SIGFPE, regs, code, regs->nip);
1167 * Illegal instruction emulation support. Originally written to
1168 * provide the PVR to user applications using the mfspr rd, PVR.
1169 * Return non-zero if we can't emulate, or -EFAULT if the associated
1170 * memory access caused an access fault. Return zero on success.
1172 * There are a couple of ways to do this, either "decode" the instruction
1173 * or directly match lots of bits. In this case, matching lots of
1174 * bits is faster and easier.
1177 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1179 u8 rT = (instword >> 21) & 0x1f;
1180 u8 rA = (instword >> 16) & 0x1f;
1181 u8 NB_RB = (instword >> 11) & 0x1f;
1186 /* Early out if we are an invalid form of lswx */
1187 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1188 if ((rT == rA) || (rT == NB_RB))
1191 EA = (rA == 0) ? 0 : regs->gpr[rA];
1193 switch (instword & PPC_INST_STRING_MASK) {
1195 case PPC_INST_STSWX:
1197 num_bytes = regs->xer & 0x7f;
1200 case PPC_INST_STSWI:
1201 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1207 while (num_bytes != 0)
1210 u32 shift = 8 * (3 - (pos & 0x3));
1212 /* if process is 32-bit, clear upper 32 bits of EA */
1213 if ((regs->msr & MSR_64BIT) == 0)
1216 switch ((instword & PPC_INST_STRING_MASK)) {
1219 if (get_user(val, (u8 __user *)EA))
1221 /* first time updating this reg,
1225 regs->gpr[rT] |= val << shift;
1227 case PPC_INST_STSWI:
1228 case PPC_INST_STSWX:
1229 val = regs->gpr[rT] >> shift;
1230 if (put_user(val, (u8 __user *)EA))
1234 /* move EA to next address */
1238 /* manage our position within the register */
1249 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1254 ra = (instword >> 16) & 0x1f;
1255 rs = (instword >> 21) & 0x1f;
1257 tmp = regs->gpr[rs];
1258 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1259 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1260 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1261 regs->gpr[ra] = tmp;
1266 static int emulate_isel(struct pt_regs *regs, u32 instword)
1268 u8 rT = (instword >> 21) & 0x1f;
1269 u8 rA = (instword >> 16) & 0x1f;
1270 u8 rB = (instword >> 11) & 0x1f;
1271 u8 BC = (instword >> 6) & 0x1f;
1275 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1276 bit = (regs->ccr >> (31 - BC)) & 0x1;
1278 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1283 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1284 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1286 /* If we're emulating a load/store in an active transaction, we cannot
1287 * emulate it as the kernel operates in transaction suspended context.
1288 * We need to abort the transaction. This creates a persistent TM
1289 * abort so tell the user what caused it with a new code.
1291 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1299 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1305 static int emulate_instruction(struct pt_regs *regs)
1310 if (!user_mode(regs))
1312 CHECK_FULL_REGS(regs);
1314 if (get_user(instword, (u32 __user *)(regs->nip)))
1317 /* Emulate the mfspr rD, PVR. */
1318 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1319 PPC_WARN_EMULATED(mfpvr, regs);
1320 rd = (instword >> 21) & 0x1f;
1321 regs->gpr[rd] = mfspr(SPRN_PVR);
1325 /* Emulating the dcba insn is just a no-op. */
1326 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1327 PPC_WARN_EMULATED(dcba, regs);
1331 /* Emulate the mcrxr insn. */
1332 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1333 int shift = (instword >> 21) & 0x1c;
1334 unsigned long msk = 0xf0000000UL >> shift;
1336 PPC_WARN_EMULATED(mcrxr, regs);
1337 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1338 regs->xer &= ~0xf0000000UL;
1342 /* Emulate load/store string insn. */
1343 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1344 if (tm_abort_check(regs,
1345 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1347 PPC_WARN_EMULATED(string, regs);
1348 return emulate_string_inst(regs, instword);
1351 /* Emulate the popcntb (Population Count Bytes) instruction. */
1352 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1353 PPC_WARN_EMULATED(popcntb, regs);
1354 return emulate_popcntb_inst(regs, instword);
1357 /* Emulate isel (Integer Select) instruction */
1358 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1359 PPC_WARN_EMULATED(isel, regs);
1360 return emulate_isel(regs, instword);
1363 /* Emulate sync instruction variants */
1364 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1365 PPC_WARN_EMULATED(sync, regs);
1366 asm volatile("sync");
1371 /* Emulate the mfspr rD, DSCR. */
1372 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1373 PPC_INST_MFSPR_DSCR_USER) ||
1374 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1375 PPC_INST_MFSPR_DSCR)) &&
1376 cpu_has_feature(CPU_FTR_DSCR)) {
1377 PPC_WARN_EMULATED(mfdscr, regs);
1378 rd = (instword >> 21) & 0x1f;
1379 regs->gpr[rd] = mfspr(SPRN_DSCR);
1382 /* Emulate the mtspr DSCR, rD. */
1383 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1384 PPC_INST_MTSPR_DSCR_USER) ||
1385 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1386 PPC_INST_MTSPR_DSCR)) &&
1387 cpu_has_feature(CPU_FTR_DSCR)) {
1388 PPC_WARN_EMULATED(mtdscr, regs);
1389 rd = (instword >> 21) & 0x1f;
1390 current->thread.dscr = regs->gpr[rd];
1391 current->thread.dscr_inherit = 1;
1392 mtspr(SPRN_DSCR, current->thread.dscr);
1400 int is_valid_bugaddr(unsigned long addr)
1402 return is_kernel_addr(addr);
1405 #ifdef CONFIG_MATH_EMULATION
1406 static int emulate_math(struct pt_regs *regs)
1409 extern int do_mathemu(struct pt_regs *regs);
1411 ret = do_mathemu(regs);
1413 PPC_WARN_EMULATED(math, regs);
1417 emulate_single_step(regs);
1421 code = __parse_fpscr(current->thread.fp_state.fpscr);
1422 _exception(SIGFPE, regs, code, regs->nip);
1426 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1433 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1436 static void do_program_check(struct pt_regs *regs)
1438 unsigned int reason = get_reason(regs);
1440 /* We can now get here via a FP Unavailable exception if the core
1441 * has no FPU, in that case the reason flags will be 0 */
1443 if (reason & REASON_FP) {
1444 /* IEEE FP exception */
1448 if (reason & REASON_TRAP) {
1449 unsigned long bugaddr;
1450 /* Debugger is first in line to stop recursive faults in
1451 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1452 if (debugger_bpt(regs))
1455 if (kprobe_handler(regs))
1458 /* trap exception */
1459 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1463 bugaddr = regs->nip;
1465 * Fixup bugaddr for BUG_ON() in real mode
1467 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1468 bugaddr += PAGE_OFFSET;
1470 if (!(regs->msr & MSR_PR) && /* not user-mode */
1471 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1475 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1478 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1479 if (reason & REASON_TM) {
1480 /* This is a TM "Bad Thing Exception" program check.
1482 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1483 * transition in TM states.
1484 * - A trechkpt is attempted when transactional.
1485 * - A treclaim is attempted when non transactional.
1486 * - A tend is illegally attempted.
1487 * - writing a TM SPR when transactional.
1489 * If usermode caused this, it's done something illegal and
1490 * gets a SIGILL slap on the wrist. We call it an illegal
1491 * operand to distinguish from the instruction just being bad
1492 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1493 * illegal /placement/ of a valid instruction.
1495 if (user_mode(regs)) {
1496 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1499 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1500 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1501 regs->nip, regs->msr, get_paca()->tm_scratch);
1502 die("Unrecoverable exception", regs, SIGABRT);
1508 * If we took the program check in the kernel skip down to sending a
1509 * SIGILL. The subsequent cases all relate to emulating instructions
1510 * which we should only do for userspace. We also do not want to enable
1511 * interrupts for kernel faults because that might lead to further
1512 * faults, and loose the context of the original exception.
1514 if (!user_mode(regs))
1517 interrupt_cond_local_irq_enable(regs);
1519 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1520 * but there seems to be a hardware bug on the 405GP (RevD)
1521 * that means ESR is sometimes set incorrectly - either to
1522 * ESR_DST (!?) or 0. In the process of chasing this with the
1523 * hardware people - not sure if it can happen on any illegal
1524 * instruction or only on FP instructions, whether there is a
1525 * pattern to occurrences etc. -dgibson 31/Mar/2003
1527 if (!emulate_math(regs))
1530 /* Try to emulate it if we should. */
1531 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1532 switch (emulate_instruction(regs)) {
1535 emulate_single_step(regs);
1538 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1544 if (reason & REASON_PRIVILEGED)
1545 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1547 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1551 DEFINE_INTERRUPT_HANDLER(program_check_exception)
1553 do_program_check(regs);
1557 * This occurs when running in hypervisor mode on POWER6 or later
1558 * and an illegal instruction is encountered.
1560 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt)
1562 regs->msr |= REASON_ILLEGAL;
1563 do_program_check(regs);
1566 DEFINE_INTERRUPT_HANDLER(alignment_exception)
1568 int sig, code, fixed = 0;
1569 unsigned long reason;
1571 interrupt_cond_local_irq_enable(regs);
1573 reason = get_reason(regs);
1574 if (reason & REASON_BOUNDARY) {
1580 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1583 /* we don't implement logging of alignment exceptions */
1584 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1585 fixed = fix_alignment(regs);
1588 /* skip over emulated instruction */
1589 regs->nip += inst_length(reason);
1590 emulate_single_step(regs);
1594 /* Operand address was bad */
1595 if (fixed == -EFAULT) {
1603 if (user_mode(regs))
1604 _exception(sig, regs, code, regs->dar);
1606 bad_page_fault(regs, sig);
1609 DEFINE_INTERRUPT_HANDLER(StackOverflow)
1611 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1612 current->comm, task_pid_nr(current), regs->gpr[1]);
1615 panic("kernel stack overflow");
1618 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception)
1620 die("Kernel stack overflow", regs, SIGSEGV);
1623 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception)
1625 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1626 "%lx at %lx\n", regs->trap, regs->nip);
1627 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1630 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception)
1632 if (user_mode(regs)) {
1633 /* A user program has executed an altivec instruction,
1634 but this kernel doesn't support altivec. */
1635 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1639 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1640 "%lx at %lx\n", regs->trap, regs->nip);
1641 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1644 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception)
1646 if (user_mode(regs)) {
1647 /* A user program has executed an vsx instruction,
1648 but this kernel doesn't support vsx. */
1649 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1653 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1654 "%lx at %lx\n", regs->trap, regs->nip);
1655 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1659 static void tm_unavailable(struct pt_regs *regs)
1661 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1662 if (user_mode(regs)) {
1663 current->thread.load_tm++;
1664 regs->msr |= MSR_TM;
1666 tm_restore_sprs(¤t->thread);
1670 pr_emerg("Unrecoverable TM Unavailable Exception "
1671 "%lx at %lx\n", regs->trap, regs->nip);
1672 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1675 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception)
1677 static char *facility_strings[] = {
1678 [FSCR_FP_LG] = "FPU",
1679 [FSCR_VECVSX_LG] = "VMX/VSX",
1680 [FSCR_DSCR_LG] = "DSCR",
1681 [FSCR_PM_LG] = "PMU SPRs",
1682 [FSCR_BHRB_LG] = "BHRB",
1683 [FSCR_TM_LG] = "TM",
1684 [FSCR_EBB_LG] = "EBB",
1685 [FSCR_TAR_LG] = "TAR",
1686 [FSCR_MSGP_LG] = "MSGP",
1687 [FSCR_SCV_LG] = "SCV",
1688 [FSCR_PREFIX_LG] = "PREFIX",
1690 char *facility = "unknown";
1696 hv = (TRAP(regs) == 0xf80);
1698 value = mfspr(SPRN_HFSCR);
1700 value = mfspr(SPRN_FSCR);
1702 status = value >> 56;
1703 if ((hv || status >= 2) &&
1704 (status < ARRAY_SIZE(facility_strings)) &&
1705 facility_strings[status])
1706 facility = facility_strings[status];
1708 /* We should not have taken this interrupt in kernel */
1709 if (!user_mode(regs)) {
1710 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1711 facility, status, regs->nip);
1712 die("Unexpected facility unavailable exception", regs, SIGABRT);
1715 interrupt_cond_local_irq_enable(regs);
1717 if (status == FSCR_DSCR_LG) {
1719 * User is accessing the DSCR register using the problem
1720 * state only SPR number (0x03) either through a mfspr or
1721 * a mtspr instruction. If it is a write attempt through
1722 * a mtspr, then we set the inherit bit. This also allows
1723 * the user to write or read the register directly in the
1724 * future by setting via the FSCR DSCR bit. But in case it
1725 * is a read DSCR attempt through a mfspr instruction, we
1726 * just emulate the instruction instead. This code path will
1727 * always emulate all the mfspr instructions till the user
1728 * has attempted at least one mtspr instruction. This way it
1729 * preserves the same behaviour when the user is accessing
1730 * the DSCR through privilege level only SPR number (0x11)
1731 * which is emulated through illegal instruction exception.
1732 * We always leave HFSCR DSCR set.
1734 if (get_user(instword, (u32 __user *)(regs->nip))) {
1735 pr_err("Failed to fetch the user instruction\n");
1739 /* Write into DSCR (mtspr 0x03, RS) */
1740 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1741 == PPC_INST_MTSPR_DSCR_USER) {
1742 rd = (instword >> 21) & 0x1f;
1743 current->thread.dscr = regs->gpr[rd];
1744 current->thread.dscr_inherit = 1;
1745 current->thread.fscr |= FSCR_DSCR;
1746 mtspr(SPRN_FSCR, current->thread.fscr);
1749 /* Read from DSCR (mfspr RT, 0x03) */
1750 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1751 == PPC_INST_MFSPR_DSCR_USER) {
1752 if (emulate_instruction(regs)) {
1753 pr_err("DSCR based mfspr emulation failed\n");
1757 emulate_single_step(regs);
1762 if (status == FSCR_TM_LG) {
1764 * If we're here then the hardware is TM aware because it
1765 * generated an exception with FSRM_TM set.
1767 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1768 * told us not to do TM, or the kernel is not built with TM
1771 * If both of those things are true, then userspace can spam the
1772 * console by triggering the printk() below just by continually
1773 * doing tbegin (or any TM instruction). So in that case just
1774 * send the process a SIGILL immediately.
1776 if (!cpu_has_feature(CPU_FTR_TM))
1779 tm_unavailable(regs);
1783 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1784 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1787 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1791 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1793 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm)
1795 /* Note: This does not handle any kind of FP laziness. */
1797 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1798 regs->nip, regs->msr);
1800 /* We can only have got here if the task started using FP after
1801 * beginning the transaction. So, the transactional regs are just a
1802 * copy of the checkpointed ones. But, we still need to recheckpoint
1803 * as we're enabling FP for the process; it will return, abort the
1804 * transaction, and probably retry but now with FP enabled. So the
1805 * checkpointed FP registers need to be loaded.
1807 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1810 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1811 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1813 * At this point, ck{fp,vr}_state contains the exact values we want to
1817 /* Enable FP for the task: */
1818 current->thread.load_fp = 1;
1821 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1823 tm_recheckpoint(¤t->thread);
1826 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm)
1828 /* See the comments in fp_unavailable_tm(). This function operates
1832 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1834 regs->nip, regs->msr);
1835 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1836 current->thread.load_vec = 1;
1837 tm_recheckpoint(¤t->thread);
1838 current->thread.used_vr = 1;
1841 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm)
1843 /* See the comments in fp_unavailable_tm(). This works similarly,
1844 * though we're loading both FP and VEC registers in here.
1846 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1847 * regs. Either way, set MSR_VSX.
1850 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1852 regs->nip, regs->msr);
1854 current->thread.used_vsr = 1;
1856 /* This reclaims FP and/or VR regs if they're already enabled */
1857 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1859 current->thread.load_vec = 1;
1860 current->thread.load_fp = 1;
1862 tm_recheckpoint(¤t->thread);
1864 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1867 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi);
1868 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi)
1870 __this_cpu_inc(irq_stat.pmu_irqs);
1878 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async);
1879 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async)
1881 __this_cpu_inc(irq_stat.pmu_irqs);
1886 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception)
1889 * On 64-bit, if perf interrupts hit in a local_irq_disable
1890 * (soft-masked) region, we consider them as NMIs. This is required to
1891 * prevent hash faults on user addresses when reading callchains (and
1892 * looks better from an irq tracing perspective).
1894 if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs)))
1895 performance_monitor_exception_nmi(regs);
1897 performance_monitor_exception_async(regs);
1902 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1903 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1907 * Determine the cause of the debug event, clear the
1908 * event flags and send a trap to the handler. Torez
1910 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1911 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1912 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1913 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1915 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
1918 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1919 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1920 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
1923 } else if (debug_status & DBSR_IAC1) {
1924 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1925 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1926 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
1929 } else if (debug_status & DBSR_IAC2) {
1930 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1931 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
1934 } else if (debug_status & DBSR_IAC3) {
1935 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1936 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1937 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
1940 } else if (debug_status & DBSR_IAC4) {
1941 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1942 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
1947 * At the point this routine was called, the MSR(DE) was turned off.
1948 * Check all other debug flags and see if that bit needs to be turned
1951 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1952 current->thread.debug.dbcr1))
1953 regs->msr |= MSR_DE;
1955 /* Make sure the IDM flag is off */
1956 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1959 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1962 DEFINE_INTERRUPT_HANDLER(DebugException)
1964 unsigned long debug_status = regs->dsisr;
1966 current->thread.debug.dbsr = debug_status;
1968 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1969 * on server, it stops on the target of the branch. In order to simulate
1970 * the server behaviour, we thus restart right away with a single step
1971 * instead of stopping here when hitting a BT
1973 if (debug_status & DBSR_BT) {
1974 regs->msr &= ~MSR_DE;
1977 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1978 /* Clear the BT event */
1979 mtspr(SPRN_DBSR, DBSR_BT);
1981 /* Do the single step trick only when coming from userspace */
1982 if (user_mode(regs)) {
1983 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1984 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1985 regs->msr |= MSR_DE;
1989 if (kprobe_post_handler(regs))
1992 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1993 5, SIGTRAP) == NOTIFY_STOP) {
1996 if (debugger_sstep(regs))
1998 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1999 regs->msr &= ~MSR_DE;
2001 /* Disable instruction completion */
2002 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
2003 /* Clear the instruction completion event */
2004 mtspr(SPRN_DBSR, DBSR_IC);
2006 if (kprobe_post_handler(regs))
2009 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
2010 5, SIGTRAP) == NOTIFY_STOP) {
2014 if (debugger_sstep(regs))
2017 if (user_mode(regs)) {
2018 current->thread.debug.dbcr0 &= ~DBCR0_IC;
2019 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
2020 current->thread.debug.dbcr1))
2021 regs->msr |= MSR_DE;
2023 /* Make sure the IDM bit is off */
2024 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
2027 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
2029 handle_debug(regs, debug_status);
2031 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2033 #ifdef CONFIG_ALTIVEC
2034 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception)
2038 if (!user_mode(regs)) {
2039 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
2040 " at %lx\n", regs->nip);
2041 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
2044 flush_altivec_to_thread(current);
2046 PPC_WARN_EMULATED(altivec, regs);
2047 err = emulate_altivec(regs);
2049 regs->nip += 4; /* skip emulated instruction */
2050 emulate_single_step(regs);
2054 if (err == -EFAULT) {
2055 /* got an error reading the instruction */
2056 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2058 /* didn't recognize the instruction */
2059 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2060 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
2061 "in %s at %lx\n", current->comm, regs->nip);
2062 current->thread.vr_state.vscr.u[3] |= 0x10000;
2065 #endif /* CONFIG_ALTIVEC */
2067 #ifdef CONFIG_FSL_BOOKE
2068 DEFINE_INTERRUPT_HANDLER(CacheLockingException)
2070 unsigned long error_code = regs->dsisr;
2072 /* We treat cache locking instructions from the user
2073 * as priv ops, in the future we could try to do
2076 if (error_code & (ESR_DLK|ESR_ILK))
2077 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
2080 #endif /* CONFIG_FSL_BOOKE */
2083 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException)
2085 extern int do_spe_mathemu(struct pt_regs *regs);
2086 unsigned long spefscr;
2088 int code = FPE_FLTUNK;
2091 interrupt_cond_local_irq_enable(regs);
2093 flush_spe_to_thread(current);
2095 spefscr = current->thread.spefscr;
2096 fpexc_mode = current->thread.fpexc_mode;
2098 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
2101 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
2104 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
2106 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
2109 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
2112 err = do_spe_mathemu(regs);
2114 regs->nip += 4; /* skip emulated instruction */
2115 emulate_single_step(regs);
2119 if (err == -EFAULT) {
2120 /* got an error reading the instruction */
2121 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2122 } else if (err == -EINVAL) {
2123 /* didn't recognize the instruction */
2124 printk(KERN_ERR "unrecognized spe instruction "
2125 "in %s at %lx\n", current->comm, regs->nip);
2127 _exception(SIGFPE, regs, code, regs->nip);
2133 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException)
2135 extern int speround_handler(struct pt_regs *regs);
2138 interrupt_cond_local_irq_enable(regs);
2141 if (regs->msr & MSR_SPE)
2142 giveup_spe(current);
2146 err = speround_handler(regs);
2148 regs->nip += 4; /* skip emulated instruction */
2149 emulate_single_step(regs);
2153 if (err == -EFAULT) {
2154 /* got an error reading the instruction */
2155 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2156 } else if (err == -EINVAL) {
2157 /* didn't recognize the instruction */
2158 printk(KERN_ERR "unrecognized spe instruction "
2159 "in %s at %lx\n", current->comm, regs->nip);
2161 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip);
2168 * We enter here if we get an unrecoverable exception, that is, one
2169 * that happened at a point where the RI (recoverable interrupt) bit
2170 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2171 * we therefore lost state by taking this exception.
2173 DEFINE_INTERRUPT_HANDLER(unrecoverable_exception)
2175 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2176 regs->trap, regs->nip, regs->msr);
2177 die("Unrecoverable exception", regs, SIGABRT);
2180 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2182 * Default handler for a Watchdog exception,
2183 * spins until a reboot occurs
2185 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2187 /* Generic WatchdogHandler, implement your own */
2188 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2192 DEFINE_INTERRUPT_HANDLER(WatchdogException) /* XXX NMI? async? */
2194 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2195 WatchdogHandler(regs);
2200 * We enter here if we discover during exception entry that we are
2201 * running in supervisor mode with a userspace value in the stack pointer.
2203 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack)
2205 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2206 regs->gpr[1], regs->nip);
2207 die("Bad kernel stack pointer", regs, SIGABRT);
2210 void __init trap_init(void)
2215 #ifdef CONFIG_PPC_EMULATED_STATS
2217 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2219 struct ppc_emulated ppc_emulated = {
2220 #ifdef CONFIG_ALTIVEC
2221 WARN_EMULATED_SETUP(altivec),
2223 WARN_EMULATED_SETUP(dcba),
2224 WARN_EMULATED_SETUP(dcbz),
2225 WARN_EMULATED_SETUP(fp_pair),
2226 WARN_EMULATED_SETUP(isel),
2227 WARN_EMULATED_SETUP(mcrxr),
2228 WARN_EMULATED_SETUP(mfpvr),
2229 WARN_EMULATED_SETUP(multiple),
2230 WARN_EMULATED_SETUP(popcntb),
2231 WARN_EMULATED_SETUP(spe),
2232 WARN_EMULATED_SETUP(string),
2233 WARN_EMULATED_SETUP(sync),
2234 WARN_EMULATED_SETUP(unaligned),
2235 #ifdef CONFIG_MATH_EMULATION
2236 WARN_EMULATED_SETUP(math),
2239 WARN_EMULATED_SETUP(vsx),
2242 WARN_EMULATED_SETUP(mfdscr),
2243 WARN_EMULATED_SETUP(mtdscr),
2244 WARN_EMULATED_SETUP(lq_stq),
2245 WARN_EMULATED_SETUP(lxvw4x),
2246 WARN_EMULATED_SETUP(lxvh8x),
2247 WARN_EMULATED_SETUP(lxvd2x),
2248 WARN_EMULATED_SETUP(lxvb16x),
2252 u32 ppc_warn_emulated;
2254 void ppc_warn_emulated_print(const char *type)
2256 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2260 static int __init ppc_warn_emulated_init(void)
2264 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2266 dir = debugfs_create_dir("emulated_instructions",
2267 powerpc_debugfs_root);
2269 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated);
2271 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++)
2272 debugfs_create_u32(entries[i].name, 0644, dir,
2273 (u32 *)&entries[i].val.counter);
2278 device_initcall(ppc_warn_emulated_init);
2280 #endif /* CONFIG_PPC_EMULATED_STATS */