1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/device.h>
5 #include <linux/percpu.h>
6 #include <linux/init.h>
7 #include <linux/sched.h>
8 #include <linux/export.h>
9 #include <linux/nodemask.h>
10 #include <linux/cpumask.h>
11 #include <linux/notifier.h>
13 #include <asm/current.h>
14 #include <asm/processor.h>
15 #include <asm/cputable.h>
16 #include <asm/hvcall.h>
18 #include <asm/machdep.h>
21 #include <asm/firmware.h>
23 #include "cacheinfo.h"
28 #include <asm/lppaca.h>
31 static DEFINE_PER_CPU(struct cpu, cpu_devices);
34 * SMT snooze delay stuff, 64-bit only for now
39 /* Time in microseconds we delay before sleeping in the idle loop */
40 static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
42 static ssize_t store_smt_snooze_delay(struct device *dev,
43 struct device_attribute *attr,
47 struct cpu *cpu = container_of(dev, struct cpu, dev);
51 ret = sscanf(buf, "%ld", &snooze);
55 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
59 static ssize_t show_smt_snooze_delay(struct device *dev,
60 struct device_attribute *attr,
63 struct cpu *cpu = container_of(dev, struct cpu, dev);
65 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
68 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
69 store_smt_snooze_delay);
71 static int __init setup_smt_snooze_delay(char *str)
76 if (!cpu_has_feature(CPU_FTR_SMT))
79 snooze = simple_strtol(str, NULL, 10);
80 for_each_possible_cpu(cpu)
81 per_cpu(smt_snooze_delay, cpu) = snooze;
85 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
87 #endif /* CONFIG_PPC64 */
89 #ifdef CONFIG_PPC_FSL_BOOK3E
93 static u64 altivec_idle_wt;
95 static unsigned int get_idle_ticks_bit(u64 ns)
100 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
102 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
110 static void do_show_pwrmgtcr0(void *val)
114 *value = mfspr(SPRN_PWRMGTCR0);
117 static ssize_t show_pw20_state(struct device *dev,
118 struct device_attribute *attr, char *buf)
121 unsigned int cpu = dev->id;
123 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
125 value &= PWRMGTCR0_PW20_WAIT;
127 return sprintf(buf, "%u\n", value ? 1 : 0);
130 static void do_store_pw20_state(void *val)
135 pw20_state = mfspr(SPRN_PWRMGTCR0);
138 pw20_state |= PWRMGTCR0_PW20_WAIT;
140 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
142 mtspr(SPRN_PWRMGTCR0, pw20_state);
145 static ssize_t store_pw20_state(struct device *dev,
146 struct device_attribute *attr,
147 const char *buf, size_t count)
150 unsigned int cpu = dev->id;
152 if (kstrtou32(buf, 0, &value))
158 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
163 static ssize_t show_pw20_wait_time(struct device *dev,
164 struct device_attribute *attr, char *buf)
170 unsigned int cpu = dev->id;
173 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
174 value = (value & PWRMGTCR0_PW20_ENT) >>
175 PWRMGTCR0_PW20_ENT_SHIFT;
177 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
178 /* convert ms to ns */
179 if (tb_ticks_per_usec > 1000) {
180 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
184 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
186 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
192 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
195 static void set_pw20_wait_entry_bit(void *val)
200 pw20_idle = mfspr(SPRN_PWRMGTCR0);
202 /* Set Automatic PW20 Core Idle Count */
204 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
207 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
209 mtspr(SPRN_PWRMGTCR0, pw20_idle);
212 static ssize_t store_pw20_wait_time(struct device *dev,
213 struct device_attribute *attr,
214 const char *buf, size_t count)
219 unsigned int cpu = dev->id;
221 if (kstrtou64(buf, 0, &value))
227 entry_bit = get_idle_ticks_bit(value);
228 if (entry_bit > MAX_BIT)
233 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
239 static ssize_t show_altivec_idle(struct device *dev,
240 struct device_attribute *attr, char *buf)
243 unsigned int cpu = dev->id;
245 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
247 value &= PWRMGTCR0_AV_IDLE_PD_EN;
249 return sprintf(buf, "%u\n", value ? 1 : 0);
252 static void do_store_altivec_idle(void *val)
257 altivec_idle = mfspr(SPRN_PWRMGTCR0);
260 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
262 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
264 mtspr(SPRN_PWRMGTCR0, altivec_idle);
267 static ssize_t store_altivec_idle(struct device *dev,
268 struct device_attribute *attr,
269 const char *buf, size_t count)
272 unsigned int cpu = dev->id;
274 if (kstrtou32(buf, 0, &value))
280 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
285 static ssize_t show_altivec_idle_wait_time(struct device *dev,
286 struct device_attribute *attr, char *buf)
292 unsigned int cpu = dev->id;
294 if (!altivec_idle_wt) {
295 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
296 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
297 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
299 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
300 /* convert ms to ns */
301 if (tb_ticks_per_usec > 1000) {
302 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
306 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
308 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
311 time = altivec_idle_wt;
314 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
317 static void set_altivec_idle_wait_entry_bit(void *val)
322 altivec_idle = mfspr(SPRN_PWRMGTCR0);
324 /* Set Automatic AltiVec Idle Count */
326 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
329 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
331 mtspr(SPRN_PWRMGTCR0, altivec_idle);
334 static ssize_t store_altivec_idle_wait_time(struct device *dev,
335 struct device_attribute *attr,
336 const char *buf, size_t count)
341 unsigned int cpu = dev->id;
343 if (kstrtou64(buf, 0, &value))
349 entry_bit = get_idle_ticks_bit(value);
350 if (entry_bit > MAX_BIT)
353 altivec_idle_wt = value;
355 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
362 * Enable/Disable interface:
363 * 0, disable. 1, enable.
365 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
366 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
369 * Set wait time interface:(Nanosecond)
370 * Example: Base on TBfreq is 41MHZ.
374 * 196~390(ns): TB[60]
375 * 391~780(ns): TB[59]
376 * 781~1560(ns): TB[58]
379 static DEVICE_ATTR(pw20_wait_time, 0600,
381 store_pw20_wait_time);
382 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
383 show_altivec_idle_wait_time,
384 store_altivec_idle_wait_time);
388 * Enabling PMCs will slow partition context switch times so we only do
389 * it the first time we write to the PMCs.
392 static DEFINE_PER_CPU(char, pmcs_enabled);
394 void ppc_enable_pmcs(void)
396 ppc_set_pmu_inuse(1);
398 /* Only need to enable them once */
399 if (__this_cpu_read(pmcs_enabled))
402 __this_cpu_write(pmcs_enabled, 1);
404 if (ppc_md.enable_pmcs)
405 ppc_md.enable_pmcs();
407 EXPORT_SYMBOL(ppc_enable_pmcs);
409 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
410 static void read_##NAME(void *val) \
412 *(unsigned long *)val = mfspr(ADDRESS); \
414 static void write_##NAME(void *val) \
417 mtspr(ADDRESS, *(unsigned long *)val); \
420 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
421 static ssize_t show_##NAME(struct device *dev, \
422 struct device_attribute *attr, \
425 struct cpu *cpu = container_of(dev, struct cpu, dev); \
427 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
428 return sprintf(buf, "%lx\n", val); \
430 static ssize_t __used \
431 store_##NAME(struct device *dev, struct device_attribute *attr, \
432 const char *buf, size_t count) \
434 struct cpu *cpu = container_of(dev, struct cpu, dev); \
436 int ret = sscanf(buf, "%lx", &val); \
439 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
443 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
444 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
445 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
446 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
447 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
448 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
450 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
451 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
453 /* Let's define all possible registers, we'll only hook up the ones
454 * that are implemented on the current processor
457 #if defined(CONFIG_PPC64)
458 #define HAS_PPC_PMC_CLASSIC 1
459 #define HAS_PPC_PMC_IBM 1
460 #define HAS_PPC_PMC_PA6T 1
461 #elif defined(CONFIG_PPC_BOOK3S_32)
462 #define HAS_PPC_PMC_CLASSIC 1
463 #define HAS_PPC_PMC_IBM 1
464 #define HAS_PPC_PMC_G4 1
468 #ifdef HAS_PPC_PMC_CLASSIC
469 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
470 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
471 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
472 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
473 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
474 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
475 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
476 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
478 #ifdef HAS_PPC_PMC_G4
479 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
483 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
484 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
486 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
487 SYSFS_SPRSETUP(purr, SPRN_PURR);
488 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
489 SYSFS_SPRSETUP(pir, SPRN_PIR);
490 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
493 Lets only enable read for phyp resources and
494 enable write when needed with a separate function.
495 Lets be conservative and default to pseries.
497 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
498 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
499 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
500 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
501 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
504 * This is the system wide DSCR register default value. Any
505 * change to this default value through the sysfs interface
506 * will update all per cpu DSCR default values across the
507 * system stored in their respective PACA structures.
509 static unsigned long dscr_default;
512 * read_dscr() - Fetch the cpu specific DSCR default
513 * @val: Returned cpu specific DSCR default value
515 * This function returns the per cpu DSCR default value
516 * for any cpu which is contained in it's PACA structure.
518 static void read_dscr(void *val)
520 *(unsigned long *)val = get_paca()->dscr_default;
525 * write_dscr() - Update the cpu specific DSCR default
526 * @val: New cpu specific DSCR default value to update
528 * This function updates the per cpu DSCR default value
529 * for any cpu which is contained in it's PACA structure.
531 static void write_dscr(void *val)
533 get_paca()->dscr_default = *(unsigned long *)val;
534 if (!current->thread.dscr_inherit) {
535 current->thread.dscr = *(unsigned long *)val;
536 mtspr(SPRN_DSCR, *(unsigned long *)val);
540 SYSFS_SPRSETUP_SHOW_STORE(dscr);
541 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
543 static void add_write_permission_dev_attr(struct device_attribute *attr)
545 attr->attr.mode |= 0200;
549 * show_dscr_default() - Fetch the system wide DSCR default
550 * @dev: Device structure
551 * @attr: Device attribute structure
552 * @buf: Interface buffer
554 * This function returns the system wide DSCR default value.
556 static ssize_t show_dscr_default(struct device *dev,
557 struct device_attribute *attr, char *buf)
559 return sprintf(buf, "%lx\n", dscr_default);
563 * store_dscr_default() - Update the system wide DSCR default
564 * @dev: Device structure
565 * @attr: Device attribute structure
566 * @buf: Interface buffer
567 * @count: Size of the update
569 * This function updates the system wide DSCR default value.
571 static ssize_t __used store_dscr_default(struct device *dev,
572 struct device_attribute *attr, const char *buf,
578 ret = sscanf(buf, "%lx", &val);
583 on_each_cpu(write_dscr, &val, 1);
588 static DEVICE_ATTR(dscr_default, 0600,
589 show_dscr_default, store_dscr_default);
591 static void sysfs_create_dscr_default(void)
593 if (cpu_has_feature(CPU_FTR_DSCR)) {
597 dscr_default = spr_default_dscr;
598 for_each_possible_cpu(cpu)
599 paca_ptrs[cpu]->dscr_default = dscr_default;
601 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
605 #endif /* CONFIG_PPC64 */
607 #ifdef HAS_PPC_PMC_PA6T
608 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
609 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
610 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
611 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
612 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
613 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
614 #ifdef CONFIG_DEBUG_MISC
615 SYSFS_SPRSETUP(hid0, SPRN_HID0);
616 SYSFS_SPRSETUP(hid1, SPRN_HID1);
617 SYSFS_SPRSETUP(hid4, SPRN_HID4);
618 SYSFS_SPRSETUP(hid5, SPRN_HID5);
619 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
620 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
621 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
622 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
623 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
624 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
625 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
626 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
627 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
628 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
629 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
630 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
631 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
632 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
633 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
634 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
635 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
636 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
637 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
638 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
639 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
640 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
641 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
642 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
643 #endif /* CONFIG_DEBUG_MISC */
644 #endif /* HAS_PPC_PMC_PA6T */
646 #ifdef HAS_PPC_PMC_IBM
647 static struct device_attribute ibm_common_attrs[] = {
648 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
649 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
651 #endif /* HAS_PPC_PMC_G4 */
653 #ifdef HAS_PPC_PMC_G4
654 static struct device_attribute g4_common_attrs[] = {
655 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
656 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
657 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
659 #endif /* HAS_PPC_PMC_G4 */
661 static struct device_attribute classic_pmc_attrs[] = {
662 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
663 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
664 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
665 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
666 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
667 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
669 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
670 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
674 #ifdef HAS_PPC_PMC_PA6T
675 static struct device_attribute pa6t_attrs[] = {
676 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
677 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
678 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
679 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
680 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
681 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
682 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
683 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
684 #ifdef CONFIG_DEBUG_MISC
685 __ATTR(hid0, 0600, show_hid0, store_hid0),
686 __ATTR(hid1, 0600, show_hid1, store_hid1),
687 __ATTR(hid4, 0600, show_hid4, store_hid4),
688 __ATTR(hid5, 0600, show_hid5, store_hid5),
689 __ATTR(ima0, 0600, show_ima0, store_ima0),
690 __ATTR(ima1, 0600, show_ima1, store_ima1),
691 __ATTR(ima2, 0600, show_ima2, store_ima2),
692 __ATTR(ima3, 0600, show_ima3, store_ima3),
693 __ATTR(ima4, 0600, show_ima4, store_ima4),
694 __ATTR(ima5, 0600, show_ima5, store_ima5),
695 __ATTR(ima6, 0600, show_ima6, store_ima6),
696 __ATTR(ima7, 0600, show_ima7, store_ima7),
697 __ATTR(ima8, 0600, show_ima8, store_ima8),
698 __ATTR(ima9, 0600, show_ima9, store_ima9),
699 __ATTR(imaat, 0600, show_imaat, store_imaat),
700 __ATTR(btcr, 0600, show_btcr, store_btcr),
701 __ATTR(pccr, 0600, show_pccr, store_pccr),
702 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
703 __ATTR(der, 0600, show_der, store_der),
704 __ATTR(mer, 0600, show_mer, store_mer),
705 __ATTR(ber, 0600, show_ber, store_ber),
706 __ATTR(ier, 0600, show_ier, store_ier),
707 __ATTR(sier, 0600, show_sier, store_sier),
708 __ATTR(siar, 0600, show_siar, store_siar),
709 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
710 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
711 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
712 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
713 #endif /* CONFIG_DEBUG_MISC */
715 #endif /* HAS_PPC_PMC_PA6T */
716 #endif /* HAS_PPC_PMC_CLASSIC */
718 static int register_cpu_online(unsigned int cpu)
720 struct cpu *c = &per_cpu(cpu_devices, cpu);
721 struct device *s = &c->dev;
722 struct device_attribute *attrs, *pmc_attrs;
725 /* For cpus present at boot a reference was already grabbed in register_cpu() */
727 s->of_node = of_get_cpu_node(cpu, NULL);
730 if (cpu_has_feature(CPU_FTR_SMT))
731 device_create_file(s, &dev_attr_smt_snooze_delay);
735 switch (cur_cpu_spec->pmc_type) {
736 #ifdef HAS_PPC_PMC_IBM
738 attrs = ibm_common_attrs;
739 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
740 pmc_attrs = classic_pmc_attrs;
742 #endif /* HAS_PPC_PMC_IBM */
743 #ifdef HAS_PPC_PMC_G4
745 attrs = g4_common_attrs;
746 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
747 pmc_attrs = classic_pmc_attrs;
749 #endif /* HAS_PPC_PMC_G4 */
750 #ifdef HAS_PPC_PMC_PA6T
752 /* PA Semi starts counting at PMC0 */
754 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
757 #endif /* HAS_PPC_PMC_PA6T */
764 for (i = 0; i < nattrs; i++)
765 device_create_file(s, &attrs[i]);
768 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
769 device_create_file(s, &pmc_attrs[i]);
772 if (cpu_has_feature(CPU_FTR_MMCRA))
773 device_create_file(s, &dev_attr_mmcra);
775 if (cpu_has_feature(CPU_FTR_PURR)) {
776 if (!firmware_has_feature(FW_FEATURE_LPAR))
777 add_write_permission_dev_attr(&dev_attr_purr);
778 device_create_file(s, &dev_attr_purr);
781 if (cpu_has_feature(CPU_FTR_SPURR))
782 device_create_file(s, &dev_attr_spurr);
784 if (cpu_has_feature(CPU_FTR_DSCR))
785 device_create_file(s, &dev_attr_dscr);
787 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
788 device_create_file(s, &dev_attr_pir);
790 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
791 !firmware_has_feature(FW_FEATURE_LPAR))
792 device_create_file(s, &dev_attr_tscr);
793 #endif /* CONFIG_PPC64 */
795 #ifdef CONFIG_PPC_FSL_BOOK3E
796 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
797 device_create_file(s, &dev_attr_pw20_state);
798 device_create_file(s, &dev_attr_pw20_wait_time);
800 device_create_file(s, &dev_attr_altivec_idle);
801 device_create_file(s, &dev_attr_altivec_idle_wait_time);
804 cacheinfo_cpu_online(cpu);
808 #ifdef CONFIG_HOTPLUG_CPU
809 static int unregister_cpu_online(unsigned int cpu)
811 struct cpu *c = &per_cpu(cpu_devices, cpu);
812 struct device *s = &c->dev;
813 struct device_attribute *attrs, *pmc_attrs;
816 BUG_ON(!c->hotpluggable);
819 if (cpu_has_feature(CPU_FTR_SMT))
820 device_remove_file(s, &dev_attr_smt_snooze_delay);
824 switch (cur_cpu_spec->pmc_type) {
825 #ifdef HAS_PPC_PMC_IBM
827 attrs = ibm_common_attrs;
828 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
829 pmc_attrs = classic_pmc_attrs;
831 #endif /* HAS_PPC_PMC_IBM */
832 #ifdef HAS_PPC_PMC_G4
834 attrs = g4_common_attrs;
835 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
836 pmc_attrs = classic_pmc_attrs;
838 #endif /* HAS_PPC_PMC_G4 */
839 #ifdef HAS_PPC_PMC_PA6T
841 /* PA Semi starts counting at PMC0 */
843 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
846 #endif /* HAS_PPC_PMC_PA6T */
853 for (i = 0; i < nattrs; i++)
854 device_remove_file(s, &attrs[i]);
857 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
858 device_remove_file(s, &pmc_attrs[i]);
861 if (cpu_has_feature(CPU_FTR_MMCRA))
862 device_remove_file(s, &dev_attr_mmcra);
864 if (cpu_has_feature(CPU_FTR_PURR))
865 device_remove_file(s, &dev_attr_purr);
867 if (cpu_has_feature(CPU_FTR_SPURR))
868 device_remove_file(s, &dev_attr_spurr);
870 if (cpu_has_feature(CPU_FTR_DSCR))
871 device_remove_file(s, &dev_attr_dscr);
873 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
874 device_remove_file(s, &dev_attr_pir);
876 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
877 !firmware_has_feature(FW_FEATURE_LPAR))
878 device_remove_file(s, &dev_attr_tscr);
879 #endif /* CONFIG_PPC64 */
881 #ifdef CONFIG_PPC_FSL_BOOK3E
882 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
883 device_remove_file(s, &dev_attr_pw20_state);
884 device_remove_file(s, &dev_attr_pw20_wait_time);
886 device_remove_file(s, &dev_attr_altivec_idle);
887 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
890 cacheinfo_cpu_offline(cpu);
891 of_node_put(s->of_node);
895 #else /* !CONFIG_HOTPLUG_CPU */
896 #define unregister_cpu_online NULL
899 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
900 ssize_t arch_cpu_probe(const char *buf, size_t count)
902 if (ppc_md.cpu_probe)
903 return ppc_md.cpu_probe(buf, count);
908 ssize_t arch_cpu_release(const char *buf, size_t count)
910 if (ppc_md.cpu_release)
911 return ppc_md.cpu_release(buf, count);
915 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
917 static DEFINE_MUTEX(cpu_mutex);
919 int cpu_add_dev_attr(struct device_attribute *attr)
923 mutex_lock(&cpu_mutex);
925 for_each_possible_cpu(cpu) {
926 device_create_file(get_cpu_device(cpu), attr);
929 mutex_unlock(&cpu_mutex);
932 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
934 int cpu_add_dev_attr_group(struct attribute_group *attrs)
940 mutex_lock(&cpu_mutex);
942 for_each_possible_cpu(cpu) {
943 dev = get_cpu_device(cpu);
944 ret = sysfs_create_group(&dev->kobj, attrs);
948 mutex_unlock(&cpu_mutex);
951 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
954 void cpu_remove_dev_attr(struct device_attribute *attr)
958 mutex_lock(&cpu_mutex);
960 for_each_possible_cpu(cpu) {
961 device_remove_file(get_cpu_device(cpu), attr);
964 mutex_unlock(&cpu_mutex);
966 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
968 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
973 mutex_lock(&cpu_mutex);
975 for_each_possible_cpu(cpu) {
976 dev = get_cpu_device(cpu);
977 sysfs_remove_group(&dev->kobj, attrs);
980 mutex_unlock(&cpu_mutex);
982 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
988 static void register_nodes(void)
992 for (i = 0; i < MAX_NUMNODES; i++)
993 register_one_node(i);
996 int sysfs_add_device_to_node(struct device *dev, int nid)
998 struct node *node = node_devices[nid];
999 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1000 kobject_name(&dev->kobj));
1002 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1004 void sysfs_remove_device_from_node(struct device *dev, int nid)
1006 struct node *node = node_devices[nid];
1007 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1009 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1012 static void register_nodes(void)
1019 /* Only valid if CPU is present. */
1020 static ssize_t show_physical_id(struct device *dev,
1021 struct device_attribute *attr, char *buf)
1023 struct cpu *cpu = container_of(dev, struct cpu, dev);
1025 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1027 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1029 static int __init topology_init(void)
1035 for_each_possible_cpu(cpu) {
1036 struct cpu *c = &per_cpu(cpu_devices, cpu);
1039 * For now, we just see if the system supports making
1040 * the RTAS calls for CPU hotplug. But, there may be a
1041 * more comprehensive way to do this for an individual
1042 * CPU. For instance, the boot cpu might never be valid
1046 c->hotpluggable = 1;
1048 if (cpu_online(cpu) || c->hotpluggable) {
1049 register_cpu(c, cpu);
1051 device_create_file(&c->dev, &dev_attr_physical_id);
1054 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1055 register_cpu_online, unregister_cpu_online);
1058 sysfs_create_dscr_default();
1059 #endif /* CONFIG_PPC64 */
1063 subsys_initcall(topology_init);