arch/powerpc/kernel/sysfs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 #include <linux/device.h>
   3 #include <linux/cpu.h>
   4 #include <linux/smp.h>
   5 #include <linux/percpu.h>
   6 #include <linux/init.h>
   7 #include <linux/sched.h>
   8 #include <linux/export.h>
   9 #include <linux/nodemask.h>
  10 #include <linux/cpumask.h>
  11 #include <linux/notifier.h>
  12
  13 #include <asm/current.h>
  14 #include <asm/processor.h>
  15 #include <asm/cputable.h>
  16 #include <asm/hvcall.h>
  17 #include <asm/prom.h>
  18 #include <asm/machdep.h>
  19 #include <asm/smp.h>
  20 #include <asm/pmc.h>
  21 #include <asm/firmware.h>
  22 #include <asm/idle.h>
  23 #include <asm/svm.h>
  24
  25 #include "cacheinfo.h"
  26 #include "setup.h"
  27
  28 #ifdef CONFIG_PPC64
  29 #include <asm/paca.h>
  30 #include <asm/lppaca.h>
  31 #endif
  32
  33 static DEFINE_PER_CPU(struct cpu, cpu_devices);
  34
  35 /*
  36  * SMT snooze delay stuff, 64-bit only for now
  37  */
  38
  39 #ifdef CONFIG_PPC64
  40
  41 /* Time in microseconds we delay before sleeping in the idle loop */
  42 static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
  43
  44 static ssize_t store_smt_snooze_delay(struct device *dev,
  45                                       struct device_attribute *attr,
  46                                       const char *buf,
  47                                       size_t count)
  48 {
  49         struct cpu *cpu = container_of(dev, struct cpu, dev);
  50         ssize_t ret;
  51         long snooze;
  52
  53         ret = sscanf(buf, "%ld", &snooze);
  54         if (ret != 1)
  55                 return -EINVAL;
  56
  57         per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
  58         return count;
  59 }
  60
  61 static ssize_t show_smt_snooze_delay(struct device *dev,
  62                                      struct device_attribute *attr,
  63                                      char *buf)
  64 {
  65         struct cpu *cpu = container_of(dev, struct cpu, dev);
  66
  67         return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
  68 }
  69
  70 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  71                    store_smt_snooze_delay);
  72
  73 static int __init setup_smt_snooze_delay(char *str)
  74 {
  75         unsigned int cpu;
  76         long snooze;
  77
  78         if (!cpu_has_feature(CPU_FTR_SMT))
  79                 return 1;
  80
  81         snooze = simple_strtol(str, NULL, 10);
  82         for_each_possible_cpu(cpu)
  83                 per_cpu(smt_snooze_delay, cpu) = snooze;
  84
  85         return 1;
  86 }
  87 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
  88
  89 #endif /* CONFIG_PPC64 */
  90
  91 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
  92 static void read_##NAME(void *val) \
  93 { \
  94         *(unsigned long *)val = mfspr(ADDRESS); \
  95 } \
  96 static void write_##NAME(void *val) \
  97 { \
  98         EXTRA; \
  99         mtspr(ADDRESS, *(unsigned long *)val);  \
 100 }
 101
 102 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 103 static ssize_t show_##NAME(struct device *dev, \
 104                         struct device_attribute *attr, \
 105                         char *buf) \
 106 { \
 107         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 108         unsigned long val; \
 109         smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 110         return sprintf(buf, "%lx\n", val); \
 111 } \
 112 static ssize_t __used \
 113         store_##NAME(struct device *dev, struct device_attribute *attr, \
 114                         const char *buf, size_t count) \
 115 { \
 116         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 117         unsigned long val; \
 118         int ret = sscanf(buf, "%lx", &val); \
 119         if (ret != 1) \
 120                 return -EINVAL; \
 121         smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 122         return count; \
 123 }
 124
 125 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
 126         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 127         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 128 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
 129         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 130         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 131
 132 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 133         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 134
 135 #ifdef CONFIG_PPC64
 136
 137 /*
 138  * This is the system wide DSCR register default value. Any
 139  * change to this default value through the sysfs interface
 140  * will update all per cpu DSCR default values across the
 141  * system stored in their respective PACA structures.
 142  */
 143 static unsigned long dscr_default;
 144
 145 /**
 146  * read_dscr() - Fetch the cpu specific DSCR default
 147  * @val:        Returned cpu specific DSCR default value
 148  *
 149  * This function returns the per cpu DSCR default value
 150  * for any cpu which is contained in it's PACA structure.
 151  */
 152 static void read_dscr(void *val)
 153 {
 154         *(unsigned long *)val = get_paca()->dscr_default;
 155 }
 156
 157
 158 /**
 159  * write_dscr() - Update the cpu specific DSCR default
 160  * @val:        New cpu specific DSCR default value to update
 161  *
 162  * This function updates the per cpu DSCR default value
 163  * for any cpu which is contained in it's PACA structure.
 164  */
 165 static void write_dscr(void *val)
 166 {
 167         get_paca()->dscr_default = *(unsigned long *)val;
 168         if (!current->thread.dscr_inherit) {
 169                 current->thread.dscr = *(unsigned long *)val;
 170                 mtspr(SPRN_DSCR, *(unsigned long *)val);
 171         }
 172 }
 173
 174 SYSFS_SPRSETUP_SHOW_STORE(dscr);
 175 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 176
 177 static void add_write_permission_dev_attr(struct device_attribute *attr)
 178 {
 179         attr->attr.mode |= 0200;
 180 }
 181
 182 /**
 183  * show_dscr_default() - Fetch the system wide DSCR default
 184  * @dev:        Device structure
 185  * @attr:       Device attribute structure
 186  * @buf:        Interface buffer
 187  *
 188  * This function returns the system wide DSCR default value.
 189  */
 190 static ssize_t show_dscr_default(struct device *dev,
 191                 struct device_attribute *attr, char *buf)
 192 {
 193         return sprintf(buf, "%lx\n", dscr_default);
 194 }
 195
 196 /**
 197  * store_dscr_default() - Update the system wide DSCR default
 198  * @dev:        Device structure
 199  * @attr:       Device attribute structure
 200  * @buf:        Interface buffer
 201  * @count:      Size of the update
 202  *
 203  * This function updates the system wide DSCR default value.
 204  */
 205 static ssize_t __used store_dscr_default(struct device *dev,
 206                 struct device_attribute *attr, const char *buf,
 207                 size_t count)
 208 {
 209         unsigned long val;
 210         int ret = 0;
 211
 212         ret = sscanf(buf, "%lx", &val);
 213         if (ret != 1)
 214                 return -EINVAL;
 215         dscr_default = val;
 216
 217         on_each_cpu(write_dscr, &val, 1);
 218
 219         return count;
 220 }
 221
 222 static DEVICE_ATTR(dscr_default, 0600,
 223                 show_dscr_default, store_dscr_default);
 224
 225 static void sysfs_create_dscr_default(void)
 226 {
 227         if (cpu_has_feature(CPU_FTR_DSCR)) {
 228                 int err = 0;
 229                 int cpu;
 230
 231                 dscr_default = spr_default_dscr;
 232                 for_each_possible_cpu(cpu)
 233                         paca_ptrs[cpu]->dscr_default = dscr_default;
 234
 235                 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
 236         }
 237 }
 238 #endif /* CONFIG_PPC64 */
 239
 240 #ifdef CONFIG_PPC_FSL_BOOK3E
 241 #define MAX_BIT                         63
 242
 243 static u64 pw20_wt;
 244 static u64 altivec_idle_wt;
 245
 246 static unsigned int get_idle_ticks_bit(u64 ns)
 247 {
 248         u64 cycle;
 249
 250         if (ns >= 10000)
 251                 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
 252         else
 253                 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
 254
 255         if (!cycle)
 256                 return 0;
 257
 258         return ilog2(cycle);
 259 }
 260
 261 static void do_show_pwrmgtcr0(void *val)
 262 {
 263         u32 *value = val;
 264
 265         *value = mfspr(SPRN_PWRMGTCR0);
 266 }
 267
 268 static ssize_t show_pw20_state(struct device *dev,
 269                                 struct device_attribute *attr, char *buf)
 270 {
 271         u32 value;
 272         unsigned int cpu = dev->id;
 273
 274         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 275
 276         value &= PWRMGTCR0_PW20_WAIT;
 277
 278         return sprintf(buf, "%u\n", value ? 1 : 0);
 279 }
 280
 281 static void do_store_pw20_state(void *val)
 282 {
 283         u32 *value = val;
 284         u32 pw20_state;
 285
 286         pw20_state = mfspr(SPRN_PWRMGTCR0);
 287
 288         if (*value)
 289                 pw20_state |= PWRMGTCR0_PW20_WAIT;
 290         else
 291                 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 292
 293         mtspr(SPRN_PWRMGTCR0, pw20_state);
 294 }
 295
 296 static ssize_t store_pw20_state(struct device *dev,
 297                                 struct device_attribute *attr,
 298                                 const char *buf, size_t count)
 299 {
 300         u32 value;
 301         unsigned int cpu = dev->id;
 302
 303         if (kstrtou32(buf, 0, &value))
 304                 return -EINVAL;
 305
 306         if (value > 1)
 307                 return -EINVAL;
 308
 309         smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 310
 311         return count;
 312 }
 313
 314 static ssize_t show_pw20_wait_time(struct device *dev,
 315                                 struct device_attribute *attr, char *buf)
 316 {
 317         u32 value;
 318         u64 tb_cycle = 1;
 319         u64 time;
 320
 321         unsigned int cpu = dev->id;
 322
 323         if (!pw20_wt) {
 324                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 325                 value = (value & PWRMGTCR0_PW20_ENT) >>
 326                                         PWRMGTCR0_PW20_ENT_SHIFT;
 327
 328                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 329                 /* convert ms to ns */
 330                 if (tb_ticks_per_usec > 1000) {
 331                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 332                 } else {
 333                         u32 rem_us;
 334
 335                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 336                                                 &rem_us);
 337                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 338                 }
 339         } else {
 340                 time = pw20_wt;
 341         }
 342
 343         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 344 }
 345
 346 static void set_pw20_wait_entry_bit(void *val)
 347 {
 348         u32 *value = val;
 349         u32 pw20_idle;
 350
 351         pw20_idle = mfspr(SPRN_PWRMGTCR0);
 352
 353         /* Set Automatic PW20 Core Idle Count */
 354         /* clear count */
 355         pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 356
 357         /* set count */
 358         pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 359
 360         mtspr(SPRN_PWRMGTCR0, pw20_idle);
 361 }
 362
 363 static ssize_t store_pw20_wait_time(struct device *dev,
 364                                 struct device_attribute *attr,
 365                                 const char *buf, size_t count)
 366 {
 367         u32 entry_bit;
 368         u64 value;
 369
 370         unsigned int cpu = dev->id;
 371
 372         if (kstrtou64(buf, 0, &value))
 373                 return -EINVAL;
 374
 375         if (!value)
 376                 return -EINVAL;
 377
 378         entry_bit = get_idle_ticks_bit(value);
 379         if (entry_bit > MAX_BIT)
 380                 return -EINVAL;
 381
 382         pw20_wt = value;
 383
 384         smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 385                                 &entry_bit, 1);
 386
 387         return count;
 388 }
 389
 390 static ssize_t show_altivec_idle(struct device *dev,
 391                                 struct device_attribute *attr, char *buf)
 392 {
 393         u32 value;
 394         unsigned int cpu = dev->id;
 395
 396         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 397
 398         value &= PWRMGTCR0_AV_IDLE_PD_EN;
 399
 400         return sprintf(buf, "%u\n", value ? 1 : 0);
 401 }
 402
 403 static void do_store_altivec_idle(void *val)
 404 {
 405         u32 *value = val;
 406         u32 altivec_idle;
 407
 408         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 409
 410         if (*value)
 411                 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 412         else
 413                 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 414
 415         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 416 }
 417
 418 static ssize_t store_altivec_idle(struct device *dev,
 419                                 struct device_attribute *attr,
 420                                 const char *buf, size_t count)
 421 {
 422         u32 value;
 423         unsigned int cpu = dev->id;
 424
 425         if (kstrtou32(buf, 0, &value))
 426                 return -EINVAL;
 427
 428         if (value > 1)
 429                 return -EINVAL;
 430
 431         smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 432
 433         return count;
 434 }
 435
 436 static ssize_t show_altivec_idle_wait_time(struct device *dev,
 437                                 struct device_attribute *attr, char *buf)
 438 {
 439         u32 value;
 440         u64 tb_cycle = 1;
 441         u64 time;
 442
 443         unsigned int cpu = dev->id;
 444
 445         if (!altivec_idle_wt) {
 446                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 447                 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 448                                         PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 449
 450                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 451                 /* convert ms to ns */
 452                 if (tb_ticks_per_usec > 1000) {
 453                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 454                 } else {
 455                         u32 rem_us;
 456
 457                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 458                                                 &rem_us);
 459                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 460                 }
 461         } else {
 462                 time = altivec_idle_wt;
 463         }
 464
 465         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 466 }
 467
 468 static void set_altivec_idle_wait_entry_bit(void *val)
 469 {
 470         u32 *value = val;
 471         u32 altivec_idle;
 472
 473         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 474
 475         /* Set Automatic AltiVec Idle Count */
 476         /* clear count */
 477         altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 478
 479         /* set count */
 480         altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 481
 482         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 483 }
 484
 485 static ssize_t store_altivec_idle_wait_time(struct device *dev,
 486                                 struct device_attribute *attr,
 487                                 const char *buf, size_t count)
 488 {
 489         u32 entry_bit;
 490         u64 value;
 491
 492         unsigned int cpu = dev->id;
 493
 494         if (kstrtou64(buf, 0, &value))
 495                 return -EINVAL;
 496
 497         if (!value)
 498                 return -EINVAL;
 499
 500         entry_bit = get_idle_ticks_bit(value);
 501         if (entry_bit > MAX_BIT)
 502                 return -EINVAL;
 503
 504         altivec_idle_wt = value;
 505
 506         smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 507                                 &entry_bit, 1);
 508
 509         return count;
 510 }
 511
 512 /*
 513  * Enable/Disable interface:
 514  * 0, disable. 1, enable.
 515  */
 516 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 517 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 518
 519 /*
 520  * Set wait time interface:(Nanosecond)
 521  * Example: Base on TBfreq is 41MHZ.
 522  * 1~48(ns): TB[63]
 523  * 49~97(ns): TB[62]
 524  * 98~195(ns): TB[61]
 525  * 196~390(ns): TB[60]
 526  * 391~780(ns): TB[59]
 527  * 781~1560(ns): TB[58]
 528  * ...
 529  */
 530 static DEVICE_ATTR(pw20_wait_time, 0600,
 531                         show_pw20_wait_time,
 532                         store_pw20_wait_time);
 533 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 534                         show_altivec_idle_wait_time,
 535                         store_altivec_idle_wait_time);
 536 #endif
 537
 538 /*
 539  * Enabling PMCs will slow partition context switch times so we only do
 540  * it the first time we write to the PMCs.
 541  */
 542
 543 static DEFINE_PER_CPU(char, pmcs_enabled);
 544
 545 void ppc_enable_pmcs(void)
 546 {
 547         ppc_set_pmu_inuse(1);
 548
 549         /* Only need to enable them once */
 550         if (__this_cpu_read(pmcs_enabled))
 551                 return;
 552
 553         __this_cpu_write(pmcs_enabled, 1);
 554
 555         if (ppc_md.enable_pmcs)
 556                 ppc_md.enable_pmcs();
 557 }
 558 EXPORT_SYMBOL(ppc_enable_pmcs);
 559
 560
 561
 562 /* Let's define all possible registers, we'll only hook up the ones
 563  * that are implemented on the current processor
 564  */
 565
 566 #ifdef CONFIG_PMU_SYSFS
 567 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
 568 #define HAS_PPC_PMC_CLASSIC     1
 569 #define HAS_PPC_PMC_IBM         1
 570 #endif
 571
 572 #ifdef CONFIG_PPC64
 573 #define HAS_PPC_PMC_PA6T        1
 574 #define HAS_PPC_PMC56          1
 575 #endif
 576
 577 #ifdef CONFIG_PPC_BOOK3S_32
 578 #define HAS_PPC_PMC_G4          1
 579 #endif
 580 #endif /* CONFIG_PMU_SYSFS */
 581
 582 #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC)
 583 #define HAS_PPC_PA6T
 584 #endif
 585 /*
 586  * SPRs which are not related to PMU.
 587  */
 588 #ifdef CONFIG_PPC64
 589 SYSFS_SPRSETUP(purr, SPRN_PURR);
 590 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 591 SYSFS_SPRSETUP(pir, SPRN_PIR);
 592 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
 593
 594 /*
 595   Lets only enable read for phyp resources and
 596   enable write when needed with a separate function.
 597   Lets be conservative and default to pseries.
 598 */
 599 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 600 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 601 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 602 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
 603 #endif /* CONFIG_PPC64 */
 604
 605 #ifdef HAS_PPC_PMC_CLASSIC
 606 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 607 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 608 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 609 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 610 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 611 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 612 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 613 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 614 #endif
 615
 616 #ifdef HAS_PPC_PMC_G4
 617 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 618 #endif
 619
 620 #ifdef HAS_PPC_PMC56
 621 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 622 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 623
 624 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 625
 626 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 627 #endif /* HAS_PPC_PMC56 */
 628
 629
 630
 631
 632 #ifdef HAS_PPC_PMC_PA6T
 633 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 634 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 635 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 636 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 637 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 638 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 639 #endif
 640
 641 #ifdef HAS_PPC_PA6T
 642 SYSFS_SPRSETUP(hid0, SPRN_HID0);
 643 SYSFS_SPRSETUP(hid1, SPRN_HID1);
 644 SYSFS_SPRSETUP(hid4, SPRN_HID4);
 645 SYSFS_SPRSETUP(hid5, SPRN_HID5);
 646 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 647 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 648 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 649 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 650 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 651 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 652 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 653 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 654 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 655 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 656 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 657 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 658 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 659 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 660 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 661 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 662 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 663 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 664 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 665 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 666 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 667 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 668 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 669 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 670 #endif /* HAS_PPC_PA6T */
 671
 672 #ifdef HAS_PPC_PMC_IBM
 673 static struct device_attribute ibm_common_attrs[] = {
 674         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 675         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 676 };
 677 #endif /* HAS_PPC_PMC_IBM */
 678
 679 #ifdef HAS_PPC_PMC_G4
 680 static struct device_attribute g4_common_attrs[] = {
 681         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 682         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 683         __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 684 };
 685 #endif /* HAS_PPC_PMC_G4 */
 686
 687 #ifdef HAS_PPC_PMC_CLASSIC
 688 static struct device_attribute classic_pmc_attrs[] = {
 689         __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 690         __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 691         __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 692         __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 693         __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 694         __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 695 #ifdef HAS_PPC_PMC56
 696         __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 697         __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 698 #endif
 699 };
 700 #endif
 701
 702 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
 703 static struct device_attribute pa6t_attrs[] = {
 704 #ifdef HAS_PPC_PMC_PA6T
 705         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 706         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 707         __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 708         __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 709         __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 710         __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 711         __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 712         __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 713 #endif
 714 #ifdef HAS_PPC_PA6T
 715         __ATTR(hid0, 0600, show_hid0, store_hid0),
 716         __ATTR(hid1, 0600, show_hid1, store_hid1),
 717         __ATTR(hid4, 0600, show_hid4, store_hid4),
 718         __ATTR(hid5, 0600, show_hid5, store_hid5),
 719         __ATTR(ima0, 0600, show_ima0, store_ima0),
 720         __ATTR(ima1, 0600, show_ima1, store_ima1),
 721         __ATTR(ima2, 0600, show_ima2, store_ima2),
 722         __ATTR(ima3, 0600, show_ima3, store_ima3),
 723         __ATTR(ima4, 0600, show_ima4, store_ima4),
 724         __ATTR(ima5, 0600, show_ima5, store_ima5),
 725         __ATTR(ima6, 0600, show_ima6, store_ima6),
 726         __ATTR(ima7, 0600, show_ima7, store_ima7),
 727         __ATTR(ima8, 0600, show_ima8, store_ima8),
 728         __ATTR(ima9, 0600, show_ima9, store_ima9),
 729         __ATTR(imaat, 0600, show_imaat, store_imaat),
 730         __ATTR(btcr, 0600, show_btcr, store_btcr),
 731         __ATTR(pccr, 0600, show_pccr, store_pccr),
 732         __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 733         __ATTR(der, 0600, show_der, store_der),
 734         __ATTR(mer, 0600, show_mer, store_mer),
 735         __ATTR(ber, 0600, show_ber, store_ber),
 736         __ATTR(ier, 0600, show_ier, store_ier),
 737         __ATTR(sier, 0600, show_sier, store_sier),
 738         __ATTR(siar, 0600, show_siar, store_siar),
 739         __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 740         __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 741         __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 742         __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 743 #endif /* HAS_PPC_PA6T */
 744 };
 745 #endif
 746
 747 #ifdef CONFIG_PPC_SVM
 748 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
 749 {
 750         return sprintf(buf, "%u\n", is_secure_guest());
 751 }
 752 static DEVICE_ATTR(svm, 0444, show_svm, NULL);
 753
 754 static void create_svm_file(void)
 755 {
 756         device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
 757 }
 758 #else
 759 static void create_svm_file(void)
 760 {
 761 }
 762 #endif /* CONFIG_PPC_SVM */
 763
 764 #ifdef CONFIG_PPC_PSERIES
 765 static void read_idle_purr(void *val)
 766 {
 767         u64 *ret = val;
 768
 769         *ret = read_this_idle_purr();
 770 }
 771
 772 static ssize_t idle_purr_show(struct device *dev,
 773                               struct device_attribute *attr, char *buf)
 774 {
 775         struct cpu *cpu = container_of(dev, struct cpu, dev);
 776         u64 val;
 777
 778         smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1);
 779         return sprintf(buf, "%llx\n", val);
 780 }
 781 static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL);
 782
 783 static void create_idle_purr_file(struct device *s)
 784 {
 785         if (firmware_has_feature(FW_FEATURE_LPAR))
 786                 device_create_file(s, &dev_attr_idle_purr);
 787 }
 788
 789 static void remove_idle_purr_file(struct device *s)
 790 {
 791         if (firmware_has_feature(FW_FEATURE_LPAR))
 792                 device_remove_file(s, &dev_attr_idle_purr);
 793 }
 794
 795 static void read_idle_spurr(void *val)
 796 {
 797         u64 *ret = val;
 798
 799         *ret = read_this_idle_spurr();
 800 }
 801
 802 static ssize_t idle_spurr_show(struct device *dev,
 803                                struct device_attribute *attr, char *buf)
 804 {
 805         struct cpu *cpu = container_of(dev, struct cpu, dev);
 806         u64 val;
 807
 808         smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1);
 809         return sprintf(buf, "%llx\n", val);
 810 }
 811 static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL);
 812
 813 static void create_idle_spurr_file(struct device *s)
 814 {
 815         if (firmware_has_feature(FW_FEATURE_LPAR))
 816                 device_create_file(s, &dev_attr_idle_spurr);
 817 }
 818
 819 static void remove_idle_spurr_file(struct device *s)
 820 {
 821         if (firmware_has_feature(FW_FEATURE_LPAR))
 822                 device_remove_file(s, &dev_attr_idle_spurr);
 823 }
 824
 825 #else /* CONFIG_PPC_PSERIES */
 826 #define create_idle_purr_file(s)
 827 #define remove_idle_purr_file(s)
 828 #define create_idle_spurr_file(s)
 829 #define remove_idle_spurr_file(s)
 830 #endif /* CONFIG_PPC_PSERIES */
 831
 832 static int register_cpu_online(unsigned int cpu)
 833 {
 834         struct cpu *c = &per_cpu(cpu_devices, cpu);
 835         struct device *s = &c->dev;
 836         struct device_attribute *attrs, *pmc_attrs;
 837         int i, nattrs;
 838
 839         /* For cpus present at boot a reference was already grabbed in register_cpu() */
 840         if (!s->of_node)
 841                 s->of_node = of_get_cpu_node(cpu, NULL);
 842
 843 #ifdef CONFIG_PPC64
 844         if (cpu_has_feature(CPU_FTR_SMT))
 845                 device_create_file(s, &dev_attr_smt_snooze_delay);
 846 #endif
 847
 848         /* PMC stuff */
 849         switch (cur_cpu_spec->pmc_type) {
 850 #ifdef HAS_PPC_PMC_IBM
 851         case PPC_PMC_IBM:
 852                 attrs = ibm_common_attrs;
 853                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 854                 pmc_attrs = classic_pmc_attrs;
 855                 break;
 856 #endif /* HAS_PPC_PMC_IBM */
 857 #ifdef HAS_PPC_PMC_G4
 858         case PPC_PMC_G4:
 859                 attrs = g4_common_attrs;
 860                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 861                 pmc_attrs = classic_pmc_attrs;
 862                 break;
 863 #endif /* HAS_PPC_PMC_G4 */
 864 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
 865         case PPC_PMC_PA6T:
 866                 /* PA Semi starts counting at PMC0 */
 867                 attrs = pa6t_attrs;
 868                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 869                 pmc_attrs = NULL;
 870                 break;
 871 #endif
 872         default:
 873                 attrs = NULL;
 874                 nattrs = 0;
 875                 pmc_attrs = NULL;
 876         }
 877
 878         for (i = 0; i < nattrs; i++)
 879                 device_create_file(s, &attrs[i]);
 880
 881         if (pmc_attrs)
 882                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 883                         device_create_file(s, &pmc_attrs[i]);
 884
 885 #ifdef CONFIG_PPC64
 886 #ifdef  CONFIG_PMU_SYSFS
 887         if (cpu_has_feature(CPU_FTR_MMCRA))
 888                 device_create_file(s, &dev_attr_mmcra);
 889 #endif /* CONFIG_PMU_SYSFS */
 890
 891         if (cpu_has_feature(CPU_FTR_PURR)) {
 892                 if (!firmware_has_feature(FW_FEATURE_LPAR))
 893                         add_write_permission_dev_attr(&dev_attr_purr);
 894                 device_create_file(s, &dev_attr_purr);
 895                 create_idle_purr_file(s);
 896         }
 897
 898         if (cpu_has_feature(CPU_FTR_SPURR)) {
 899                 device_create_file(s, &dev_attr_spurr);
 900                 create_idle_spurr_file(s);
 901         }
 902
 903         if (cpu_has_feature(CPU_FTR_DSCR))
 904                 device_create_file(s, &dev_attr_dscr);
 905
 906         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 907                 device_create_file(s, &dev_attr_pir);
 908
 909         if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 910                 !firmware_has_feature(FW_FEATURE_LPAR))
 911                 device_create_file(s, &dev_attr_tscr);
 912 #endif /* CONFIG_PPC64 */
 913
 914 #ifdef CONFIG_PPC_FSL_BOOK3E
 915         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 916                 device_create_file(s, &dev_attr_pw20_state);
 917                 device_create_file(s, &dev_attr_pw20_wait_time);
 918
 919                 device_create_file(s, &dev_attr_altivec_idle);
 920                 device_create_file(s, &dev_attr_altivec_idle_wait_time);
 921         }
 922 #endif
 923         cacheinfo_cpu_online(cpu);
 924         return 0;
 925 }
 926
 927 #ifdef CONFIG_HOTPLUG_CPU
 928 static int unregister_cpu_online(unsigned int cpu)
 929 {
 930         struct cpu *c = &per_cpu(cpu_devices, cpu);
 931         struct device *s = &c->dev;
 932         struct device_attribute *attrs, *pmc_attrs;
 933         int i, nattrs;
 934
 935         BUG_ON(!c->hotpluggable);
 936
 937 #ifdef CONFIG_PPC64
 938         if (cpu_has_feature(CPU_FTR_SMT))
 939                 device_remove_file(s, &dev_attr_smt_snooze_delay);
 940 #endif
 941
 942         /* PMC stuff */
 943         switch (cur_cpu_spec->pmc_type) {
 944 #ifdef HAS_PPC_PMC_IBM
 945         case PPC_PMC_IBM:
 946                 attrs = ibm_common_attrs;
 947                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 948                 pmc_attrs = classic_pmc_attrs;
 949                 break;
 950 #endif /* HAS_PPC_PMC_IBM */
 951 #ifdef HAS_PPC_PMC_G4
 952         case PPC_PMC_G4:
 953                 attrs = g4_common_attrs;
 954                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 955                 pmc_attrs = classic_pmc_attrs;
 956                 break;
 957 #endif /* HAS_PPC_PMC_G4 */
 958 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
 959         case PPC_PMC_PA6T:
 960                 /* PA Semi starts counting at PMC0 */
 961                 attrs = pa6t_attrs;
 962                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 963                 pmc_attrs = NULL;
 964                 break;
 965 #endif
 966         default:
 967                 attrs = NULL;
 968                 nattrs = 0;
 969                 pmc_attrs = NULL;
 970         }
 971
 972         for (i = 0; i < nattrs; i++)
 973                 device_remove_file(s, &attrs[i]);
 974
 975         if (pmc_attrs)
 976                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 977                         device_remove_file(s, &pmc_attrs[i]);
 978
 979 #ifdef CONFIG_PPC64
 980 #ifdef CONFIG_PMU_SYSFS
 981         if (cpu_has_feature(CPU_FTR_MMCRA))
 982                 device_remove_file(s, &dev_attr_mmcra);
 983 #endif /* CONFIG_PMU_SYSFS */
 984
 985         if (cpu_has_feature(CPU_FTR_PURR)) {
 986                 device_remove_file(s, &dev_attr_purr);
 987                 remove_idle_purr_file(s);
 988         }
 989
 990         if (cpu_has_feature(CPU_FTR_SPURR)) {
 991                 device_remove_file(s, &dev_attr_spurr);
 992                 remove_idle_spurr_file(s);
 993         }
 994
 995         if (cpu_has_feature(CPU_FTR_DSCR))
 996                 device_remove_file(s, &dev_attr_dscr);
 997
 998         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 999                 device_remove_file(s, &dev_attr_pir);
1000
1001         if (cpu_has_feature(CPU_FTR_ARCH_206) &&
1002                 !firmware_has_feature(FW_FEATURE_LPAR))
1003                 device_remove_file(s, &dev_attr_tscr);
1004 #endif /* CONFIG_PPC64 */
1005
1006 #ifdef CONFIG_PPC_FSL_BOOK3E
1007         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
1008                 device_remove_file(s, &dev_attr_pw20_state);
1009                 device_remove_file(s, &dev_attr_pw20_wait_time);
1010
1011                 device_remove_file(s, &dev_attr_altivec_idle);
1012                 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
1013         }
1014 #endif
1015         cacheinfo_cpu_offline(cpu);
1016         of_node_put(s->of_node);
1017         s->of_node = NULL;
1018         return 0;
1019 }
1020 #else /* !CONFIG_HOTPLUG_CPU */
1021 #define unregister_cpu_online NULL
1022 #endif
1023
1024 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
1025 ssize_t arch_cpu_probe(const char *buf, size_t count)
1026 {
1027         if (ppc_md.cpu_probe)
1028                 return ppc_md.cpu_probe(buf, count);
1029
1030         return -EINVAL;
1031 }
1032
1033 ssize_t arch_cpu_release(const char *buf, size_t count)
1034 {
1035         if (ppc_md.cpu_release)
1036                 return ppc_md.cpu_release(buf, count);
1037
1038         return -EINVAL;
1039 }
1040 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
1041
1042 static DEFINE_MUTEX(cpu_mutex);
1043
1044 int cpu_add_dev_attr(struct device_attribute *attr)
1045 {
1046         int cpu;
1047
1048         mutex_lock(&cpu_mutex);
1049
1050         for_each_possible_cpu(cpu) {
1051                 device_create_file(get_cpu_device(cpu), attr);
1052         }
1053
1054         mutex_unlock(&cpu_mutex);
1055         return 0;
1056 }
1057 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
1058
1059 int cpu_add_dev_attr_group(struct attribute_group *attrs)
1060 {
1061         int cpu;
1062         struct device *dev;
1063         int ret;
1064
1065         mutex_lock(&cpu_mutex);
1066
1067         for_each_possible_cpu(cpu) {
1068                 dev = get_cpu_device(cpu);
1069                 ret = sysfs_create_group(&dev->kobj, attrs);
1070                 WARN_ON(ret != 0);
1071         }
1072
1073         mutex_unlock(&cpu_mutex);
1074         return 0;
1075 }
1076 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
1077
1078
1079 void cpu_remove_dev_attr(struct device_attribute *attr)
1080 {
1081         int cpu;
1082
1083         mutex_lock(&cpu_mutex);
1084
1085         for_each_possible_cpu(cpu) {
1086                 device_remove_file(get_cpu_device(cpu), attr);
1087         }
1088
1089         mutex_unlock(&cpu_mutex);
1090 }
1091 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
1092
1093 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
1094 {
1095         int cpu;
1096         struct device *dev;
1097
1098         mutex_lock(&cpu_mutex);
1099
1100         for_each_possible_cpu(cpu) {
1101                 dev = get_cpu_device(cpu);
1102                 sysfs_remove_group(&dev->kobj, attrs);
1103         }
1104
1105         mutex_unlock(&cpu_mutex);
1106 }
1107 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
1108
1109
1110 /* NUMA stuff */
1111
1112 #ifdef CONFIG_NUMA
1113 static void register_nodes(void)
1114 {
1115         int i;
1116
1117         for (i = 0; i < MAX_NUMNODES; i++)
1118                 register_one_node(i);
1119 }
1120
1121 int sysfs_add_device_to_node(struct device *dev, int nid)
1122 {
1123         struct node *node = node_devices[nid];
1124         return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1125                         kobject_name(&dev->kobj));
1126 }
1127 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1128
1129 void sysfs_remove_device_from_node(struct device *dev, int nid)
1130 {
1131         struct node *node = node_devices[nid];
1132         sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1133 }
1134 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1135
1136 #else
1137 static void register_nodes(void)
1138 {
1139         return;
1140 }
1141
1142 #endif
1143
1144 /* Only valid if CPU is present. */
1145 static ssize_t show_physical_id(struct device *dev,
1146                                 struct device_attribute *attr, char *buf)
1147 {
1148         struct cpu *cpu = container_of(dev, struct cpu, dev);
1149
1150         return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1151 }
1152 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1153
1154 static int __init topology_init(void)
1155 {
1156         int cpu, r;
1157
1158         register_nodes();
1159
1160         for_each_possible_cpu(cpu) {
1161                 struct cpu *c = &per_cpu(cpu_devices, cpu);
1162
1163                 /*
1164                  * For now, we just see if the system supports making
1165                  * the RTAS calls for CPU hotplug.  But, there may be a
1166                  * more comprehensive way to do this for an individual
1167                  * CPU.  For instance, the boot cpu might never be valid
1168                  * for hotplugging.
1169                  */
1170                 if (ppc_md.cpu_die)
1171                         c->hotpluggable = 1;
1172
1173                 if (cpu_online(cpu) || c->hotpluggable) {
1174                         register_cpu(c, cpu);
1175
1176                         device_create_file(&c->dev, &dev_attr_physical_id);
1177                 }
1178         }
1179         r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1180                               register_cpu_online, unregister_cpu_online);
1181         WARN_ON(r < 0);
1182 #ifdef CONFIG_PPC64
1183         sysfs_create_dscr_default();
1184 #endif /* CONFIG_PPC64 */
1185
1186         create_svm_file();
1187
1188         return 0;
1189 }
1190 subsys_initcall(topology_init);