3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/export.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/reboot.h>
19 #include <linux/delay.h>
20 #include <linux/initrd.h>
21 #include <linux/seq_file.h>
22 #include <linux/ioport.h>
23 #include <linux/console.h>
24 #include <linux/utsname.h>
25 #include <linux/tty.h>
26 #include <linux/root_dev.h>
27 #include <linux/notifier.h>
28 #include <linux/cpu.h>
29 #include <linux/unistd.h>
30 #include <linux/serial.h>
31 #include <linux/serial_8250.h>
32 #include <linux/bootmem.h>
33 #include <linux/pci.h>
34 #include <linux/lockdep.h>
35 #include <linux/memblock.h>
36 #include <linux/memory.h>
37 #include <linux/nmi.h>
39 #include <asm/debugfs.h>
41 #include <asm/kdump.h>
43 #include <asm/processor.h>
44 #include <asm/pgtable.h>
47 #include <asm/machdep.h>
50 #include <asm/cputable.h>
51 #include <asm/dt_cpu_ftrs.h>
52 #include <asm/sections.h>
53 #include <asm/btext.h>
54 #include <asm/nvram.h>
55 #include <asm/setup.h>
57 #include <asm/iommu.h>
58 #include <asm/serial.h>
59 #include <asm/cache.h>
62 #include <asm/firmware.h>
65 #include <asm/kexec.h>
66 #include <asm/code-patching.h>
67 #include <asm/livepatch.h>
69 #include <asm/cputhreads.h>
70 #include <asm/hw_irq.h>
75 #define DBG(fmt...) udbg_printf(fmt)
80 int spinning_secondaries;
83 struct ppc64_caches ppc64_caches = {
93 EXPORT_SYMBOL_GPL(ppc64_caches);
95 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
96 void __init setup_tlb_core_data(void)
100 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
102 for_each_possible_cpu(cpu) {
103 int first = cpu_first_thread_sibling(cpu);
106 * If we boot via kdump on a non-primary thread,
107 * make sure we point at the thread that actually
110 if (cpu_first_thread_sibling(boot_cpuid) == first)
113 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
116 * If we have threads, we need either tlbsrx.
117 * or e6500 tablewalk mode, or else TLB handlers
118 * will be racy and could produce duplicate entries.
119 * Should we panic instead?
121 WARN_ONCE(smt_enabled_at_boot >= 2 &&
122 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
123 book3e_htw_mode != PPC_HTW_E6500,
124 "%s: unsupported MMU configuration\n", __func__);
131 static char *smt_enabled_cmdline;
133 /* Look for ibm,smt-enabled OF option */
134 void __init check_smt_enabled(void)
136 struct device_node *dn;
137 const char *smt_option;
139 /* Default to enabling all threads */
140 smt_enabled_at_boot = threads_per_core;
142 /* Allow the command line to overrule the OF option */
143 if (smt_enabled_cmdline) {
144 if (!strcmp(smt_enabled_cmdline, "on"))
145 smt_enabled_at_boot = threads_per_core;
146 else if (!strcmp(smt_enabled_cmdline, "off"))
147 smt_enabled_at_boot = 0;
152 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
154 smt_enabled_at_boot =
155 min(threads_per_core, smt);
158 dn = of_find_node_by_path("/options");
160 smt_option = of_get_property(dn, "ibm,smt-enabled",
164 if (!strcmp(smt_option, "on"))
165 smt_enabled_at_boot = threads_per_core;
166 else if (!strcmp(smt_option, "off"))
167 smt_enabled_at_boot = 0;
175 /* Look for smt-enabled= cmdline option */
176 static int __init early_smt_enabled(char *p)
178 smt_enabled_cmdline = p;
181 early_param("smt-enabled", early_smt_enabled);
183 #endif /* CONFIG_SMP */
185 /** Fix up paca fields required for the boot cpu */
186 static void __init fixup_boot_paca(void)
188 /* The boot cpu is started */
189 get_paca()->cpu_start = 1;
190 /* Allow percpu accesses to work until we setup percpu data */
191 get_paca()->data_offset = 0;
192 /* Mark interrupts disabled in PACA */
193 irq_soft_mask_set(IRQS_DISABLED);
196 static void __init configure_exceptions(void)
199 * Setup the trampolines from the lowmem exception vectors
200 * to the kdump kernel when not using a relocatable kernel.
202 setup_kdump_trampoline();
204 /* Under a PAPR hypervisor, we need hypercalls */
205 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
206 /* Enable AIL if possible */
207 pseries_enable_reloc_on_exc();
210 * Tell the hypervisor that we want our exceptions to
211 * be taken in little endian mode.
213 * We don't call this for big endian as our calling convention
214 * makes us always enter in BE, and the call may fail under
215 * some circumstances with kdump.
217 #ifdef __LITTLE_ENDIAN__
218 pseries_little_endian_exceptions();
221 /* Set endian mode using OPAL */
222 if (firmware_has_feature(FW_FEATURE_OPAL))
223 opal_configure_cores();
225 /* AIL on native is done in cpu_ready_for_interrupts() */
229 static void cpu_ready_for_interrupts(void)
232 * Enable AIL if supported, and we are in hypervisor mode. This
233 * is called once for every processor.
235 * If we are not in hypervisor mode the job is done once for
236 * the whole partition in configure_exceptions().
238 if (cpu_has_feature(CPU_FTR_HVMODE) &&
239 cpu_has_feature(CPU_FTR_ARCH_207S)) {
240 unsigned long lpcr = mfspr(SPRN_LPCR);
241 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
245 * Fixup HFSCR:TM based on CPU features. The bit is set by our
246 * early asm init because at that point we haven't updated our
247 * CPU features from firmware and device-tree. Here we have,
250 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
251 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
253 /* Set IR and DR in PACA MSR */
254 get_paca()->kernel_msr = MSR_KERNEL;
257 unsigned long spr_default_dscr = 0;
259 void __init record_spr_defaults(void)
261 if (early_cpu_has_feature(CPU_FTR_DSCR))
262 spr_default_dscr = mfspr(SPRN_DSCR);
266 * Early initialization entry point. This is called by head.S
267 * with MMU translation disabled. We rely on the "feature" of
268 * the CPU that ignores the top 2 bits of the address in real
269 * mode so we can access kernel globals normally provided we
270 * only toy with things in the RMO region. From here, we do
271 * some early parsing of the device-tree to setup out MEMBLOCK
272 * data structures, and allocate & initialize the hash table
273 * and segment tables so we can start running with translation
276 * It is this function which will call the probe() callback of
277 * the various platform types and copy the matching one to the
278 * global ppc_md structure. Your platform can eventually do
279 * some very early initializations from the probe() routine, but
280 * this is not recommended, be very careful as, for example, the
281 * device-tree is not accessible via normal means at this point.
284 void __init early_setup(unsigned long dt_ptr)
286 static __initdata struct paca_struct boot_paca;
288 /* -------- printk is _NOT_ safe to use here ! ------- */
290 /* Try new device tree based feature discovery ... */
291 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
292 /* Otherwise use the old style CPU table */
293 identify_cpu(0, mfspr(SPRN_PVR));
295 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
296 initialise_paca(&boot_paca, 0);
297 setup_paca(&boot_paca);
300 /* -------- printk is now safe to use ------- */
302 /* Enable early debugging if any specified (see udbg.h) */
305 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
308 * Do early initialization using the flattened device
309 * tree, such as retrieving the physical memory map or
310 * calculating/retrieving the hash table size.
312 early_init_devtree(__va(dt_ptr));
314 /* Now we know the logical id of our boot cpu, setup the paca. */
315 if (boot_cpuid != 0) {
316 /* Poison paca_ptrs[0] again if it's not the boot cpu */
317 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
319 setup_paca(paca_ptrs[boot_cpuid]);
323 * Configure exception handlers. This include setting up trampolines
324 * if needed, setting exception endian mode, etc...
326 configure_exceptions();
328 /* Apply all the dynamic patching */
329 apply_feature_fixups();
330 setup_feature_keys();
332 /* Initialize the hash table or TLB handling */
336 * After firmware and early platform setup code has set things up,
337 * we note the SPR values for configurable control/performance
338 * registers, and use those as initial defaults.
340 record_spr_defaults();
343 * At this point, we can let interrupts switch to virtual mode
344 * (the MMU has been setup), so adjust the MSR in the PACA to
345 * have IR and DR set and enable AIL if it exists
347 cpu_ready_for_interrupts();
350 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
351 * will only actually get enabled on the boot cpu much later once
352 * ftrace itself has been initialized.
354 this_cpu_enable_ftrace();
356 DBG(" <- early_setup()\n");
358 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
360 * This needs to be done *last* (after the above DBG() even)
362 * Right after we return from this function, we turn on the MMU
363 * which means the real-mode access trick that btext does will
364 * no longer work, it needs to switch to using a real MMU
365 * mapping. This call will ensure that it does
368 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
372 void early_setup_secondary(void)
374 /* Mark interrupts disabled in PACA */
375 irq_soft_mask_set(IRQS_DISABLED);
377 /* Initialize the hash table or TLB handling */
378 early_init_mmu_secondary();
381 * At this point, we can let interrupts switch to virtual mode
382 * (the MMU has been setup), so adjust the MSR in the PACA to
383 * have IR and DR set.
385 cpu_ready_for_interrupts();
388 #endif /* CONFIG_SMP */
390 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
391 static bool use_spinloop(void)
393 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
395 * See comments in head_64.S -- not all platforms insert
396 * secondaries at __secondary_hold and wait at the spin
399 if (firmware_has_feature(FW_FEATURE_OPAL))
405 * When book3e boots from kexec, the ePAPR spin table does
408 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
411 void smp_release_cpus(void)
419 DBG(" -> smp_release_cpus()\n");
421 /* All secondary cpus are spinning on a common spinloop, release them
422 * all now so they can start to spin on their individual paca
423 * spinloops. For non SMP kernels, the secondary cpus never get out
424 * of the common spinloop.
427 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
429 *ptr = ppc_function_entry(generic_secondary_smp_init);
431 /* And wait a bit for them to catch up */
432 for (i = 0; i < 100000; i++) {
435 if (spinning_secondaries == 0)
439 DBG("spinning_secondaries = %d\n", spinning_secondaries);
441 DBG(" <- smp_release_cpus()\n");
443 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
446 * Initialize some remaining members of the ppc64_caches and systemcfg
448 * (at least until we get rid of them completely). This is mostly some
449 * cache informations about the CPU that will be used by cache flush
450 * routines and/or provided to userland
453 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
458 info->line_size = lsize;
459 info->block_size = bsize;
460 info->log_block_size = __ilog2(bsize);
462 info->blocks_per_page = PAGE_SIZE / bsize;
464 info->blocks_per_page = 0;
467 info->assoc = 0xffff;
469 info->assoc = size / (sets * lsize);
472 static bool __init parse_cache_info(struct device_node *np,
474 struct ppc_cache_info *info)
476 static const char *ipropnames[] __initdata = {
479 "i-cache-block-size",
482 static const char *dpropnames[] __initdata = {
485 "d-cache-block-size",
488 const char **propnames = icache ? ipropnames : dpropnames;
489 const __be32 *sizep, *lsizep, *bsizep, *setsp;
490 u32 size, lsize, bsize, sets;
495 lsize = bsize = cur_cpu_spec->dcache_bsize;
496 sizep = of_get_property(np, propnames[0], NULL);
498 size = be32_to_cpu(*sizep);
499 setsp = of_get_property(np, propnames[1], NULL);
501 sets = be32_to_cpu(*setsp);
502 bsizep = of_get_property(np, propnames[2], NULL);
503 lsizep = of_get_property(np, propnames[3], NULL);
507 lsize = be32_to_cpu(*lsizep);
509 bsize = be32_to_cpu(*bsizep);
510 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
514 * OF is weird .. it represents fully associative caches
515 * as "1 way" which doesn't make much sense and doesn't
516 * leave room for direct mapped. We'll assume that 0
517 * in OF means direct mapped for that reason.
524 init_cache_info(info, size, lsize, bsize, sets);
529 void __init initialize_cache_info(void)
531 struct device_node *cpu = NULL, *l2, *l3 = NULL;
534 DBG(" -> initialize_cache_info()\n");
537 * All shipping POWER8 machines have a firmware bug that
538 * puts incorrect information in the device-tree. This will
539 * be (hopefully) fixed for future chips but for now hard
540 * code the values if we are running on one of these
542 pvr = PVR_VER(mfspr(SPRN_PVR));
543 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
544 pvr == PVR_POWER8NVL) {
545 /* size lsize blk sets */
546 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
547 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
548 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
549 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
551 cpu = of_find_node_by_type(NULL, "cpu");
554 * We're assuming *all* of the CPUs have the same
555 * d-cache and i-cache sizes... -Peter
558 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
559 DBG("Argh, can't find dcache properties !\n");
561 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
562 DBG("Argh, can't find icache properties !\n");
565 * Try to find the L2 and L3 if any. Assume they are
566 * unified and use the D-side properties.
568 l2 = of_find_next_cache_node(cpu);
571 parse_cache_info(l2, false, &ppc64_caches.l2);
572 l3 = of_find_next_cache_node(l2);
576 parse_cache_info(l3, false, &ppc64_caches.l3);
581 /* For use by binfmt_elf */
582 dcache_bsize = ppc64_caches.l1d.block_size;
583 icache_bsize = ppc64_caches.l1i.block_size;
585 cur_cpu_spec->dcache_bsize = dcache_bsize;
586 cur_cpu_spec->icache_bsize = icache_bsize;
588 DBG(" <- initialize_cache_info()\n");
592 * This returns the limit below which memory accesses to the linear
593 * mapping are guarnateed not to cause an architectural exception (e.g.,
594 * TLB or SLB miss fault).
596 * This is used to allocate PACAs and various interrupt stacks that
597 * that are accessed early in interrupt handlers that must not cause
598 * re-entrant interrupts.
600 __init u64 ppc64_bolted_size(void)
602 #ifdef CONFIG_PPC_BOOK3E
603 /* Freescale BookE bolts the entire linear mapping */
604 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
605 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
606 return linear_map_top;
607 /* Other BookE, we assume the first GB is bolted */
610 /* BookS radix, does not take faults on linear mapping */
611 if (early_radix_enabled())
614 /* BookS hash, the first segment is bolted */
615 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
616 return 1UL << SID_SHIFT_1T;
617 return 1UL << SID_SHIFT;
621 static void *__init alloc_stack(unsigned long limit, int cpu)
625 pa = memblock_alloc_base_nid(THREAD_SIZE, THREAD_SIZE, limit,
626 early_cpu_to_node(cpu), MEMBLOCK_NONE);
628 pa = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
630 panic("cannot allocate stacks");
636 void __init irqstack_early_init(void)
638 u64 limit = ppc64_bolted_size();
642 * Interrupt stacks must be in the first segment since we
643 * cannot afford to take SLB misses on them. They are not
644 * accessed in realmode.
646 for_each_possible_cpu(i) {
647 softirq_ctx[i] = alloc_stack(limit, i);
648 hardirq_ctx[i] = alloc_stack(limit, i);
652 #ifdef CONFIG_PPC_BOOK3E
653 void __init exc_lvl_early_init(void)
657 for_each_possible_cpu(i) {
660 sp = alloc_stack(ULONG_MAX, i);
662 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
664 sp = alloc_stack(ULONG_MAX, i);
666 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
668 sp = alloc_stack(ULONG_MAX, i);
669 mcheckirq_ctx[i] = sp;
670 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
673 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
674 patch_exception(0x040, exc_debug_debug_book3e);
679 * Emergency stacks are used for a range of things, from asynchronous
680 * NMIs (system reset, machine check) to synchronous, process context.
681 * We set preempt_count to zero, even though that isn't necessarily correct. To
682 * get the right value we'd need to copy it from the previous thread_info, but
683 * doing that might fault causing more problems.
684 * TODO: what to do with accounting?
686 static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
690 ti->preempt_count = 0;
693 klp_init_thread_info(ti);
697 * Stack space used when we detect a bad kernel stack pointer, and
698 * early in SMP boots before relocation is enabled. Exclusive emergency
699 * stack for machine checks.
701 void __init emergency_stack_init(void)
707 * Emergency stacks must be under 256MB, we cannot afford to take
708 * SLB misses on them. The ABI also requires them to be 128-byte
711 * Since we use these as temporary stacks during secondary CPU
712 * bringup, machine check, system reset, and HMI, we need to get
713 * at them in real mode. This means they must also be within the RMO
716 * The IRQ stacks allocated elsewhere in this file are zeroed and
717 * initialized in kernel/irq.c. These are initialized here in order
718 * to have emergency stacks available as early as possible.
720 limit = min(ppc64_bolted_size(), ppc64_rma_size);
722 for_each_possible_cpu(i) {
723 struct thread_info *ti;
725 ti = alloc_stack(limit, i);
726 memset(ti, 0, THREAD_SIZE);
727 emerg_stack_init_thread_info(ti, i);
728 paca_ptrs[i]->emergency_sp = (void *)ti + THREAD_SIZE;
730 #ifdef CONFIG_PPC_BOOK3S_64
731 /* emergency stack for NMI exception handling. */
732 ti = alloc_stack(limit, i);
733 memset(ti, 0, THREAD_SIZE);
734 emerg_stack_init_thread_info(ti, i);
735 paca_ptrs[i]->nmi_emergency_sp = (void *)ti + THREAD_SIZE;
737 /* emergency stack for machine check exception handling. */
738 ti = alloc_stack(limit, i);
739 memset(ti, 0, THREAD_SIZE);
740 emerg_stack_init_thread_info(ti, i);
741 paca_ptrs[i]->mc_emergency_sp = (void *)ti + THREAD_SIZE;
747 #define PCPU_DYN_SIZE ()
749 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
751 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
752 __pa(MAX_DMA_ADDRESS));
755 static void __init pcpu_fc_free(void *ptr, size_t size)
757 free_bootmem(__pa(ptr), size);
760 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
762 if (early_cpu_to_node(from) == early_cpu_to_node(to))
763 return LOCAL_DISTANCE;
765 return REMOTE_DISTANCE;
768 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
769 EXPORT_SYMBOL(__per_cpu_offset);
771 void __init setup_per_cpu_areas(void)
773 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
780 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
781 * to group units. For larger mappings, use 1M atom which
782 * should be large enough to contain a number of units.
784 if (mmu_linear_psize == MMU_PAGE_4K)
785 atom_size = PAGE_SIZE;
789 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
790 pcpu_fc_alloc, pcpu_fc_free);
792 panic("cannot initialize percpu area (err=%d)", rc);
794 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
795 for_each_possible_cpu(cpu) {
796 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
797 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
802 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
803 unsigned long memory_block_size_bytes(void)
805 if (ppc_md.memory_block_size)
806 return ppc_md.memory_block_size();
808 return MIN_MEMORY_BLOCK_SIZE;
812 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
813 struct ppc_pci_io ppc_pci_io;
814 EXPORT_SYMBOL(ppc_pci_io);
817 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
818 u64 hw_nmi_get_sample_period(int watchdog_thresh)
820 return ppc_proc_freq * watchdog_thresh;
825 * The perf based hardlockup detector breaks PMU event based branches, so
826 * disable it by default. Book3S has a soft-nmi hardlockup detector based
827 * on the decrementer interrupt, so it does not suffer from this problem.
829 * It is likely to get false positives in VM guests, so disable it there
832 static int __init disable_hardlockup_detector(void)
834 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
835 hardlockup_detector_disable();
837 if (firmware_has_feature(FW_FEATURE_LPAR))
838 hardlockup_detector_disable();
843 early_initcall(disable_hardlockup_detector);
845 #ifdef CONFIG_PPC_BOOK3S_64
846 static enum l1d_flush_type enabled_flush_types;
847 static void *l1d_flush_fallback_area;
848 static bool no_rfi_flush;
851 static int __init handle_no_rfi_flush(char *p)
853 pr_info("rfi-flush: disabled on command line.");
857 early_param("no_rfi_flush", handle_no_rfi_flush);
860 * The RFI flush is not KPTI, but because users will see doco that says to use
861 * nopti we hijack that option here to also disable the RFI flush.
863 static int __init handle_no_pti(char *p)
865 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
866 handle_no_rfi_flush(NULL);
869 early_param("nopti", handle_no_pti);
871 static void do_nothing(void *unused)
874 * We don't need to do the flush explicitly, just enter+exit kernel is
875 * sufficient, the RFI exit handlers will do the right thing.
879 void rfi_flush_enable(bool enable)
882 do_rfi_flush_fixups(enabled_flush_types);
883 on_each_cpu(do_nothing, NULL, 1);
885 do_rfi_flush_fixups(L1D_FLUSH_NONE);
890 static void __ref init_fallback_flush(void)
895 /* Only allocate the fallback flush area once (at boot time). */
896 if (l1d_flush_fallback_area)
899 l1d_size = ppc64_caches.l1d.size;
902 * If there is no d-cache-size property in the device tree, l1d_size
903 * could be zero. That leads to the loop in the asm wrapping around to
904 * 2^64-1, and then walking off the end of the fallback area and
905 * eventually causing a page fault which is fatal. Just default to
906 * something vaguely sane.
909 l1d_size = (64 * 1024);
911 limit = min(ppc64_bolted_size(), ppc64_rma_size);
914 * Align to L1d size, and size it at 2x L1d size, to catch possible
915 * hardware prefetch runoff. We don't have a recipe for load patterns to
916 * reliably avoid the prefetcher.
918 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
919 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
921 for_each_possible_cpu(cpu) {
922 struct paca_struct *paca = paca_ptrs[cpu];
923 paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
924 paca->l1d_flush_size = l1d_size;
928 void setup_rfi_flush(enum l1d_flush_type types, bool enable)
930 if (types & L1D_FLUSH_FALLBACK) {
931 pr_info("rfi-flush: fallback displacement flush available\n");
932 init_fallback_flush();
935 if (types & L1D_FLUSH_ORI)
936 pr_info("rfi-flush: ori type flush available\n");
938 if (types & L1D_FLUSH_MTTRIG)
939 pr_info("rfi-flush: mttrig type flush available\n");
941 enabled_flush_types = types;
944 rfi_flush_enable(enable);
947 #ifdef CONFIG_DEBUG_FS
948 static int rfi_flush_set(void *data, u64 val)
959 /* Only do anything if we're changing state */
960 if (enable != rfi_flush)
961 rfi_flush_enable(enable);
966 static int rfi_flush_get(void *data, u64 *val)
968 *val = rfi_flush ? 1 : 0;
972 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
974 static __init int rfi_flush_debugfs_init(void)
976 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
979 device_initcall(rfi_flush_debugfs_init);
981 #endif /* CONFIG_PPC_BOOK3S_64 */