1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
44 #include <asm/pgtable.h>
46 #include <asm/processor.h>
49 #include <asm/machdep.h>
51 #include <asm/runlatch.h>
52 #include <asm/syscalls.h>
53 #include <asm/switch_to.h>
55 #include <asm/debug.h>
57 #include <asm/firmware.h>
58 #include <asm/hw_irq.h>
60 #include <asm/code-patching.h>
62 #include <asm/livepatch.h>
63 #include <asm/cpu_has_feature.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/stacktrace.h>
66 #include <asm/hw_breakpoint.h>
68 #include <linux/kprobes.h>
69 #include <linux/kdebug.h>
71 /* Transactional Memory debug */
73 #define TM_DEBUG(x...) printk(KERN_INFO x)
75 #define TM_DEBUG(x...) do { } while(0)
78 extern unsigned long _get_SP(void);
80 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
82 * Are we running in "Suspend disabled" mode? If so we have to block any
83 * sigreturn that would get us into suspended state, and we also warn in some
84 * other paths that we should never reach with suspend disabled.
86 bool tm_suspend_disabled __ro_after_init = false;
88 static void check_if_tm_restore_required(struct task_struct *tsk)
91 * If we are saving the current thread's registers, and the
92 * thread is in a transactional state, set the TIF_RESTORE_TM
93 * bit so that we know to restore the registers before
94 * returning to userspace.
96 if (tsk == current && tsk->thread.regs &&
97 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
98 !test_thread_flag(TIF_RESTORE_TM)) {
99 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
100 set_thread_flag(TIF_RESTORE_TM);
104 static bool tm_active_with_fp(struct task_struct *tsk)
106 return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
107 (tsk->thread.ckpt_regs.msr & MSR_FP);
110 static bool tm_active_with_altivec(struct task_struct *tsk)
112 return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
113 (tsk->thread.ckpt_regs.msr & MSR_VEC);
116 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
117 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
118 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
119 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
121 bool strict_msr_control;
122 EXPORT_SYMBOL(strict_msr_control);
124 static int __init enable_strict_msr_control(char *str)
126 strict_msr_control = true;
127 pr_info("Enabling strict facility control\n");
131 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
133 /* notrace because it's called by restore_math */
134 unsigned long notrace msr_check_and_set(unsigned long bits)
136 unsigned long oldmsr = mfmsr();
137 unsigned long newmsr;
139 newmsr = oldmsr | bits;
142 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
146 if (oldmsr != newmsr)
151 EXPORT_SYMBOL_GPL(msr_check_and_set);
153 /* notrace because it's called by restore_math */
154 void notrace __msr_check_and_clear(unsigned long bits)
156 unsigned long oldmsr = mfmsr();
157 unsigned long newmsr;
159 newmsr = oldmsr & ~bits;
162 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
166 if (oldmsr != newmsr)
169 EXPORT_SYMBOL(__msr_check_and_clear);
171 #ifdef CONFIG_PPC_FPU
172 static void __giveup_fpu(struct task_struct *tsk)
177 msr = tsk->thread.regs->msr;
178 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
180 if (cpu_has_feature(CPU_FTR_VSX))
183 tsk->thread.regs->msr = msr;
186 void giveup_fpu(struct task_struct *tsk)
188 check_if_tm_restore_required(tsk);
190 msr_check_and_set(MSR_FP);
192 msr_check_and_clear(MSR_FP);
194 EXPORT_SYMBOL(giveup_fpu);
197 * Make sure the floating-point register state in the
198 * the thread_struct is up to date for task tsk.
200 void flush_fp_to_thread(struct task_struct *tsk)
202 if (tsk->thread.regs) {
204 * We need to disable preemption here because if we didn't,
205 * another process could get scheduled after the regs->msr
206 * test but before we have finished saving the FP registers
207 * to the thread_struct. That process could take over the
208 * FPU, and then when we get scheduled again we would store
209 * bogus values for the remaining FP registers.
212 if (tsk->thread.regs->msr & MSR_FP) {
214 * This should only ever be called for current or
215 * for a stopped child process. Since we save away
216 * the FP register state on context switch,
217 * there is something wrong if a stopped child appears
218 * to still have its FP state in the CPU registers.
220 BUG_ON(tsk != current);
226 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
228 void enable_kernel_fp(void)
230 unsigned long cpumsr;
232 WARN_ON(preemptible());
234 cpumsr = msr_check_and_set(MSR_FP);
236 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
237 check_if_tm_restore_required(current);
239 * If a thread has already been reclaimed then the
240 * checkpointed registers are on the CPU but have definitely
241 * been saved by the reclaim code. Don't need to and *cannot*
242 * giveup as this would save to the 'live' structure not the
243 * checkpointed structure.
245 if (!MSR_TM_ACTIVE(cpumsr) &&
246 MSR_TM_ACTIVE(current->thread.regs->msr))
248 __giveup_fpu(current);
251 EXPORT_SYMBOL(enable_kernel_fp);
253 static int restore_fp(struct task_struct *tsk)
255 if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
256 load_fp_state(¤t->thread.fp_state);
257 current->thread.load_fp++;
263 static int restore_fp(struct task_struct *tsk) { return 0; }
264 #endif /* CONFIG_PPC_FPU */
266 #ifdef CONFIG_ALTIVEC
267 #define loadvec(thr) ((thr).load_vec)
269 static void __giveup_altivec(struct task_struct *tsk)
274 msr = tsk->thread.regs->msr;
277 if (cpu_has_feature(CPU_FTR_VSX))
280 tsk->thread.regs->msr = msr;
283 void giveup_altivec(struct task_struct *tsk)
285 check_if_tm_restore_required(tsk);
287 msr_check_and_set(MSR_VEC);
288 __giveup_altivec(tsk);
289 msr_check_and_clear(MSR_VEC);
291 EXPORT_SYMBOL(giveup_altivec);
293 void enable_kernel_altivec(void)
295 unsigned long cpumsr;
297 WARN_ON(preemptible());
299 cpumsr = msr_check_and_set(MSR_VEC);
301 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
302 check_if_tm_restore_required(current);
304 * If a thread has already been reclaimed then the
305 * checkpointed registers are on the CPU but have definitely
306 * been saved by the reclaim code. Don't need to and *cannot*
307 * giveup as this would save to the 'live' structure not the
308 * checkpointed structure.
310 if (!MSR_TM_ACTIVE(cpumsr) &&
311 MSR_TM_ACTIVE(current->thread.regs->msr))
313 __giveup_altivec(current);
316 EXPORT_SYMBOL(enable_kernel_altivec);
319 * Make sure the VMX/Altivec register state in the
320 * the thread_struct is up to date for task tsk.
322 void flush_altivec_to_thread(struct task_struct *tsk)
324 if (tsk->thread.regs) {
326 if (tsk->thread.regs->msr & MSR_VEC) {
327 BUG_ON(tsk != current);
333 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
335 static int restore_altivec(struct task_struct *tsk)
337 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
338 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
339 load_vr_state(&tsk->thread.vr_state);
340 tsk->thread.used_vr = 1;
341 tsk->thread.load_vec++;
348 #define loadvec(thr) 0
349 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
350 #endif /* CONFIG_ALTIVEC */
353 static void __giveup_vsx(struct task_struct *tsk)
355 unsigned long msr = tsk->thread.regs->msr;
358 * We should never be ssetting MSR_VSX without also setting
361 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
363 /* __giveup_fpu will clear MSR_VSX */
367 __giveup_altivec(tsk);
370 static void giveup_vsx(struct task_struct *tsk)
372 check_if_tm_restore_required(tsk);
374 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
376 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
379 void enable_kernel_vsx(void)
381 unsigned long cpumsr;
383 WARN_ON(preemptible());
385 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
387 if (current->thread.regs &&
388 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
389 check_if_tm_restore_required(current);
391 * If a thread has already been reclaimed then the
392 * checkpointed registers are on the CPU but have definitely
393 * been saved by the reclaim code. Don't need to and *cannot*
394 * giveup as this would save to the 'live' structure not the
395 * checkpointed structure.
397 if (!MSR_TM_ACTIVE(cpumsr) &&
398 MSR_TM_ACTIVE(current->thread.regs->msr))
400 __giveup_vsx(current);
403 EXPORT_SYMBOL(enable_kernel_vsx);
405 void flush_vsx_to_thread(struct task_struct *tsk)
407 if (tsk->thread.regs) {
409 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
410 BUG_ON(tsk != current);
416 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
418 static int restore_vsx(struct task_struct *tsk)
420 if (cpu_has_feature(CPU_FTR_VSX)) {
421 tsk->thread.used_vsr = 1;
428 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
429 #endif /* CONFIG_VSX */
432 void giveup_spe(struct task_struct *tsk)
434 check_if_tm_restore_required(tsk);
436 msr_check_and_set(MSR_SPE);
438 msr_check_and_clear(MSR_SPE);
440 EXPORT_SYMBOL(giveup_spe);
442 void enable_kernel_spe(void)
444 WARN_ON(preemptible());
446 msr_check_and_set(MSR_SPE);
448 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
449 check_if_tm_restore_required(current);
450 __giveup_spe(current);
453 EXPORT_SYMBOL(enable_kernel_spe);
455 void flush_spe_to_thread(struct task_struct *tsk)
457 if (tsk->thread.regs) {
459 if (tsk->thread.regs->msr & MSR_SPE) {
460 BUG_ON(tsk != current);
461 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
467 #endif /* CONFIG_SPE */
469 static unsigned long msr_all_available;
471 static int __init init_msr_all_available(void)
473 #ifdef CONFIG_PPC_FPU
474 msr_all_available |= MSR_FP;
476 #ifdef CONFIG_ALTIVEC
477 if (cpu_has_feature(CPU_FTR_ALTIVEC))
478 msr_all_available |= MSR_VEC;
481 if (cpu_has_feature(CPU_FTR_VSX))
482 msr_all_available |= MSR_VSX;
485 if (cpu_has_feature(CPU_FTR_SPE))
486 msr_all_available |= MSR_SPE;
491 early_initcall(init_msr_all_available);
493 void giveup_all(struct task_struct *tsk)
495 unsigned long usermsr;
497 if (!tsk->thread.regs)
500 usermsr = tsk->thread.regs->msr;
502 if ((usermsr & msr_all_available) == 0)
505 msr_check_and_set(msr_all_available);
506 check_if_tm_restore_required(tsk);
508 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
510 #ifdef CONFIG_PPC_FPU
511 if (usermsr & MSR_FP)
514 #ifdef CONFIG_ALTIVEC
515 if (usermsr & MSR_VEC)
516 __giveup_altivec(tsk);
519 if (usermsr & MSR_SPE)
523 msr_check_and_clear(msr_all_available);
525 EXPORT_SYMBOL(giveup_all);
528 * The exception exit path calls restore_math() with interrupts hard disabled
529 * but the soft irq state not "reconciled". ftrace code that calls
530 * local_irq_save/restore causes warnings.
532 * Rather than complicate the exit path, just don't trace restore_math. This
533 * could be done by having ftrace entry code check for this un-reconciled
534 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
535 * temporarily fix it up for the duration of the ftrace call.
537 void notrace restore_math(struct pt_regs *regs)
541 if (!MSR_TM_ACTIVE(regs->msr) &&
542 !current->thread.load_fp && !loadvec(current->thread))
546 msr_check_and_set(msr_all_available);
549 * Only reload if the bit is not set in the user MSR, the bit BEING set
550 * indicates that the registers are hot
552 if ((!(msr & MSR_FP)) && restore_fp(current))
553 msr |= MSR_FP | current->thread.fpexc_mode;
555 if ((!(msr & MSR_VEC)) && restore_altivec(current))
558 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
559 restore_vsx(current)) {
563 msr_check_and_clear(msr_all_available);
568 static void save_all(struct task_struct *tsk)
570 unsigned long usermsr;
572 if (!tsk->thread.regs)
575 usermsr = tsk->thread.regs->msr;
577 if ((usermsr & msr_all_available) == 0)
580 msr_check_and_set(msr_all_available);
582 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
584 if (usermsr & MSR_FP)
587 if (usermsr & MSR_VEC)
590 if (usermsr & MSR_SPE)
593 msr_check_and_clear(msr_all_available);
594 thread_pkey_regs_save(&tsk->thread);
597 void flush_all_to_thread(struct task_struct *tsk)
599 if (tsk->thread.regs) {
601 BUG_ON(tsk != current);
603 if (tsk->thread.regs->msr & MSR_SPE)
604 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
611 EXPORT_SYMBOL(flush_all_to_thread);
613 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
614 void do_send_trap(struct pt_regs *regs, unsigned long address,
615 unsigned long error_code, int breakpt)
617 current->thread.trap_nr = TRAP_HWBKPT;
618 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
619 11, SIGSEGV) == NOTIFY_STOP)
622 /* Deliver the signal to userspace */
623 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
624 (void __user *)address);
626 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
627 void do_break (struct pt_regs *regs, unsigned long address,
628 unsigned long error_code)
630 current->thread.trap_nr = TRAP_HWBKPT;
631 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
632 11, SIGSEGV) == NOTIFY_STOP)
635 if (debugger_break_match(regs))
638 /* Clear the breakpoint */
639 hw_breakpoint_disable();
641 /* Deliver the signal to userspace */
642 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address);
644 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
646 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
648 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
650 * Set the debug registers back to their default "safe" values.
652 static void set_debug_reg_defaults(struct thread_struct *thread)
654 thread->debug.iac1 = thread->debug.iac2 = 0;
655 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
656 thread->debug.iac3 = thread->debug.iac4 = 0;
658 thread->debug.dac1 = thread->debug.dac2 = 0;
659 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
660 thread->debug.dvc1 = thread->debug.dvc2 = 0;
662 thread->debug.dbcr0 = 0;
665 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
667 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
668 DBCR1_IAC3US | DBCR1_IAC4US;
670 * Force Data Address Compare User/Supervisor bits to be User-only
671 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
673 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
675 thread->debug.dbcr1 = 0;
679 static void prime_debug_regs(struct debug_reg *debug)
682 * We could have inherited MSR_DE from userspace, since
683 * it doesn't get cleared on exception entry. Make sure
684 * MSR_DE is clear before we enable any debug events.
686 mtmsr(mfmsr() & ~MSR_DE);
688 mtspr(SPRN_IAC1, debug->iac1);
689 mtspr(SPRN_IAC2, debug->iac2);
690 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
691 mtspr(SPRN_IAC3, debug->iac3);
692 mtspr(SPRN_IAC4, debug->iac4);
694 mtspr(SPRN_DAC1, debug->dac1);
695 mtspr(SPRN_DAC2, debug->dac2);
696 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
697 mtspr(SPRN_DVC1, debug->dvc1);
698 mtspr(SPRN_DVC2, debug->dvc2);
700 mtspr(SPRN_DBCR0, debug->dbcr0);
701 mtspr(SPRN_DBCR1, debug->dbcr1);
703 mtspr(SPRN_DBCR2, debug->dbcr2);
707 * Unless neither the old or new thread are making use of the
708 * debug registers, set the debug registers from the values
709 * stored in the new thread.
711 void switch_booke_debug_regs(struct debug_reg *new_debug)
713 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
714 || (new_debug->dbcr0 & DBCR0_IDM))
715 prime_debug_regs(new_debug);
717 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
718 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
719 #ifndef CONFIG_HAVE_HW_BREAKPOINT
720 static void set_breakpoint(struct arch_hw_breakpoint *brk)
723 __set_breakpoint(brk);
727 static void set_debug_reg_defaults(struct thread_struct *thread)
729 thread->hw_brk.address = 0;
730 thread->hw_brk.type = 0;
731 if (ppc_breakpoint_available())
732 set_breakpoint(&thread->hw_brk);
734 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
735 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
737 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
738 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
740 mtspr(SPRN_DAC1, dabr);
741 #ifdef CONFIG_PPC_47x
746 #elif defined(CONFIG_PPC_BOOK3S)
747 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
749 mtspr(SPRN_DABR, dabr);
750 if (cpu_has_feature(CPU_FTR_DABRX))
751 mtspr(SPRN_DABRX, dabrx);
754 #elif defined(CONFIG_PPC_8xx)
755 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
757 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
758 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
759 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
761 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
763 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
765 else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
768 mtspr(SPRN_LCTRL2, 0);
769 mtspr(SPRN_CMPE, addr);
770 mtspr(SPRN_CMPF, addr + 4);
771 mtspr(SPRN_LCTRL1, lctrl1);
772 mtspr(SPRN_LCTRL2, lctrl2);
777 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
783 static inline int set_dabr(struct arch_hw_breakpoint *brk)
785 unsigned long dabr, dabrx;
787 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
788 dabrx = ((brk->type >> 3) & 0x7);
791 return ppc_md.set_dabr(dabr, dabrx);
793 return __set_dabr(dabr, dabrx);
796 void __set_breakpoint(struct arch_hw_breakpoint *brk)
798 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk));
803 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
807 // Shouldn't happen due to higher level checks
811 /* Check if we have DAWR or DABR hardware */
812 bool ppc_breakpoint_available(void)
815 return true; /* POWER8 DAWR or POWER9 forced DAWR */
816 if (cpu_has_feature(CPU_FTR_ARCH_207S))
817 return false; /* POWER9 with DAWR disabled */
818 /* DABR: Everything but POWER8 and POWER9 */
821 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
823 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
824 struct arch_hw_breakpoint *b)
826 if (a->address != b->address)
828 if (a->type != b->type)
830 if (a->len != b->len)
835 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
837 static inline bool tm_enabled(struct task_struct *tsk)
839 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
842 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
845 * Use the current MSR TM suspended bit to track if we have
846 * checkpointed state outstanding.
847 * On signal delivery, we'd normally reclaim the checkpointed
848 * state to obtain stack pointer (see:get_tm_stackpointer()).
849 * This will then directly return to userspace without going
850 * through __switch_to(). However, if the stack frame is bad,
851 * we need to exit this thread which calls __switch_to() which
852 * will again attempt to reclaim the already saved tm state.
853 * Hence we need to check that we've not already reclaimed
855 * We do this using the current MSR, rather tracking it in
856 * some specific thread_struct bit, as it has the additional
857 * benefit of checking for a potential TM bad thing exception.
859 if (!MSR_TM_SUSPENDED(mfmsr()))
862 giveup_all(container_of(thr, struct task_struct, thread));
864 tm_reclaim(thr, cause);
867 * If we are in a transaction and FP is off then we can't have
868 * used FP inside that transaction. Hence the checkpointed
869 * state is the same as the live state. We need to copy the
870 * live state to the checkpointed state so that when the
871 * transaction is restored, the checkpointed state is correct
872 * and the aborted transaction sees the correct state. We use
873 * ckpt_regs.msr here as that's what tm_reclaim will use to
874 * determine if it's going to write the checkpointed state or
875 * not. So either this will write the checkpointed registers,
876 * or reclaim will. Similarly for VMX.
878 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
879 memcpy(&thr->ckfp_state, &thr->fp_state,
880 sizeof(struct thread_fp_state));
881 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
882 memcpy(&thr->ckvr_state, &thr->vr_state,
883 sizeof(struct thread_vr_state));
886 void tm_reclaim_current(uint8_t cause)
889 tm_reclaim_thread(¤t->thread, cause);
892 static inline void tm_reclaim_task(struct task_struct *tsk)
894 /* We have to work out if we're switching from/to a task that's in the
895 * middle of a transaction.
897 * In switching we need to maintain a 2nd register state as
898 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
899 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
902 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
904 struct thread_struct *thr = &tsk->thread;
909 if (!MSR_TM_ACTIVE(thr->regs->msr))
910 goto out_and_saveregs;
912 WARN_ON(tm_suspend_disabled);
914 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
915 "ccr=%lx, msr=%lx, trap=%lx)\n",
916 tsk->pid, thr->regs->nip,
917 thr->regs->ccr, thr->regs->msr,
920 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
922 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
926 /* Always save the regs here, even if a transaction's not active.
927 * This context-switches a thread's TM info SPRs. We do it here to
928 * be consistent with the restore path (in recheckpoint) which
929 * cannot happen later in _switch().
934 extern void __tm_recheckpoint(struct thread_struct *thread);
936 void tm_recheckpoint(struct thread_struct *thread)
940 if (!(thread->regs->msr & MSR_TM))
943 /* We really can't be interrupted here as the TEXASR registers can't
944 * change and later in the trecheckpoint code, we have a userspace R1.
945 * So let's hard disable over this region.
947 local_irq_save(flags);
950 /* The TM SPRs are restored here, so that TEXASR.FS can be set
951 * before the trecheckpoint and no explosion occurs.
953 tm_restore_sprs(thread);
955 __tm_recheckpoint(thread);
957 local_irq_restore(flags);
960 static inline void tm_recheckpoint_new_task(struct task_struct *new)
962 if (!cpu_has_feature(CPU_FTR_TM))
965 /* Recheckpoint the registers of the thread we're about to switch to.
967 * If the task was using FP, we non-lazily reload both the original and
968 * the speculative FP register states. This is because the kernel
969 * doesn't see if/when a TM rollback occurs, so if we take an FP
970 * unavailable later, we are unable to determine which set of FP regs
971 * need to be restored.
973 if (!tm_enabled(new))
976 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
977 tm_restore_sprs(&new->thread);
980 /* Recheckpoint to restore original checkpointed register state. */
981 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
982 new->pid, new->thread.regs->msr);
984 tm_recheckpoint(&new->thread);
987 * The checkpointed state has been restored but the live state has
988 * not, ensure all the math functionality is turned off to trigger
989 * restore_math() to reload.
991 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
993 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
994 "(kernel msr 0x%lx)\n",
998 static inline void __switch_to_tm(struct task_struct *prev,
999 struct task_struct *new)
1001 if (cpu_has_feature(CPU_FTR_TM)) {
1002 if (tm_enabled(prev) || tm_enabled(new))
1005 if (tm_enabled(prev)) {
1006 prev->thread.load_tm++;
1007 tm_reclaim_task(prev);
1008 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1009 prev->thread.regs->msr &= ~MSR_TM;
1012 tm_recheckpoint_new_task(new);
1017 * This is called if we are on the way out to userspace and the
1018 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1019 * FP and/or vector state and does so if necessary.
1020 * If userspace is inside a transaction (whether active or
1021 * suspended) and FP/VMX/VSX instructions have ever been enabled
1022 * inside that transaction, then we have to keep them enabled
1023 * and keep the FP/VMX/VSX state loaded while ever the transaction
1024 * continues. The reason is that if we didn't, and subsequently
1025 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1026 * we don't know whether it's the same transaction, and thus we
1027 * don't know which of the checkpointed state and the transactional
1030 void restore_tm_state(struct pt_regs *regs)
1032 unsigned long msr_diff;
1035 * This is the only moment we should clear TIF_RESTORE_TM as
1036 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1037 * again, anything else could lead to an incorrect ckpt_msr being
1038 * saved and therefore incorrect signal contexts.
1040 clear_thread_flag(TIF_RESTORE_TM);
1041 if (!MSR_TM_ACTIVE(regs->msr))
1044 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1045 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1047 /* Ensure that restore_math() will restore */
1048 if (msr_diff & MSR_FP)
1049 current->thread.load_fp = 1;
1050 #ifdef CONFIG_ALTIVEC
1051 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1052 current->thread.load_vec = 1;
1056 regs->msr |= msr_diff;
1060 #define tm_recheckpoint_new_task(new)
1061 #define __switch_to_tm(prev, new)
1062 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1064 static inline void save_sprs(struct thread_struct *t)
1066 #ifdef CONFIG_ALTIVEC
1067 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1068 t->vrsave = mfspr(SPRN_VRSAVE);
1070 #ifdef CONFIG_PPC_BOOK3S_64
1071 if (cpu_has_feature(CPU_FTR_DSCR))
1072 t->dscr = mfspr(SPRN_DSCR);
1074 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1075 t->bescr = mfspr(SPRN_BESCR);
1076 t->ebbhr = mfspr(SPRN_EBBHR);
1077 t->ebbrr = mfspr(SPRN_EBBRR);
1079 t->fscr = mfspr(SPRN_FSCR);
1082 * Note that the TAR is not available for use in the kernel.
1083 * (To provide this, the TAR should be backed up/restored on
1084 * exception entry/exit instead, and be in pt_regs. FIXME,
1085 * this should be in pt_regs anyway (for debug).)
1087 t->tar = mfspr(SPRN_TAR);
1091 thread_pkey_regs_save(t);
1094 static inline void restore_sprs(struct thread_struct *old_thread,
1095 struct thread_struct *new_thread)
1097 #ifdef CONFIG_ALTIVEC
1098 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1099 old_thread->vrsave != new_thread->vrsave)
1100 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1102 #ifdef CONFIG_PPC_BOOK3S_64
1103 if (cpu_has_feature(CPU_FTR_DSCR)) {
1104 u64 dscr = get_paca()->dscr_default;
1105 if (new_thread->dscr_inherit)
1106 dscr = new_thread->dscr;
1108 if (old_thread->dscr != dscr)
1109 mtspr(SPRN_DSCR, dscr);
1112 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1113 if (old_thread->bescr != new_thread->bescr)
1114 mtspr(SPRN_BESCR, new_thread->bescr);
1115 if (old_thread->ebbhr != new_thread->ebbhr)
1116 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1117 if (old_thread->ebbrr != new_thread->ebbrr)
1118 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1120 if (old_thread->fscr != new_thread->fscr)
1121 mtspr(SPRN_FSCR, new_thread->fscr);
1123 if (old_thread->tar != new_thread->tar)
1124 mtspr(SPRN_TAR, new_thread->tar);
1127 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1128 old_thread->tidr != new_thread->tidr)
1129 mtspr(SPRN_TIDR, new_thread->tidr);
1132 thread_pkey_regs_restore(new_thread, old_thread);
1135 struct task_struct *__switch_to(struct task_struct *prev,
1136 struct task_struct *new)
1138 struct thread_struct *new_thread, *old_thread;
1139 struct task_struct *last;
1140 #ifdef CONFIG_PPC_BOOK3S_64
1141 struct ppc64_tlb_batch *batch;
1144 new_thread = &new->thread;
1145 old_thread = ¤t->thread;
1147 WARN_ON(!irqs_disabled());
1149 #ifdef CONFIG_PPC_BOOK3S_64
1150 batch = this_cpu_ptr(&ppc64_tlb_batch);
1151 if (batch->active) {
1152 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1154 __flush_tlb_pending(batch);
1157 #endif /* CONFIG_PPC_BOOK3S_64 */
1159 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1160 switch_booke_debug_regs(&new->thread.debug);
1163 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1166 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1167 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk)))
1168 __set_breakpoint(&new->thread.hw_brk);
1169 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1173 * We need to save SPRs before treclaim/trecheckpoint as these will
1174 * change a number of them.
1176 save_sprs(&prev->thread);
1178 /* Save FPU, Altivec, VSX and SPE state */
1181 __switch_to_tm(prev, new);
1183 if (!radix_enabled()) {
1185 * We can't take a PMU exception inside _switch() since there
1186 * is a window where the kernel stack SLB and the kernel stack
1187 * are out of sync. Hard disable here.
1193 * Call restore_sprs() before calling _switch(). If we move it after
1194 * _switch() then we miss out on calling it for new tasks. The reason
1195 * for this is we manually create a stack frame for new tasks that
1196 * directly returns through ret_from_fork() or
1197 * ret_from_kernel_thread(). See copy_thread() for details.
1199 restore_sprs(old_thread, new_thread);
1201 last = _switch(old_thread, new_thread);
1203 #ifdef CONFIG_PPC_BOOK3S_64
1204 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1205 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1206 batch = this_cpu_ptr(&ppc64_tlb_batch);
1210 if (current->thread.regs) {
1211 restore_math(current->thread.regs);
1214 * The copy-paste buffer can only store into foreign real
1215 * addresses, so unprivileged processes can not see the
1216 * data or use it in any way unless they have foreign real
1217 * mappings. If the new process has the foreign real address
1218 * mappings, we must issue a cp_abort to clear any state and
1219 * prevent snooping, corruption or a covert channel.
1221 if (current->thread.used_vas)
1222 asm volatile(PPC_CP_ABORT);
1224 #endif /* CONFIG_PPC_BOOK3S_64 */
1229 #define NR_INSN_TO_PRINT 16
1231 static void show_instructions(struct pt_regs *regs)
1234 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1236 printk("Instruction dump:");
1238 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1244 #if !defined(CONFIG_BOOKE)
1245 /* If executing with the IMMU off, adjust pc rather
1246 * than print XXXXXXXX.
1248 if (!(regs->msr & MSR_IR))
1249 pc = (unsigned long)phys_to_virt(pc);
1252 if (!__kernel_text_address(pc) ||
1253 probe_kernel_address((const void *)pc, instr)) {
1254 pr_cont("XXXXXXXX ");
1256 if (regs->nip == pc)
1257 pr_cont("<%08x> ", instr);
1259 pr_cont("%08x ", instr);
1268 void show_user_instructions(struct pt_regs *regs)
1271 int n = NR_INSN_TO_PRINT;
1273 char buf[96]; /* enough for 8 times 9 + 2 chars */
1275 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1278 * Make sure the NIP points at userspace, not kernel text/data or
1281 if (!__access_ok(pc, NR_INSN_TO_PRINT * sizeof(int), USER_DS)) {
1282 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1283 current->comm, current->pid);
1287 seq_buf_init(&s, buf, sizeof(buf));
1294 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1297 if (probe_kernel_address((const void *)pc, instr)) {
1298 seq_buf_printf(&s, "XXXXXXXX ");
1301 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1304 if (!seq_buf_has_overflowed(&s))
1305 pr_info("%s[%d]: code: %s\n", current->comm,
1306 current->pid, s.buffer);
1315 static struct regbit msr_bits[] = {
1316 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1338 #ifndef CONFIG_BOOKE
1345 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1349 for (; bits->bit; ++bits)
1350 if (val & bits->bit) {
1351 pr_cont("%s%s", s, bits->name);
1356 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1357 static struct regbit msr_tm_bits[] = {
1364 static void print_tm_bits(unsigned long val)
1367 * This only prints something if at least one of the TM bit is set.
1368 * Inside the TM[], the output means:
1369 * E: Enabled (bit 32)
1370 * S: Suspended (bit 33)
1371 * T: Transactional (bit 34)
1373 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1375 print_bits(val, msr_tm_bits, "");
1380 static void print_tm_bits(unsigned long val) {}
1383 static void print_msr_bits(unsigned long val)
1386 print_bits(val, msr_bits, ",");
1392 #define REG "%016lx"
1393 #define REGS_PER_LINE 4
1394 #define LAST_VOLATILE 13
1397 #define REGS_PER_LINE 8
1398 #define LAST_VOLATILE 12
1401 void show_regs(struct pt_regs * regs)
1405 show_regs_print_info(KERN_DEFAULT);
1407 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1408 regs->nip, regs->link, regs->ctr);
1409 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1410 regs, regs->trap, print_tainted(), init_utsname()->release);
1411 printk("MSR: "REG" ", regs->msr);
1412 print_msr_bits(regs->msr);
1413 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1415 if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1416 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1417 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1418 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1419 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1421 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1424 pr_cont("IRQMASK: %lx ", regs->softe);
1426 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1427 if (MSR_TM_ACTIVE(regs->msr))
1428 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1431 for (i = 0; i < 32; i++) {
1432 if ((i % REGS_PER_LINE) == 0)
1433 pr_cont("\nGPR%02d: ", i);
1434 pr_cont(REG " ", regs->gpr[i]);
1435 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1439 #ifdef CONFIG_KALLSYMS
1441 * Lookup NIP late so we have the best change of getting the
1442 * above info out without failing
1444 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1445 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1447 show_stack(current, (unsigned long *) regs->gpr[1]);
1448 if (!user_mode(regs))
1449 show_instructions(regs);
1452 void flush_thread(void)
1454 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1455 flush_ptrace_hw_breakpoint(current);
1456 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1457 set_debug_reg_defaults(¤t->thread);
1458 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1461 #ifdef CONFIG_PPC_BOOK3S_64
1462 void arch_setup_new_exec(void)
1464 if (radix_enabled())
1466 hash__setup_new_exec();
1470 int set_thread_uses_vas(void)
1472 #ifdef CONFIG_PPC_BOOK3S_64
1473 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1476 current->thread.used_vas = 1;
1479 * Even a process that has no foreign real address mapping can use
1480 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1481 * to clear any pending COPY and prevent a covert channel.
1483 * __switch_to() will issue CP_ABORT on future context switches.
1485 asm volatile(PPC_CP_ABORT);
1487 #endif /* CONFIG_PPC_BOOK3S_64 */
1493 * Assign a TIDR (thread ID) for task @t and set it in the thread
1494 * structure. For now, we only support setting TIDR for 'current' task.
1496 * Since the TID value is a truncated form of it PID, it is possible
1497 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1498 * that 2 threads share the same TID and are waiting, one of the following
1499 * cases will happen:
1501 * 1. The correct thread is running, the wrong thread is not
1502 * In this situation, the correct thread is woken and proceeds to pass it's
1505 * 2. Neither threads are running
1506 * In this situation, neither thread will be woken. When scheduled, the waiting
1507 * threads will execute either a wait, which will return immediately, followed
1508 * by a condition check, which will pass for the correct thread and fail
1509 * for the wrong thread, or they will execute the condition check immediately.
1511 * 3. The wrong thread is running, the correct thread is not
1512 * The wrong thread will be woken, but will fail it's condition check and
1513 * re-execute wait. The correct thread, when scheduled, will execute either
1514 * it's condition check (which will pass), or wait, which returns immediately
1515 * when called the first time after the thread is scheduled, followed by it's
1516 * condition check (which will pass).
1518 * 4. Both threads are running
1519 * Both threads will be woken. The wrong thread will fail it's condition check
1520 * and execute another wait, while the correct thread will pass it's condition
1523 * @t: the task to set the thread ID for
1525 int set_thread_tidr(struct task_struct *t)
1527 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1536 t->thread.tidr = (u16)task_pid_nr(t);
1537 mtspr(SPRN_TIDR, t->thread.tidr);
1541 EXPORT_SYMBOL_GPL(set_thread_tidr);
1543 #endif /* CONFIG_PPC64 */
1546 release_thread(struct task_struct *t)
1551 * this gets called so that we can store coprocessor state into memory and
1552 * copy the current task into the new thread.
1554 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1556 flush_all_to_thread(src);
1558 * Flush TM state out so we can copy it. __switch_to_tm() does this
1559 * flush but it removes the checkpointed state from the current CPU and
1560 * transitions the CPU out of TM mode. Hence we need to call
1561 * tm_recheckpoint_new_task() (on the same task) to restore the
1562 * checkpointed state back and the TM mode.
1564 * Can't pass dst because it isn't ready. Doesn't matter, passing
1565 * dst is only important for __switch_to()
1567 __switch_to_tm(src, src);
1571 clear_task_ebb(dst);
1576 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1578 #ifdef CONFIG_PPC_BOOK3S_64
1579 unsigned long sp_vsid;
1580 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1582 if (radix_enabled())
1585 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1586 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1587 << SLB_VSID_SHIFT_1T;
1589 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1591 sp_vsid |= SLB_VSID_KERNEL | llp;
1592 p->thread.ksp_vsid = sp_vsid;
1601 * Copy architecture-specific thread state
1603 int copy_thread(unsigned long clone_flags, unsigned long usp,
1604 unsigned long kthread_arg, struct task_struct *p)
1606 struct pt_regs *childregs, *kregs;
1607 extern void ret_from_fork(void);
1608 extern void ret_from_kernel_thread(void);
1610 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1611 struct thread_info *ti = task_thread_info(p);
1613 klp_init_thread_info(p);
1615 /* Copy registers */
1616 sp -= sizeof(struct pt_regs);
1617 childregs = (struct pt_regs *) sp;
1618 if (unlikely(p->flags & PF_KTHREAD)) {
1620 memset(childregs, 0, sizeof(struct pt_regs));
1621 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1624 childregs->gpr[14] = ppc_function_entry((void *)usp);
1626 clear_tsk_thread_flag(p, TIF_32BIT);
1627 childregs->softe = IRQS_ENABLED;
1629 childregs->gpr[15] = kthread_arg;
1630 p->thread.regs = NULL; /* no user register state */
1631 ti->flags |= _TIF_RESTOREALL;
1632 f = ret_from_kernel_thread;
1635 struct pt_regs *regs = current_pt_regs();
1636 CHECK_FULL_REGS(regs);
1639 childregs->gpr[1] = usp;
1640 p->thread.regs = childregs;
1641 childregs->gpr[3] = 0; /* Result from fork() */
1642 if (clone_flags & CLONE_SETTLS) {
1644 if (!is_32bit_task())
1645 childregs->gpr[13] = childregs->gpr[6];
1648 childregs->gpr[2] = childregs->gpr[6];
1653 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1654 sp -= STACK_FRAME_OVERHEAD;
1657 * The way this works is that at some point in the future
1658 * some task will call _switch to switch to the new task.
1659 * That will pop off the stack frame created below and start
1660 * the new task running at ret_from_fork. The new task will
1661 * do some house keeping and then return from the fork or clone
1662 * system call, using the stack frame created above.
1664 ((unsigned long *)sp)[0] = 0;
1665 sp -= sizeof(struct pt_regs);
1666 kregs = (struct pt_regs *) sp;
1667 sp -= STACK_FRAME_OVERHEAD;
1670 p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1672 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1673 p->thread.ptrace_bps[0] = NULL;
1676 p->thread.fp_save_area = NULL;
1677 #ifdef CONFIG_ALTIVEC
1678 p->thread.vr_save_area = NULL;
1681 setup_ksp_vsid(p, sp);
1684 if (cpu_has_feature(CPU_FTR_DSCR)) {
1685 p->thread.dscr_inherit = current->thread.dscr_inherit;
1686 p->thread.dscr = mfspr(SPRN_DSCR);
1688 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1689 childregs->ppr = DEFAULT_PPR;
1693 kregs->nip = ppc_function_entry(f);
1697 void preload_new_slb_context(unsigned long start, unsigned long sp);
1700 * Set up a thread for executing a new program
1702 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1705 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1707 #ifdef CONFIG_PPC_BOOK3S_64
1708 if (!radix_enabled())
1709 preload_new_slb_context(start, sp);
1714 * If we exec out of a kernel thread then thread.regs will not be
1717 if (!current->thread.regs) {
1718 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1719 current->thread.regs = regs - 1;
1722 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1724 * Clear any transactional state, we're exec()ing. The cause is
1725 * not important as there will never be a recheckpoint so it's not
1728 if (MSR_TM_SUSPENDED(mfmsr()))
1729 tm_reclaim_current(0);
1732 memset(regs->gpr, 0, sizeof(regs->gpr));
1740 * We have just cleared all the nonvolatile GPRs, so make
1741 * FULL_REGS(regs) return true. This is necessary to allow
1742 * ptrace to examine the thread immediately after exec.
1749 regs->msr = MSR_USER;
1751 if (!is_32bit_task()) {
1752 unsigned long entry;
1754 if (is_elf2_task()) {
1755 /* Look ma, no function descriptors! */
1760 * The latest iteration of the ABI requires that when
1761 * calling a function (at its global entry point),
1762 * the caller must ensure r12 holds the entry point
1763 * address (so that the function can quickly
1764 * establish addressability).
1766 regs->gpr[12] = start;
1767 /* Make sure that's restored on entry to userspace. */
1768 set_thread_flag(TIF_RESTOREALL);
1772 /* start is a relocated pointer to the function
1773 * descriptor for the elf _start routine. The first
1774 * entry in the function descriptor is the entry
1775 * address of _start and the second entry is the TOC
1776 * value we need to use.
1778 __get_user(entry, (unsigned long __user *)start);
1779 __get_user(toc, (unsigned long __user *)start+1);
1781 /* Check whether the e_entry function descriptor entries
1782 * need to be relocated before we can use them.
1784 if (load_addr != 0) {
1791 regs->msr = MSR_USER64;
1795 regs->msr = MSR_USER32;
1799 current->thread.used_vsr = 0;
1801 current->thread.load_slb = 0;
1802 current->thread.load_fp = 0;
1803 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1804 current->thread.fp_save_area = NULL;
1805 #ifdef CONFIG_ALTIVEC
1806 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1807 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1808 current->thread.vr_save_area = NULL;
1809 current->thread.vrsave = 0;
1810 current->thread.used_vr = 0;
1811 current->thread.load_vec = 0;
1812 #endif /* CONFIG_ALTIVEC */
1814 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1815 current->thread.acc = 0;
1816 current->thread.spefscr = 0;
1817 current->thread.used_spe = 0;
1818 #endif /* CONFIG_SPE */
1819 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1820 current->thread.tm_tfhar = 0;
1821 current->thread.tm_texasr = 0;
1822 current->thread.tm_tfiar = 0;
1823 current->thread.load_tm = 0;
1824 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1826 thread_pkey_regs_init(¤t->thread);
1828 EXPORT_SYMBOL(start_thread);
1830 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1831 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1833 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1835 struct pt_regs *regs = tsk->thread.regs;
1837 /* This is a bit hairy. If we are an SPE enabled processor
1838 * (have embedded fp) we store the IEEE exception enable flags in
1839 * fpexc_mode. fpexc_mode is also used for setting FP exception
1840 * mode (asyn, precise, disabled) for 'Classic' FP. */
1841 if (val & PR_FP_EXC_SW_ENABLE) {
1843 if (cpu_has_feature(CPU_FTR_SPE)) {
1845 * When the sticky exception bits are set
1846 * directly by userspace, it must call prctl
1847 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1848 * in the existing prctl settings) or
1849 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1850 * the bits being set). <fenv.h> functions
1851 * saving and restoring the whole
1852 * floating-point environment need to do so
1853 * anyway to restore the prctl settings from
1854 * the saved environment.
1856 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1857 tsk->thread.fpexc_mode = val &
1858 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1868 /* on a CONFIG_SPE this does not hurt us. The bits that
1869 * __pack_fe01 use do not overlap with bits used for
1870 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1871 * on CONFIG_SPE implementations are reserved so writing to
1872 * them does not change anything */
1873 if (val > PR_FP_EXC_PRECISE)
1875 tsk->thread.fpexc_mode = __pack_fe01(val);
1876 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1877 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1878 | tsk->thread.fpexc_mode;
1882 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1886 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1888 if (cpu_has_feature(CPU_FTR_SPE)) {
1890 * When the sticky exception bits are set
1891 * directly by userspace, it must call prctl
1892 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1893 * in the existing prctl settings) or
1894 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1895 * the bits being set). <fenv.h> functions
1896 * saving and restoring the whole
1897 * floating-point environment need to do so
1898 * anyway to restore the prctl settings from
1899 * the saved environment.
1901 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1902 val = tsk->thread.fpexc_mode;
1909 val = __unpack_fe01(tsk->thread.fpexc_mode);
1910 return put_user(val, (unsigned int __user *) adr);
1913 int set_endian(struct task_struct *tsk, unsigned int val)
1915 struct pt_regs *regs = tsk->thread.regs;
1917 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1918 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1924 if (val == PR_ENDIAN_BIG)
1925 regs->msr &= ~MSR_LE;
1926 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1927 regs->msr |= MSR_LE;
1934 int get_endian(struct task_struct *tsk, unsigned long adr)
1936 struct pt_regs *regs = tsk->thread.regs;
1939 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1940 !cpu_has_feature(CPU_FTR_REAL_LE))
1946 if (regs->msr & MSR_LE) {
1947 if (cpu_has_feature(CPU_FTR_REAL_LE))
1948 val = PR_ENDIAN_LITTLE;
1950 val = PR_ENDIAN_PPC_LITTLE;
1952 val = PR_ENDIAN_BIG;
1954 return put_user(val, (unsigned int __user *)adr);
1957 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1959 tsk->thread.align_ctl = val;
1963 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1965 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1968 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1969 unsigned long nbytes)
1971 unsigned long stack_page;
1972 unsigned long cpu = task_cpu(p);
1974 stack_page = (unsigned long)hardirq_ctx[cpu];
1975 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1978 stack_page = (unsigned long)softirq_ctx[cpu];
1979 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1985 int validate_sp(unsigned long sp, struct task_struct *p,
1986 unsigned long nbytes)
1988 unsigned long stack_page = (unsigned long)task_stack_page(p);
1990 if (sp < THREAD_SIZE)
1993 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1996 return valid_irq_stack(sp, p, nbytes);
1999 EXPORT_SYMBOL(validate_sp);
2001 static unsigned long __get_wchan(struct task_struct *p)
2003 unsigned long ip, sp;
2006 if (!p || p == current || p->state == TASK_RUNNING)
2010 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2014 sp = *(unsigned long *)sp;
2015 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2016 p->state == TASK_RUNNING)
2019 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2020 if (!in_sched_functions(ip))
2023 } while (count++ < 16);
2027 unsigned long get_wchan(struct task_struct *p)
2031 if (!try_get_task_stack(p))
2034 ret = __get_wchan(p);
2041 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2043 void show_stack(struct task_struct *tsk, unsigned long *stack)
2045 unsigned long sp, ip, lr, newsp;
2048 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2049 struct ftrace_ret_stack *ret_stack;
2050 extern void return_to_handler(void);
2051 unsigned long rth = (unsigned long)return_to_handler;
2058 if (!try_get_task_stack(tsk))
2061 sp = (unsigned long) stack;
2064 sp = current_stack_pointer();
2066 sp = tsk->thread.ksp;
2070 printk("Call Trace:\n");
2072 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2075 stack = (unsigned long *) sp;
2077 ip = stack[STACK_FRAME_LR_SAVE];
2078 if (!firstframe || ip != lr) {
2079 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2080 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2081 if ((ip == rth) && curr_frame >= 0) {
2082 ret_stack = ftrace_graph_get_ret_stack(current,
2086 (void *)ret_stack->ret);
2092 pr_cont(" (unreliable)");
2098 * See if this is an exception frame.
2099 * We look for the "regshere" marker in the current frame.
2101 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2102 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2103 struct pt_regs *regs = (struct pt_regs *)
2104 (sp + STACK_FRAME_OVERHEAD);
2106 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2107 regs->trap, (void *)regs->nip, (void *)lr);
2112 } while (count++ < kstack_depth_to_print);
2114 put_task_stack(tsk);
2118 /* Called with hard IRQs off */
2119 void notrace __ppc64_runlatch_on(void)
2121 struct thread_info *ti = current_thread_info();
2123 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2125 * Least significant bit (RUN) is the only writable bit of
2126 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2127 * earliest ISA where this is the case, but it's convenient.
2129 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2134 * Some architectures (e.g., Cell) have writable fields other
2135 * than RUN, so do the read-modify-write.
2137 ctrl = mfspr(SPRN_CTRLF);
2138 ctrl |= CTRL_RUNLATCH;
2139 mtspr(SPRN_CTRLT, ctrl);
2142 ti->local_flags |= _TLF_RUNLATCH;
2145 /* Called with hard IRQs off */
2146 void notrace __ppc64_runlatch_off(void)
2148 struct thread_info *ti = current_thread_info();
2150 ti->local_flags &= ~_TLF_RUNLATCH;
2152 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2153 mtspr(SPRN_CTRLT, 0);
2157 ctrl = mfspr(SPRN_CTRLF);
2158 ctrl &= ~CTRL_RUNLATCH;
2159 mtspr(SPRN_CTRLT, ctrl);
2162 #endif /* CONFIG_PPC64 */
2164 unsigned long arch_align_stack(unsigned long sp)
2166 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2167 sp -= get_random_int() & ~PAGE_MASK;
2171 static inline unsigned long brk_rnd(void)
2173 unsigned long rnd = 0;
2175 /* 8MB for 32bit, 1GB for 64bit */
2176 if (is_32bit_task())
2177 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2179 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2181 return rnd << PAGE_SHIFT;
2184 unsigned long arch_randomize_brk(struct mm_struct *mm)
2186 unsigned long base = mm->brk;
2189 #ifdef CONFIG_PPC_BOOK3S_64
2191 * If we are using 1TB segments and we are allowed to randomise
2192 * the heap, we can put it above 1TB so it is backed by a 1TB
2193 * segment. Otherwise the heap will be in the bottom 1TB
2194 * which always uses 256MB segments and this may result in a
2195 * performance penalty. We don't need to worry about radix. For
2196 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2198 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2199 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2202 ret = PAGE_ALIGN(base + brk_rnd());