2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = slab_is_available();
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
93 void pcibios_free_controller(struct pci_controller *phb)
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 struct pci_controller *phb = pci_bus_to_host(bus);
114 if (phb->controller_ops.window_alignment)
115 return phb->controller_ops.window_alignment(bus, type);
118 * PCI core will figure out the default
119 * alignment: 4KiB for I/O and 1MiB for
125 void pcibios_reset_secondary_bus(struct pci_dev *dev)
127 struct pci_controller *phb = pci_bus_to_host(dev->bus);
129 if (phb->controller_ops.reset_secondary_bus) {
130 phb->controller_ops.reset_secondary_bus(dev);
134 pci_reset_secondary_bus(dev);
137 #ifdef CONFIG_PCI_IOV
138 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
140 if (ppc_md.pcibios_iov_resource_alignment)
141 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
143 return pci_iov_resource_size(pdev, resno);
145 #endif /* CONFIG_PCI_IOV */
147 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
150 return hose->pci_io_size;
152 return resource_size(&hose->io_resource);
156 int pcibios_vaddr_is_ioport(void __iomem *address)
159 struct pci_controller *hose;
160 resource_size_t size;
162 spin_lock(&hose_spinlock);
163 list_for_each_entry(hose, &hose_list, list_node) {
164 size = pcibios_io_size(hose);
165 if (address >= hose->io_base_virt &&
166 address < (hose->io_base_virt + size)) {
171 spin_unlock(&hose_spinlock);
175 unsigned long pci_address_to_pio(phys_addr_t address)
177 struct pci_controller *hose;
178 resource_size_t size;
179 unsigned long ret = ~0;
181 spin_lock(&hose_spinlock);
182 list_for_each_entry(hose, &hose_list, list_node) {
183 size = pcibios_io_size(hose);
184 if (address >= hose->io_base_phys &&
185 address < (hose->io_base_phys + size)) {
187 (unsigned long)hose->io_base_virt - _IO_BASE;
188 ret = base + (address - hose->io_base_phys);
192 spin_unlock(&hose_spinlock);
196 EXPORT_SYMBOL_GPL(pci_address_to_pio);
199 * Return the domain number for this bus.
201 int pci_domain_nr(struct pci_bus *bus)
203 struct pci_controller *hose = pci_bus_to_host(bus);
205 return hose->global_number;
207 EXPORT_SYMBOL(pci_domain_nr);
209 /* This routine is meant to be used early during boot, when the
210 * PCI bus numbers have not yet been assigned, and you need to
211 * issue PCI config cycles to an OF device.
212 * It could also be used to "fix" RTAS config cycles if you want
213 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
216 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
219 struct pci_controller *hose, *tmp;
220 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
221 if (hose->dn == node)
229 * Reads the interrupt pin to determine if interrupt is use by card.
230 * If the interrupt is used, then gets the interrupt line from the
231 * openfirmware and sets it in the pci_dev and pci_config line.
233 static int pci_read_irq_line(struct pci_dev *pci_dev)
235 struct of_phandle_args oirq;
238 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
241 memset(&oirq, 0xff, sizeof(oirq));
243 /* Try to get a mapping from the device-tree */
244 if (of_irq_parse_pci(pci_dev, &oirq)) {
247 /* If that fails, lets fallback to what is in the config
248 * space and map that through the default controller. We
249 * also set the type to level low since that's what PCI
250 * interrupts are. If your platform does differently, then
251 * either provide a proper interrupt tree or don't use this
254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
258 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
259 line == 0xff || line == 0) {
262 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
265 virq = irq_create_mapping(NULL, line);
267 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
269 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
270 oirq.args_count, oirq.args[0], oirq.args[1],
271 of_node_full_name(oirq.np));
273 virq = irq_create_of_mapping(&oirq);
276 pr_debug(" Failed to map !\n");
280 pr_debug(" Mapped to linux irq %d\n", virq);
288 * Platform support for /proc/bus/pci/X/Y mmap()s,
289 * modelled on the sparc64 implementation by Dave Miller.
294 * Adjust vm_pgoff of VMA such that it is the physical page offset
295 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
297 * Basically, the user finds the base address for his device which he wishes
298 * to mmap. They read the 32-bit value from the config space base register,
299 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
300 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
302 * Returns negative error code on failure, zero on success.
304 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
305 resource_size_t *offset,
306 enum pci_mmap_state mmap_state)
308 struct pci_controller *hose = pci_bus_to_host(dev->bus);
309 unsigned long io_offset = 0;
313 return NULL; /* should never happen */
315 /* If memory, add on the PCI bridge address offset */
316 if (mmap_state == pci_mmap_mem) {
317 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
318 *offset += hose->pci_mem_offset;
320 res_bit = IORESOURCE_MEM;
322 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
323 *offset += io_offset;
324 res_bit = IORESOURCE_IO;
328 * Check that the offset requested corresponds to one of the
329 * resources of the device.
331 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
332 struct resource *rp = &dev->resource[i];
333 int flags = rp->flags;
335 /* treat ROM as memory (should be already) */
336 if (i == PCI_ROM_RESOURCE)
337 flags |= IORESOURCE_MEM;
339 /* Active and same type? */
340 if ((flags & res_bit) == 0)
343 /* In the range of this resource? */
344 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
347 /* found it! construct the final physical address */
348 if (mmap_state == pci_mmap_io)
349 *offset += hose->io_base_phys - io_offset;
357 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
360 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
362 enum pci_mmap_state mmap_state,
366 /* Write combine is always 0 on non-memory space mappings. On
367 * memory space, if the user didn't pass 1, we check for a
368 * "prefetchable" resource. This is a bit hackish, but we use
369 * this to workaround the inability of /sysfs to provide a write
372 if (mmap_state != pci_mmap_mem)
374 else if (write_combine == 0) {
375 if (rp->flags & IORESOURCE_PREFETCH)
379 /* XXX would be nice to have a way to ask for write-through */
381 return pgprot_noncached_wc(protection);
383 return pgprot_noncached(protection);
387 * This one is used by /dev/mem and fbdev who have no clue about the
388 * PCI device, it tries to find the PCI device first and calls the
391 pgprot_t pci_phys_mem_access_prot(struct file *file,
396 struct pci_dev *pdev = NULL;
397 struct resource *found = NULL;
398 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
401 if (page_is_ram(pfn))
404 prot = pgprot_noncached(prot);
405 for_each_pci_dev(pdev) {
406 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
407 struct resource *rp = &pdev->resource[i];
408 int flags = rp->flags;
410 /* Active and same type? */
411 if ((flags & IORESOURCE_MEM) == 0)
413 /* In the range of this resource? */
414 if (offset < (rp->start & PAGE_MASK) ||
424 if (found->flags & IORESOURCE_PREFETCH)
425 prot = pgprot_noncached_wc(prot);
429 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
430 (unsigned long long)offset, pgprot_val(prot));
437 * Perform the actual remap of the pages for a PCI device mapping, as
438 * appropriate for this architecture. The region in the process to map
439 * is described by vm_start and vm_end members of VMA, the base physical
440 * address is found in vm_pgoff.
441 * The pci device structure is provided so that architectures may make mapping
442 * decisions on a per-device or per-bus basis.
444 * Returns a negative error code on failure, zero on success.
446 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
447 enum pci_mmap_state mmap_state, int write_combine)
449 resource_size_t offset =
450 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
454 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
458 vma->vm_pgoff = offset >> PAGE_SHIFT;
459 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
461 mmap_state, write_combine);
463 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
464 vma->vm_end - vma->vm_start, vma->vm_page_prot);
469 /* This provides legacy IO read access on a bus */
470 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
472 unsigned long offset;
473 struct pci_controller *hose = pci_bus_to_host(bus);
474 struct resource *rp = &hose->io_resource;
477 /* Check if port can be supported by that bus. We only check
478 * the ranges of the PHB though, not the bus itself as the rules
479 * for forwarding legacy cycles down bridges are not our problem
480 * here. So if the host bridge supports it, we do it.
482 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
485 if (!(rp->flags & IORESOURCE_IO))
487 if (offset < rp->start || (offset + size) > rp->end)
489 addr = hose->io_base_virt + port;
493 *((u8 *)val) = in_8(addr);
498 *((u16 *)val) = in_le16(addr);
503 *((u32 *)val) = in_le32(addr);
509 /* This provides legacy IO write access on a bus */
510 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
512 unsigned long offset;
513 struct pci_controller *hose = pci_bus_to_host(bus);
514 struct resource *rp = &hose->io_resource;
517 /* Check if port can be supported by that bus. We only check
518 * the ranges of the PHB though, not the bus itself as the rules
519 * for forwarding legacy cycles down bridges are not our problem
520 * here. So if the host bridge supports it, we do it.
522 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
525 if (!(rp->flags & IORESOURCE_IO))
527 if (offset < rp->start || (offset + size) > rp->end)
529 addr = hose->io_base_virt + port;
531 /* WARNING: The generic code is idiotic. It gets passed a pointer
532 * to what can be a 1, 2 or 4 byte quantity and always reads that
533 * as a u32, which means that we have to correct the location of
534 * the data read within those 32 bits for size 1 and 2
538 out_8(addr, val >> 24);
543 out_le16(addr, val >> 16);
554 /* This provides legacy IO or memory mmap access on a bus */
555 int pci_mmap_legacy_page_range(struct pci_bus *bus,
556 struct vm_area_struct *vma,
557 enum pci_mmap_state mmap_state)
559 struct pci_controller *hose = pci_bus_to_host(bus);
560 resource_size_t offset =
561 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
562 resource_size_t size = vma->vm_end - vma->vm_start;
565 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
566 pci_domain_nr(bus), bus->number,
567 mmap_state == pci_mmap_mem ? "MEM" : "IO",
568 (unsigned long long)offset,
569 (unsigned long long)(offset + size - 1));
571 if (mmap_state == pci_mmap_mem) {
574 * Because X is lame and can fail starting if it gets an error trying
575 * to mmap legacy_mem (instead of just moving on without legacy memory
576 * access) we fake it here by giving it anonymous memory, effectively
577 * behaving just like /dev/zero
579 if ((offset + size) > hose->isa_mem_size) {
581 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
582 current->comm, current->pid, pci_domain_nr(bus), bus->number);
583 if (vma->vm_flags & VM_SHARED)
584 return shmem_zero_setup(vma);
587 offset += hose->isa_mem_phys;
589 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
590 unsigned long roffset = offset + io_offset;
591 rp = &hose->io_resource;
592 if (!(rp->flags & IORESOURCE_IO))
594 if (roffset < rp->start || (roffset + size) > rp->end)
596 offset += hose->io_base_phys;
598 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
600 vma->vm_pgoff = offset >> PAGE_SHIFT;
601 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
602 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
603 vma->vm_end - vma->vm_start,
607 void pci_resource_to_user(const struct pci_dev *dev, int bar,
608 const struct resource *rsrc,
609 resource_size_t *start, resource_size_t *end)
611 struct pci_controller *hose = pci_bus_to_host(dev->bus);
612 resource_size_t offset = 0;
617 if (rsrc->flags & IORESOURCE_IO)
618 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
620 /* We pass a fully fixed up address to userland for MMIO instead of
621 * a BAR value because X is lame and expects to be able to use that
622 * to pass to /dev/mem !
624 * That means that we'll have potentially 64 bits values where some
625 * userland apps only expect 32 (like X itself since it thinks only
626 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
629 * Hopefully, the sysfs insterface is immune to that gunk. Once X
630 * has been fixed (and the fix spread enough), we can re-enable the
631 * 2 lines below and pass down a BAR value to userland. In that case
632 * we'll also have to re-enable the matching code in
633 * __pci_mmap_make_offset().
638 else if (rsrc->flags & IORESOURCE_MEM)
639 offset = hose->pci_mem_offset;
642 *start = rsrc->start - offset;
643 *end = rsrc->end - offset;
647 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
648 * @hose: newly allocated pci_controller to be setup
649 * @dev: device node of the host bridge
650 * @primary: set if primary bus (32 bits only, soon to be deprecated)
652 * This function will parse the "ranges" property of a PCI host bridge device
653 * node and setup the resource mapping of a pci controller based on its
656 * Life would be boring if it wasn't for a few issues that we have to deal
659 * - We can only cope with one IO space range and up to 3 Memory space
660 * ranges. However, some machines (thanks Apple !) tend to split their
661 * space into lots of small contiguous ranges. So we have to coalesce.
663 * - Some busses have IO space not starting at 0, which causes trouble with
664 * the way we do our IO resource renumbering. The code somewhat deals with
665 * it for 64 bits but I would expect problems on 32 bits.
667 * - Some 32 bits platforms such as 4xx can have physical space larger than
668 * 32 bits so we need to use 64 bits values for the parsing
670 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
671 struct device_node *dev, int primary)
674 struct resource *res;
675 struct of_pci_range range;
676 struct of_pci_range_parser parser;
678 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
679 dev->full_name, primary ? "(primary)" : "");
681 /* Check for ranges property */
682 if (of_pci_range_parser_init(&parser, dev))
686 for_each_of_pci_range(&parser, &range) {
687 /* If we failed translation or got a zero-sized region
688 * (some FW try to feed us with non sensical zero sized regions
689 * such as power3 which look like some kind of attempt at exposing
690 * the VGA memory hole)
692 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
695 /* Act based on address space type */
697 switch (range.flags & IORESOURCE_TYPE_BITS) {
700 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
701 range.cpu_addr, range.cpu_addr + range.size - 1,
704 /* We support only one IO range */
705 if (hose->pci_io_size) {
707 " \\--> Skipped (too many) !\n");
711 /* On 32 bits, limit I/O space to 16MB */
712 if (range.size > 0x01000000)
713 range.size = 0x01000000;
715 /* 32 bits needs to map IOs here */
716 hose->io_base_virt = ioremap(range.cpu_addr,
719 /* Expect trouble if pci_addr is not 0 */
722 (unsigned long)hose->io_base_virt;
723 #endif /* CONFIG_PPC32 */
724 /* pci_io_size and io_base_phys always represent IO
725 * space starting at 0 so we factor in pci_addr
727 hose->pci_io_size = range.pci_addr + range.size;
728 hose->io_base_phys = range.cpu_addr - range.pci_addr;
731 res = &hose->io_resource;
732 range.cpu_addr = range.pci_addr;
736 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
737 range.cpu_addr, range.cpu_addr + range.size - 1,
739 (range.pci_space & 0x40000000) ?
742 /* We support only 3 memory ranges */
745 " \\--> Skipped (too many) !\n");
748 /* Handles ISA memory hole space here */
749 if (range.pci_addr == 0) {
750 if (primary || isa_mem_base == 0)
751 isa_mem_base = range.cpu_addr;
752 hose->isa_mem_phys = range.cpu_addr;
753 hose->isa_mem_size = range.size;
757 hose->mem_offset[memno] = range.cpu_addr -
759 res = &hose->mem_resources[memno++];
763 res->name = dev->full_name;
764 res->flags = range.flags;
765 res->start = range.cpu_addr;
766 res->end = range.cpu_addr + range.size - 1;
767 res->parent = res->child = res->sibling = NULL;
772 /* Decide whether to display the domain number in /proc */
773 int pci_proc_domain(struct pci_bus *bus)
775 struct pci_controller *hose = pci_bus_to_host(bus);
777 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
779 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
780 return hose->global_number != 0;
784 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
786 if (ppc_md.pcibios_root_bridge_prepare)
787 return ppc_md.pcibios_root_bridge_prepare(bridge);
792 /* This header fixup will do the resource fixup for all devices as they are
793 * probed, but not for bridge ranges
795 static void pcibios_fixup_resources(struct pci_dev *dev)
797 struct pci_controller *hose = pci_bus_to_host(dev->bus);
801 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
809 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
810 struct resource *res = dev->resource + i;
811 struct pci_bus_region reg;
815 /* If we're going to re-assign everything, we mark all resources
816 * as unset (and 0-base them). In addition, we mark BARs starting
817 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
818 * since in that case, we don't want to re-assign anything
820 pcibios_resource_to_bus(dev->bus, ®, res);
821 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
822 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
823 /* Only print message if not re-assigning */
824 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
825 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
828 (unsigned long long)res->start,
829 (unsigned long long)res->end,
830 (unsigned int)res->flags);
831 res->end -= res->start;
833 res->flags |= IORESOURCE_UNSET;
837 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
839 (unsigned long long)res->start,\
840 (unsigned long long)res->end,
841 (unsigned int)res->flags);
844 /* Call machine specific resource fixup */
845 if (ppc_md.pcibios_fixup_resources)
846 ppc_md.pcibios_fixup_resources(dev);
848 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
850 /* This function tries to figure out if a bridge resource has been initialized
851 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
852 * things go more smoothly when it gets it right. It should covers cases such
853 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
855 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
856 struct resource *res)
858 struct pci_controller *hose = pci_bus_to_host(bus);
859 struct pci_dev *dev = bus->self;
860 resource_size_t offset;
861 struct pci_bus_region region;
865 /* We don't do anything if PCI_PROBE_ONLY is set */
866 if (pci_has_flag(PCI_PROBE_ONLY))
869 /* Job is a bit different between memory and IO */
870 if (res->flags & IORESOURCE_MEM) {
871 pcibios_resource_to_bus(dev->bus, ®ion, res);
873 /* If the BAR is non-0 then it's probably been initialized */
874 if (region.start != 0)
877 /* The BAR is 0, let's check if memory decoding is enabled on
878 * the bridge. If not, we consider it unassigned
880 pci_read_config_word(dev, PCI_COMMAND, &command);
881 if ((command & PCI_COMMAND_MEMORY) == 0)
884 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
885 * resources covers that starting address (0 then it's good enough for
886 * us for memory space)
888 for (i = 0; i < 3; i++) {
889 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
890 hose->mem_resources[i].start == hose->mem_offset[i])
894 /* Well, it starts at 0 and we know it will collide so we may as
895 * well consider it as unassigned. That covers the Apple case.
899 /* If the BAR is non-0, then we consider it assigned */
900 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
901 if (((res->start - offset) & 0xfffffffful) != 0)
904 /* Here, we are a bit different than memory as typically IO space
905 * starting at low addresses -is- valid. What we do instead if that
906 * we consider as unassigned anything that doesn't have IO enabled
907 * in the PCI command register, and that's it.
909 pci_read_config_word(dev, PCI_COMMAND, &command);
910 if (command & PCI_COMMAND_IO)
913 /* It's starting at 0 and IO is disabled in the bridge, consider
920 /* Fixup resources of a PCI<->PCI bridge */
921 static void pcibios_fixup_bridge(struct pci_bus *bus)
923 struct resource *res;
926 struct pci_dev *dev = bus->self;
928 pci_bus_for_each_resource(bus, res, i) {
929 if (!res || !res->flags)
931 if (i >= 3 && bus->self->transparent)
934 /* If we're going to reassign everything, we can
935 * shrink the P2P resource to have size as being
936 * of 0 in order to save space.
938 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
939 res->flags |= IORESOURCE_UNSET;
945 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
947 (unsigned long long)res->start,\
948 (unsigned long long)res->end,
949 (unsigned int)res->flags);
951 /* Try to detect uninitialized P2P bridge resources,
952 * and clear them out so they get re-assigned later
954 if (pcibios_uninitialized_bridge_resource(bus, res)) {
956 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
961 void pcibios_setup_bus_self(struct pci_bus *bus)
963 struct pci_controller *phb;
965 /* Fix up the bus resources for P2P bridges */
966 if (bus->self != NULL)
967 pcibios_fixup_bridge(bus);
969 /* Platform specific bus fixups. This is currently only used
970 * by fsl_pci and I'm hoping to get rid of it at some point
972 if (ppc_md.pcibios_fixup_bus)
973 ppc_md.pcibios_fixup_bus(bus);
975 /* Setup bus DMA mappings */
976 phb = pci_bus_to_host(bus);
977 if (phb->controller_ops.dma_bus_setup)
978 phb->controller_ops.dma_bus_setup(bus);
981 static void pcibios_setup_device(struct pci_dev *dev)
983 struct pci_controller *phb;
984 /* Fixup NUMA node as it may not be setup yet by the generic
985 * code and is needed by the DMA init
987 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
989 /* Hook up default DMA ops */
990 set_dma_ops(&dev->dev, pci_dma_ops);
991 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
993 /* Additional platform DMA/iommu setup */
994 phb = pci_bus_to_host(dev->bus);
995 if (phb->controller_ops.dma_dev_setup)
996 phb->controller_ops.dma_dev_setup(dev);
998 /* Read default IRQs and fixup if necessary */
999 pci_read_irq_line(dev);
1000 if (ppc_md.pci_irq_fixup)
1001 ppc_md.pci_irq_fixup(dev);
1004 int pcibios_add_device(struct pci_dev *dev)
1007 * We can only call pcibios_setup_device() after bus setup is complete,
1008 * since some of the platform specific DMA setup code depends on it.
1010 if (dev->bus->is_added)
1011 pcibios_setup_device(dev);
1013 #ifdef CONFIG_PCI_IOV
1014 if (ppc_md.pcibios_fixup_sriov)
1015 ppc_md.pcibios_fixup_sriov(dev);
1016 #endif /* CONFIG_PCI_IOV */
1021 void pcibios_setup_bus_devices(struct pci_bus *bus)
1023 struct pci_dev *dev;
1025 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1026 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1028 list_for_each_entry(dev, &bus->devices, bus_list) {
1029 /* Cardbus can call us to add new devices to a bus, so ignore
1030 * those who are already fully discovered
1035 pcibios_setup_device(dev);
1039 void pcibios_set_master(struct pci_dev *dev)
1041 /* No special bus mastering setup handling */
1044 void pcibios_fixup_bus(struct pci_bus *bus)
1046 /* When called from the generic PCI probe, read PCI<->PCI bridge
1047 * bases. This is -not- called when generating the PCI tree from
1048 * the OF device-tree.
1050 pci_read_bridge_bases(bus);
1052 /* Now fixup the bus bus */
1053 pcibios_setup_bus_self(bus);
1055 /* Now fixup devices on that bus */
1056 pcibios_setup_bus_devices(bus);
1058 EXPORT_SYMBOL(pcibios_fixup_bus);
1060 void pci_fixup_cardbus(struct pci_bus *bus)
1062 /* Now fixup devices on that bus */
1063 pcibios_setup_bus_devices(bus);
1067 static int skip_isa_ioresource_align(struct pci_dev *dev)
1069 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1070 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1076 * We need to avoid collisions with `mirrored' VGA ports
1077 * and other strange ISA hardware, so we always want the
1078 * addresses to be allocated in the 0x000-0x0ff region
1081 * Why? Because some silly external IO cards only decode
1082 * the low 10 bits of the IO address. The 0x00-0xff region
1083 * is reserved for motherboard devices that decode all 16
1084 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1085 * but we want to try to avoid allocating at 0x2900-0x2bff
1086 * which might have be mirrored at 0x0100-0x03ff..
1088 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1089 resource_size_t size, resource_size_t align)
1091 struct pci_dev *dev = data;
1092 resource_size_t start = res->start;
1094 if (res->flags & IORESOURCE_IO) {
1095 if (skip_isa_ioresource_align(dev))
1098 start = (start + 0x3ff) & ~0x3ff;
1103 EXPORT_SYMBOL(pcibios_align_resource);
1106 * Reparent resource children of pr that conflict with res
1107 * under res, and make res replace those children.
1109 static int reparent_resources(struct resource *parent,
1110 struct resource *res)
1112 struct resource *p, **pp;
1113 struct resource **firstpp = NULL;
1115 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1116 if (p->end < res->start)
1118 if (res->end < p->start)
1120 if (p->start < res->start || p->end > res->end)
1121 return -1; /* not completely contained */
1122 if (firstpp == NULL)
1125 if (firstpp == NULL)
1126 return -1; /* didn't find any conflicting entries? */
1127 res->parent = parent;
1128 res->child = *firstpp;
1132 for (p = res->child; p != NULL; p = p->sibling) {
1134 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1136 (unsigned long long)p->start,
1137 (unsigned long long)p->end, res->name);
1143 * Handle resources of PCI devices. If the world were perfect, we could
1144 * just allocate all the resource regions and do nothing more. It isn't.
1145 * On the other hand, we cannot just re-allocate all devices, as it would
1146 * require us to know lots of host bridge internals. So we attempt to
1147 * keep as much of the original configuration as possible, but tweak it
1148 * when it's found to be wrong.
1150 * Known BIOS problems we have to work around:
1151 * - I/O or memory regions not configured
1152 * - regions configured, but not enabled in the command register
1153 * - bogus I/O addresses above 64K used
1154 * - expansion ROMs left enabled (this may sound harmless, but given
1155 * the fact the PCI specs explicitly allow address decoders to be
1156 * shared between expansion ROMs and other resource regions, it's
1157 * at least dangerous)
1160 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1161 * This gives us fixed barriers on where we can allocate.
1162 * (2) Allocate resources for all enabled devices. If there is
1163 * a collision, just mark the resource as unallocated. Also
1164 * disable expansion ROMs during this step.
1165 * (3) Try to allocate resources for disabled devices. If the
1166 * resources were assigned correctly, everything goes well,
1167 * if they weren't, they won't disturb allocation of other
1169 * (4) Assign new addresses to resources which were either
1170 * not configured at all or misconfigured. If explicitly
1171 * requested by the user, configure expansion ROM address
1175 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1179 struct resource *res, *pr;
1181 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1182 pci_domain_nr(bus), bus->number);
1184 pci_bus_for_each_resource(bus, res, i) {
1185 if (!res || !res->flags || res->start > res->end || res->parent)
1188 /* If the resource was left unset at this point, we clear it */
1189 if (res->flags & IORESOURCE_UNSET)
1190 goto clear_resource;
1192 if (bus->parent == NULL)
1193 pr = (res->flags & IORESOURCE_IO) ?
1194 &ioport_resource : &iomem_resource;
1196 pr = pci_find_parent_resource(bus->self, res);
1198 /* this happens when the generic PCI
1199 * code (wrongly) decides that this
1200 * bridge is transparent -- paulus
1206 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1207 "[0x%x], parent %p (%s)\n",
1208 bus->self ? pci_name(bus->self) : "PHB",
1210 (unsigned long long)res->start,
1211 (unsigned long long)res->end,
1212 (unsigned int)res->flags,
1213 pr, (pr && pr->name) ? pr->name : "nil");
1215 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1216 struct pci_dev *dev = bus->self;
1218 if (request_resource(pr, res) == 0)
1221 * Must be a conflict with an existing entry.
1222 * Move that entry (or entries) under the
1223 * bridge resource and try again.
1225 if (reparent_resources(pr, res) == 0)
1228 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1229 pci_claim_bridge_resource(dev,
1230 i + PCI_BRIDGE_RESOURCES) == 0)
1233 pr_warning("PCI: Cannot allocate resource region "
1234 "%d of PCI bridge %d, will remap\n", i, bus->number);
1236 /* The resource might be figured out when doing
1237 * reassignment based on the resources required
1238 * by the downstream PCI devices. Here we set
1239 * the size of the resource to be 0 in order to
1247 list_for_each_entry(b, &bus->children, node)
1248 pcibios_allocate_bus_resources(b);
1251 static inline void alloc_resource(struct pci_dev *dev, int idx)
1253 struct resource *pr, *r = &dev->resource[idx];
1255 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1257 (unsigned long long)r->start,
1258 (unsigned long long)r->end,
1259 (unsigned int)r->flags);
1261 pr = pci_find_parent_resource(dev, r);
1262 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1263 request_resource(pr, r) < 0) {
1264 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1265 " of device %s, will remap\n", idx, pci_name(dev));
1267 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1269 (unsigned long long)pr->start,
1270 (unsigned long long)pr->end,
1271 (unsigned int)pr->flags);
1272 /* We'll assign a new address later */
1273 r->flags |= IORESOURCE_UNSET;
1279 static void __init pcibios_allocate_resources(int pass)
1281 struct pci_dev *dev = NULL;
1286 for_each_pci_dev(dev) {
1287 pci_read_config_word(dev, PCI_COMMAND, &command);
1288 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1289 r = &dev->resource[idx];
1290 if (r->parent) /* Already allocated */
1292 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1293 continue; /* Not assigned at all */
1294 /* We only allocate ROMs on pass 1 just in case they
1295 * have been screwed up by firmware
1297 if (idx == PCI_ROM_RESOURCE )
1299 if (r->flags & IORESOURCE_IO)
1300 disabled = !(command & PCI_COMMAND_IO);
1302 disabled = !(command & PCI_COMMAND_MEMORY);
1303 if (pass == disabled)
1304 alloc_resource(dev, idx);
1308 r = &dev->resource[PCI_ROM_RESOURCE];
1310 /* Turn the ROM off, leave the resource region,
1311 * but keep it unregistered.
1314 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1315 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1316 pr_debug("PCI: Switching off ROM of %s\n",
1318 r->flags &= ~IORESOURCE_ROM_ENABLE;
1319 pci_write_config_dword(dev, dev->rom_base_reg,
1320 reg & ~PCI_ROM_ADDRESS_ENABLE);
1326 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1328 struct pci_controller *hose = pci_bus_to_host(bus);
1329 resource_size_t offset;
1330 struct resource *res, *pres;
1333 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1336 if (!(hose->io_resource.flags & IORESOURCE_IO))
1338 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1339 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1340 BUG_ON(res == NULL);
1341 res->name = "Legacy IO";
1342 res->flags = IORESOURCE_IO;
1343 res->start = offset;
1344 res->end = (offset + 0xfff) & 0xfffffffful;
1345 pr_debug("Candidate legacy IO: %pR\n", res);
1346 if (request_resource(&hose->io_resource, res)) {
1348 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1349 pci_domain_nr(bus), bus->number, res);
1354 /* Check for memory */
1355 for (i = 0; i < 3; i++) {
1356 pres = &hose->mem_resources[i];
1357 offset = hose->mem_offset[i];
1358 if (!(pres->flags & IORESOURCE_MEM))
1360 pr_debug("hose mem res: %pR\n", pres);
1361 if ((pres->start - offset) <= 0xa0000 &&
1362 (pres->end - offset) >= 0xbffff)
1367 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1368 BUG_ON(res == NULL);
1369 res->name = "Legacy VGA memory";
1370 res->flags = IORESOURCE_MEM;
1371 res->start = 0xa0000 + offset;
1372 res->end = 0xbffff + offset;
1373 pr_debug("Candidate VGA memory: %pR\n", res);
1374 if (request_resource(pres, res)) {
1376 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1377 pci_domain_nr(bus), bus->number, res);
1382 void __init pcibios_resource_survey(void)
1386 /* Allocate and assign resources */
1387 list_for_each_entry(b, &pci_root_buses, node)
1388 pcibios_allocate_bus_resources(b);
1389 pcibios_allocate_resources(0);
1390 pcibios_allocate_resources(1);
1392 /* Before we start assigning unassigned resource, we try to reserve
1393 * the low IO area and the VGA memory area if they intersect the
1394 * bus available resources to avoid allocating things on top of them
1396 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1397 list_for_each_entry(b, &pci_root_buses, node)
1398 pcibios_reserve_legacy_regions(b);
1401 /* Now, if the platform didn't decide to blindly trust the firmware,
1402 * we proceed to assigning things that were left unassigned
1404 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1405 pr_debug("PCI: Assigning unassigned resources...\n");
1406 pci_assign_unassigned_resources();
1409 /* Call machine dependent fixup */
1410 if (ppc_md.pcibios_fixup)
1411 ppc_md.pcibios_fixup();
1414 /* This is used by the PCI hotplug driver to allocate resource
1415 * of newly plugged busses. We can try to consolidate with the
1416 * rest of the code later, for now, keep it as-is as our main
1417 * resource allocation function doesn't deal with sub-trees yet.
1419 void pcibios_claim_one_bus(struct pci_bus *bus)
1421 struct pci_dev *dev;
1422 struct pci_bus *child_bus;
1424 list_for_each_entry(dev, &bus->devices, bus_list) {
1427 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1428 struct resource *r = &dev->resource[i];
1430 if (r->parent || !r->start || !r->flags)
1433 pr_debug("PCI: Claiming %s: "
1434 "Resource %d: %016llx..%016llx [%x]\n",
1436 (unsigned long long)r->start,
1437 (unsigned long long)r->end,
1438 (unsigned int)r->flags);
1440 if (pci_claim_resource(dev, i) == 0)
1443 pci_claim_bridge_resource(dev, i);
1447 list_for_each_entry(child_bus, &bus->children, node)
1448 pcibios_claim_one_bus(child_bus);
1452 /* pcibios_finish_adding_to_bus
1454 * This is to be called by the hotplug code after devices have been
1455 * added to a bus, this include calling it for a PHB that is just
1458 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1460 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1461 pci_domain_nr(bus), bus->number);
1463 /* Allocate bus and devices resources */
1464 pcibios_allocate_bus_resources(bus);
1465 pcibios_claim_one_bus(bus);
1466 if (!pci_has_flag(PCI_PROBE_ONLY))
1467 pci_assign_unassigned_bus_resources(bus);
1470 eeh_add_device_tree_late(bus);
1472 /* Add new devices to global lists. Register in proc, sysfs. */
1473 pci_bus_add_devices(bus);
1475 /* sysfs files should only be added after devices are added */
1476 eeh_add_sysfs_files(bus);
1478 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1480 int pcibios_enable_device(struct pci_dev *dev, int mask)
1482 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1484 if (phb->controller_ops.enable_device_hook)
1485 if (!phb->controller_ops.enable_device_hook(dev))
1488 return pci_enable_resources(dev, mask);
1491 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1493 return (unsigned long) hose->io_base_virt - _IO_BASE;
1496 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1497 struct list_head *resources)
1499 struct resource *res;
1500 resource_size_t offset;
1503 /* Hookup PHB IO resource */
1504 res = &hose->io_resource;
1507 pr_info("PCI: I/O resource not set for host"
1508 " bridge %s (domain %d)\n",
1509 hose->dn->full_name, hose->global_number);
1511 offset = pcibios_io_space_offset(hose);
1513 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1514 (unsigned long long)res->start,
1515 (unsigned long long)res->end,
1516 (unsigned long)res->flags,
1517 (unsigned long long)offset);
1518 pci_add_resource_offset(resources, res, offset);
1521 /* Hookup PHB Memory resources */
1522 for (i = 0; i < 3; ++i) {
1523 res = &hose->mem_resources[i];
1526 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1527 "host bridge %s (domain %d)\n",
1528 hose->dn->full_name, hose->global_number);
1531 offset = hose->mem_offset[i];
1534 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1535 (unsigned long long)res->start,
1536 (unsigned long long)res->end,
1537 (unsigned long)res->flags,
1538 (unsigned long long)offset);
1540 pci_add_resource_offset(resources, res, offset);
1545 * Null PCI config access functions, for the case when we can't
1548 #define NULL_PCI_OP(rw, size, type) \
1550 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1552 return PCIBIOS_DEVICE_NOT_FOUND; \
1556 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1559 return PCIBIOS_DEVICE_NOT_FOUND;
1563 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1566 return PCIBIOS_DEVICE_NOT_FOUND;
1569 static struct pci_ops null_pci_ops =
1571 .read = null_read_config,
1572 .write = null_write_config,
1576 * These functions are used early on before PCI scanning is done
1577 * and all of the pci_dev and pci_bus structures have been created.
1579 static struct pci_bus *
1580 fake_pci_bus(struct pci_controller *hose, int busnr)
1582 static struct pci_bus bus;
1585 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1589 bus.ops = hose? hose->ops: &null_pci_ops;
1593 #define EARLY_PCI_OP(rw, size, type) \
1594 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1595 int devfn, int offset, type value) \
1597 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1598 devfn, offset, value); \
1601 EARLY_PCI_OP(read, byte, u8 *)
1602 EARLY_PCI_OP(read, word, u16 *)
1603 EARLY_PCI_OP(read, dword, u32 *)
1604 EARLY_PCI_OP(write, byte, u8)
1605 EARLY_PCI_OP(write, word, u16)
1606 EARLY_PCI_OP(write, dword, u32)
1608 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1611 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1614 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1616 struct pci_controller *hose = bus->sysdata;
1618 return of_node_get(hose->dn);
1622 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1623 * @hose: Pointer to the PCI host controller instance structure
1625 void pcibios_scan_phb(struct pci_controller *hose)
1627 LIST_HEAD(resources);
1628 struct pci_bus *bus;
1629 struct device_node *node = hose->dn;
1632 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1634 /* Get some IO space for the new PHB */
1635 pcibios_setup_phb_io_space(hose);
1637 /* Wire up PHB bus resources */
1638 pcibios_setup_phb_resources(hose, &resources);
1640 hose->busn.start = hose->first_busno;
1641 hose->busn.end = hose->last_busno;
1642 hose->busn.flags = IORESOURCE_BUS;
1643 pci_add_resource(&resources, &hose->busn);
1645 /* Create an empty bus for the toplevel */
1646 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1647 hose->ops, hose, &resources);
1649 pr_err("Failed to create bus for PCI domain %04x\n",
1650 hose->global_number);
1651 pci_free_resource_list(&resources);
1656 /* Get probe mode and perform scan */
1657 mode = PCI_PROBE_NORMAL;
1658 if (node && hose->controller_ops.probe_mode)
1659 mode = hose->controller_ops.probe_mode(bus);
1660 pr_debug(" probe mode: %d\n", mode);
1661 if (mode == PCI_PROBE_DEVTREE)
1662 of_scan_bus(node, bus);
1664 if (mode == PCI_PROBE_NORMAL) {
1665 pci_bus_update_busn_res_end(bus, 255);
1666 hose->last_busno = pci_scan_child_bus(bus);
1667 pci_bus_update_busn_res_end(bus, hose->last_busno);
1670 /* Platform gets a chance to do some global fixups before
1671 * we proceed to resource allocation
1673 if (ppc_md.pcibios_fixup_phb)
1674 ppc_md.pcibios_fixup_phb(hose);
1676 /* Configure PCI Express settings */
1677 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1678 struct pci_bus *child;
1679 list_for_each_entry(child, &bus->children, node)
1680 pcie_bus_configure_settings(child);
1684 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1686 int i, class = dev->class >> 8;
1687 /* When configured as agent, programing interface = 1 */
1688 int prog_if = dev->class & 0xf;
1690 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1691 class == PCI_CLASS_BRIDGE_OTHER) &&
1692 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1694 (dev->bus->parent == NULL)) {
1695 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1696 dev->resource[i].start = 0;
1697 dev->resource[i].end = 0;
1698 dev->resource[i].flags = 0;
1702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1705 static void fixup_vga(struct pci_dev *pdev)
1709 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1710 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1711 vga_set_default_device(pdev);
1714 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1715 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);