2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
35 #include <linux/numa.h>
37 #include <asm/processor.h>
40 #include <asm/pci-bridge.h>
41 #include <asm/byteorder.h>
42 #include <asm/machdep.h>
43 #include <asm/ppc-pci.h>
46 #include "../../../drivers/pci/pci.h"
48 /* hose_spinlock protects accesses to the the phb_bitmap. */
49 static DEFINE_SPINLOCK(hose_spinlock);
52 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
53 #define MAX_PHBS 0x10000
56 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
57 * Accesses to this bitmap should be protected by hose_spinlock.
59 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
61 /* ISA Memory physical address */
62 resource_size_t isa_mem_base;
63 EXPORT_SYMBOL(isa_mem_base);
66 static const struct dma_map_ops *pci_dma_ops;
68 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
70 pci_dma_ops = dma_ops;
74 * This function should run under locking protection, specifically
77 static int get_phb_number(struct device_node *dn)
84 * Try fixed PHB numbering first, by checking archs and reading
85 * the respective device-tree properties. Firstly, try powernv by
86 * reading "ibm,opal-phbid", only present in OPAL environment.
88 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
90 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
95 phb_id = (int)(prop & (MAX_PHBS - 1));
97 /* We need to be sure to not use the same PHB number twice. */
98 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
102 * If not pseries nor powernv, or if fixed PHB numbering tried to add
103 * the same PHB number twice, then fallback to dynamic PHB numbering.
105 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
106 BUG_ON(phb_id >= MAX_PHBS);
107 set_bit(phb_id, phb_bitmap);
112 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
114 struct pci_controller *phb;
116 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
119 spin_lock(&hose_spinlock);
120 phb->global_number = get_phb_number(dev);
121 list_add_tail(&phb->list_node, &hose_list);
122 spin_unlock(&hose_spinlock);
124 phb->is_dynamic = slab_is_available();
127 int nid = of_node_to_nid(dev);
129 if (nid < 0 || !node_online(nid))
132 PHB_SET_NODE(phb, nid);
137 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
139 void pcibios_free_controller(struct pci_controller *phb)
141 spin_lock(&hose_spinlock);
143 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
144 if (phb->global_number < MAX_PHBS)
145 clear_bit(phb->global_number, phb_bitmap);
147 list_del(&phb->list_node);
148 spin_unlock(&hose_spinlock);
153 EXPORT_SYMBOL_GPL(pcibios_free_controller);
156 * This function is used to call pcibios_free_controller()
157 * in a deferred manner: a callback from the PCI subsystem.
159 * _*DO NOT*_ call pcibios_free_controller() explicitly if
160 * this is used (or it may access an invalid *phb pointer).
162 * The callback occurs when all references to the root bus
163 * are dropped (e.g., child buses/devices and their users).
165 * It's called as .release_fn() of 'struct pci_host_bridge'
166 * which is associated with the 'struct pci_controller.bus'
167 * (root bus) - it expects .release_data to hold a pointer
168 * to 'struct pci_controller'.
170 * In order to use it, register .release_fn()/release_data
173 * pci_set_host_bridge_release(bridge,
174 * pcibios_free_controller_deferred
177 * e.g. in the pcibios_root_bridge_prepare() callback from
178 * pci_create_root_bus().
180 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
182 struct pci_controller *phb = (struct pci_controller *)
183 bridge->release_data;
185 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
187 pcibios_free_controller(phb);
189 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
192 * The function is used to return the minimal alignment
193 * for memory or I/O windows of the associated P2P bridge.
194 * By default, 4KiB alignment for I/O windows and 1MiB for
197 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
200 struct pci_controller *phb = pci_bus_to_host(bus);
202 if (phb->controller_ops.window_alignment)
203 return phb->controller_ops.window_alignment(bus, type);
206 * PCI core will figure out the default
207 * alignment: 4KiB for I/O and 1MiB for
213 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
215 struct pci_controller *hose = pci_bus_to_host(bus);
217 if (hose->controller_ops.setup_bridge)
218 hose->controller_ops.setup_bridge(bus, type);
221 void pcibios_reset_secondary_bus(struct pci_dev *dev)
223 struct pci_controller *phb = pci_bus_to_host(dev->bus);
225 if (phb->controller_ops.reset_secondary_bus) {
226 phb->controller_ops.reset_secondary_bus(dev);
230 pci_reset_secondary_bus(dev);
233 resource_size_t pcibios_default_alignment(void)
235 if (ppc_md.pcibios_default_alignment)
236 return ppc_md.pcibios_default_alignment();
241 #ifdef CONFIG_PCI_IOV
242 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
244 if (ppc_md.pcibios_iov_resource_alignment)
245 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
247 return pci_iov_resource_size(pdev, resno);
250 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
252 if (ppc_md.pcibios_sriov_enable)
253 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
258 int pcibios_sriov_disable(struct pci_dev *pdev)
260 if (ppc_md.pcibios_sriov_disable)
261 return ppc_md.pcibios_sriov_disable(pdev);
266 #endif /* CONFIG_PCI_IOV */
268 void pcibios_bus_add_device(struct pci_dev *pdev)
270 if (ppc_md.pcibios_bus_add_device)
271 ppc_md.pcibios_bus_add_device(pdev);
274 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
277 return hose->pci_io_size;
279 return resource_size(&hose->io_resource);
283 int pcibios_vaddr_is_ioport(void __iomem *address)
286 struct pci_controller *hose;
287 resource_size_t size;
289 spin_lock(&hose_spinlock);
290 list_for_each_entry(hose, &hose_list, list_node) {
291 size = pcibios_io_size(hose);
292 if (address >= hose->io_base_virt &&
293 address < (hose->io_base_virt + size)) {
298 spin_unlock(&hose_spinlock);
302 unsigned long pci_address_to_pio(phys_addr_t address)
304 struct pci_controller *hose;
305 resource_size_t size;
306 unsigned long ret = ~0;
308 spin_lock(&hose_spinlock);
309 list_for_each_entry(hose, &hose_list, list_node) {
310 size = pcibios_io_size(hose);
311 if (address >= hose->io_base_phys &&
312 address < (hose->io_base_phys + size)) {
314 (unsigned long)hose->io_base_virt - _IO_BASE;
315 ret = base + (address - hose->io_base_phys);
319 spin_unlock(&hose_spinlock);
323 EXPORT_SYMBOL_GPL(pci_address_to_pio);
326 * Return the domain number for this bus.
328 int pci_domain_nr(struct pci_bus *bus)
330 struct pci_controller *hose = pci_bus_to_host(bus);
332 return hose->global_number;
334 EXPORT_SYMBOL(pci_domain_nr);
336 /* This routine is meant to be used early during boot, when the
337 * PCI bus numbers have not yet been assigned, and you need to
338 * issue PCI config cycles to an OF device.
339 * It could also be used to "fix" RTAS config cycles if you want
340 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
343 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
346 struct pci_controller *hose, *tmp;
347 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
348 if (hose->dn == node)
355 struct pci_controller *pci_find_controller_for_domain(int domain_nr)
357 struct pci_controller *hose;
359 list_for_each_entry(hose, &hose_list, list_node)
360 if (hose->global_number == domain_nr)
367 * Reads the interrupt pin to determine if interrupt is use by card.
368 * If the interrupt is used, then gets the interrupt line from the
369 * openfirmware and sets it in the pci_dev and pci_config line.
371 static int pci_read_irq_line(struct pci_dev *pci_dev)
375 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
377 /* Try to get a mapping from the device-tree */
378 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
382 /* If that fails, lets fallback to what is in the config
383 * space and map that through the default controller. We
384 * also set the type to level low since that's what PCI
385 * interrupts are. If your platform does differently, then
386 * either provide a proper interrupt tree or don't use this
389 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
393 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
394 line == 0xff || line == 0) {
397 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
400 virq = irq_create_mapping(NULL, line);
402 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
406 pr_debug(" Failed to map !\n");
410 pr_debug(" Mapped to linux irq %d\n", virq);
418 * Platform support for /proc/bus/pci/X/Y mmap()s.
421 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
423 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
424 resource_size_t ioaddr = pci_resource_start(pdev, bar);
429 /* Convert to an offset within this PCI controller */
430 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
432 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
437 * This one is used by /dev/mem and fbdev who have no clue about the
438 * PCI device, it tries to find the PCI device first and calls the
441 pgprot_t pci_phys_mem_access_prot(struct file *file,
446 struct pci_dev *pdev = NULL;
447 struct resource *found = NULL;
448 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
451 if (page_is_ram(pfn))
454 prot = pgprot_noncached(prot);
455 for_each_pci_dev(pdev) {
456 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
457 struct resource *rp = &pdev->resource[i];
458 int flags = rp->flags;
460 /* Active and same type? */
461 if ((flags & IORESOURCE_MEM) == 0)
463 /* In the range of this resource? */
464 if (offset < (rp->start & PAGE_MASK) ||
474 if (found->flags & IORESOURCE_PREFETCH)
475 prot = pgprot_noncached_wc(prot);
479 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
480 (unsigned long long)offset, pgprot_val(prot));
485 /* This provides legacy IO read access on a bus */
486 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
488 unsigned long offset;
489 struct pci_controller *hose = pci_bus_to_host(bus);
490 struct resource *rp = &hose->io_resource;
493 /* Check if port can be supported by that bus. We only check
494 * the ranges of the PHB though, not the bus itself as the rules
495 * for forwarding legacy cycles down bridges are not our problem
496 * here. So if the host bridge supports it, we do it.
498 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
501 if (!(rp->flags & IORESOURCE_IO))
503 if (offset < rp->start || (offset + size) > rp->end)
505 addr = hose->io_base_virt + port;
509 *((u8 *)val) = in_8(addr);
514 *((u16 *)val) = in_le16(addr);
519 *((u32 *)val) = in_le32(addr);
525 /* This provides legacy IO write access on a bus */
526 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
528 unsigned long offset;
529 struct pci_controller *hose = pci_bus_to_host(bus);
530 struct resource *rp = &hose->io_resource;
533 /* Check if port can be supported by that bus. We only check
534 * the ranges of the PHB though, not the bus itself as the rules
535 * for forwarding legacy cycles down bridges are not our problem
536 * here. So if the host bridge supports it, we do it.
538 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
541 if (!(rp->flags & IORESOURCE_IO))
543 if (offset < rp->start || (offset + size) > rp->end)
545 addr = hose->io_base_virt + port;
547 /* WARNING: The generic code is idiotic. It gets passed a pointer
548 * to what can be a 1, 2 or 4 byte quantity and always reads that
549 * as a u32, which means that we have to correct the location of
550 * the data read within those 32 bits for size 1 and 2
554 out_8(addr, val >> 24);
559 out_le16(addr, val >> 16);
570 /* This provides legacy IO or memory mmap access on a bus */
571 int pci_mmap_legacy_page_range(struct pci_bus *bus,
572 struct vm_area_struct *vma,
573 enum pci_mmap_state mmap_state)
575 struct pci_controller *hose = pci_bus_to_host(bus);
576 resource_size_t offset =
577 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
578 resource_size_t size = vma->vm_end - vma->vm_start;
581 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
582 pci_domain_nr(bus), bus->number,
583 mmap_state == pci_mmap_mem ? "MEM" : "IO",
584 (unsigned long long)offset,
585 (unsigned long long)(offset + size - 1));
587 if (mmap_state == pci_mmap_mem) {
590 * Because X is lame and can fail starting if it gets an error trying
591 * to mmap legacy_mem (instead of just moving on without legacy memory
592 * access) we fake it here by giving it anonymous memory, effectively
593 * behaving just like /dev/zero
595 if ((offset + size) > hose->isa_mem_size) {
597 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
598 current->comm, current->pid, pci_domain_nr(bus), bus->number);
599 if (vma->vm_flags & VM_SHARED)
600 return shmem_zero_setup(vma);
603 offset += hose->isa_mem_phys;
605 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
606 unsigned long roffset = offset + io_offset;
607 rp = &hose->io_resource;
608 if (!(rp->flags & IORESOURCE_IO))
610 if (roffset < rp->start || (roffset + size) > rp->end)
612 offset += hose->io_base_phys;
614 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
616 vma->vm_pgoff = offset >> PAGE_SHIFT;
617 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
618 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
619 vma->vm_end - vma->vm_start,
623 void pci_resource_to_user(const struct pci_dev *dev, int bar,
624 const struct resource *rsrc,
625 resource_size_t *start, resource_size_t *end)
627 struct pci_bus_region region;
629 if (rsrc->flags & IORESOURCE_IO) {
630 pcibios_resource_to_bus(dev->bus, ®ion,
631 (struct resource *) rsrc);
632 *start = region.start;
637 /* We pass a CPU physical address to userland for MMIO instead of a
638 * BAR value because X is lame and expects to be able to use that
639 * to pass to /dev/mem!
641 * That means we may have 64-bit values where some apps only expect
642 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
644 *start = rsrc->start;
649 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
650 * @hose: newly allocated pci_controller to be setup
651 * @dev: device node of the host bridge
652 * @primary: set if primary bus (32 bits only, soon to be deprecated)
654 * This function will parse the "ranges" property of a PCI host bridge device
655 * node and setup the resource mapping of a pci controller based on its
658 * Life would be boring if it wasn't for a few issues that we have to deal
661 * - We can only cope with one IO space range and up to 3 Memory space
662 * ranges. However, some machines (thanks Apple !) tend to split their
663 * space into lots of small contiguous ranges. So we have to coalesce.
665 * - Some busses have IO space not starting at 0, which causes trouble with
666 * the way we do our IO resource renumbering. The code somewhat deals with
667 * it for 64 bits but I would expect problems on 32 bits.
669 * - Some 32 bits platforms such as 4xx can have physical space larger than
670 * 32 bits so we need to use 64 bits values for the parsing
672 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
673 struct device_node *dev, int primary)
676 struct resource *res;
677 struct of_pci_range range;
678 struct of_pci_range_parser parser;
680 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
681 dev, primary ? "(primary)" : "");
683 /* Check for ranges property */
684 if (of_pci_range_parser_init(&parser, dev))
688 for_each_of_pci_range(&parser, &range) {
689 /* If we failed translation or got a zero-sized region
690 * (some FW try to feed us with non sensical zero sized regions
691 * such as power3 which look like some kind of attempt at exposing
692 * the VGA memory hole)
694 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
697 /* Act based on address space type */
699 switch (range.flags & IORESOURCE_TYPE_BITS) {
702 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
703 range.cpu_addr, range.cpu_addr + range.size - 1,
706 /* We support only one IO range */
707 if (hose->pci_io_size) {
709 " \\--> Skipped (too many) !\n");
713 /* On 32 bits, limit I/O space to 16MB */
714 if (range.size > 0x01000000)
715 range.size = 0x01000000;
717 /* 32 bits needs to map IOs here */
718 hose->io_base_virt = ioremap(range.cpu_addr,
721 /* Expect trouble if pci_addr is not 0 */
724 (unsigned long)hose->io_base_virt;
725 #endif /* CONFIG_PPC32 */
726 /* pci_io_size and io_base_phys always represent IO
727 * space starting at 0 so we factor in pci_addr
729 hose->pci_io_size = range.pci_addr + range.size;
730 hose->io_base_phys = range.cpu_addr - range.pci_addr;
733 res = &hose->io_resource;
734 range.cpu_addr = range.pci_addr;
738 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
739 range.cpu_addr, range.cpu_addr + range.size - 1,
741 (range.pci_space & 0x40000000) ?
744 /* We support only 3 memory ranges */
747 " \\--> Skipped (too many) !\n");
750 /* Handles ISA memory hole space here */
751 if (range.pci_addr == 0) {
752 if (primary || isa_mem_base == 0)
753 isa_mem_base = range.cpu_addr;
754 hose->isa_mem_phys = range.cpu_addr;
755 hose->isa_mem_size = range.size;
759 hose->mem_offset[memno] = range.cpu_addr -
761 res = &hose->mem_resources[memno++];
765 res->name = dev->full_name;
766 res->flags = range.flags;
767 res->start = range.cpu_addr;
768 res->end = range.cpu_addr + range.size - 1;
769 res->parent = res->child = res->sibling = NULL;
774 /* Decide whether to display the domain number in /proc */
775 int pci_proc_domain(struct pci_bus *bus)
777 struct pci_controller *hose = pci_bus_to_host(bus);
779 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
781 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
782 return hose->global_number != 0;
786 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
788 if (ppc_md.pcibios_root_bridge_prepare)
789 return ppc_md.pcibios_root_bridge_prepare(bridge);
794 /* This header fixup will do the resource fixup for all devices as they are
795 * probed, but not for bridge ranges
797 static void pcibios_fixup_resources(struct pci_dev *dev)
799 struct pci_controller *hose = pci_bus_to_host(dev->bus);
803 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
811 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
812 struct resource *res = dev->resource + i;
813 struct pci_bus_region reg;
817 /* If we're going to re-assign everything, we mark all resources
818 * as unset (and 0-base them). In addition, we mark BARs starting
819 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
820 * since in that case, we don't want to re-assign anything
822 pcibios_resource_to_bus(dev->bus, ®, res);
823 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
824 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
825 /* Only print message if not re-assigning */
826 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
827 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
828 pci_name(dev), i, res);
829 res->end -= res->start;
831 res->flags |= IORESOURCE_UNSET;
835 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
838 /* Call machine specific resource fixup */
839 if (ppc_md.pcibios_fixup_resources)
840 ppc_md.pcibios_fixup_resources(dev);
842 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
844 /* This function tries to figure out if a bridge resource has been initialized
845 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
846 * things go more smoothly when it gets it right. It should covers cases such
847 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
849 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
850 struct resource *res)
852 struct pci_controller *hose = pci_bus_to_host(bus);
853 struct pci_dev *dev = bus->self;
854 resource_size_t offset;
855 struct pci_bus_region region;
859 /* We don't do anything if PCI_PROBE_ONLY is set */
860 if (pci_has_flag(PCI_PROBE_ONLY))
863 /* Job is a bit different between memory and IO */
864 if (res->flags & IORESOURCE_MEM) {
865 pcibios_resource_to_bus(dev->bus, ®ion, res);
867 /* If the BAR is non-0 then it's probably been initialized */
868 if (region.start != 0)
871 /* The BAR is 0, let's check if memory decoding is enabled on
872 * the bridge. If not, we consider it unassigned
874 pci_read_config_word(dev, PCI_COMMAND, &command);
875 if ((command & PCI_COMMAND_MEMORY) == 0)
878 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
879 * resources covers that starting address (0 then it's good enough for
880 * us for memory space)
882 for (i = 0; i < 3; i++) {
883 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
884 hose->mem_resources[i].start == hose->mem_offset[i])
888 /* Well, it starts at 0 and we know it will collide so we may as
889 * well consider it as unassigned. That covers the Apple case.
893 /* If the BAR is non-0, then we consider it assigned */
894 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
895 if (((res->start - offset) & 0xfffffffful) != 0)
898 /* Here, we are a bit different than memory as typically IO space
899 * starting at low addresses -is- valid. What we do instead if that
900 * we consider as unassigned anything that doesn't have IO enabled
901 * in the PCI command register, and that's it.
903 pci_read_config_word(dev, PCI_COMMAND, &command);
904 if (command & PCI_COMMAND_IO)
907 /* It's starting at 0 and IO is disabled in the bridge, consider
914 /* Fixup resources of a PCI<->PCI bridge */
915 static void pcibios_fixup_bridge(struct pci_bus *bus)
917 struct resource *res;
920 struct pci_dev *dev = bus->self;
922 pci_bus_for_each_resource(bus, res, i) {
923 if (!res || !res->flags)
925 if (i >= 3 && bus->self->transparent)
928 /* If we're going to reassign everything, we can
929 * shrink the P2P resource to have size as being
930 * of 0 in order to save space.
932 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
933 res->flags |= IORESOURCE_UNSET;
939 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
941 /* Try to detect uninitialized P2P bridge resources,
942 * and clear them out so they get re-assigned later
944 if (pcibios_uninitialized_bridge_resource(bus, res)) {
946 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
951 void pcibios_setup_bus_self(struct pci_bus *bus)
953 struct pci_controller *phb;
955 /* Fix up the bus resources for P2P bridges */
956 if (bus->self != NULL)
957 pcibios_fixup_bridge(bus);
959 /* Platform specific bus fixups. This is currently only used
960 * by fsl_pci and I'm hoping to get rid of it at some point
962 if (ppc_md.pcibios_fixup_bus)
963 ppc_md.pcibios_fixup_bus(bus);
965 /* Setup bus DMA mappings */
966 phb = pci_bus_to_host(bus);
967 if (phb->controller_ops.dma_bus_setup)
968 phb->controller_ops.dma_bus_setup(bus);
971 static void pcibios_setup_device(struct pci_dev *dev)
973 struct pci_controller *phb;
974 /* Fixup NUMA node as it may not be setup yet by the generic
975 * code and is needed by the DMA init
977 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
979 /* Hook up default DMA ops */
980 set_dma_ops(&dev->dev, pci_dma_ops);
981 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
983 /* Additional platform DMA/iommu setup */
984 phb = pci_bus_to_host(dev->bus);
985 if (phb->controller_ops.dma_dev_setup)
986 phb->controller_ops.dma_dev_setup(dev);
988 /* Read default IRQs and fixup if necessary */
989 pci_read_irq_line(dev);
990 if (ppc_md.pci_irq_fixup)
991 ppc_md.pci_irq_fixup(dev);
994 int pcibios_add_device(struct pci_dev *dev)
997 * We can only call pcibios_setup_device() after bus setup is complete,
998 * since some of the platform specific DMA setup code depends on it.
1000 if (dev->bus->is_added)
1001 pcibios_setup_device(dev);
1003 #ifdef CONFIG_PCI_IOV
1004 if (ppc_md.pcibios_fixup_sriov)
1005 ppc_md.pcibios_fixup_sriov(dev);
1006 #endif /* CONFIG_PCI_IOV */
1011 void pcibios_setup_bus_devices(struct pci_bus *bus)
1013 struct pci_dev *dev;
1015 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1016 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1018 list_for_each_entry(dev, &bus->devices, bus_list) {
1019 /* Cardbus can call us to add new devices to a bus, so ignore
1020 * those who are already fully discovered
1022 if (pci_dev_is_added(dev))
1025 pcibios_setup_device(dev);
1029 void pcibios_set_master(struct pci_dev *dev)
1031 /* No special bus mastering setup handling */
1034 void pcibios_fixup_bus(struct pci_bus *bus)
1036 /* When called from the generic PCI probe, read PCI<->PCI bridge
1037 * bases. This is -not- called when generating the PCI tree from
1038 * the OF device-tree.
1040 pci_read_bridge_bases(bus);
1042 /* Now fixup the bus bus */
1043 pcibios_setup_bus_self(bus);
1045 /* Now fixup devices on that bus */
1046 pcibios_setup_bus_devices(bus);
1048 EXPORT_SYMBOL(pcibios_fixup_bus);
1050 void pci_fixup_cardbus(struct pci_bus *bus)
1052 /* Now fixup devices on that bus */
1053 pcibios_setup_bus_devices(bus);
1057 static int skip_isa_ioresource_align(struct pci_dev *dev)
1059 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1060 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1066 * We need to avoid collisions with `mirrored' VGA ports
1067 * and other strange ISA hardware, so we always want the
1068 * addresses to be allocated in the 0x000-0x0ff region
1071 * Why? Because some silly external IO cards only decode
1072 * the low 10 bits of the IO address. The 0x00-0xff region
1073 * is reserved for motherboard devices that decode all 16
1074 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1075 * but we want to try to avoid allocating at 0x2900-0x2bff
1076 * which might have be mirrored at 0x0100-0x03ff..
1078 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1079 resource_size_t size, resource_size_t align)
1081 struct pci_dev *dev = data;
1082 resource_size_t start = res->start;
1084 if (res->flags & IORESOURCE_IO) {
1085 if (skip_isa_ioresource_align(dev))
1088 start = (start + 0x3ff) & ~0x3ff;
1093 EXPORT_SYMBOL(pcibios_align_resource);
1096 * Reparent resource children of pr that conflict with res
1097 * under res, and make res replace those children.
1099 static int reparent_resources(struct resource *parent,
1100 struct resource *res)
1102 struct resource *p, **pp;
1103 struct resource **firstpp = NULL;
1105 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1106 if (p->end < res->start)
1108 if (res->end < p->start)
1110 if (p->start < res->start || p->end > res->end)
1111 return -1; /* not completely contained */
1112 if (firstpp == NULL)
1115 if (firstpp == NULL)
1116 return -1; /* didn't find any conflicting entries? */
1117 res->parent = parent;
1118 res->child = *firstpp;
1122 for (p = res->child; p != NULL; p = p->sibling) {
1124 pr_debug("PCI: Reparented %s %pR under %s\n",
1125 p->name, p, res->name);
1131 * Handle resources of PCI devices. If the world were perfect, we could
1132 * just allocate all the resource regions and do nothing more. It isn't.
1133 * On the other hand, we cannot just re-allocate all devices, as it would
1134 * require us to know lots of host bridge internals. So we attempt to
1135 * keep as much of the original configuration as possible, but tweak it
1136 * when it's found to be wrong.
1138 * Known BIOS problems we have to work around:
1139 * - I/O or memory regions not configured
1140 * - regions configured, but not enabled in the command register
1141 * - bogus I/O addresses above 64K used
1142 * - expansion ROMs left enabled (this may sound harmless, but given
1143 * the fact the PCI specs explicitly allow address decoders to be
1144 * shared between expansion ROMs and other resource regions, it's
1145 * at least dangerous)
1148 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1149 * This gives us fixed barriers on where we can allocate.
1150 * (2) Allocate resources for all enabled devices. If there is
1151 * a collision, just mark the resource as unallocated. Also
1152 * disable expansion ROMs during this step.
1153 * (3) Try to allocate resources for disabled devices. If the
1154 * resources were assigned correctly, everything goes well,
1155 * if they weren't, they won't disturb allocation of other
1157 * (4) Assign new addresses to resources which were either
1158 * not configured at all or misconfigured. If explicitly
1159 * requested by the user, configure expansion ROM address
1163 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1167 struct resource *res, *pr;
1169 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1170 pci_domain_nr(bus), bus->number);
1172 pci_bus_for_each_resource(bus, res, i) {
1173 if (!res || !res->flags || res->start > res->end || res->parent)
1176 /* If the resource was left unset at this point, we clear it */
1177 if (res->flags & IORESOURCE_UNSET)
1178 goto clear_resource;
1180 if (bus->parent == NULL)
1181 pr = (res->flags & IORESOURCE_IO) ?
1182 &ioport_resource : &iomem_resource;
1184 pr = pci_find_parent_resource(bus->self, res);
1186 /* this happens when the generic PCI
1187 * code (wrongly) decides that this
1188 * bridge is transparent -- paulus
1194 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1195 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1196 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1198 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1199 struct pci_dev *dev = bus->self;
1201 if (request_resource(pr, res) == 0)
1204 * Must be a conflict with an existing entry.
1205 * Move that entry (or entries) under the
1206 * bridge resource and try again.
1208 if (reparent_resources(pr, res) == 0)
1211 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1212 pci_claim_bridge_resource(dev,
1213 i + PCI_BRIDGE_RESOURCES) == 0)
1216 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1219 /* The resource might be figured out when doing
1220 * reassignment based on the resources required
1221 * by the downstream PCI devices. Here we set
1222 * the size of the resource to be 0 in order to
1230 list_for_each_entry(b, &bus->children, node)
1231 pcibios_allocate_bus_resources(b);
1234 static inline void alloc_resource(struct pci_dev *dev, int idx)
1236 struct resource *pr, *r = &dev->resource[idx];
1238 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1239 pci_name(dev), idx, r);
1241 pr = pci_find_parent_resource(dev, r);
1242 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1243 request_resource(pr, r) < 0) {
1244 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1245 " of device %s, will remap\n", idx, pci_name(dev));
1247 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1248 /* We'll assign a new address later */
1249 r->flags |= IORESOURCE_UNSET;
1255 static void __init pcibios_allocate_resources(int pass)
1257 struct pci_dev *dev = NULL;
1262 for_each_pci_dev(dev) {
1263 pci_read_config_word(dev, PCI_COMMAND, &command);
1264 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1265 r = &dev->resource[idx];
1266 if (r->parent) /* Already allocated */
1268 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1269 continue; /* Not assigned at all */
1270 /* We only allocate ROMs on pass 1 just in case they
1271 * have been screwed up by firmware
1273 if (idx == PCI_ROM_RESOURCE )
1275 if (r->flags & IORESOURCE_IO)
1276 disabled = !(command & PCI_COMMAND_IO);
1278 disabled = !(command & PCI_COMMAND_MEMORY);
1279 if (pass == disabled)
1280 alloc_resource(dev, idx);
1284 r = &dev->resource[PCI_ROM_RESOURCE];
1286 /* Turn the ROM off, leave the resource region,
1287 * but keep it unregistered.
1290 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1291 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1292 pr_debug("PCI: Switching off ROM of %s\n",
1294 r->flags &= ~IORESOURCE_ROM_ENABLE;
1295 pci_write_config_dword(dev, dev->rom_base_reg,
1296 reg & ~PCI_ROM_ADDRESS_ENABLE);
1302 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1304 struct pci_controller *hose = pci_bus_to_host(bus);
1305 resource_size_t offset;
1306 struct resource *res, *pres;
1309 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1312 if (!(hose->io_resource.flags & IORESOURCE_IO))
1314 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1315 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1316 BUG_ON(res == NULL);
1317 res->name = "Legacy IO";
1318 res->flags = IORESOURCE_IO;
1319 res->start = offset;
1320 res->end = (offset + 0xfff) & 0xfffffffful;
1321 pr_debug("Candidate legacy IO: %pR\n", res);
1322 if (request_resource(&hose->io_resource, res)) {
1324 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1325 pci_domain_nr(bus), bus->number, res);
1330 /* Check for memory */
1331 for (i = 0; i < 3; i++) {
1332 pres = &hose->mem_resources[i];
1333 offset = hose->mem_offset[i];
1334 if (!(pres->flags & IORESOURCE_MEM))
1336 pr_debug("hose mem res: %pR\n", pres);
1337 if ((pres->start - offset) <= 0xa0000 &&
1338 (pres->end - offset) >= 0xbffff)
1343 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1344 BUG_ON(res == NULL);
1345 res->name = "Legacy VGA memory";
1346 res->flags = IORESOURCE_MEM;
1347 res->start = 0xa0000 + offset;
1348 res->end = 0xbffff + offset;
1349 pr_debug("Candidate VGA memory: %pR\n", res);
1350 if (request_resource(pres, res)) {
1352 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1353 pci_domain_nr(bus), bus->number, res);
1358 void __init pcibios_resource_survey(void)
1362 /* Allocate and assign resources */
1363 list_for_each_entry(b, &pci_root_buses, node)
1364 pcibios_allocate_bus_resources(b);
1365 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1366 pcibios_allocate_resources(0);
1367 pcibios_allocate_resources(1);
1370 /* Before we start assigning unassigned resource, we try to reserve
1371 * the low IO area and the VGA memory area if they intersect the
1372 * bus available resources to avoid allocating things on top of them
1374 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1375 list_for_each_entry(b, &pci_root_buses, node)
1376 pcibios_reserve_legacy_regions(b);
1379 /* Now, if the platform didn't decide to blindly trust the firmware,
1380 * we proceed to assigning things that were left unassigned
1382 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1383 pr_debug("PCI: Assigning unassigned resources...\n");
1384 pci_assign_unassigned_resources();
1387 /* Call machine dependent fixup */
1388 if (ppc_md.pcibios_fixup)
1389 ppc_md.pcibios_fixup();
1392 /* This is used by the PCI hotplug driver to allocate resource
1393 * of newly plugged busses. We can try to consolidate with the
1394 * rest of the code later, for now, keep it as-is as our main
1395 * resource allocation function doesn't deal with sub-trees yet.
1397 void pcibios_claim_one_bus(struct pci_bus *bus)
1399 struct pci_dev *dev;
1400 struct pci_bus *child_bus;
1402 list_for_each_entry(dev, &bus->devices, bus_list) {
1405 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1406 struct resource *r = &dev->resource[i];
1408 if (r->parent || !r->start || !r->flags)
1411 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1412 pci_name(dev), i, r);
1414 if (pci_claim_resource(dev, i) == 0)
1417 pci_claim_bridge_resource(dev, i);
1421 list_for_each_entry(child_bus, &bus->children, node)
1422 pcibios_claim_one_bus(child_bus);
1424 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1427 /* pcibios_finish_adding_to_bus
1429 * This is to be called by the hotplug code after devices have been
1430 * added to a bus, this include calling it for a PHB that is just
1433 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1435 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1436 pci_domain_nr(bus), bus->number);
1438 /* Allocate bus and devices resources */
1439 pcibios_allocate_bus_resources(bus);
1440 pcibios_claim_one_bus(bus);
1441 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1443 pci_assign_unassigned_bridge_resources(bus->self);
1445 pci_assign_unassigned_bus_resources(bus);
1449 eeh_add_device_tree_late(bus);
1451 /* Add new devices to global lists. Register in proc, sysfs. */
1452 pci_bus_add_devices(bus);
1454 /* sysfs files should only be added after devices are added */
1455 eeh_add_sysfs_files(bus);
1457 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1459 int pcibios_enable_device(struct pci_dev *dev, int mask)
1461 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1463 if (phb->controller_ops.enable_device_hook)
1464 if (!phb->controller_ops.enable_device_hook(dev))
1467 return pci_enable_resources(dev, mask);
1470 void pcibios_disable_device(struct pci_dev *dev)
1472 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1474 if (phb->controller_ops.disable_device)
1475 phb->controller_ops.disable_device(dev);
1478 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1480 return (unsigned long) hose->io_base_virt - _IO_BASE;
1483 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1484 struct list_head *resources)
1486 struct resource *res;
1487 resource_size_t offset;
1490 /* Hookup PHB IO resource */
1491 res = &hose->io_resource;
1494 pr_debug("PCI: I/O resource not set for host"
1495 " bridge %pOF (domain %d)\n",
1496 hose->dn, hose->global_number);
1498 offset = pcibios_io_space_offset(hose);
1500 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1501 res, (unsigned long long)offset);
1502 pci_add_resource_offset(resources, res, offset);
1505 /* Hookup PHB Memory resources */
1506 for (i = 0; i < 3; ++i) {
1507 res = &hose->mem_resources[i];
1511 offset = hose->mem_offset[i];
1512 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1513 res, (unsigned long long)offset);
1515 pci_add_resource_offset(resources, res, offset);
1520 * Null PCI config access functions, for the case when we can't
1523 #define NULL_PCI_OP(rw, size, type) \
1525 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1527 return PCIBIOS_DEVICE_NOT_FOUND; \
1531 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1534 return PCIBIOS_DEVICE_NOT_FOUND;
1538 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1541 return PCIBIOS_DEVICE_NOT_FOUND;
1544 static struct pci_ops null_pci_ops =
1546 .read = null_read_config,
1547 .write = null_write_config,
1551 * These functions are used early on before PCI scanning is done
1552 * and all of the pci_dev and pci_bus structures have been created.
1554 static struct pci_bus *
1555 fake_pci_bus(struct pci_controller *hose, int busnr)
1557 static struct pci_bus bus;
1560 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1564 bus.ops = hose? hose->ops: &null_pci_ops;
1568 #define EARLY_PCI_OP(rw, size, type) \
1569 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1570 int devfn, int offset, type value) \
1572 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1573 devfn, offset, value); \
1576 EARLY_PCI_OP(read, byte, u8 *)
1577 EARLY_PCI_OP(read, word, u16 *)
1578 EARLY_PCI_OP(read, dword, u32 *)
1579 EARLY_PCI_OP(write, byte, u8)
1580 EARLY_PCI_OP(write, word, u16)
1581 EARLY_PCI_OP(write, dword, u32)
1583 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1586 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1589 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1591 struct pci_controller *hose = bus->sysdata;
1593 return of_node_get(hose->dn);
1597 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1598 * @hose: Pointer to the PCI host controller instance structure
1600 void pcibios_scan_phb(struct pci_controller *hose)
1602 LIST_HEAD(resources);
1603 struct pci_bus *bus;
1604 struct device_node *node = hose->dn;
1607 pr_debug("PCI: Scanning PHB %pOF\n", node);
1609 /* Get some IO space for the new PHB */
1610 pcibios_setup_phb_io_space(hose);
1612 /* Wire up PHB bus resources */
1613 pcibios_setup_phb_resources(hose, &resources);
1615 hose->busn.start = hose->first_busno;
1616 hose->busn.end = hose->last_busno;
1617 hose->busn.flags = IORESOURCE_BUS;
1618 pci_add_resource(&resources, &hose->busn);
1620 /* Create an empty bus for the toplevel */
1621 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1622 hose->ops, hose, &resources);
1624 pr_err("Failed to create bus for PCI domain %04x\n",
1625 hose->global_number);
1626 pci_free_resource_list(&resources);
1631 /* Get probe mode and perform scan */
1632 mode = PCI_PROBE_NORMAL;
1633 if (node && hose->controller_ops.probe_mode)
1634 mode = hose->controller_ops.probe_mode(bus);
1635 pr_debug(" probe mode: %d\n", mode);
1636 if (mode == PCI_PROBE_DEVTREE)
1637 of_scan_bus(node, bus);
1639 if (mode == PCI_PROBE_NORMAL) {
1640 pci_bus_update_busn_res_end(bus, 255);
1641 hose->last_busno = pci_scan_child_bus(bus);
1642 pci_bus_update_busn_res_end(bus, hose->last_busno);
1645 /* Platform gets a chance to do some global fixups before
1646 * we proceed to resource allocation
1648 if (ppc_md.pcibios_fixup_phb)
1649 ppc_md.pcibios_fixup_phb(hose);
1651 /* Configure PCI Express settings */
1652 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1653 struct pci_bus *child;
1654 list_for_each_entry(child, &bus->children, node)
1655 pcie_bus_configure_settings(child);
1658 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1660 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1662 int i, class = dev->class >> 8;
1663 /* When configured as agent, programing interface = 1 */
1664 int prog_if = dev->class & 0xf;
1666 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1667 class == PCI_CLASS_BRIDGE_OTHER) &&
1668 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1670 (dev->bus->parent == NULL)) {
1671 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1672 dev->resource[i].start = 0;
1673 dev->resource[i].end = 0;
1674 dev->resource[i].flags = 0;
1678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);