2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
28 #include <asm/ptrace.h>
30 #include <asm/export.h>
34 _GLOBAL(call_do_softirq)
37 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
48 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
58 .tc ppc64_caches[TC],ppc64_caches
62 * Write any modified data cache blocks out to memory
63 * and invalidate the corresponding instruction cache blocks.
65 * flush_icache_range(unsigned long start, unsigned long stop)
67 * flush all bytes from start through stop-1 inclusive
70 _GLOBAL_TOC(flush_icache_range)
74 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
76 * Flush the data cache to memory
78 * Different systems have different cache line sizes
79 * and in some cases i-cache and d-cache line sizes differ from
82 ld r10,PPC64_CACHES@toc(r2)
83 lwz r7,DCACHEL1BLOCKSIZE(r10)/* Get cache block size */
85 andc r6,r3,r5 /* round low to line bdy */
86 subf r8,r6,r4 /* compute length */
87 add r8,r8,r5 /* ensure we get enough */
88 lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */
89 srw. r8,r8,r9 /* compute line count */
90 beqlr /* nothing to do? */
97 /* Now invalidate the instruction cache */
99 lwz r7,ICACHEL1BLOCKSIZE(r10) /* Get Icache block size */
101 andc r6,r3,r5 /* round low to line bdy */
102 subf r8,r6,r4 /* compute length */
104 lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */
105 srw. r8,r8,r9 /* compute line count */
106 beqlr /* nothing to do? */
113 _ASM_NOKPROBE_SYMBOL(flush_icache_range)
114 EXPORT_SYMBOL(flush_icache_range)
117 * Like above, but only do the D-cache.
119 * flush_dcache_range(unsigned long start, unsigned long stop)
121 * flush all bytes from start to stop-1 inclusive
123 _GLOBAL_TOC(flush_dcache_range)
126 * Flush the data cache to memory
128 * Different systems have different cache line sizes
130 ld r10,PPC64_CACHES@toc(r2)
131 lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */
133 andc r6,r3,r5 /* round low to line bdy */
134 subf r8,r6,r4 /* compute length */
135 add r8,r8,r5 /* ensure we get enough */
136 lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
137 srw. r8,r8,r9 /* compute line count */
138 beqlr /* nothing to do? */
145 EXPORT_SYMBOL(flush_dcache_range)
147 _GLOBAL(flush_inval_dcache_range)
148 ld r10,PPC64_CACHES@toc(r2)
149 lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */
151 andc r6,r3,r5 /* round low to line bdy */
152 subf r8,r6,r4 /* compute length */
153 add r8,r8,r5 /* ensure we get enough */
154 lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
155 srw. r8,r8,r9 /* compute line count */
156 beqlr /* nothing to do? */
169 * Flush a particular page from the data cache to RAM.
170 * Note: this is necessary because the instruction cache does *not*
171 * snoop from the data cache.
173 * void __flush_dcache_icache(void *page)
175 _GLOBAL(__flush_dcache_icache)
177 * Flush the data cache to memory
179 * Different systems have different cache line sizes
185 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
187 /* Flush the dcache */
188 ld r7,PPC64_CACHES@toc(r2)
189 clrrdi r3,r3,PAGE_SHIFT /* Page align */
190 lwz r4,DCACHEL1BLOCKSPERPAGE(r7) /* Get # dcache blocks per page */
191 lwz r5,DCACHEL1BLOCKSIZE(r7) /* Get dcache block size */
199 /* Now invalidate the icache */
201 lwz r4,ICACHEL1BLOCKSPERPAGE(r7) /* Get # icache blocks per page */
202 lwz r5,ICACHEL1BLOCKSIZE(r7) /* Get icache block size */
211 EXPORT_SYMBOL(__bswapdi2)
213 rlwinm r7,r3,8,0xffffffff
215 rlwinm r9,r8,8,0xffffffff
216 rlwimi r7,r3,24,16,23
218 rlwimi r9,r8,24,16,23
224 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
254 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
256 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
259 * Do an IO access in real mode
290 * Do an IO access in real mode
319 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
321 #ifdef CONFIG_PPC_PASEMI
323 _GLOBAL(real_205_readb)
338 _GLOBAL(real_205_writeb)
353 #endif /* CONFIG_PPC_PASEMI */
356 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
358 * SCOM access functions for 970 (FX only for now)
360 * unsigned long scom970_read(unsigned int address);
361 * void scom970_write(unsigned int address, unsigned long value);
363 * The address passed in is the 24 bits register address. This code
364 * is 970 specific and will not check the status bits, so you should
365 * know what you are doing.
367 _GLOBAL(scom970_read)
374 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
375 * (including parity). On current CPUs they must be 0'd,
376 * and finally or in RW bit
381 /* do the actual scom read */
390 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
391 * that's the best we can do). Not implemented yet as we don't use
392 * the scom on any of the bogus CPUs yet, but may have to be done
396 /* restore interrupts */
401 _GLOBAL(scom970_write)
408 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
409 * (including parity). On current CPUs they must be 0'd.
415 mtspr SPRN_SCOMD,r4 /* write data */
417 mtspr SPRN_SCOMC,r3 /* write command */
422 /* restore interrupts */
425 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
427 /* kexec_wait(phys_cpu)
429 * wait for the flag to change, indicating this kernel is going away but
430 * the slave code for the next one is at addresses 0 to 100.
432 * This is used by all slaves, even those that did not find a matching
433 * paca in the secondary startup code.
435 * Physical (hardware) cpu id should be in r3.
440 addi r5,r5,kexec_flag-1b
443 #ifdef CONFIG_KEXEC_CORE /* use no memory without kexec */
447 #ifdef CONFIG_PPC_BOOK3S_64
450 clrrdi r11,r11,1 /* Clear MSR_LE */
455 /* Create TLB entry in book3e_secondary_core_init */
461 /* this can be in text because we won't change it until we are
462 * running in real anyways
468 #ifdef CONFIG_KEXEC_CORE
469 #ifdef CONFIG_PPC_BOOK3E
471 * BOOK3E has no real MMU mode, so we have to setup the initial TLB
472 * for a core to identity map v:0 to p:0. This current implementation
473 * assumes that 1G is enough for kexec.
477 * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
478 * IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
484 mfspr r10,SPRN_TLB1CFG
485 andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
486 subi r10,r10,1 /* Last entry: no conflict with kernel text */
487 lis r9,MAS0_TLBSEL(1)@h
488 rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
490 /* Set up a temp identity mapping v:0 to p:0 and return to it. */
491 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
492 #define M_IF_NEEDED MAS2_M
494 #define M_IF_NEEDED 0
498 lis r9,(MAS1_VALID|MAS1_IPROT)@h
499 ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
502 LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
505 LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
515 /* kexec_smp_wait(void)
517 * call with interrupts off
518 * note: this is a terminal routine, it does not save lr
520 * get phys id from paca
521 * switch to real mode
522 * mark the paca as no longer used
523 * join other cpus in kexec_wait(phys_id)
525 _GLOBAL(kexec_smp_wait)
526 lhz r3,PACAHWCPUID(r13)
529 li r4,KEXEC_STATE_REAL_MODE
530 stb r4,PACAKEXECSTATE(r13)
536 * switch to real mode (turn mmu off)
537 * we use the early kernel trick that the hardware ignores bits
538 * 0 and 1 (big endian) of the effective address in real mode
540 * don't overwrite r3 here, it is live for kexec_wait above.
542 real_mode: /* assume normal blr return */
543 #ifdef CONFIG_PPC_BOOK3E
544 /* Create an identity mapping. */
549 mflr r11 /* return address to SRR0 */
561 * kexec_sequence(newstack, start, image, control, clear_all(),
564 * does the grungy work with stack switching and real mode switches
565 * also does simple calls to other code
568 _GLOBAL(kexec_sequence)
572 /* switch stacks to newstack -- &kexec_stack.stack */
573 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
581 * This is the best time to turn AMR/IAMR off.
582 * key 0 is used in radix for supervisor<->user
583 * protection, but on hash key 0 is reserved
584 * ideally we want to enter with a clean state.
585 * NOTE, we rely on r0 being 0 from above.
588 BEGIN_FTR_SECTION_NESTED(42)
590 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
591 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
593 /* save regs for local vars on new stack.
594 * yes, we won't go back, but ...
604 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
606 /* save args into preserved regs */
607 mr r31,r3 /* newstack (both) */
608 mr r30,r4 /* start (real) */
609 mr r29,r5 /* image (virt) */
610 mr r28,r6 /* control, unused */
611 mr r27,r7 /* clear_all() fn desc */
612 mr r26,r8 /* copy_with_mmu_off */
613 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
615 /* disable interrupts, we are overwriting kernel data next */
616 #ifdef CONFIG_PPC_BOOK3E
624 /* We need to turn the MMU off unless we are in hash mode
631 /* copy dest pages, flush whole dest image */
633 bl kexec_copy_flush /* (image) */
635 /* turn off mmu now if not done earlier */
640 /* copy 0x100 bytes starting at start to 0 */
642 mr r4,r30 /* start, aka phys mem offset */
645 bl copy_and_flush /* (dest, src, copy limit, start offset) */
646 1: /* assume normal blr return */
648 /* release other cpus to the new kernel secondary start at 0x60 */
651 stw r6,kexec_flag-1b(5)
656 /* clear out hardware hash page table and tlb */
657 #ifdef PPC64_ELF_ABI_v1
658 ld r12,0(r27) /* deref function descriptor */
663 bctrl /* mmu_hash_ops.hpte_clear_all(void); */
666 * kexec image calling is:
667 * the first 0x100 bytes of the entry point are copied to 0
669 * all slaves branch to slave = 0x60 (absolute)
670 * slave(phys_cpu_id);
672 * master goes to start = entry point
673 * start(phys_cpu_id, start, 0);
676 * a wrapper is needed to call existing kernels, here is an approximate
677 * description of one method:
680 * start will be near the boot_block (maybe 0x100 bytes before it?)
681 * it will have a 0x60, which will b to boot_block, where it will wait
682 * and 0 will store phys into struct boot-block and load r3 from there,
683 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
686 * boot block will have all cpus scanning device tree to see if they
687 * are the boot cpu ?????
688 * other device tree differences (prop sizes, va vs pa, etc)...
690 1: mr r3,r25 # my phys cpu
691 mr r4,r30 # start, aka phys mem offset
694 blr /* image->start(physid, image->start, 0); */
695 #endif /* CONFIG_KEXEC_CORE */