2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
46 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
51 * Used by threads before entering deep idle states. Saves SPRs
52 * in interrupt stack frame
56 * Note all register i.e per-core, per-subcore or per-thread is saved
57 * here since any thread in the core might wake up first
61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
71 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
89 * On POWER9, there are idle states such as stop4, invoked via cpuidle,
90 * that lose hypervisor resources. In such cases, we need to save
91 * additional SPRs before entering those idle states so that they can
92 * be restored to their older values on wakeup from the idle state.
94 * On POWER8, the only such deep idle state is winkle which is used
95 * only in the context of CPU-Hotplug, where these additional SPRs are
96 * reinitiazed to a sane value. Hence there is no need to save/restore
101 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
103 power9_save_additional_sprs:
106 std r3, STOP_PID(r13)
107 std r4, STOP_LDBAR(r13)
111 std r3, STOP_FSCR(r13)
112 std r4, STOP_HFSCR(r13)
116 std r3, STOP_MMCRA(r13)
121 std r3, STOP_MMCR1(r13)
122 std r4, STOP_MMCR2(r13)
125 power9_restore_additional_sprs:
131 ld r3, STOP_LDBAR(r13)
132 ld r4, STOP_FSCR(r13)
136 ld r3, STOP_HFSCR(r13)
137 ld r4, STOP_MMCRA(r13)
142 ld r4, STOP_MMCR1(r13)
146 ld r3, STOP_MMCR2(r13)
151 * Used by threads when the lock bit of core_idle_state is set.
152 * Threads will spin in HMT_LOW until the lock bit is cleared.
153 * r14 - pointer to core_idle_state
154 * r15 - used to load contents of core_idle_state
155 * r9 - used as a temporary variable
161 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
165 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
166 bne- core_idle_lock_held
170 * Pass requested state in r3:
171 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
172 * - Requested PSSCR value in POWER9
174 * Address of idle handler to branch to in realmode in r4
176 pnv_powersave_common:
177 /* Use r3 to pass state nap/sleep/winkle */
178 /* NAP is a state loss, we create a regs frame on the
179 * stack, fill it up with the state we care about and
180 * stick a pointer to it in PACAR1. We really only
181 * need to save PC, some CR bits and the NV GPRs,
182 * but for now an interrupt frame will do.
188 stdu r1,-INT_FRAME_SIZE(r1)
192 /* We haven't lost state ... yet */
194 stb r0,PACA_NAPSTATELOST(r13)
196 /* Continue saving state */
205 * POWER9 does not require real mode to stop, and presently does not
206 * set hwthread_state for KVM (threads don't share MMU context), so
207 * we can remain in virtual mode for this.
210 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
213 * Go to real mode to do the nap, as required by the architecture.
214 * Also, we need to be in real mode before setting hwthread_state,
215 * because as soon as we do that, another thread can switch
216 * the MMU context to the guest.
218 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
223 * This is the sequence required to execute idle instructions, as
224 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
226 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
227 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
231 236: cmpd cr0,r0,r0; \
236 .globl pnv_enter_arch207_idle_mode
237 pnv_enter_arch207_idle_mode:
238 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
239 /* Tell KVM we're entering idle */
240 li r4,KVM_HWTHREAD_IN_IDLE
241 /******************************************************/
242 /* N O T E W E L L ! ! ! N O T E W E L L */
243 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
244 /* MUST occur in real mode, i.e. with the MMU off, */
245 /* and the MMU must stay off until we clear this flag */
246 /* and test HSTATE_HWTHREAD_REQ(r13) in */
247 /* pnv_powersave_wakeup in this file. */
248 /* The reason is that another thread can switch the */
249 /* MMU to a guest context whenever this flag is set */
250 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
251 /* that would potentially cause this thread to start */
252 /* executing instructions from guest memory in */
253 /* hypervisor mode, leading to a host crash or data */
254 /* corruption, or worse. */
255 /******************************************************/
256 stb r4,HSTATE_HWTHREAD_STATE(r13)
258 stb r3,PACA_THREAD_IDLE_STATE(r13)
259 cmpwi cr3,r3,PNV_THREAD_SLEEP
261 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
264 /* Sleep or winkle */
265 lbz r7,PACA_THREAD_MASK(r13)
266 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
269 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
274 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
275 bnel- core_idle_lock_held
277 add r15,r15,r5 /* Add if winkle */
278 andc r15,r15,r7 /* Clear thread bit */
280 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
283 * If cr0 = 0, then current thread is the last thread of the core entering
284 * sleep. Last thread needs to execute the hardware bug workaround code if
285 * required by the platform.
286 * Make the workaround call unconditionally here. The below branch call is
287 * patched out when the idle states are discovered if the platform does not
290 .global pnv_fastsleep_workaround_at_entry
291 pnv_fastsleep_workaround_at_entry:
292 beq fastsleep_workaround_at_entry
298 common_enter: /* common code for all the threads entering sleep or winkle */
300 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
302 fastsleep_workaround_at_entry:
303 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
308 /* Fast sleep workaround */
311 bl opal_config_cpu_idle_state
314 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
320 bl save_sprs_to_stack
322 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
325 * r3 - PSSCR value corresponding to the requested stop state.
329 * Check if we are executing the lite variant with ESL=EC=0
331 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
332 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
333 bne .Lhandle_esl_ec_set
335 li r3,0 /* Since we didn't lose state, return 0 */
336 std r3, PACA_REQ_PSSCR(r13)
339 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
340 * it can determine if the wakeup reason is an HMI in
341 * CHECK_HMI_INTERRUPT.
343 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
344 * reason, so there is no point setting r12 to SRR1.
346 * Further, we clear r12 here, so that we don't accidentally enter the
347 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
355 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after
356 * a state-loss idle. Saving and restoring MMCR0 over idle is a
361 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
364 * Check if the requested state is a deep idle state.
366 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
367 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
369 bge .Lhandle_deep_stop
370 PPC_STOP /* Does not return (system reset interrupt) */
374 * Entering deep idle state.
375 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
376 * stack and enter stop
378 lbz r7,PACA_THREAD_MASK(r13)
379 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
383 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
384 bnel- core_idle_lock_held
385 andc r15,r15,r7 /* Clear thread bit */
391 bl save_sprs_to_stack
393 PPC_STOP /* Does not return (system reset interrupt) */
396 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
397 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
399 _GLOBAL(power7_idle_insn)
400 /* Now check if user or arch enabled NAP mode */
401 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
402 b pnv_powersave_common
404 #define CHECK_HMI_INTERRUPT \
405 BEGIN_FTR_SECTION_NESTED(66); \
406 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
407 FTR_SECTION_ELSE_NESTED(66); \
408 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
409 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
410 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
412 /* Invoke opal call to handle hmi */ \
413 ld r2,PACATOC(r13); \
415 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
416 li r3,0; /* NULL argument */ \
417 bl hmi_exception_realmode; \
419 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
423 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
424 * r3 contains desired PSSCR register value.
426 * Offline (CPU unplug) case also must notify KVM that the CPU is
429 _GLOBAL(power9_offline_stop)
430 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
432 * Tell KVM we're entering idle.
433 * This does not have to be done in real mode because the P9 MMU
434 * is independent per-thread. Some steppings share radix/hash mode
435 * between threads, but in that case KVM has a barrier sync in real
436 * mode before and after switching between radix and hash.
438 li r4,KVM_HWTHREAD_IN_IDLE
439 stb r4,HSTATE_HWTHREAD_STATE(r13)
443 _GLOBAL(power9_idle_stop)
444 std r3, PACA_REQ_PSSCR(r13)
445 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
448 lwz r5, PACA_DONT_STOP(r13)
451 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
454 LOAD_REG_ADDR(r4,power_enter_stop)
455 b pnv_powersave_common
457 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
460 * We get here when TM / thread reconfiguration bug workaround
461 * code wants to get the CPU into SMT4 mode, and therefore
462 * we are being asked not to stop.
465 std r3, PACA_REQ_PSSCR(r13)
466 blr /* return 0 for wakeup cause / SRR1 value */
470 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
471 * HSPRG0 will be set to the HSPRG0 value of one of the
472 * threads in this core. Thus the value we have in r13
473 * may not be this thread's paca pointer.
475 * Fortunately, the TIR remains invariant. Since this thread's
476 * paca pointer is recorded in all its sibling's paca, we can
477 * correctly recover this thread's paca pointer if we
478 * know the index of this thread in the core.
480 * This index can be obtained from the TIR.
482 * i.e, thread's position in the core = TIR.
483 * If this value is i, then this thread's paca is
484 * paca->thread_sibling_pacas[i].
486 power9_dd1_recover_paca:
489 * Since each entry in thread_sibling_pacas is 8 bytes
490 * we need to left-shift by 3 bits. Thus r4 = i * 8
493 /* Get &paca->thread_sibling_pacas[0] in r5 */
494 ld r5, PACA_SIBLING_PACA_PTRS(r13)
495 /* Load paca->thread_sibling_pacas[i] into r13 */
499 * Indicate that we have lost NVGPR state
500 * which needs to be restored from the stack.
503 stb r3,PACA_NAPSTATELOST(r13)
507 * Called from machine check handler for powersave wakeups.
508 * Low level machine check processing has already been done. Now just
509 * go through the wake up path to get everything in order.
511 * r3 - The original SRR1 value.
512 * Original SRR[01] have been clobbered.
515 .global pnv_powersave_wakeup_mce
516 pnv_powersave_wakeup_mce:
517 /* Set cr3 for pnv_powersave_wakeup */
518 rlwinm r11,r3,47-31,30,31
522 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
523 * reason into r12, which allows reuse of the system reset wakeup
524 * code without being mistaken for another type of wakeup.
526 oris r12,r3,SRR1_WAKEMCE_RESVD@h
528 b pnv_powersave_wakeup
531 * Called from reset vector for powersave wakeups.
532 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
535 .global pnv_powersave_wakeup
536 pnv_powersave_wakeup:
540 BEGIN_FTR_SECTION_NESTED(70)
541 bl power9_dd1_recover_paca
542 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
543 bl pnv_restore_hyp_resource_arch300
545 bl pnv_restore_hyp_resource_arch207
546 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
548 li r0,PNV_THREAD_RUNNING
549 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
553 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
554 lbz r0,HSTATE_HWTHREAD_STATE(r13)
555 cmpwi r0,KVM_HWTHREAD_IN_KERNEL
557 li r0,KVM_HWTHREAD_IN_KERNEL
558 stb r0,HSTATE_HWTHREAD_STATE(r13)
559 /* Order setting hwthread_state vs. testing hwthread_req */
561 0: lbz r0,HSTATE_HWTHREAD_REQ(r13)
568 /* Return SRR1 from power7_nap() */
569 blt cr3,pnv_wakeup_noloss
573 * Check whether we have woken up with hypervisor state loss.
574 * If yes, restore hypervisor state and return back to link.
576 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
578 pnv_restore_hyp_resource_arch300:
580 * Workaround for POWER9, if we lost resources, the ERAT
581 * might have been mixed up and needs flushing. We also need
582 * to reload MMCR0 (see comment above). We also need to set
583 * then clear bit 60 in MMCRA to ensure the PMU starts running.
591 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
593 ori r4,r4,(1 << (63-60))
595 xori r4,r4,(1 << (63-60))
599 * POWER ISA 3. Use PSSCR to determine if we
600 * are waking up from deep idle state
602 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
603 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
605 BEGIN_FTR_SECTION_NESTED(71)
607 * Assume that we are waking up from the state
608 * same as the Requested Level (RL) in the PSSCR
609 * which are Bits 60-63
611 ld r5,PACA_REQ_PSSCR(r13)
613 FTR_SECTION_ELSE_NESTED(71)
615 * 0-3 bits correspond to Power-Saving Level Status
616 * which indicates the idle state we are waking up from
620 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
621 li r0, 0 /* clear requested_psscr to say we're awake */
622 std r0, PACA_REQ_PSSCR(r13)
624 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
626 blr /* Waking up without hypervisor state loss. */
628 /* Same calling convention as arch300 */
629 pnv_restore_hyp_resource_arch207:
631 * POWER ISA 2.07 or less.
632 * Check if we slept with sleep or winkle.
634 lbz r4,PACA_THREAD_IDLE_STATE(r13)
635 cmpwi cr2,r4,PNV_THREAD_NAP
636 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
639 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
640 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
641 * indicates we are waking with hypervisor state loss from nap.
645 blr /* Waking up without hypervisor state loss */
648 * Called if waking up from idle state which can cause either partial or
649 * complete hyp state loss.
650 * In POWER8, called if waking up from fastsleep or winkle
651 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
654 * cr3 - gt if waking up with partial/complete hypervisor state loss
657 * cr4 - gt or eq if waking up from complete hypervisor state loss.
660 * r4 - PACA_THREAD_IDLE_STATE
665 * Before entering any idle state, the NVGPRs are saved in the stack.
666 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
667 * NVGPRs are restored. If we are here, it is likely that state is lost,
668 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
669 * here are the same as the test to restore NVGPRS:
670 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
671 * and SRR1 test for restoring NVGPRs.
673 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
674 * guarantee they will always be restored. This might be tightened
675 * with careful reading of specs (particularly for ISA300) but this
676 * is already a slow wakeup path and it's simpler to be safe.
679 stb r0,PACA_NAPSTATELOST(r13)
683 * Save SRR1 and LR in NVGPRs as they might be clobbered in
684 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
685 * to determine the wakeup reason if we branch to kvm_start_guest. LR
686 * is required to return back to reset vector after hypervisor state
687 * restore is complete.
694 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
696 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
697 lbz r7,PACA_THREAD_MASK(r13)
700 * Take the core lock to synchronize against other threads.
702 * Lock bit is set in one of the 2 cases-
703 * a. In the sleep/winkle enter path, the last thread is executing
704 * fastsleep workaround code.
705 * b. In the wake up path, another thread is executing fastsleep
706 * workaround undo code or resyncing timebase or restoring context
707 * In either case loop until the lock bit is cleared.
711 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
712 bnel- core_idle_lock_held
713 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
718 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
723 * cr2 - eq if first thread to wakeup in core
724 * cr3- gt if waking up with partial/complete hypervisor state loss
726 * cr4 - gt or eq if waking up from complete hypervisor state loss.
732 * If yes, check if all threads were in winkle, decrement our
733 * winkle count, set all thread winkle bits if all were in winkle.
734 * Check if our thread has a winkle bit set, and set cr4 accordingly
735 * (to match ISA300, above). Pseudo-code for core idle state
736 * transitions for ISA207 is as follows (everything happens atomically
737 * due to store conditional and/or lock bit):
744 * core_idle_state &= ~thread_in_core
749 * bool first_in_core, first_in_subcore;
751 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
752 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
754 * core_idle_state |= thread_in_core;
759 * core_idle_state &= ~thread_in_core;
760 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
765 * bool first_in_core, first_in_subcore, winkle_state_lost;
767 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
768 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
770 * core_idle_state |= thread_in_core;
772 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
773 * core_idle_state |= THREAD_WINKLE_BITS;
774 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
776 * winkle_state_lost = core_idle_state &
777 * (thread_in_core << WINKLE_THREAD_SHIFT);
778 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
782 cmpwi r18,PNV_THREAD_WINKLE
784 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
785 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
787 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
789 /* Shift thread bit to winkle mask, then test if this thread is set,
790 * and remove it from the winkle bits */
794 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
796 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
798 cmpwi r4,0 /* Check if first in subcore */
800 or r15,r15,r7 /* Set thread bit */
801 beq first_thread_in_subcore
802 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
804 or r15,r15,r7 /* Set thread bit */
805 beq cr2,first_thread_in_core
807 /* Not first thread in core or subcore to wake up */
810 first_thread_in_subcore:
812 * If waking up from sleep, subcore state is not lost. Hence
813 * skip subcore state restore
815 blt cr4,subcore_state_restored
817 /* Restore per-subcore state */
826 subcore_state_restored:
828 * Check if the thread is also the first thread in the core. If not,
829 * skip to clear_lock.
833 first_thread_in_core:
836 * First thread in the core waking up from any state which can cause
837 * partial or complete hypervisor state loss. It needs to
838 * call the fastsleep workaround code if the platform requires it.
839 * Call it unconditionally here. The below branch instruction will
840 * be patched out if the platform does not have fastsleep or does not
841 * require the workaround. Patching will be performed during the
842 * discovery of idle-states.
844 .global pnv_fastsleep_workaround_at_exit
845 pnv_fastsleep_workaround_at_exit:
846 b fastsleep_workaround_at_exit
850 * Use cr3 which indicates that we are waking up with atleast partial
851 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
853 ble cr3,.Ltb_resynced
854 /* Time base re-sync */
855 bl opal_resync_timebase;
857 * If waking up from sleep (POWER8), per core state
858 * is not lost, skip to clear_lock.
864 * First thread in the core to wake up and its waking up with
865 * complete hypervisor state loss. Restore per core hypervisor
875 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
883 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
889 * Common to all threads.
891 * If waking up from sleep, hypervisor state is not lost. Hence
892 * skip hypervisor state restore.
894 blt cr4,hypervisor_state_restored
896 /* Waking up from winkle */
898 BEGIN_MMU_FTR_SECTION
900 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
901 /* Restore SLB from PACA */
902 ld r8,PACA_SLBSHADOWPTR(r13)
905 li r3, SLBSHADOW_SAVEAREA
909 andis. r7,r5,SLB_ESID_V@h
916 /* Restore per thread state */
927 /* Call cur_cpu_spec->cpu_restore() */
928 LOAD_REG_ADDR(r4, cur_cpu_spec)
930 ld r12,CPU_SPEC_RESTORE(r4)
931 #ifdef PPC64_ELF_ABI_v1
938 * On POWER9, we can come here on wakeup from a cpuidle stop state.
939 * Hence restore the additional SPRs to the saved value.
941 * On POWER8, we come here only on winkle. Since winkle is used
942 * only in the case of CPU-Hotplug, we don't need to restore
943 * the additional SPRs.
946 bl power9_restore_additional_sprs
947 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
948 hypervisor_state_restored:
952 blr /* return to pnv_powersave_wakeup */
954 fastsleep_workaround_at_exit:
957 bl opal_config_cpu_idle_state
961 * R3 here contains the value that will be returned to the caller
963 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
965 .global pnv_wakeup_loss
970 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
976 addi r1,r1,INT_FRAME_SIZE
983 * R3 here contains the value that will be returned to the caller
985 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
988 lbz r0,PACA_NAPSTATELOST(r13)
994 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
998 addi r1,r1,INT_FRAME_SIZE