2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
26 #include <asm/asm-compat.h>
31 * Use unused space in the interrupt stack to save and restore
32 * registers for winkle support.
47 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
52 * Used by threads before entering deep idle states. Saves SPRs
53 * in interrupt stack frame
57 * Note all register i.e per-core, per-subcore or per-thread is saved
58 * here since any thread in the core might wake up first
62 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
72 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
90 * On POWER9, there are idle states such as stop4, invoked via cpuidle,
91 * that lose hypervisor resources. In such cases, we need to save
92 * additional SPRs before entering those idle states so that they can
93 * be restored to their older values on wakeup from the idle state.
95 * On POWER8, the only such deep idle state is winkle which is used
96 * only in the context of CPU-Hotplug, where these additional SPRs are
97 * reinitiazed to a sane value. Hence there is no need to save/restore
102 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
104 power9_save_additional_sprs:
107 std r3, STOP_PID(r13)
108 std r4, STOP_LDBAR(r13)
112 std r3, STOP_FSCR(r13)
113 std r4, STOP_HFSCR(r13)
117 std r3, STOP_MMCRA(r13)
122 std r3, STOP_MMCR1(r13)
123 std r4, STOP_MMCR2(r13)
126 power9_restore_additional_sprs:
132 ld r3, STOP_LDBAR(r13)
133 ld r4, STOP_FSCR(r13)
137 ld r3, STOP_HFSCR(r13)
138 ld r4, STOP_MMCRA(r13)
143 ld r4, STOP_MMCR1(r13)
147 ld r3, STOP_MMCR2(r13)
152 * Used by threads when the lock bit of core_idle_state is set.
153 * Threads will spin in HMT_LOW until the lock bit is cleared.
154 * r14 - pointer to core_idle_state
155 * r15 - used to load contents of core_idle_state
156 * r9 - used as a temporary variable
162 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
166 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
167 bne- core_idle_lock_held
171 * Pass requested state in r3:
172 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
173 * - Requested PSSCR value in POWER9
175 * Address of idle handler to branch to in realmode in r4
177 pnv_powersave_common:
178 /* Use r3 to pass state nap/sleep/winkle */
179 /* NAP is a state loss, we create a regs frame on the
180 * stack, fill it up with the state we care about and
181 * stick a pointer to it in PACAR1. We really only
182 * need to save PC, some CR bits and the NV GPRs,
183 * but for now an interrupt frame will do.
189 stdu r1,-INT_FRAME_SIZE(r1)
193 /* We haven't lost state ... yet */
195 stb r0,PACA_NAPSTATELOST(r13)
197 /* Continue saving state */
206 * POWER9 does not require real mode to stop, and presently does not
207 * set hwthread_state for KVM (threads don't share MMU context), so
208 * we can remain in virtual mode for this.
211 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
214 * Go to real mode to do the nap, as required by the architecture.
215 * Also, we need to be in real mode before setting hwthread_state,
216 * because as soon as we do that, another thread can switch
217 * the MMU context to the guest.
219 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
224 * This is the sequence required to execute idle instructions, as
225 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
227 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
228 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
232 236: cmpd cr0,r0,r0; \
237 .globl pnv_enter_arch207_idle_mode
238 pnv_enter_arch207_idle_mode:
239 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
240 /* Tell KVM we're entering idle */
241 li r4,KVM_HWTHREAD_IN_IDLE
242 /******************************************************/
243 /* N O T E W E L L ! ! ! N O T E W E L L */
244 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
245 /* MUST occur in real mode, i.e. with the MMU off, */
246 /* and the MMU must stay off until we clear this flag */
247 /* and test HSTATE_HWTHREAD_REQ(r13) in */
248 /* pnv_powersave_wakeup in this file. */
249 /* The reason is that another thread can switch the */
250 /* MMU to a guest context whenever this flag is set */
251 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
252 /* that would potentially cause this thread to start */
253 /* executing instructions from guest memory in */
254 /* hypervisor mode, leading to a host crash or data */
255 /* corruption, or worse. */
256 /******************************************************/
257 stb r4,HSTATE_HWTHREAD_STATE(r13)
259 stb r3,PACA_THREAD_IDLE_STATE(r13)
260 cmpwi cr3,r3,PNV_THREAD_SLEEP
262 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
265 /* Sleep or winkle */
266 lbz r7,PACA_THREAD_MASK(r13)
267 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
270 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
275 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
276 bnel- core_idle_lock_held
278 add r15,r15,r5 /* Add if winkle */
279 andc r15,r15,r7 /* Clear thread bit */
281 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
284 * If cr0 = 0, then current thread is the last thread of the core entering
285 * sleep. Last thread needs to execute the hardware bug workaround code if
286 * required by the platform.
287 * Make the workaround call unconditionally here. The below branch call is
288 * patched out when the idle states are discovered if the platform does not
291 .global pnv_fastsleep_workaround_at_entry
292 pnv_fastsleep_workaround_at_entry:
293 beq fastsleep_workaround_at_entry
299 common_enter: /* common code for all the threads entering sleep or winkle */
301 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
303 fastsleep_workaround_at_entry:
304 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
309 /* Fast sleep workaround */
312 bl opal_config_cpu_idle_state
315 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
321 bl save_sprs_to_stack
323 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
326 * r3 - PSSCR value corresponding to the requested stop state.
330 * Check if we are executing the lite variant with ESL=EC=0
332 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
333 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
334 bne .Lhandle_esl_ec_set
336 li r3,0 /* Since we didn't lose state, return 0 */
337 std r3, PACA_REQ_PSSCR(r13)
340 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
341 * it can determine if the wakeup reason is an HMI in
342 * CHECK_HMI_INTERRUPT.
344 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
345 * reason, so there is no point setting r12 to SRR1.
347 * Further, we clear r12 here, so that we don't accidentally enter the
348 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
356 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after
357 * a state-loss idle. Saving and restoring MMCR0 over idle is a
362 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
365 * Check if the requested state is a deep idle state.
367 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
368 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
370 bge .Lhandle_deep_stop
371 PPC_STOP /* Does not return (system reset interrupt) */
375 * Entering deep idle state.
376 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
377 * stack and enter stop
379 lbz r7,PACA_THREAD_MASK(r13)
380 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
384 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
385 bnel- core_idle_lock_held
386 andc r15,r15,r7 /* Clear thread bit */
392 bl save_sprs_to_stack
394 PPC_STOP /* Does not return (system reset interrupt) */
397 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
398 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
400 _GLOBAL(power7_idle_insn)
401 /* Now check if user or arch enabled NAP mode */
402 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
403 b pnv_powersave_common
405 #define CHECK_HMI_INTERRUPT \
406 BEGIN_FTR_SECTION_NESTED(66); \
407 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
408 FTR_SECTION_ELSE_NESTED(66); \
409 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
410 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
411 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
413 /* Invoke opal call to handle hmi */ \
414 ld r2,PACATOC(r13); \
416 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
417 li r3,0; /* NULL argument */ \
418 bl hmi_exception_realmode; \
420 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
424 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
425 * r3 contains desired PSSCR register value.
427 * Offline (CPU unplug) case also must notify KVM that the CPU is
430 _GLOBAL(power9_offline_stop)
431 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
433 * Tell KVM we're entering idle.
434 * This does not have to be done in real mode because the P9 MMU
435 * is independent per-thread. Some steppings share radix/hash mode
436 * between threads, but in that case KVM has a barrier sync in real
437 * mode before and after switching between radix and hash.
439 li r4,KVM_HWTHREAD_IN_IDLE
440 stb r4,HSTATE_HWTHREAD_STATE(r13)
444 _GLOBAL(power9_idle_stop)
445 std r3, PACA_REQ_PSSCR(r13)
446 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
449 lwz r5, PACA_DONT_STOP(r13)
452 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
455 LOAD_REG_ADDR(r4,power_enter_stop)
456 b pnv_powersave_common
458 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
461 * We get here when TM / thread reconfiguration bug workaround
462 * code wants to get the CPU into SMT4 mode, and therefore
463 * we are being asked not to stop.
466 std r3, PACA_REQ_PSSCR(r13)
467 blr /* return 0 for wakeup cause / SRR1 value */
471 * Called from machine check handler for powersave wakeups.
472 * Low level machine check processing has already been done. Now just
473 * go through the wake up path to get everything in order.
475 * r3 - The original SRR1 value.
476 * Original SRR[01] have been clobbered.
479 .global pnv_powersave_wakeup_mce
480 pnv_powersave_wakeup_mce:
481 /* Set cr3 for pnv_powersave_wakeup */
482 rlwinm r11,r3,47-31,30,31
486 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
487 * reason into r12, which allows reuse of the system reset wakeup
488 * code without being mistaken for another type of wakeup.
490 oris r12,r3,SRR1_WAKEMCE_RESVD@h
492 b pnv_powersave_wakeup
495 * Called from reset vector for powersave wakeups.
496 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
499 .global pnv_powersave_wakeup
500 pnv_powersave_wakeup:
504 bl pnv_restore_hyp_resource_arch300
506 bl pnv_restore_hyp_resource_arch207
507 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
509 li r0,PNV_THREAD_RUNNING
510 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
514 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
515 lbz r0,HSTATE_HWTHREAD_STATE(r13)
516 cmpwi r0,KVM_HWTHREAD_IN_KERNEL
518 li r0,KVM_HWTHREAD_IN_KERNEL
519 stb r0,HSTATE_HWTHREAD_STATE(r13)
520 /* Order setting hwthread_state vs. testing hwthread_req */
522 0: lbz r0,HSTATE_HWTHREAD_REQ(r13)
529 /* Return SRR1 from power7_nap() */
530 blt cr3,pnv_wakeup_noloss
534 * Check whether we have woken up with hypervisor state loss.
535 * If yes, restore hypervisor state and return back to link.
537 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
539 pnv_restore_hyp_resource_arch300:
541 * Workaround for POWER9, if we lost resources, the ERAT
542 * might have been mixed up and needs flushing. We also need
543 * to reload MMCR0 (see comment above). We also need to set
544 * then clear bit 60 in MMCRA to ensure the PMU starts running.
552 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
554 ori r4,r4,(1 << (63-60))
556 xori r4,r4,(1 << (63-60))
560 * POWER ISA 3. Use PSSCR to determine if we
561 * are waking up from deep idle state
563 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
564 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
567 * 0-3 bits correspond to Power-Saving Level Status
568 * which indicates the idle state we are waking up from
572 li r0, 0 /* clear requested_psscr to say we're awake */
573 std r0, PACA_REQ_PSSCR(r13)
575 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
577 blr /* Waking up without hypervisor state loss. */
579 /* Same calling convention as arch300 */
580 pnv_restore_hyp_resource_arch207:
582 * POWER ISA 2.07 or less.
583 * Check if we slept with sleep or winkle.
585 lbz r4,PACA_THREAD_IDLE_STATE(r13)
586 cmpwi cr2,r4,PNV_THREAD_NAP
587 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
590 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
591 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
592 * indicates we are waking with hypervisor state loss from nap.
596 blr /* Waking up without hypervisor state loss */
599 * Called if waking up from idle state which can cause either partial or
600 * complete hyp state loss.
601 * In POWER8, called if waking up from fastsleep or winkle
602 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
605 * cr3 - gt if waking up with partial/complete hypervisor state loss
608 * cr4 - gt or eq if waking up from complete hypervisor state loss.
611 * r4 - PACA_THREAD_IDLE_STATE
616 * Before entering any idle state, the NVGPRs are saved in the stack.
617 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
618 * NVGPRs are restored. If we are here, it is likely that state is lost,
619 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
620 * here are the same as the test to restore NVGPRS:
621 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
622 * and SRR1 test for restoring NVGPRs.
624 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
625 * guarantee they will always be restored. This might be tightened
626 * with careful reading of specs (particularly for ISA300) but this
627 * is already a slow wakeup path and it's simpler to be safe.
630 stb r0,PACA_NAPSTATELOST(r13)
634 * Save SRR1 and LR in NVGPRs as they might be clobbered in
635 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
636 * to determine the wakeup reason if we branch to kvm_start_guest. LR
637 * is required to return back to reset vector after hypervisor state
638 * restore is complete.
645 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
647 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
648 lbz r7,PACA_THREAD_MASK(r13)
651 * Take the core lock to synchronize against other threads.
653 * Lock bit is set in one of the 2 cases-
654 * a. In the sleep/winkle enter path, the last thread is executing
655 * fastsleep workaround code.
656 * b. In the wake up path, another thread is executing fastsleep
657 * workaround undo code or resyncing timebase or restoring context
658 * In either case loop until the lock bit is cleared.
662 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
663 bnel- core_idle_lock_held
664 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
669 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
674 * cr2 - eq if first thread to wakeup in core
675 * cr3- gt if waking up with partial/complete hypervisor state loss
677 * cr4 - gt or eq if waking up from complete hypervisor state loss.
683 * If yes, check if all threads were in winkle, decrement our
684 * winkle count, set all thread winkle bits if all were in winkle.
685 * Check if our thread has a winkle bit set, and set cr4 accordingly
686 * (to match ISA300, above). Pseudo-code for core idle state
687 * transitions for ISA207 is as follows (everything happens atomically
688 * due to store conditional and/or lock bit):
695 * core_idle_state &= ~thread_in_core
700 * bool first_in_core, first_in_subcore;
702 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
703 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
705 * core_idle_state |= thread_in_core;
710 * core_idle_state &= ~thread_in_core;
711 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
716 * bool first_in_core, first_in_subcore, winkle_state_lost;
718 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
719 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
721 * core_idle_state |= thread_in_core;
723 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
724 * core_idle_state |= THREAD_WINKLE_BITS;
725 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
727 * winkle_state_lost = core_idle_state &
728 * (thread_in_core << WINKLE_THREAD_SHIFT);
729 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
733 cmpwi r18,PNV_THREAD_WINKLE
735 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
736 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
738 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
740 /* Shift thread bit to winkle mask, then test if this thread is set,
741 * and remove it from the winkle bits */
745 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
747 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
749 cmpwi r4,0 /* Check if first in subcore */
751 or r15,r15,r7 /* Set thread bit */
752 beq first_thread_in_subcore
753 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
755 or r15,r15,r7 /* Set thread bit */
756 beq cr2,first_thread_in_core
758 /* Not first thread in core or subcore to wake up */
761 first_thread_in_subcore:
763 * If waking up from sleep, subcore state is not lost. Hence
764 * skip subcore state restore
766 blt cr4,subcore_state_restored
768 /* Restore per-subcore state */
777 subcore_state_restored:
779 * Check if the thread is also the first thread in the core. If not,
780 * skip to clear_lock.
784 first_thread_in_core:
787 * First thread in the core waking up from any state which can cause
788 * partial or complete hypervisor state loss. It needs to
789 * call the fastsleep workaround code if the platform requires it.
790 * Call it unconditionally here. The below branch instruction will
791 * be patched out if the platform does not have fastsleep or does not
792 * require the workaround. Patching will be performed during the
793 * discovery of idle-states.
795 .global pnv_fastsleep_workaround_at_exit
796 pnv_fastsleep_workaround_at_exit:
797 b fastsleep_workaround_at_exit
801 * Use cr3 which indicates that we are waking up with atleast partial
802 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
804 ble cr3,.Ltb_resynced
805 /* Time base re-sync */
806 bl opal_resync_timebase;
808 * If waking up from sleep (POWER8), per core state
809 * is not lost, skip to clear_lock.
815 * First thread in the core to wake up and its waking up with
816 * complete hypervisor state loss. Restore per core hypervisor
826 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
834 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
840 * Common to all threads.
842 * If waking up from sleep, hypervisor state is not lost. Hence
843 * skip hypervisor state restore.
845 blt cr4,hypervisor_state_restored
847 /* Waking up from winkle */
849 BEGIN_MMU_FTR_SECTION
851 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
852 /* Restore SLB from PACA */
853 ld r8,PACA_SLBSHADOWPTR(r13)
856 li r3, SLBSHADOW_SAVEAREA
860 andis. r7,r5,SLB_ESID_V@h
867 /* Restore per thread state */
878 /* Call cur_cpu_spec->cpu_restore() */
879 LOAD_REG_ADDR(r4, cur_cpu_spec)
881 ld r12,CPU_SPEC_RESTORE(r4)
882 #ifdef PPC64_ELF_ABI_v1
889 * On POWER9, we can come here on wakeup from a cpuidle stop state.
890 * Hence restore the additional SPRs to the saved value.
892 * On POWER8, we come here only on winkle. Since winkle is used
893 * only in the case of CPU-Hotplug, we don't need to restore
894 * the additional SPRs.
897 bl power9_restore_additional_sprs
898 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
899 hypervisor_state_restored:
903 blr /* return to pnv_powersave_wakeup */
905 fastsleep_workaround_at_exit:
908 bl opal_config_cpu_idle_state
912 * R3 here contains the value that will be returned to the caller
914 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
916 .global pnv_wakeup_loss
921 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
927 addi r1,r1,INT_FRAME_SIZE
934 * R3 here contains the value that will be returned to the caller
936 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
939 lbz r0,PACA_NAPSTATELOST(r13)
945 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
949 addi r1,r1,INT_FRAME_SIZE