1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
4 * using the CPU's debug registers. Derived from
5 * "arch/x86/kernel/hw_breakpoint.c"
7 * Copyright 2010 IBM Corporation
8 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
11 #include <linux/hw_breakpoint.h>
12 #include <linux/notifier.h>
13 #include <linux/kprobes.h>
14 #include <linux/percpu.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/smp.h>
18 #include <linux/debugfs.h>
19 #include <linux/init.h>
21 #include <asm/hw_breakpoint.h>
22 #include <asm/processor.h>
23 #include <asm/sstep.h>
24 #include <asm/debug.h>
25 #include <asm/hvcall.h>
27 #include <linux/uaccess.h>
30 * Stores the breakpoints currently in use on each breakpoint address
31 * register for every cpu
33 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM_MAX]);
36 * Returns total number of data or instruction breakpoints available.
38 int hw_breakpoint_slots(int type)
40 if (type == TYPE_DATA)
42 return 0; /* no instruction breakpoints available */
45 static bool single_step_pending(void)
49 for (i = 0; i < nr_wp_slots(); i++) {
50 if (current->thread.last_hit_ubp[i])
57 * Install a perf counter breakpoint.
59 * We seek a free debug address register and use it for this
62 * Atomic: we hold the counter->ctx->lock and we only handle variables
63 * and registers local to this cpu.
65 int arch_install_hw_breakpoint(struct perf_event *bp)
67 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
68 struct perf_event **slot;
71 for (i = 0; i < nr_wp_slots(); i++) {
72 slot = this_cpu_ptr(&bp_per_reg[i]);
79 if (WARN_ONCE(i == nr_wp_slots(), "Can't find any breakpoint slot"))
83 * Do not install DABR values if the instruction must be single-stepped.
84 * If so, DABR will be populated in single_step_dabr_instruction().
86 if (!single_step_pending())
87 __set_breakpoint(i, info);
93 * Uninstall the breakpoint contained in the given counter.
95 * First we search the debug address register it uses and then we disable
98 * Atomic: we hold the counter->ctx->lock and we only handle variables
99 * and registers local to this cpu.
101 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
103 struct arch_hw_breakpoint null_brk = {0};
104 struct perf_event **slot;
107 for (i = 0; i < nr_wp_slots(); i++) {
108 slot = this_cpu_ptr(&bp_per_reg[i]);
115 if (WARN_ONCE(i == nr_wp_slots(), "Can't find any breakpoint slot"))
118 __set_breakpoint(i, &null_brk);
121 static bool is_ptrace_bp(struct perf_event *bp)
123 return bp->overflow_handler == ptrace_triggered;
127 struct list_head list;
128 struct perf_event *bp;
132 static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
133 static LIST_HEAD(task_bps);
135 static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
137 struct breakpoint *tmp;
139 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
141 return ERR_PTR(-ENOMEM);
143 tmp->ptrace_bp = is_ptrace_bp(bp);
147 static bool bp_addr_range_overlap(struct perf_event *bp1, struct perf_event *bp2)
149 __u64 bp1_saddr, bp1_eaddr, bp2_saddr, bp2_eaddr;
151 bp1_saddr = ALIGN_DOWN(bp1->attr.bp_addr, HW_BREAKPOINT_SIZE);
152 bp1_eaddr = ALIGN(bp1->attr.bp_addr + bp1->attr.bp_len, HW_BREAKPOINT_SIZE);
153 bp2_saddr = ALIGN_DOWN(bp2->attr.bp_addr, HW_BREAKPOINT_SIZE);
154 bp2_eaddr = ALIGN(bp2->attr.bp_addr + bp2->attr.bp_len, HW_BREAKPOINT_SIZE);
156 return (bp1_saddr < bp2_eaddr && bp1_eaddr > bp2_saddr);
159 static bool alternate_infra_bp(struct breakpoint *b, struct perf_event *bp)
161 return is_ptrace_bp(bp) ? !b->ptrace_bp : b->ptrace_bp;
164 static bool can_co_exist(struct breakpoint *b, struct perf_event *bp)
166 return !(alternate_infra_bp(b, bp) && bp_addr_range_overlap(b->bp, bp));
169 static int task_bps_add(struct perf_event *bp)
171 struct breakpoint *tmp;
173 tmp = alloc_breakpoint(bp);
177 list_add(&tmp->list, &task_bps);
181 static void task_bps_remove(struct perf_event *bp)
183 struct list_head *pos, *q;
185 list_for_each_safe(pos, q, &task_bps) {
186 struct breakpoint *tmp = list_entry(pos, struct breakpoint, list);
189 list_del(&tmp->list);
197 * If any task has breakpoint from alternate infrastructure,
198 * return true. Otherwise return false.
200 static bool all_task_bps_check(struct perf_event *bp)
202 struct breakpoint *tmp;
204 list_for_each_entry(tmp, &task_bps, list) {
205 if (!can_co_exist(tmp, bp))
212 * If same task has breakpoint from alternate infrastructure,
213 * return true. Otherwise return false.
215 static bool same_task_bps_check(struct perf_event *bp)
217 struct breakpoint *tmp;
219 list_for_each_entry(tmp, &task_bps, list) {
220 if (tmp->bp->hw.target == bp->hw.target &&
221 !can_co_exist(tmp, bp))
227 static int cpu_bps_add(struct perf_event *bp)
229 struct breakpoint **cpu_bp;
230 struct breakpoint *tmp;
233 tmp = alloc_breakpoint(bp);
237 cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
238 for (i = 0; i < nr_wp_slots(); i++) {
247 static void cpu_bps_remove(struct perf_event *bp)
249 struct breakpoint **cpu_bp;
252 cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
253 for (i = 0; i < nr_wp_slots(); i++) {
257 if (cpu_bp[i]->bp == bp) {
265 static bool cpu_bps_check(int cpu, struct perf_event *bp)
267 struct breakpoint **cpu_bp;
270 cpu_bp = per_cpu_ptr(cpu_bps, cpu);
271 for (i = 0; i < nr_wp_slots(); i++) {
272 if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp))
278 static bool all_cpu_bps_check(struct perf_event *bp)
282 for_each_online_cpu(cpu) {
283 if (cpu_bps_check(cpu, bp))
290 * We don't use any locks to serialize accesses to cpu_bps or task_bps
291 * because are already inside nr_bp_mutex.
293 int arch_reserve_bp_slot(struct perf_event *bp)
297 /* ptrace breakpoint */
298 if (is_ptrace_bp(bp)) {
299 if (all_cpu_bps_check(bp))
302 if (same_task_bps_check(bp))
305 return task_bps_add(bp);
308 /* perf breakpoint */
309 if (is_kernel_addr(bp->attr.bp_addr))
312 if (bp->hw.target && bp->cpu == -1) {
313 if (same_task_bps_check(bp))
316 return task_bps_add(bp);
317 } else if (!bp->hw.target && bp->cpu != -1) {
318 if (all_task_bps_check(bp))
321 return cpu_bps_add(bp);
324 if (same_task_bps_check(bp))
327 ret = cpu_bps_add(bp);
330 ret = task_bps_add(bp);
337 void arch_release_bp_slot(struct perf_event *bp)
339 if (!is_kernel_addr(bp->attr.bp_addr)) {
348 * Perform cleanup of arch-specific counters during unregistration
351 void arch_unregister_hw_breakpoint(struct perf_event *bp)
354 * If the breakpoint is unregistered between a hw_breakpoint_handler()
355 * and the single_step_dabr_instruction(), then cleanup the breakpoint
356 * restoration variables to prevent dangling pointers.
357 * FIXME, this should not be using bp->ctx at all! Sayeth peterz.
359 if (bp->ctx && bp->ctx->task && bp->ctx->task != ((void *)-1L)) {
362 for (i = 0; i < nr_wp_slots(); i++) {
363 if (bp->ctx->task->thread.last_hit_ubp[i] == bp)
364 bp->ctx->task->thread.last_hit_ubp[i] = NULL;
370 * Check for virtual address in kernel space.
372 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
374 return is_kernel_addr(hw->address);
377 int arch_bp_generic_fields(int type, int *gen_bp_type)
380 if (type & HW_BRK_TYPE_READ)
381 *gen_bp_type |= HW_BREAKPOINT_R;
382 if (type & HW_BRK_TYPE_WRITE)
383 *gen_bp_type |= HW_BREAKPOINT_W;
384 if (*gen_bp_type == 0)
390 * Watchpoint match range is always doubleword(8 bytes) aligned on
391 * powerpc. If the given range is crossing doubleword boundary, we
392 * need to increase the length such that next doubleword also get
395 * address len = 6 bytes
397 * |------------v--|------v--------|
398 * | | | | | | | | | | | | | | | | |
399 * |---------------|---------------|
402 * In this case, we should configure hw as:
403 * start_addr = address & ~(HW_BREAKPOINT_SIZE - 1)
406 * @start_addr is inclusive but @end_addr is exclusive.
408 static int hw_breakpoint_validate_len(struct arch_hw_breakpoint *hw)
410 u16 max_len = DABR_MAX_LEN;
412 unsigned long start_addr, end_addr;
414 start_addr = ALIGN_DOWN(hw->address, HW_BREAKPOINT_SIZE);
415 end_addr = ALIGN(hw->address + hw->len, HW_BREAKPOINT_SIZE);
416 hw_len = end_addr - start_addr;
418 if (dawr_enabled()) {
419 max_len = DAWR_MAX_LEN;
420 /* DAWR region can't cross 512 bytes boundary on p10 predecessors */
421 if (!cpu_has_feature(CPU_FTR_ARCH_31) &&
422 (ALIGN_DOWN(start_addr, SZ_512) != ALIGN_DOWN(end_addr - 1, SZ_512)))
424 } else if (IS_ENABLED(CONFIG_PPC_8xx)) {
425 /* 8xx can setup a range without limitation */
429 if (hw_len > max_len)
437 * Validate the arch-specific HW Breakpoint register settings
439 int hw_breakpoint_arch_parse(struct perf_event *bp,
440 const struct perf_event_attr *attr,
441 struct arch_hw_breakpoint *hw)
445 if (!bp || !attr->bp_len)
448 hw->type = HW_BRK_TYPE_TRANSLATE;
449 if (attr->bp_type & HW_BREAKPOINT_R)
450 hw->type |= HW_BRK_TYPE_READ;
451 if (attr->bp_type & HW_BREAKPOINT_W)
452 hw->type |= HW_BRK_TYPE_WRITE;
453 if (hw->type == HW_BRK_TYPE_TRANSLATE)
454 /* must set alteast read or write */
456 if (!attr->exclude_user)
457 hw->type |= HW_BRK_TYPE_USER;
458 if (!attr->exclude_kernel)
459 hw->type |= HW_BRK_TYPE_KERNEL;
460 if (!attr->exclude_hv)
461 hw->type |= HW_BRK_TYPE_HYP;
462 hw->address = attr->bp_addr;
463 hw->len = attr->bp_len;
465 if (!ppc_breakpoint_available())
468 return hw_breakpoint_validate_len(hw);
472 * Restores the breakpoint on the debug registers.
473 * Invoke this function if it is known that the execution context is
474 * about to change to cause loss of MSR_SE settings.
476 void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
478 struct arch_hw_breakpoint *info;
481 for (i = 0; i < nr_wp_slots(); i++) {
482 if (unlikely(tsk->thread.last_hit_ubp[i]))
488 regs_set_return_msr(regs, regs->msr & ~MSR_SE);
489 for (i = 0; i < nr_wp_slots(); i++) {
490 info = counter_arch_bp(__this_cpu_read(bp_per_reg[i]));
491 __set_breakpoint(i, info);
492 tsk->thread.last_hit_ubp[i] = NULL;
496 static bool is_larx_stcx_instr(int type)
498 return type == LARX || type == STCX;
501 static bool is_octword_vsx_instr(int type, int size)
503 return ((type == LOAD_VSX || type == STORE_VSX) && size == 32);
507 * We've failed in reliably handling the hw-breakpoint. Unregister
508 * it and throw a warning message to let the user know about it.
510 static void handler_error(struct perf_event *bp, struct arch_hw_breakpoint *info)
512 WARN(1, "Unable to handle hardware breakpoint. Breakpoint at 0x%lx will be disabled.",
514 perf_event_disable_inatomic(bp);
517 static void larx_stcx_err(struct perf_event *bp, struct arch_hw_breakpoint *info)
519 printk_ratelimited("Breakpoint hit on instruction that can't be emulated. Breakpoint at 0x%lx will be disabled.\n",
521 perf_event_disable_inatomic(bp);
524 static bool stepping_handler(struct pt_regs *regs, struct perf_event **bp,
525 struct arch_hw_breakpoint **info, int *hit,
526 struct ppc_inst instr)
531 /* Do not emulate user-space instructions, instead single-step them */
532 if (user_mode(regs)) {
533 for (i = 0; i < nr_wp_slots(); i++) {
536 current->thread.last_hit_ubp[i] = bp[i];
539 regs_set_return_msr(regs, regs->msr | MSR_SE);
543 stepped = emulate_step(regs, instr);
545 for (i = 0; i < nr_wp_slots(); i++) {
548 handler_error(bp[i], info[i]);
556 static void handle_p10dd1_spurious_exception(struct arch_hw_breakpoint **info,
557 int *hit, unsigned long ea)
560 unsigned long hw_end_addr;
563 * Handle spurious exception only when any bp_per_reg is set.
564 * Otherwise this might be created by xmon and not actually a
565 * spurious exception.
567 for (i = 0; i < nr_wp_slots(); i++) {
571 hw_end_addr = ALIGN(info[i]->address + info[i]->len, HW_BREAKPOINT_SIZE);
574 * Ending address of DAWR range is less than starting
577 if ((hw_end_addr - 1) >= ea)
581 * Those addresses need to be in the same or in two
582 * consecutive 512B blocks;
584 if (((hw_end_addr - 1) >> 10) != (ea >> 10))
588 * 'op address + 64B' generates an address that has a
589 * carry into bit 52 (crosses 2K boundary).
591 if ((ea & 0x800) == ((ea + 64) & 0x800))
597 if (i == nr_wp_slots())
600 for (i = 0; i < nr_wp_slots(); i++) {
603 info[i]->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
608 int hw_breakpoint_handler(struct die_args *args)
611 int rc = NOTIFY_STOP;
612 struct perf_event *bp[HBP_NUM_MAX] = { NULL };
613 struct pt_regs *regs = args->regs;
614 struct arch_hw_breakpoint *info[HBP_NUM_MAX] = { NULL };
616 int hit[HBP_NUM_MAX] = {0};
618 bool ptrace_bp = false;
619 struct ppc_inst instr = ppc_inst(0);
624 /* Disable breakpoints during exception handling */
625 hw_breakpoint_disable();
628 * The counter may be concurrently released but that can only
629 * occur from a call_rcu() path. We can then safely fetch
630 * the breakpoint, use its callback, touch its counter
631 * while we are in an rcu_read_lock() path.
635 if (!IS_ENABLED(CONFIG_PPC_8xx))
636 wp_get_instr_detail(regs, &instr, &type, &size, &ea);
638 for (i = 0; i < nr_wp_slots(); i++) {
639 bp[i] = __this_cpu_read(bp_per_reg[i]);
643 info[i] = counter_arch_bp(bp[i]);
644 info[i]->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
646 if (wp_check_constraints(regs, instr, ea, type, size, info[i])) {
647 if (!IS_ENABLED(CONFIG_PPC_8xx) &&
648 ppc_inst_equal(instr, ppc_inst(0))) {
649 handler_error(bp[i], info[i]);
655 if (is_ptrace_bp(bp[i]))
666 /* Workaround for Power10 DD1 */
667 if (!IS_ENABLED(CONFIG_PPC_8xx) && mfspr(SPRN_PVR) == 0x800100 &&
668 is_octword_vsx_instr(type, size)) {
669 handle_p10dd1_spurious_exception(info, hit, ea);
677 * Return early after invoking user-callback function without restoring
678 * DABR if the breakpoint is from ptrace which always operates in
679 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
680 * generated in do_dabr().
683 for (i = 0; i < nr_wp_slots(); i++) {
686 perf_bp_event(bp[i], regs);
693 if (!IS_ENABLED(CONFIG_PPC_8xx)) {
694 if (is_larx_stcx_instr(type)) {
695 for (i = 0; i < nr_wp_slots(); i++) {
698 larx_stcx_err(bp[i], info[i]);
704 if (!stepping_handler(regs, bp, info, hit, instr))
709 * As a policy, the callback is invoked in a 'trigger-after-execute'
712 for (i = 0; i < nr_wp_slots(); i++) {
715 if (!(info[i]->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
716 perf_bp_event(bp[i], regs);
720 for (i = 0; i < nr_wp_slots(); i++) {
723 __set_breakpoint(i, info[i]);
730 NOKPROBE_SYMBOL(hw_breakpoint_handler);
733 * Handle single-step exceptions following a DABR hit.
735 static int single_step_dabr_instruction(struct die_args *args)
737 struct pt_regs *regs = args->regs;
738 struct perf_event *bp = NULL;
739 struct arch_hw_breakpoint *info;
744 * Check if we are single-stepping as a result of a
745 * previous HW Breakpoint exception
747 for (i = 0; i < nr_wp_slots(); i++) {
748 bp = current->thread.last_hit_ubp[i];
754 info = counter_arch_bp(bp);
757 * We shall invoke the user-defined callback function in the
758 * single stepping handler to confirm to 'trigger-after-execute'
761 if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
762 perf_bp_event(bp, regs);
763 current->thread.last_hit_ubp[i] = NULL;
769 for (i = 0; i < nr_wp_slots(); i++) {
770 bp = __this_cpu_read(bp_per_reg[i]);
774 info = counter_arch_bp(bp);
775 __set_breakpoint(i, info);
779 * If the process was being single-stepped by ptrace, let the
780 * other single-step actions occur (e.g. generate SIGTRAP).
782 if (test_thread_flag(TIF_SINGLESTEP))
787 NOKPROBE_SYMBOL(single_step_dabr_instruction);
790 * Handle debug exception notifications.
792 int hw_breakpoint_exceptions_notify(
793 struct notifier_block *unused, unsigned long val, void *data)
795 int ret = NOTIFY_DONE;
799 ret = hw_breakpoint_handler(data);
802 ret = single_step_dabr_instruction(data);
808 NOKPROBE_SYMBOL(hw_breakpoint_exceptions_notify);
811 * Release the user breakpoints used by ptrace
813 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
816 struct thread_struct *t = &tsk->thread;
818 for (i = 0; i < nr_wp_slots(); i++) {
819 unregister_hw_breakpoint(t->ptrace_bps[i]);
820 t->ptrace_bps[i] = NULL;
824 void hw_breakpoint_pmu_read(struct perf_event *bp)
829 void ptrace_triggered(struct perf_event *bp,
830 struct perf_sample_data *data, struct pt_regs *regs)
832 struct perf_event_attr attr;
835 * Disable the breakpoint request here since ptrace has defined a
836 * one-shot behaviour for breakpoint exceptions in PPC64.
837 * The SIGTRAP signal is generated automatically for us in do_dabr().
838 * We don't have to do anything about that here
841 attr.disabled = true;
842 modify_user_hw_breakpoint(bp, &attr);