arch/powerpc/kernel/head_booke.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __HEAD_BOOKE_H__
   3 #define __HEAD_BOOKE_H__
   4
   5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
   6 #include <asm/kvm_asm.h>
   7 #include <asm/kvm_booke_hv_asm.h>
   8
   9 #ifdef __ASSEMBLY__
  10
  11 /*
  12  * Macros used for common Book-e exception handling
  13  */
  14
  15 #define SET_IVOR(vector_number, vector_label)           \
  16                 li      r26,vector_label@l;             \
  17                 mtspr   SPRN_IVOR##vector_number,r26;   \
  18                 sync
  19
  20 #if (THREAD_SHIFT < 15)
  21 #define ALLOC_STACK_FRAME(reg, val)                     \
  22         addi reg,reg,val
  23 #else
  24 #define ALLOC_STACK_FRAME(reg, val)                     \
  25         addis   reg,reg,val@ha;                         \
  26         addi    reg,reg,val@l
  27 #endif
  28
  29 /*
  30  * Macro used to get to thread save registers.
  31  * Note that entries 0-3 are used for the prolog code, and the remaining
  32  * entries are available for specific exception use in the event a handler
  33  * requires more than 4 scratch registers.
  34  */
  35 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
  36
  37 #ifdef CONFIG_PPC_FSL_BOOK3E
  38 #define BOOKE_CLEAR_BTB(reg)                                                                    \
  39 START_BTB_FLUSH_SECTION                                                         \
  40         BTB_FLUSH(reg)                                                                  \
  41 END_BTB_FLUSH_SECTION
  42 #else
  43 #define BOOKE_CLEAR_BTB(reg)
  44 #endif
  45
  46
  47 #define NORMAL_EXCEPTION_PROLOG(intno)                                               \
  48         mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
  49         mfspr   r10, SPRN_SPRG_THREAD;                                       \
  50         stw     r11, THREAD_NORMSAVE(0)(r10);                                \
  51         stw     r13, THREAD_NORMSAVE(2)(r10);                                \
  52         mfcr    r13;                    /* save CR in r13 for now          */\
  53         mfspr   r11, SPRN_SRR1;                                              \
  54         DO_KVM  BOOKE_INTERRUPT_##intno SPRN_SRR1;                           \
  55         andi.   r11, r11, MSR_PR;       /* check whether user or kernel    */\
  56         mr      r11, r1;                                                     \
  57         beq     1f;                                                          \
  58         BOOKE_CLEAR_BTB(r11)                                            \
  59         /* if from user, start at top of this thread's kernel stack */       \
  60         lwz     r11, TASK_STACK - THREAD(r10);                               \
  61         ALLOC_STACK_FRAME(r11, THREAD_SIZE);                                 \
  62 1 :     subi    r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */     \
  63         stw     r13, _CCR(r11);         /* save various registers */         \
  64         stw     r12,GPR12(r11);                                              \
  65         stw     r9,GPR9(r11);                                                \
  66         mfspr   r13, SPRN_SPRG_RSCRATCH0;                                    \
  67         stw     r13, GPR10(r11);                                             \
  68         lwz     r12, THREAD_NORMSAVE(0)(r10);                                \
  69         stw     r12,GPR11(r11);                                              \
  70         lwz     r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */              \
  71         mflr    r10;                                                         \
  72         stw     r10,_LINK(r11);                                              \
  73         mfspr   r12,SPRN_SRR0;                                               \
  74         stw     r1, GPR1(r11);                                               \
  75         mfspr   r9,SPRN_SRR1;                                                \
  76         stw     r1, 0(r11);                                                  \
  77         mr      r1, r11;                                                     \
  78         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
  79         stw     r0,GPR0(r11);                                                \
  80         lis     r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
  81         addi    r10, r10, STACK_FRAME_REGS_MARKER@l;                         \
  82         stw     r10, 8(r11);                                                 \
  83         SAVE_4GPRS(3, r11);                                                  \
  84         SAVE_2GPRS(7, r11)
  85
  86 .macro SYSCALL_ENTRY trapno intno srr1
  87         mfspr   r10, SPRN_SPRG_THREAD
  88 #ifdef CONFIG_KVM_BOOKE_HV
  89 BEGIN_FTR_SECTION
  90         mtspr   SPRN_SPRG_WSCRATCH0, r10
  91         stw     r11, THREAD_NORMSAVE(0)(r10)
  92         stw     r13, THREAD_NORMSAVE(2)(r10)
  93         mfcr    r13                     /* save CR in r13 for now          */
  94         mfspr   r11, SPRN_SRR1
  95         mtocrf  0x80, r11       /* check MSR[GS] without clobbering reg */
  96         bf      3, 1975f
  97         b       kvmppc_handler_\intno\()_\srr1
  98 1975:
  99         mr      r12, r13
 100         lwz     r13, THREAD_NORMSAVE(2)(r10)
 101 FTR_SECTION_ELSE
 102 #endif
 103         mfcr    r12
 104 #ifdef CONFIG_KVM_BOOKE_HV
 105 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
 106 #endif
 107         mfspr   r9, SPRN_SRR1
 108         BOOKE_CLEAR_BTB(r11)
 109         andi.   r11, r9, MSR_PR
 110         lwz     r11, TASK_STACK - THREAD(r10)
 111         rlwinm  r12,r12,0,4,2   /* Clear SO bit in CR */
 112         beq-    99f
 113         ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE)
 114         stw     r12, _CCR(r11)          /* save various registers */
 115         mflr    r12
 116         stw     r12,_LINK(r11)
 117         mfspr   r12,SPRN_SRR0
 118         stw     r1, GPR1(r11)
 119         stw     r1, 0(r11)
 120         mr      r1, r11
 121         stw     r12,_NIP(r11)
 122         rlwinm  r9,r9,0,14,12           /* clear MSR_WE (necessary?)       */
 123         lis     r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
 124         stw     r2,GPR2(r11)
 125         addi    r12, r12, STACK_FRAME_REGS_MARKER@l
 126         stw     r9,_MSR(r11)
 127         li      r2, \trapno + 1
 128         stw     r12, 8(r11)
 129         stw     r2,_TRAP(r11)
 130         SAVE_GPR(0, r11)
 131         SAVE_4GPRS(3, r11)
 132         SAVE_2GPRS(7, r11)
 133
 134         addi    r11,r1,STACK_FRAME_OVERHEAD
 135         addi    r2,r10,-THREAD
 136         stw     r11,PT_REGS(r10)
 137         /* Check to see if the dbcr0 register is set up to debug.  Use the
 138            internal debug mode bit to do this. */
 139         lwz     r12,THREAD_DBCR0(r10)
 140         andis.  r12,r12,DBCR0_IDM@h
 141         ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
 142         beq+    3f
 143         /* From user and task is ptraced - load up global dbcr0 */
 144         li      r12,-1                  /* clear all pending debug events */
 145         mtspr   SPRN_DBSR,r12
 146         lis     r11,global_dbcr0@ha
 147         tophys(r11,r11)
 148         addi    r11,r11,global_dbcr0@l
 149 #ifdef CONFIG_SMP
 150         lwz     r10, TASK_CPU(r2)
 151         slwi    r10, r10, 3
 152         add     r11, r11, r10
 153 #endif
 154         lwz     r12,0(r11)
 155         mtspr   SPRN_DBCR0,r12
 156         lwz     r12,4(r11)
 157         addi    r12,r12,-1
 158         stw     r12,4(r11)
 159
 160 3:
 161         tovirt(r2, r2)                  /* set r2 to current */
 162         lis     r11, transfer_to_syscall@h
 163         ori     r11, r11, transfer_to_syscall@l
 164 #ifdef CONFIG_TRACE_IRQFLAGS
 165         /*
 166          * If MSR is changing we need to keep interrupts disabled at this point
 167          * otherwise we might risk taking an interrupt before we tell lockdep
 168          * they are enabled.
 169          */
 170         lis     r10, MSR_KERNEL@h
 171         ori     r10, r10, MSR_KERNEL@l
 172         rlwimi  r10, r9, 0, MSR_EE
 173 #else
 174         lis     r10, (MSR_KERNEL | MSR_EE)@h
 175         ori     r10, r10, (MSR_KERNEL | MSR_EE)@l
 176 #endif
 177         mtspr   SPRN_SRR1,r10
 178         mtspr   SPRN_SRR0,r11
 179         RFI                             /* jump to handler, enable MMU */
 180 99:     b       ret_from_kernel_syscall
 181 .endm
 182
 183 /* To handle the additional exception priority levels on 40x and Book-E
 184  * processors we allocate a stack per additional priority level.
 185  *
 186  * On 40x critical is the only additional level
 187  * On 44x/e500 we have critical and machine check
 188  * On e200 we have critical and debug (machine check occurs via critical)
 189  *
 190  * Additionally we reserve a SPRG for each priority level so we can free up a
 191  * GPR to use as the base for indirect access to the exception stacks.  This
 192  * is necessary since the MMU is always on, for Book-E parts, and the stacks
 193  * are offset from KERNELBASE.
 194  *
 195  * There is some space optimization to be had here if desired.  However
 196  * to allow for a common kernel with support for debug exceptions either
 197  * going to critical or their own debug level we aren't currently
 198  * providing configurations that micro-optimize space usage.
 199  */
 200
 201 #define MC_STACK_BASE           mcheckirq_ctx
 202 #define CRIT_STACK_BASE         critirq_ctx
 203
 204 /* only on e500mc/e200 */
 205 #define DBG_STACK_BASE          dbgirq_ctx
 206
 207 #define EXC_LVL_FRAME_OVERHEAD  (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
 208
 209 #ifdef CONFIG_SMP
 210 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
 211         mfspr   r8,SPRN_PIR;                            \
 212         slwi    r8,r8,2;                                \
 213         addis   r8,r8,level##_STACK_BASE@ha;            \
 214         lwz     r8,level##_STACK_BASE@l(r8);            \
 215         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 216 #else
 217 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
 218         lis     r8,level##_STACK_BASE@ha;               \
 219         lwz     r8,level##_STACK_BASE@l(r8);            \
 220         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 221 #endif
 222
 223 /*
 224  * Exception prolog for critical/machine check exceptions.  This is a
 225  * little different from the normal exception prolog above since a
 226  * critical/machine check exception can potentially occur at any point
 227  * during normal exception processing. Thus we cannot use the same SPRG
 228  * registers as the normal prolog above. Instead we use a portion of the
 229  * critical/machine check exception stack at low physical addresses.
 230  */
 231 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
 232         mtspr   SPRN_SPRG_WSCRATCH_##exc_level,r8;                           \
 233         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
 234         stw     r9,GPR9(r8);            /* save various registers          */\
 235         mfcr    r9;                     /* save CR in r9 for now           */\
 236         stw     r10,GPR10(r8);                                               \
 237         stw     r11,GPR11(r8);                                               \
 238         stw     r9,_CCR(r8);            /* save CR on stack                */\
 239         mfspr   r11,exc_level_srr1;     /* check whether user or kernel    */\
 240         DO_KVM  BOOKE_INTERRUPT_##intno exc_level_srr1;                      \
 241         BOOKE_CLEAR_BTB(r10)                                            \
 242         andi.   r11,r11,MSR_PR;                                              \
 243         mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
 244         lwz     r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
 245         addi    r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame    */\
 246         beq     1f;                                                          \
 247         /* COMING FROM USER MODE */                                          \
 248         stw     r9,_CCR(r11);           /* save CR                         */\
 249         lwz     r10,GPR10(r8);          /* copy regs from exception stack  */\
 250         lwz     r9,GPR9(r8);                                                 \
 251         stw     r10,GPR10(r11);                                              \
 252         lwz     r10,GPR11(r8);                                               \
 253         stw     r9,GPR9(r11);                                                \
 254         stw     r10,GPR11(r11);                                              \
 255         b       2f;                                                          \
 256         /* COMING FROM PRIV MODE */                                          \
 257 1:      mr      r11, r8;                                                             \
 258 2:      mfspr   r8,SPRN_SPRG_RSCRATCH_##exc_level;                           \
 259         stw     r12,GPR12(r11);         /* save various registers          */\
 260         mflr    r10;                                                         \
 261         stw     r10,_LINK(r11);                                              \
 262         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 263         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 264         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 265         stw     r9,_ESR(r11);           /* exception was taken             */\
 266         mfspr   r12,exc_level_srr0;                                          \
 267         stw     r1,GPR1(r11);                                                \
 268         mfspr   r9,exc_level_srr1;                                           \
 269         stw     r1,0(r11);                                                   \
 270         mr      r1,r11;                                                      \
 271         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 272         stw     r0,GPR0(r11);                                                \
 273         SAVE_4GPRS(3, r11);                                                  \
 274         SAVE_2GPRS(7, r11)
 275
 276 #define CRITICAL_EXCEPTION_PROLOG(intno) \
 277                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
 278 #define DEBUG_EXCEPTION_PROLOG \
 279                 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
 280 #define MCHECK_EXCEPTION_PROLOG \
 281                 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
 282                         SPRN_MCSRR0, SPRN_MCSRR1)
 283
 284 /*
 285  * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
 286  * being delivered to the host.  This exception can only happen
 287  * inside a KVM guest -- so we just handle up to the DO_KVM rather
 288  * than try to fit this into one of the existing prolog macros.
 289  */
 290 #define GUEST_DOORBELL_EXCEPTION \
 291         START_EXCEPTION(GuestDoorbell);                                      \
 292         mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
 293         mfspr   r10, SPRN_SPRG_THREAD;                                       \
 294         stw     r11, THREAD_NORMSAVE(0)(r10);                                \
 295         mfspr   r11, SPRN_SRR1;                                              \
 296         stw     r13, THREAD_NORMSAVE(2)(r10);                                \
 297         mfcr    r13;                    /* save CR in r13 for now          */\
 298         DO_KVM  BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1;                      \
 299         trap
 300
 301 /*
 302  * Exception vectors.
 303  */
 304 #define START_EXCEPTION(label)                                               \
 305         .align 5;                                                            \
 306 label:
 307
 308 #define EXCEPTION(n, intno, label, hdlr, xfer)                  \
 309         START_EXCEPTION(label);                                 \
 310         NORMAL_EXCEPTION_PROLOG(intno);                         \
 311         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 312         xfer(n, hdlr)
 313
 314 #define CRITICAL_EXCEPTION(n, intno, label, hdlr)                       \
 315         START_EXCEPTION(label);                                         \
 316         CRITICAL_EXCEPTION_PROLOG(intno);                               \
 317         addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
 318         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 319                           crit_transfer_to_handler, ret_from_crit_exc)
 320
 321 #define MCHECK_EXCEPTION(n, label, hdlr)                        \
 322         START_EXCEPTION(label);                                 \
 323         MCHECK_EXCEPTION_PROLOG;                                \
 324         mfspr   r5,SPRN_ESR;                                    \
 325         stw     r5,_ESR(r11);                                   \
 326         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 327         EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 328                           mcheck_transfer_to_handler, ret_from_mcheck_exc)
 329
 330 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret)   \
 331         li      r10,trap;                                       \
 332         stw     r10,_TRAP(r11);                                 \
 333         lis     r10,msr@h;                                      \
 334         ori     r10,r10,msr@l;                                  \
 335         bl      tfer;                                           \
 336         .long   hdlr;                                           \
 337         .long   ret
 338
 339 #define EXC_XFER_STD(n, hdlr)           \
 340         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \
 341                           ret_from_except_full)
 342
 343 #define EXC_XFER_LITE(n, hdlr)          \
 344         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
 345                           ret_from_except)
 346
 347 /* Check for a single step debug exception while in an exception
 348  * handler before state has been saved.  This is to catch the case
 349  * where an instruction that we are trying to single step causes
 350  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 351  * the exception handler generates a single step debug exception.
 352  *
 353  * If we get a debug trap on the first instruction of an exception handler,
 354  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 355  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 356  * The exception handler was handling a non-critical interrupt, so it will
 357  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 358  * the MSR_DE bit set.
 359  */
 360 #define DEBUG_DEBUG_EXCEPTION                                                 \
 361         START_EXCEPTION(DebugDebug);                                          \
 362         DEBUG_EXCEPTION_PROLOG;                                               \
 363                                                                               \
 364         /*                                                                    \
 365          * If there is a single step or branch-taken exception in an          \
 366          * exception entry sequence, it was probably meant to apply to        \
 367          * the code where the exception occurred (since exception entry       \
 368          * doesn't turn off DE automatically).  We simulate the effect        \
 369          * of turning off DE on entry to an exception handler by turning      \
 370          * off DE in the DSRR1 value and clearing the debug status.           \
 371          */                                                                   \
 372         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 373         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
 374         beq+    2f;                                                           \
 375                                                                               \
 376         lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
 377         ori     r10,r10,interrupt_base@l;                                     \
 378         cmplw   r12,r10;                                                      \
 379         blt+    2f;                     /* addr below exception vectors */    \
 380                                                                               \
 381         lis     r10,interrupt_end@h;                                          \
 382         ori     r10,r10,interrupt_end@l;                                      \
 383         cmplw   r12,r10;                                                      \
 384         bgt+    2f;                     /* addr above exception vectors */    \
 385                                                                               \
 386         /* here it looks like we got an inappropriate debug exception. */     \
 387 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CDRR1 value */     \
 388         lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
 389         mtspr   SPRN_DBSR,r10;                                                \
 390         /* restore state and get out */                                       \
 391         lwz     r10,_CCR(r11);                                                \
 392         lwz     r0,GPR0(r11);                                                 \
 393         lwz     r1,GPR1(r11);                                                 \
 394         mtcrf   0x80,r10;                                                     \
 395         mtspr   SPRN_DSRR0,r12;                                               \
 396         mtspr   SPRN_DSRR1,r9;                                                \
 397         lwz     r9,GPR9(r11);                                                 \
 398         lwz     r12,GPR12(r11);                                               \
 399         mtspr   SPRN_SPRG_WSCRATCH_DBG,r8;                                    \
 400         BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
 401         lwz     r10,GPR10(r8);                                                \
 402         lwz     r11,GPR11(r8);                                                \
 403         mfspr   r8,SPRN_SPRG_RSCRATCH_DBG;                                    \
 404                                                                               \
 405         PPC_RFDI;                                                             \
 406         b       .;                                                            \
 407                                                                               \
 408         /* continue normal handling for a debug exception... */               \
 409 2:      mfspr   r4,SPRN_DBSR;                                                 \
 410         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 411         EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), debug_transfer_to_handler, ret_from_debug_exc)
 412
 413 #define DEBUG_CRIT_EXCEPTION                                                  \
 414         START_EXCEPTION(DebugCrit);                                           \
 415         CRITICAL_EXCEPTION_PROLOG(DEBUG);                                     \
 416                                                                               \
 417         /*                                                                    \
 418          * If there is a single step or branch-taken exception in an          \
 419          * exception entry sequence, it was probably meant to apply to        \
 420          * the code where the exception occurred (since exception entry       \
 421          * doesn't turn off DE automatically).  We simulate the effect        \
 422          * of turning off DE on entry to an exception handler by turning      \
 423          * off DE in the CSRR1 value and clearing the debug status.           \
 424          */                                                                   \
 425         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 426         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
 427         beq+    2f;                                                           \
 428                                                                               \
 429         lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
 430         ori     r10,r10,interrupt_base@l;                                     \
 431         cmplw   r12,r10;                                                      \
 432         blt+    2f;                     /* addr below exception vectors */    \
 433                                                                               \
 434         lis     r10,interrupt_end@h;                                          \
 435         ori     r10,r10,interrupt_end@l;                                      \
 436         cmplw   r12,r10;                                                      \
 437         bgt+    2f;                     /* addr above exception vectors */    \
 438                                                                               \
 439         /* here it looks like we got an inappropriate debug exception. */     \
 440 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
 441         lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
 442         mtspr   SPRN_DBSR,r10;                                                \
 443         /* restore state and get out */                                       \
 444         lwz     r10,_CCR(r11);                                                \
 445         lwz     r0,GPR0(r11);                                                 \
 446         lwz     r1,GPR1(r11);                                                 \
 447         mtcrf   0x80,r10;                                                     \
 448         mtspr   SPRN_CSRR0,r12;                                               \
 449         mtspr   SPRN_CSRR1,r9;                                                \
 450         lwz     r9,GPR9(r11);                                                 \
 451         lwz     r12,GPR12(r11);                                               \
 452         mtspr   SPRN_SPRG_WSCRATCH_CRIT,r8;                                   \
 453         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
 454         lwz     r10,GPR10(r8);                                                \
 455         lwz     r11,GPR11(r8);                                                \
 456         mfspr   r8,SPRN_SPRG_RSCRATCH_CRIT;                                   \
 457                                                                               \
 458         rfci;                                                                 \
 459         b       .;                                                            \
 460                                                                               \
 461         /* continue normal handling for a critical exception... */            \
 462 2:      mfspr   r4,SPRN_DBSR;                                                 \
 463         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 464         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), crit_transfer_to_handler, ret_from_crit_exc)
 465
 466 #define DATA_STORAGE_EXCEPTION                                                \
 467         START_EXCEPTION(DataStorage)                                          \
 468         NORMAL_EXCEPTION_PROLOG(DATA_STORAGE);                \
 469         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 470         stw     r5,_ESR(r11);                                                 \
 471         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR */                   \
 472         stw     r4, _DEAR(r11);                                               \
 473         EXC_XFER_LITE(0x0300, handle_page_fault)
 474
 475 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
 476         START_EXCEPTION(InstructionStorage)                                   \
 477         NORMAL_EXCEPTION_PROLOG(INST_STORAGE);                \
 478         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 479         stw     r5,_ESR(r11);                                                 \
 480         mr      r4,r12;                 /* Pass SRR0 as arg2 */               \
 481         stw     r4, _DEAR(r11);                                               \
 482         li      r5,0;                   /* Pass zero as arg3 */               \
 483         EXC_XFER_LITE(0x0400, handle_page_fault)
 484
 485 #define ALIGNMENT_EXCEPTION                                                   \
 486         START_EXCEPTION(Alignment)                                            \
 487         NORMAL_EXCEPTION_PROLOG(ALIGNMENT);                   \
 488         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */       \
 489         stw     r4,_DEAR(r11);                                                \
 490         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 491         EXC_XFER_STD(0x0600, alignment_exception)
 492
 493 #define PROGRAM_EXCEPTION                                                     \
 494         START_EXCEPTION(Program)                                              \
 495         NORMAL_EXCEPTION_PROLOG(PROGRAM);                     \
 496         mfspr   r4,SPRN_ESR;            /* Grab the ESR and save it */        \
 497         stw     r4,_ESR(r11);                                                 \
 498         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 499         EXC_XFER_STD(0x0700, program_check_exception)
 500
 501 #define DECREMENTER_EXCEPTION                                                 \
 502         START_EXCEPTION(Decrementer)                                          \
 503         NORMAL_EXCEPTION_PROLOG(DECREMENTER);                 \
 504         lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
 505         mtspr   SPRN_TSR,r0;            /* Clear the DEC interrupt */         \
 506         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 507         EXC_XFER_LITE(0x0900, timer_interrupt)
 508
 509 #define FP_UNAVAILABLE_EXCEPTION                                              \
 510         START_EXCEPTION(FloatingPointUnavailable)                             \
 511         NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL);                  \
 512         beq     1f;                                                           \
 513         bl      load_up_fpu;            /* if from user, just load it up */   \
 514         b       fast_exception_return;                                        \
 515 1:      addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 516         EXC_XFER_STD(0x800, kernel_fp_unavailable_exception)
 517
 518 #else /* __ASSEMBLY__ */
 519 struct exception_regs {
 520         unsigned long mas0;
 521         unsigned long mas1;
 522         unsigned long mas2;
 523         unsigned long mas3;
 524         unsigned long mas6;
 525         unsigned long mas7;
 526         unsigned long srr0;
 527         unsigned long srr1;
 528         unsigned long csrr0;
 529         unsigned long csrr1;
 530         unsigned long dsrr0;
 531         unsigned long dsrr1;
 532         unsigned long saved_ksp_limit;
 533 };
 534
 535 /* ensure this structure is always sized to a multiple of the stack alignment */
 536 #define STACK_EXC_LVL_FRAME_SIZE        ALIGN(sizeof (struct exception_regs), 16)
 537
 538 #endif /* __ASSEMBLY__ */
 539 #endif /* __HEAD_BOOKE_H__ */