arch/powerpc/kernel/head_booke.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __HEAD_BOOKE_H__
   3 #define __HEAD_BOOKE_H__
   4
   5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
   6 #include <asm/kvm_asm.h>
   7 #include <asm/kvm_booke_hv_asm.h>
   8
   9 #ifdef __ASSEMBLY__
  10
  11 /*
  12  * Macros used for common Book-e exception handling
  13  */
  14
  15 #define SET_IVOR(vector_number, vector_label)           \
  16                 li      r26,vector_label@l;             \
  17                 mtspr   SPRN_IVOR##vector_number,r26;   \
  18                 sync
  19
  20 #if (THREAD_SHIFT < 15)
  21 #define ALLOC_STACK_FRAME(reg, val)                     \
  22         addi reg,reg,val
  23 #else
  24 #define ALLOC_STACK_FRAME(reg, val)                     \
  25         addis   reg,reg,val@ha;                         \
  26         addi    reg,reg,val@l
  27 #endif
  28
  29 /*
  30  * Macro used to get to thread save registers.
  31  * Note that entries 0-3 are used for the prolog code, and the remaining
  32  * entries are available for specific exception use in the event a handler
  33  * requires more than 4 scratch registers.
  34  */
  35 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
  36
  37 #ifdef CONFIG_PPC_FSL_BOOK3E
  38 #define BOOKE_CLEAR_BTB(reg)                                                                    \
  39 START_BTB_FLUSH_SECTION                                                         \
  40         BTB_FLUSH(reg)                                                                  \
  41 END_BTB_FLUSH_SECTION
  42 #else
  43 #define BOOKE_CLEAR_BTB(reg)
  44 #endif
  45
  46
  47 #define NORMAL_EXCEPTION_PROLOG(trapno, intno)                                               \
  48         mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
  49         mfspr   r10, SPRN_SPRG_THREAD;                                       \
  50         stw     r11, THREAD_NORMSAVE(0)(r10);                                \
  51         stw     r13, THREAD_NORMSAVE(2)(r10);                                \
  52         mfcr    r13;                    /* save CR in r13 for now          */\
  53         mfspr   r11, SPRN_SRR1;                                              \
  54         DO_KVM  BOOKE_INTERRUPT_##intno SPRN_SRR1;                           \
  55         andi.   r11, r11, MSR_PR;       /* check whether user or kernel    */\
  56         LOAD_REG_IMMEDIATE(r11, MSR_KERNEL);                            \
  57         mtmsr   r11;                                                    \
  58         mr      r11, r1;                                                     \
  59         beq     1f;                                                          \
  60         BOOKE_CLEAR_BTB(r11)                                            \
  61         /* if from user, start at top of this thread's kernel stack */       \
  62         lwz     r11, TASK_STACK - THREAD(r10);                               \
  63         ALLOC_STACK_FRAME(r11, THREAD_SIZE);                                 \
  64 1 :     subi    r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */     \
  65         stw     r13, _CCR(r11);         /* save various registers */         \
  66         stw     r12,GPR12(r11);                                              \
  67         stw     r9,GPR9(r11);                                                \
  68         mfspr   r13, SPRN_SPRG_RSCRATCH0;                                    \
  69         stw     r13, GPR10(r11);                                             \
  70         lwz     r12, THREAD_NORMSAVE(0)(r10);                                \
  71         stw     r12,GPR11(r11);                                              \
  72         lwz     r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */              \
  73         mflr    r10;                                                         \
  74         stw     r10,_LINK(r11);                                              \
  75         mfspr   r12,SPRN_SRR0;                                               \
  76         stw     r1, GPR1(r11);                                               \
  77         mfspr   r9,SPRN_SRR1;                                                \
  78         stw     r1, 0(r11);                                                  \
  79         mr      r1, r11;                                                     \
  80         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
  81         COMMON_EXCEPTION_PROLOG_END trapno
  82
  83 .macro COMMON_EXCEPTION_PROLOG_END trapno
  84         stw     r0,GPR0(r1)
  85         lis     r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
  86         addi    r10, r10, STACK_FRAME_REGS_MARKER@l
  87         stw     r10, 8(r1)
  88         li      r10, \trapno
  89         stw     r10,_TRAP(r1)
  90         SAVE_4GPRS(3, r1)
  91         SAVE_2GPRS(7, r1)
  92         SAVE_NVGPRS(r1)
  93         stw     r2,GPR2(r1)
  94         stw     r12,_NIP(r1)
  95         stw     r9,_MSR(r1)
  96         mfctr   r10
  97         mfspr   r2,SPRN_SPRG_THREAD
  98         stw     r10,_CTR(r1)
  99         tovirt(r2, r2)
 100         mfspr   r10,SPRN_XER
 101         addi    r2, r2, -THREAD
 102         stw     r10,_XER(r1)
 103         addi    r3,r1,STACK_FRAME_OVERHEAD
 104 .endm
 105
 106 .macro prepare_transfer_to_handler
 107 #ifdef CONFIG_E500
 108         andi.   r12,r9,MSR_PR
 109         bne     777f
 110         bl      prepare_transfer_to_handler
 111 777:
 112 #endif
 113 .endm
 114
 115 .macro SYSCALL_ENTRY trapno intno srr1
 116         mfspr   r10, SPRN_SPRG_THREAD
 117 #ifdef CONFIG_KVM_BOOKE_HV
 118 BEGIN_FTR_SECTION
 119         mtspr   SPRN_SPRG_WSCRATCH0, r10
 120         stw     r11, THREAD_NORMSAVE(0)(r10)
 121         stw     r13, THREAD_NORMSAVE(2)(r10)
 122         mfcr    r13                     /* save CR in r13 for now          */
 123         mfspr   r11, SPRN_SRR1
 124         mtocrf  0x80, r11       /* check MSR[GS] without clobbering reg */
 125         bf      3, 1975f
 126         b       kvmppc_handler_\intno\()_\srr1
 127 1975:
 128         mr      r12, r13
 129         lwz     r13, THREAD_NORMSAVE(2)(r10)
 130 FTR_SECTION_ELSE
 131 #endif
 132         mfcr    r12
 133 #ifdef CONFIG_KVM_BOOKE_HV
 134 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
 135 #endif
 136         mfspr   r9, SPRN_SRR1
 137         BOOKE_CLEAR_BTB(r11)
 138         lwz     r11, TASK_STACK - THREAD(r10)
 139         rlwinm  r12,r12,0,4,2   /* Clear SO bit in CR */
 140         ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE)
 141         stw     r12, _CCR(r11)          /* save various registers */
 142         mflr    r12
 143         stw     r12,_LINK(r11)
 144         mfspr   r12,SPRN_SRR0
 145         stw     r1, GPR1(r11)
 146         stw     r1, 0(r11)
 147         mr      r1, r11
 148         stw     r12,_NIP(r11)
 149         rlwinm  r9,r9,0,14,12           /* clear MSR_WE (necessary?)       */
 150         lis     r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
 151         stw     r2,GPR2(r11)
 152         addi    r12, r12, STACK_FRAME_REGS_MARKER@l
 153         stw     r9,_MSR(r11)
 154         li      r2, \trapno
 155         stw     r12, 8(r11)
 156         stw     r2,_TRAP(r11)
 157         SAVE_GPR(0, r11)
 158         SAVE_4GPRS(3, r11)
 159         SAVE_2GPRS(7, r11)
 160
 161         addi    r2,r10,-THREAD
 162         b       transfer_to_syscall     /* jump to handler */
 163 .endm
 164
 165 /* To handle the additional exception priority levels on 40x and Book-E
 166  * processors we allocate a stack per additional priority level.
 167  *
 168  * On 40x critical is the only additional level
 169  * On 44x/e500 we have critical and machine check
 170  *
 171  * Additionally we reserve a SPRG for each priority level so we can free up a
 172  * GPR to use as the base for indirect access to the exception stacks.  This
 173  * is necessary since the MMU is always on, for Book-E parts, and the stacks
 174  * are offset from KERNELBASE.
 175  *
 176  * There is some space optimization to be had here if desired.  However
 177  * to allow for a common kernel with support for debug exceptions either
 178  * going to critical or their own debug level we aren't currently
 179  * providing configurations that micro-optimize space usage.
 180  */
 181
 182 #define MC_STACK_BASE           mcheckirq_ctx
 183 #define CRIT_STACK_BASE         critirq_ctx
 184
 185 /* only on e500mc */
 186 #define DBG_STACK_BASE          dbgirq_ctx
 187
 188 #define EXC_LVL_FRAME_OVERHEAD  (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
 189
 190 #ifdef CONFIG_SMP
 191 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
 192         mfspr   r8,SPRN_PIR;                            \
 193         slwi    r8,r8,2;                                \
 194         addis   r8,r8,level##_STACK_BASE@ha;            \
 195         lwz     r8,level##_STACK_BASE@l(r8);            \
 196         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 197 #else
 198 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
 199         lis     r8,level##_STACK_BASE@ha;               \
 200         lwz     r8,level##_STACK_BASE@l(r8);            \
 201         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 202 #endif
 203
 204 /*
 205  * Exception prolog for critical/machine check exceptions.  This is a
 206  * little different from the normal exception prolog above since a
 207  * critical/machine check exception can potentially occur at any point
 208  * during normal exception processing. Thus we cannot use the same SPRG
 209  * registers as the normal prolog above. Instead we use a portion of the
 210  * critical/machine check exception stack at low physical addresses.
 211  */
 212 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, trapno, intno, exc_level_srr0, exc_level_srr1) \
 213         mtspr   SPRN_SPRG_WSCRATCH_##exc_level,r8;                           \
 214         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
 215         stw     r9,GPR9(r8);            /* save various registers          */\
 216         mfcr    r9;                     /* save CR in r9 for now           */\
 217         stw     r10,GPR10(r8);                                               \
 218         stw     r11,GPR11(r8);                                               \
 219         stw     r9,_CCR(r8);            /* save CR on stack                */\
 220         mfspr   r11,exc_level_srr1;     /* check whether user or kernel    */\
 221         DO_KVM  BOOKE_INTERRUPT_##intno exc_level_srr1;                      \
 222         BOOKE_CLEAR_BTB(r10)                                            \
 223         andi.   r11,r11,MSR_PR;                                              \
 224         LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));  \
 225         mtmsr   r11;                                                    \
 226         mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
 227         lwz     r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
 228         addi    r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame    */\
 229         beq     1f;                                                          \
 230         /* COMING FROM USER MODE */                                          \
 231         stw     r9,_CCR(r11);           /* save CR                         */\
 232         lwz     r10,GPR10(r8);          /* copy regs from exception stack  */\
 233         lwz     r9,GPR9(r8);                                                 \
 234         stw     r10,GPR10(r11);                                              \
 235         lwz     r10,GPR11(r8);                                               \
 236         stw     r9,GPR9(r11);                                                \
 237         stw     r10,GPR11(r11);                                              \
 238         b       2f;                                                          \
 239         /* COMING FROM PRIV MODE */                                          \
 240 1:      mr      r11, r8;                                                             \
 241 2:      mfspr   r8,SPRN_SPRG_RSCRATCH_##exc_level;                           \
 242         stw     r12,GPR12(r11);         /* save various registers          */\
 243         mflr    r10;                                                         \
 244         stw     r10,_LINK(r11);                                              \
 245         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 246         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 247         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 248         stw     r9,_ESR(r11);           /* exception was taken             */\
 249         mfspr   r12,exc_level_srr0;                                          \
 250         stw     r1,GPR1(r11);                                                \
 251         mfspr   r9,exc_level_srr1;                                           \
 252         stw     r1,0(r11);                                                   \
 253         mr      r1,r11;                                                      \
 254         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 255         COMMON_EXCEPTION_PROLOG_END trapno
 256
 257 #define SAVE_xSRR(xSRR)                 \
 258         mfspr   r0,SPRN_##xSRR##0;      \
 259         stw     r0,_##xSRR##0(r1);      \
 260         mfspr   r0,SPRN_##xSRR##1;      \
 261         stw     r0,_##xSRR##1(r1)
 262
 263
 264 .macro SAVE_MMU_REGS
 265 #ifdef CONFIG_PPC_BOOK3E_MMU
 266         mfspr   r0,SPRN_MAS0
 267         stw     r0,MAS0(r1)
 268         mfspr   r0,SPRN_MAS1
 269         stw     r0,MAS1(r1)
 270         mfspr   r0,SPRN_MAS2
 271         stw     r0,MAS2(r1)
 272         mfspr   r0,SPRN_MAS3
 273         stw     r0,MAS3(r1)
 274         mfspr   r0,SPRN_MAS6
 275         stw     r0,MAS6(r1)
 276 #ifdef CONFIG_PHYS_64BIT
 277         mfspr   r0,SPRN_MAS7
 278         stw     r0,MAS7(r1)
 279 #endif /* CONFIG_PHYS_64BIT */
 280 #endif /* CONFIG_PPC_BOOK3E_MMU */
 281 #ifdef CONFIG_44x
 282         mfspr   r0,SPRN_MMUCR
 283         stw     r0,MMUCR(r1)
 284 #endif
 285 .endm
 286
 287 #define CRITICAL_EXCEPTION_PROLOG(trapno, intno) \
 288                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, trapno+2, intno, SPRN_CSRR0, SPRN_CSRR1)
 289 #define DEBUG_EXCEPTION_PROLOG(trapno) \
 290                 EXC_LEVEL_EXCEPTION_PROLOG(DBG, trapno+8, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
 291 #define MCHECK_EXCEPTION_PROLOG(trapno) \
 292                 EXC_LEVEL_EXCEPTION_PROLOG(MC, trapno+4, MACHINE_CHECK, \
 293                         SPRN_MCSRR0, SPRN_MCSRR1)
 294
 295 /*
 296  * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
 297  * being delivered to the host.  This exception can only happen
 298  * inside a KVM guest -- so we just handle up to the DO_KVM rather
 299  * than try to fit this into one of the existing prolog macros.
 300  */
 301 #define GUEST_DOORBELL_EXCEPTION \
 302         START_EXCEPTION(GuestDoorbell);                                      \
 303         mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
 304         mfspr   r10, SPRN_SPRG_THREAD;                                       \
 305         stw     r11, THREAD_NORMSAVE(0)(r10);                                \
 306         mfspr   r11, SPRN_SRR1;                                              \
 307         stw     r13, THREAD_NORMSAVE(2)(r10);                                \
 308         mfcr    r13;                    /* save CR in r13 for now          */\
 309         DO_KVM  BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1;                      \
 310         trap
 311
 312 /*
 313  * Exception vectors.
 314  */
 315 #define START_EXCEPTION(label)                                               \
 316         .align 5;                                                            \
 317 label:
 318
 319 #define EXCEPTION(n, intno, label, hdlr)                        \
 320         START_EXCEPTION(label);                                 \
 321         NORMAL_EXCEPTION_PROLOG(n, intno);                      \
 322         prepare_transfer_to_handler;                            \
 323         bl      hdlr;                                           \
 324         b       interrupt_return
 325
 326 #define CRITICAL_EXCEPTION(n, intno, label, hdlr)                       \
 327         START_EXCEPTION(label);                                         \
 328         CRITICAL_EXCEPTION_PROLOG(n, intno);                            \
 329         SAVE_MMU_REGS;                                                  \
 330         SAVE_xSRR(SRR);                                                 \
 331         prepare_transfer_to_handler;                                    \
 332         bl      hdlr;                                                   \
 333         b       ret_from_crit_exc
 334
 335 #define MCHECK_EXCEPTION(n, label, hdlr)                        \
 336         START_EXCEPTION(label);                                 \
 337         MCHECK_EXCEPTION_PROLOG(n);                             \
 338         mfspr   r5,SPRN_ESR;                                    \
 339         stw     r5,_ESR(r11);                                   \
 340         SAVE_xSRR(DSRR);                                        \
 341         SAVE_xSRR(CSRR);                                        \
 342         SAVE_MMU_REGS;                                          \
 343         SAVE_xSRR(SRR);                                         \
 344         prepare_transfer_to_handler;                            \
 345         bl      hdlr;                                           \
 346         b       ret_from_mcheck_exc
 347
 348 /* Check for a single step debug exception while in an exception
 349  * handler before state has been saved.  This is to catch the case
 350  * where an instruction that we are trying to single step causes
 351  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 352  * the exception handler generates a single step debug exception.
 353  *
 354  * If we get a debug trap on the first instruction of an exception handler,
 355  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 356  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 357  * The exception handler was handling a non-critical interrupt, so it will
 358  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 359  * the MSR_DE bit set.
 360  */
 361 #define DEBUG_DEBUG_EXCEPTION                                                 \
 362         START_EXCEPTION(DebugDebug);                                          \
 363         DEBUG_EXCEPTION_PROLOG(2000);                                                 \
 364                                                                               \
 365         /*                                                                    \
 366          * If there is a single step or branch-taken exception in an          \
 367          * exception entry sequence, it was probably meant to apply to        \
 368          * the code where the exception occurred (since exception entry       \
 369          * doesn't turn off DE automatically).  We simulate the effect        \
 370          * of turning off DE on entry to an exception handler by turning      \
 371          * off DE in the DSRR1 value and clearing the debug status.           \
 372          */                                                                   \
 373         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 374         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
 375         beq+    2f;                                                           \
 376                                                                               \
 377         lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
 378         ori     r10,r10,interrupt_base@l;                                     \
 379         cmplw   r12,r10;                                                      \
 380         blt+    2f;                     /* addr below exception vectors */    \
 381                                                                               \
 382         lis     r10,interrupt_end@h;                                          \
 383         ori     r10,r10,interrupt_end@l;                                      \
 384         cmplw   r12,r10;                                                      \
 385         bgt+    2f;                     /* addr above exception vectors */    \
 386                                                                               \
 387         /* here it looks like we got an inappropriate debug exception. */     \
 388 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CDRR1 value */     \
 389         lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
 390         mtspr   SPRN_DBSR,r10;                                                \
 391         /* restore state and get out */                                       \
 392         lwz     r10,_CCR(r11);                                                \
 393         lwz     r0,GPR0(r11);                                                 \
 394         lwz     r1,GPR1(r11);                                                 \
 395         mtcrf   0x80,r10;                                                     \
 396         mtspr   SPRN_DSRR0,r12;                                               \
 397         mtspr   SPRN_DSRR1,r9;                                                \
 398         lwz     r9,GPR9(r11);                                                 \
 399         lwz     r12,GPR12(r11);                                               \
 400         mtspr   SPRN_SPRG_WSCRATCH_DBG,r8;                                    \
 401         BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
 402         lwz     r10,GPR10(r8);                                                \
 403         lwz     r11,GPR11(r8);                                                \
 404         mfspr   r8,SPRN_SPRG_RSCRATCH_DBG;                                    \
 405                                                                               \
 406         PPC_RFDI;                                                             \
 407         b       .;                                                            \
 408                                                                               \
 409         /* continue normal handling for a debug exception... */               \
 410 2:      mfspr   r4,SPRN_DBSR;                                                 \
 411         stw     r4,_ESR(r11);           /* DebugException takes DBSR in _ESR */\
 412         SAVE_xSRR(CSRR);                                                      \
 413         SAVE_MMU_REGS;                                                        \
 414         SAVE_xSRR(SRR);                                                       \
 415         prepare_transfer_to_handler;                                  \
 416         bl      DebugException;                                               \
 417         b       ret_from_debug_exc
 418
 419 #define DEBUG_CRIT_EXCEPTION                                                  \
 420         START_EXCEPTION(DebugCrit);                                           \
 421         CRITICAL_EXCEPTION_PROLOG(2000,DEBUG);                                \
 422                                                                               \
 423         /*                                                                    \
 424          * If there is a single step or branch-taken exception in an          \
 425          * exception entry sequence, it was probably meant to apply to        \
 426          * the code where the exception occurred (since exception entry       \
 427          * doesn't turn off DE automatically).  We simulate the effect        \
 428          * of turning off DE on entry to an exception handler by turning      \
 429          * off DE in the CSRR1 value and clearing the debug status.           \
 430          */                                                                   \
 431         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 432         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
 433         beq+    2f;                                                           \
 434                                                                               \
 435         lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
 436         ori     r10,r10,interrupt_base@l;                                     \
 437         cmplw   r12,r10;                                                      \
 438         blt+    2f;                     /* addr below exception vectors */    \
 439                                                                               \
 440         lis     r10,interrupt_end@h;                                          \
 441         ori     r10,r10,interrupt_end@l;                                      \
 442         cmplw   r12,r10;                                                      \
 443         bgt+    2f;                     /* addr above exception vectors */    \
 444                                                                               \
 445         /* here it looks like we got an inappropriate debug exception. */     \
 446 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
 447         lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
 448         mtspr   SPRN_DBSR,r10;                                                \
 449         /* restore state and get out */                                       \
 450         lwz     r10,_CCR(r11);                                                \
 451         lwz     r0,GPR0(r11);                                                 \
 452         lwz     r1,GPR1(r11);                                                 \
 453         mtcrf   0x80,r10;                                                     \
 454         mtspr   SPRN_CSRR0,r12;                                               \
 455         mtspr   SPRN_CSRR1,r9;                                                \
 456         lwz     r9,GPR9(r11);                                                 \
 457         lwz     r12,GPR12(r11);                                               \
 458         mtspr   SPRN_SPRG_WSCRATCH_CRIT,r8;                                   \
 459         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
 460         lwz     r10,GPR10(r8);                                                \
 461         lwz     r11,GPR11(r8);                                                \
 462         mfspr   r8,SPRN_SPRG_RSCRATCH_CRIT;                                   \
 463                                                                               \
 464         rfci;                                                                 \
 465         b       .;                                                            \
 466                                                                               \
 467         /* continue normal handling for a critical exception... */            \
 468 2:      mfspr   r4,SPRN_DBSR;                                                 \
 469         stw     r4,_ESR(r11);           /* DebugException takes DBSR in _ESR */\
 470         SAVE_MMU_REGS;                                                        \
 471         SAVE_xSRR(SRR);                                                       \
 472         prepare_transfer_to_handler;                                          \
 473         bl      DebugException;                                               \
 474         b       ret_from_crit_exc
 475
 476 #define DATA_STORAGE_EXCEPTION                                                \
 477         START_EXCEPTION(DataStorage)                                          \
 478         NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE);                 \
 479         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 480         stw     r5,_ESR(r11);                                                 \
 481         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR */                   \
 482         stw     r4, _DEAR(r11);                                               \
 483         prepare_transfer_to_handler;                                          \
 484         bl      do_page_fault;                                                \
 485         b       interrupt_return
 486
 487 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
 488         START_EXCEPTION(InstructionStorage)                                   \
 489         NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE);                 \
 490         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 491         stw     r5,_ESR(r11);                                                 \
 492         stw     r12, _DEAR(r11);        /* Pass SRR0 as arg2 */               \
 493         prepare_transfer_to_handler;                                          \
 494         bl      do_page_fault;                                                \
 495         b       interrupt_return
 496
 497 #define ALIGNMENT_EXCEPTION                                                   \
 498         START_EXCEPTION(Alignment)                                            \
 499         NORMAL_EXCEPTION_PROLOG(0x600, ALIGNMENT);                    \
 500         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */       \
 501         stw     r4,_DEAR(r11);                                                \
 502         prepare_transfer_to_handler;                                          \
 503         bl      alignment_exception;                                          \
 504         REST_NVGPRS(r1);                                                      \
 505         b       interrupt_return
 506
 507 #define PROGRAM_EXCEPTION                                                     \
 508         START_EXCEPTION(Program)                                              \
 509         NORMAL_EXCEPTION_PROLOG(0x700, PROGRAM);                      \
 510         mfspr   r4,SPRN_ESR;            /* Grab the ESR and save it */        \
 511         stw     r4,_ESR(r11);                                                 \
 512         prepare_transfer_to_handler;                                          \
 513         bl      program_check_exception;                                      \
 514         REST_NVGPRS(r1);                                                      \
 515         b       interrupt_return
 516
 517 #define DECREMENTER_EXCEPTION                                                 \
 518         START_EXCEPTION(Decrementer)                                          \
 519         NORMAL_EXCEPTION_PROLOG(0x900, DECREMENTER);                  \
 520         lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
 521         mtspr   SPRN_TSR,r0;            /* Clear the DEC interrupt */         \
 522         prepare_transfer_to_handler;                                          \
 523         bl      timer_interrupt;                                              \
 524         b       interrupt_return
 525
 526 #define FP_UNAVAILABLE_EXCEPTION                                              \
 527         START_EXCEPTION(FloatingPointUnavailable)                             \
 528         NORMAL_EXCEPTION_PROLOG(0x800, FP_UNAVAIL);                   \
 529         beq     1f;                                                           \
 530         bl      load_up_fpu;            /* if from user, just load it up */   \
 531         b       fast_exception_return;                                        \
 532 1:      prepare_transfer_to_handler;                                          \
 533         bl      kernel_fp_unavailable_exception;                              \
 534         b       interrupt_return
 535
 536 #else /* __ASSEMBLY__ */
 537 struct exception_regs {
 538         unsigned long mas0;
 539         unsigned long mas1;
 540         unsigned long mas2;
 541         unsigned long mas3;
 542         unsigned long mas6;
 543         unsigned long mas7;
 544         unsigned long srr0;
 545         unsigned long srr1;
 546         unsigned long csrr0;
 547         unsigned long csrr1;
 548         unsigned long dsrr0;
 549         unsigned long dsrr1;
 550 };
 551
 552 /* ensure this structure is always sized to a multiple of the stack alignment */
 553 #define STACK_EXC_LVL_FRAME_SIZE        ALIGN(sizeof (struct exception_regs), 16)
 554
 555 #endif /* __ASSEMBLY__ */
 556 #endif /* __HEAD_BOOKE_H__ */