3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/export.h>
34 #include <asm/code-patching-asm.h>
36 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
37 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
38 #define SIMPLE_KERNEL_ADDRESS 1
42 * We need an ITLB miss handler for kernel addresses if:
43 * - Either we have modules
44 * - Or we have not pinned the first 8M
46 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
47 defined(CONFIG_DEBUG_PAGEALLOC)
48 #define ITLB_MISS_KERNEL 1
52 * Value for the bits that have fixed value in RPN entries.
53 * Also used for tagging DAR for DTLBerror.
55 #define RPN_PATTERN 0x00f0
57 #define PAGE_SHIFT_512K 19
58 #define PAGE_SHIFT_8M 23
65 * This port was done on an MBX board with an 860. Right now I only
66 * support an ELF compressed (zImage) boot from EPPC-Bug because the
67 * code there loads up some registers before calling us:
68 * r3: ptr to board info data
69 * r4: initrd_start or if no initrd then 0
70 * r5: initrd_end - unused if r4 is 0
71 * r6: Start of command line string
72 * r7: End of command line string
74 * I decided to use conditional compilation instead of checking PVR and
75 * adding more processor specific branches around code I don't need.
76 * Since this is an embedded processor, I also appreciate any memory
79 * The MPC8xx does not have any BATs, but it supports large page sizes.
80 * We first initialize the MMU to support 8M byte pages, then load one
81 * entry into each of the instruction and data TLBs to map the first
82 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
83 * the "internal" processor registers before MMU_init is called.
89 mr r31,r3 /* save device tree ptr */
91 /* We have to turn on the MMU right away so we get cache modes
96 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
102 ori r0,r0,MSR_DR|MSR_IR
105 ori r0,r0,start_here@l
107 rfi /* enables MMU */
110 #ifdef CONFIG_PERF_EVENTS
113 .globl itlb_miss_counter
117 .globl dtlb_miss_counter
121 .globl instruction_counter
127 * Exception entry code. This code runs with address translation
128 * turned off, i.e. using physical addresses.
129 * We assume sprg3 has the physical address of the current
130 * task's thread_struct.
132 #define EXCEPTION_PROLOG \
133 mtspr SPRN_SPRG_SCRATCH0, r10; \
134 mtspr SPRN_SPRG_SCRATCH1, r11; \
136 EXCEPTION_PROLOG_1; \
139 #define EXCEPTION_PROLOG_1 \
140 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
141 andi. r11,r11,MSR_PR; \
142 tophys(r11,r1); /* use tophys(r1) if kernel */ \
144 mfspr r11,SPRN_SPRG_THREAD; \
145 lwz r11,THREAD_INFO-THREAD(r11); \
146 addi r11,r11,THREAD_SIZE; \
148 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
151 #define EXCEPTION_PROLOG_2 \
152 stw r10,_CCR(r11); /* save registers */ \
153 stw r12,GPR12(r11); \
155 mfspr r10,SPRN_SPRG_SCRATCH0; \
156 stw r10,GPR10(r11); \
157 mfspr r12,SPRN_SPRG_SCRATCH1; \
158 stw r12,GPR11(r11); \
160 stw r10,_LINK(r11); \
161 mfspr r12,SPRN_SRR0; \
162 mfspr r9,SPRN_SRR1; \
165 tovirt(r1,r11); /* set new kernel sp */ \
166 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
169 lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
170 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
172 SAVE_4GPRS(3, r11); \
176 * Note: code which follows this uses cr0.eq (set if from kernel),
177 * r11, r12 (SRR0), and r9 (SRR1).
179 * Note2: once we have set r1 we are in a position to take exceptions
180 * again, and we could thus set MSR:RI at that point.
186 #define EXCEPTION(n, label, hdlr, xfer) \
190 addi r3,r1,STACK_FRAME_OVERHEAD; \
193 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
195 stw r10,_TRAP(r11); \
203 #define COPY_EE(d, s) rlwimi d,s,0,16,16
206 #define EXC_XFER_STD(n, hdlr) \
207 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
208 ret_from_except_full)
210 #define EXC_XFER_LITE(n, hdlr) \
211 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
214 #define EXC_XFER_EE(n, hdlr) \
215 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
216 ret_from_except_full)
218 #define EXC_XFER_EE_LITE(n, hdlr) \
219 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
223 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
232 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
235 addi r3,r1,STACK_FRAME_OVERHEAD
236 EXC_XFER_STD(0x200, machine_check_exception)
238 /* Data access exception.
239 * This is "never generated" by the MPC8xx.
244 /* Instruction access exception.
245 * This is "never generated" by the MPC8xx.
250 /* External interrupt */
251 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
253 /* Alignment exception */
260 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
263 addi r3,r1,STACK_FRAME_OVERHEAD
264 EXC_XFER_EE(0x600, alignment_exception)
266 /* Program check exception */
267 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
269 /* No FPU on MPC8xx. This exception is not supposed to happen.
271 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
274 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
276 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
277 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
283 EXC_XFER_EE_LITE(0xc00, DoSyscall)
285 /* Single step - not used on 601 */
286 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
287 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
288 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
290 /* On the MPC8xx, this is a software emulation interrupt. It occurs
291 * for all unimplemented and illegal instructions.
293 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
297 * For the MPC8xx, this is a software tablewalk to load the instruction
298 * TLB. The task switch loads the M_TWB register with the pointer to the first
300 * If we discover there is no second level table (value is zero) or if there
301 * is an invalid pte, we load that into the TLB, which causes another fault
302 * into the TLB Error interrupt where we can handle such problems.
303 * We have to use the MD_xxx registers for the tablewalk because the
304 * equivalent MI_xxx registers only perform the attribute functions.
307 #ifdef CONFIG_8xx_CPU15
308 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
309 addi addr, addr, PAGE_SIZE; \
311 addi addr, addr, -(PAGE_SIZE << 1); \
313 addi addr, addr, PAGE_SIZE
315 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
319 mtspr SPRN_SPRG_SCRATCH0, r10
320 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
321 mtspr SPRN_SPRG_SCRATCH1, r11
324 /* If we are faulting a kernel address, we have to use the
325 * kernel page tables.
327 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
328 INVALIDATE_ADJACENT_PAGES_CPU15(r10)
329 mtspr SPRN_MD_EPN, r10
330 /* Only modules will cause ITLB Misses as we always
331 * pin the first 8MB of kernel memory */
332 #ifdef ITLB_MISS_KERNEL
334 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
335 cmpi cr0, r10, 0 /* Address >= 0x80000000 */
337 rlwinm r10, r10, 16, 0xfff8
338 cmpli cr0, r10, PAGE_OFFSET@h
339 #ifndef CONFIG_PIN_TLB_TEXT
340 /* It is assumed that kernel code fits into the first 8M page */
341 0: cmpli cr7, r10, (PAGE_OFFSET + 0x0800000)@h
342 patch_site 0b, patch__itlbmiss_linmem_top
346 mfspr r10, SPRN_M_TWB /* Get level 1 table */
347 #ifdef ITLB_MISS_KERNEL
348 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
353 #ifndef CONFIG_PIN_TLB_TEXT
354 blt cr7, ITLBMissLinear
356 rlwinm r10, r10, 0, 20, 31
357 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
360 lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
361 mtspr SPRN_MI_TWC, r10 /* Set segment attributes */
363 mtspr SPRN_MD_TWC, r10
364 mfspr r10, SPRN_MD_TWC
365 lwz r10, 0(r10) /* Get the pte */
366 #ifdef ITLB_MISS_KERNEL
370 rlwinm r11, r10, 32-5, _PAGE_PRESENT
372 rlwimi r10, r11, 0, _PAGE_PRESENT
374 /* The Linux PTE won't go exactly into the MMU TLB.
375 * Software indicator bits 20 and 23 must be clear.
376 * Software indicator bits 22, 24, 25, 26, and 27 must be
377 * set. All other Linux PTE bits control the behavior
380 rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
381 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
382 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
383 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
385 /* Restore registers */
386 0: mfspr r10, SPRN_SPRG_SCRATCH0
387 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
388 mfspr r11, SPRN_SPRG_SCRATCH1
391 patch_site 0b, patch__itlbmiss_exit_1
393 #ifdef CONFIG_PERF_EVENTS
394 patch_site 0f, patch__itlbmiss_perf
395 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
397 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
398 mfspr r10, SPRN_SPRG_SCRATCH0
399 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
400 mfspr r11, SPRN_SPRG_SCRATCH1
405 #ifndef CONFIG_PIN_TLB_TEXT
408 /* Set 8M byte page and mark it valid */
409 li r11, MI_PS8MEG | MI_SVALID
410 mtspr SPRN_MI_TWC, r11
411 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
412 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
414 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
416 0: mfspr r10, SPRN_SPRG_SCRATCH0
417 mfspr r11, SPRN_SPRG_SCRATCH1
419 patch_site 0b, patch__itlbmiss_exit_2
424 mtspr SPRN_SPRG_SCRATCH0, r10
425 mtspr SPRN_SPRG_SCRATCH1, r11
428 /* If we are faulting a kernel address, we have to use the
429 * kernel page tables.
431 mfspr r10, SPRN_MD_EPN
432 rlwinm r10, r10, 16, 0xfff8
433 cmpli cr0, r10, PAGE_OFFSET@h
434 #ifndef CONFIG_PIN_TLB_IMMR
435 cmpli cr6, r10, VIRT_IMMR_BASE@h
437 0: cmpli cr7, r10, (PAGE_OFFSET + 0x1800000)@h
438 patch_site 0b, patch__dtlbmiss_linmem_top
440 mfspr r10, SPRN_M_TWB /* Get level 1 table */
442 #ifndef CONFIG_PIN_TLB_IMMR
443 0: beq- cr6, DTLBMissIMMR
444 patch_site 0b, patch__dtlbmiss_immr_jmp
446 blt cr7, DTLBMissLinear
447 rlwinm r10, r10, 0, 20, 31
448 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
451 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
453 mtspr SPRN_MD_TWC, r11
454 mfspr r10, SPRN_MD_TWC
455 lwz r10, 0(r10) /* Get the pte */
457 /* Insert the Guarded flag into the TWC from the Linux PTE.
458 * It is bit 27 of both the Linux PTE and the TWC (at least
459 * I got that right :-). It will be better when we can put
460 * this into the Linux pgd/pmd and load it in the operation
463 rlwimi r11, r10, 0, _PAGE_GUARDED
464 mtspr SPRN_MD_TWC, r11
466 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
467 * We also need to know if the insn is a load/store, so:
468 * Clear _PAGE_PRESENT and load that which will
469 * trap into DTLB Error with store bit set accordinly.
471 /* PRESENT=0x1, ACCESSED=0x20
472 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
473 * r10 = (r10 & ~PRESENT) | r11;
476 rlwinm r11, r10, 32-5, _PAGE_PRESENT
478 rlwimi r10, r11, 0, _PAGE_PRESENT
480 /* The Linux PTE won't go exactly into the MMU TLB.
481 * Software indicator bits 24, 25, 26, and 27 must be
482 * set. All other Linux PTE bits control the behavior
486 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
487 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
489 /* Restore registers */
490 mtspr SPRN_DAR, r11 /* Tag DAR */
492 0: mfspr r10, SPRN_SPRG_SCRATCH0
493 mfspr r11, SPRN_SPRG_SCRATCH1
495 patch_site 0b, patch__dtlbmiss_exit_1
497 #ifdef CONFIG_PERF_EVENTS
498 patch_site 0f, patch__dtlbmiss_perf
499 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
501 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
502 mfspr r10, SPRN_SPRG_SCRATCH0
503 mfspr r11, SPRN_SPRG_SCRATCH1
509 /* Set 512k byte guarded page and mark it valid */
510 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
511 mtspr SPRN_MD_TWC, r10
512 mfspr r10, SPRN_IMMR /* Get current IMMR */
513 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
514 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
515 _PAGE_PRESENT | _PAGE_NO_CACHE
516 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
519 mtspr SPRN_DAR, r11 /* Tag DAR */
521 0: mfspr r10, SPRN_SPRG_SCRATCH0
522 mfspr r11, SPRN_SPRG_SCRATCH1
524 patch_site 0b, patch__dtlbmiss_exit_2
528 /* Set 8M byte page and mark it valid */
529 li r11, MD_PS8MEG | MD_SVALID
530 mtspr SPRN_MD_TWC, r11
531 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
532 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
534 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
537 mtspr SPRN_DAR, r11 /* Tag DAR */
539 0: mfspr r10, SPRN_SPRG_SCRATCH0
540 mfspr r11, SPRN_SPRG_SCRATCH1
542 patch_site 0b, patch__dtlbmiss_exit_3
544 /* This is an instruction TLB error on the MPC8xx. This could be due
545 * to many reasons, such as executing guarded memory or illegal instruction
546 * addresses. There is nothing to do but handle a big time error fault.
552 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
553 andis. r10,r9,SRR1_ISI_NOPT@h
557 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
558 1: EXC_XFER_LITE(0x400, handle_page_fault)
560 /* This is the data TLB error on the MPC8xx. This could be due to
561 * many reasons, including a dirty update to a pte. We bail out to
562 * a higher level function that can handle it.
566 mtspr SPRN_SPRG_SCRATCH0, r10
567 mtspr SPRN_SPRG_SCRATCH1, r11
571 cmpwi cr0, r11, RPN_PATTERN
572 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
573 DARFixed:/* Return from dcbx instruction bug workaround */
579 andis. r10,r5,DSISR_NOHPTE@h
583 1: li r10,RPN_PATTERN
584 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
585 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
586 EXC_XFER_LITE(0x300, handle_page_fault)
588 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
589 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
590 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
591 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
592 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
593 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
594 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
596 /* On the MPC8xx, these next four traps are used for development
597 * support of breakpoints and such. Someday I will get around to
602 mtspr SPRN_SPRG_SCRATCH0, r10
603 mtspr SPRN_SPRG_SCRATCH1, r11
606 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
607 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
612 addi r3,r1,STACK_FRAME_OVERHEAD
616 EXC_XFER_EE(0x1c00, do_break)
619 mfspr r10, SPRN_SPRG_SCRATCH0
620 mfspr r11, SPRN_SPRG_SCRATCH1
623 #ifdef CONFIG_PERF_EVENTS
625 InstructionBreakpoint:
626 mtspr SPRN_SPRG_SCRATCH0, r10
627 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
629 stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
632 mtspr SPRN_COUNTA, r10
633 mfspr r10, SPRN_SPRG_SCRATCH0
636 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
638 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
639 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
643 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
644 * by decoding the registers used by the dcbx instruction and adding them.
645 * DAR is set to the calculated address.
647 /* define if you don't want to use self modifying code */
648 #define NO_SELF_MODIFYING_CODE
649 FixupDAR:/* Entry point for dcbx workaround. */
651 /* fetch instruction from memory. */
653 mtspr SPRN_MD_EPN, r10
654 rlwinm r11, r10, 16, 0xfff8
655 cmpli cr0, r11, PAGE_OFFSET@h
656 mfspr r11, SPRN_M_TWB /* Get level 1 table */
658 rlwinm r11, r10, 16, 0xfff8
660 0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
661 patch_site 0b, patch__fixupdar_linmem_top
663 /* create physical page address from effective address */
666 mfspr r11, SPRN_M_TWB /* Get level 1 table */
667 rlwinm r11, r11, 0, 20, 31
668 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
670 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
671 mtspr SPRN_MD_TWC, r11
673 mfspr r11, SPRN_MD_TWC
674 lwz r11, 0(r11) /* Get the pte */
675 bt 28,200f /* bit 28 = Large page (8M) */
676 bt 29,202f /* bit 29 = Large page (8M or 512K) */
677 /* concat physical page address(r11) and page offset(r10) */
678 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
680 /* Check if it really is a dcbx instruction. */
681 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
682 * no need to include them here */
683 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
684 rlwinm r10, r10, 0, 21, 5
685 cmpwi cr0, r10, 2028 /* Is dcbz? */
687 cmpwi cr0, r10, 940 /* Is dcbi? */
689 cmpwi cr0, r10, 108 /* Is dcbst? */
690 beq+ 144f /* Fix up store bit! */
691 cmpwi cr0, r10, 172 /* Is dcbf? */
693 cmpwi cr0, r10, 1964 /* Is icbi? */
695 141: mfspr r10,SPRN_M_TW
696 b DARFixed /* Nope, go back to normal TLB processing */
699 /* concat physical page address(r11) and page offset(r10) */
700 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
704 /* concat physical page address(r11) and page offset(r10) */
705 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
708 144: mfspr r10, SPRN_DSISR
709 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
710 mtspr SPRN_DSISR, r10
711 142: /* continue, it was a dcbx, dcbi instruction. */
712 #ifndef NO_SELF_MODIFYING_CODE
713 andis. r10,r11,0x1f /* test if reg RA is r0 */
714 li r10,modified_instr@l
715 dcbtst r0,r10 /* touch for store */
716 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
717 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
719 stw r11,0(r10) /* store add/and instruction */
720 dcbf 0,r10 /* flush new instr. to memory. */
721 icbi 0,r10 /* invalidate instr. cache line */
722 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
723 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
724 isync /* Wait until new instr is loaded from memory */
726 .space 4 /* this is where the add instr. is stored */
728 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
729 143: mtdar r10 /* store faulting EA in DAR */
731 b DARFixed /* Go back to normal TLB handling */
734 mtdar r10 /* save ctr reg in DAR */
735 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
736 addi r10, r10, 150f@l /* add start of table */
737 mtctr r10 /* load ctr with jump address */
738 xor r10, r10, r10 /* sum starts at zero */
739 bctr /* jump into table */
741 add r10, r10, r0 ;b 151f
742 add r10, r10, r1 ;b 151f
743 add r10, r10, r2 ;b 151f
744 add r10, r10, r3 ;b 151f
745 add r10, r10, r4 ;b 151f
746 add r10, r10, r5 ;b 151f
747 add r10, r10, r6 ;b 151f
748 add r10, r10, r7 ;b 151f
749 add r10, r10, r8 ;b 151f
750 add r10, r10, r9 ;b 151f
751 mtctr r11 ;b 154f /* r10 needs special handling */
752 mtctr r11 ;b 153f /* r11 needs special handling */
753 add r10, r10, r12 ;b 151f
754 add r10, r10, r13 ;b 151f
755 add r10, r10, r14 ;b 151f
756 add r10, r10, r15 ;b 151f
757 add r10, r10, r16 ;b 151f
758 add r10, r10, r17 ;b 151f
759 add r10, r10, r18 ;b 151f
760 add r10, r10, r19 ;b 151f
761 add r10, r10, r20 ;b 151f
762 add r10, r10, r21 ;b 151f
763 add r10, r10, r22 ;b 151f
764 add r10, r10, r23 ;b 151f
765 add r10, r10, r24 ;b 151f
766 add r10, r10, r25 ;b 151f
767 add r10, r10, r26 ;b 151f
768 add r10, r10, r27 ;b 151f
769 add r10, r10, r28 ;b 151f
770 add r10, r10, r29 ;b 151f
771 add r10, r10, r30 ;b 151f
774 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
775 beq 152f /* if reg RA is zero, don't add it */
776 addi r11, r11, 150b@l /* add start of table */
777 mtctr r11 /* load ctr with jump address */
778 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
779 bctr /* jump into table */
782 mtctr r11 /* restore ctr reg from DAR */
783 mtdar r10 /* save fault EA to DAR */
785 b DARFixed /* Go back to normal TLB handling */
787 /* special handling for r10,r11 since these are modified already */
788 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
789 add r10, r10, r11 /* add it */
790 mfctr r11 /* restore r11 */
792 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
793 add r10, r10, r11 /* add it */
794 mfctr r11 /* restore r11 */
799 * This is where the main kernel code starts.
804 ori r2,r2,init_task@l
806 /* ptr to phys current thread */
808 addi r4,r4,THREAD /* init task's THREAD */
809 mtspr SPRN_SPRG_THREAD,r4
812 lis r1,init_thread_union@ha
813 addi r1,r1,init_thread_union@l
815 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
817 lis r6, swapper_pg_dir@ha
821 bl early_init /* We have to do this with MMU on */
824 * Decide what sort of machine this is and initialize the MMU.
832 * Go back to running unmapped so we can load up new values
833 * and change to using our exception vectors.
834 * On the 8xx, all we have to do is invalidate the TLB to clear
835 * the old 8M byte TLB mappings and load the page table base register.
837 /* The right way to do this would be to track it down through
838 * init's THREAD like the context switch code does, but this is
839 * easier......until someone changes init's static structures.
844 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
848 /* Load up the kernel context */
850 tlbia /* Clear all TLB entries */
851 sync /* wait for tlbia/tlbie to finish */
853 /* set up the PTE pointers for the Abatron bdiGDB.
856 lis r5, abatron_pteptrs@h
857 ori r5, r5, abatron_pteptrs@l
858 stw r5, 0xf0(0) /* Must match your Abatron config file */
862 /* Now turn on the MMU for real! */
864 lis r3,start_kernel@h
865 ori r3,r3,start_kernel@l
868 rfi /* enable MMU and jump to start_kernel */
870 /* Set up the initial MMU state so we can do the first level of
871 * kernel initialization. This maps the first 8 MBytes of memory 1:1
872 * virtual to physical. Also, set the cache mode since that is defined
873 * by TLB entries and perform any additional mapping (like of the IMMR).
874 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
875 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
876 * these mappings is mapped by page tables.
880 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
881 lis r10, MD_RESETVAL@h
882 #ifndef CONFIG_8xx_COPYBACK
883 oris r10, r10, MD_WTDEF@h
885 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
887 tlbia /* Invalidate all TLB entries */
888 #ifdef CONFIG_PIN_TLB_TEXT
892 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
895 #ifdef CONFIG_PIN_TLB_DATA
896 oris r10, r10, MD_RSV4I@h
897 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
900 /* Now map the lower 8 Meg into the ITLB. */
901 lis r8, KERNELBASE@h /* Create vaddr for TLB */
902 ori r8, r8, MI_EVALID /* Mark it valid */
903 mtspr SPRN_MI_EPN, r8
904 li r8, MI_PS8MEG /* Set 8M byte page */
905 ori r8, r8, MI_SVALID /* Make it valid */
906 mtspr SPRN_MI_TWC, r8
907 li r8, MI_BOOTINIT /* Create RPN for address 0 */
908 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
910 lis r8, MI_APG_INIT@h /* Set protection modes */
911 ori r8, r8, MI_APG_INIT@l
913 lis r8, MD_APG_INIT@h
914 ori r8, r8, MD_APG_INIT@l
917 /* Map a 512k page for the IMMR to get the processor
918 * internal registers (among other things).
920 #ifdef CONFIG_PIN_TLB_IMMR
921 oris r10, r10, MD_RSV4I@h
923 mtspr SPRN_MD_CTR, r10
925 mfspr r9, 638 /* Get current IMMR */
926 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
928 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
929 ori r8, r8, MD_EVALID /* Mark it valid */
930 mtspr SPRN_MD_EPN, r8
931 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
932 ori r8, r8, MD_SVALID /* Make it valid */
933 mtspr SPRN_MD_TWC, r8
934 mr r8, r9 /* Create paddr for TLB */
935 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
936 mtspr SPRN_MD_RPN, r8
939 /* Since the cache is enabled according to the information we
940 * just loaded into the TLB, invalidate and enable the caches here.
941 * We should probably check/set other modes....later.
944 mtspr SPRN_IC_CST, r8
945 mtspr SPRN_DC_CST, r8
947 mtspr SPRN_IC_CST, r8
948 #ifdef CONFIG_8xx_COPYBACK
949 mtspr SPRN_DC_CST, r8
951 /* For a debug option, I left this here to easily enable
952 * the write through cache mode
955 mtspr SPRN_DC_CST, r8
957 mtspr SPRN_DC_CST, r8
959 /* Disable debug mode entry on breakpoints */
961 #ifdef CONFIG_PERF_EVENTS
962 rlwinm r8, r8, 0, ~0xc
964 rlwinm r8, r8, 0, ~0x8
971 * We put a few things here that have to be page-aligned.
972 * This stuff goes at the beginning of the data segment,
973 * which is page-aligned.
978 .globl empty_zero_page
982 EXPORT_SYMBOL(empty_zero_page)
984 .globl swapper_pg_dir
986 .space PGD_TABLE_SIZE
988 /* Room for two PTE table poiners, usually the kernel and current user
989 * pointer to their respective root page table (pgdir).