3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/export.h>
34 #include <asm/code-patching-asm.h>
36 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
37 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
38 #define SIMPLE_KERNEL_ADDRESS 1
42 * We need an ITLB miss handler for kernel addresses if:
43 * - Either we have modules
44 * - Or we have not pinned the first 8M
46 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
47 defined(CONFIG_DEBUG_PAGEALLOC)
48 #define ITLB_MISS_KERNEL 1
52 * Value for the bits that have fixed value in RPN entries.
53 * Also used for tagging DAR for DTLBerror.
55 #define RPN_PATTERN 0x00f0
57 #define PAGE_SHIFT_512K 19
58 #define PAGE_SHIFT_8M 23
65 * This port was done on an MBX board with an 860. Right now I only
66 * support an ELF compressed (zImage) boot from EPPC-Bug because the
67 * code there loads up some registers before calling us:
68 * r3: ptr to board info data
69 * r4: initrd_start or if no initrd then 0
70 * r5: initrd_end - unused if r4 is 0
71 * r6: Start of command line string
72 * r7: End of command line string
74 * I decided to use conditional compilation instead of checking PVR and
75 * adding more processor specific branches around code I don't need.
76 * Since this is an embedded processor, I also appreciate any memory
79 * The MPC8xx does not have any BATs, but it supports large page sizes.
80 * We first initialize the MMU to support 8M byte pages, then load one
81 * entry into each of the instruction and data TLBs to map the first
82 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
83 * the "internal" processor registers before MMU_init is called.
89 mr r31,r3 /* save device tree ptr */
91 /* We have to turn on the MMU right away so we get cache modes
96 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
102 ori r0,r0,MSR_DR|MSR_IR
105 ori r0,r0,start_here@l
107 rfi /* enables MMU */
110 #ifdef CONFIG_PERF_EVENTS
113 .globl itlb_miss_counter
117 .globl dtlb_miss_counter
121 .globl instruction_counter
127 * Exception entry code. This code runs with address translation
128 * turned off, i.e. using physical addresses.
129 * We assume sprg3 has the physical address of the current
130 * task's thread_struct.
132 #define EXCEPTION_PROLOG \
133 mtspr SPRN_SPRG_SCRATCH0, r10; \
134 mtspr SPRN_SPRG_SCRATCH1, r11; \
136 EXCEPTION_PROLOG_1; \
139 #define EXCEPTION_PROLOG_1 \
140 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
141 andi. r11,r11,MSR_PR; \
142 tophys(r11,r1); /* use tophys(r1) if kernel */ \
144 mfspr r11,SPRN_SPRG_THREAD; \
145 lwz r11,TASK_STACK-THREAD(r11); \
146 addi r11,r11,THREAD_SIZE; \
148 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
151 #define EXCEPTION_PROLOG_2 \
152 stw r10,_CCR(r11); /* save registers */ \
153 stw r12,GPR12(r11); \
155 mfspr r10,SPRN_SPRG_SCRATCH0; \
156 stw r10,GPR10(r11); \
157 mfspr r12,SPRN_SPRG_SCRATCH1; \
158 stw r12,GPR11(r11); \
160 stw r10,_LINK(r11); \
161 mfspr r12,SPRN_SRR0; \
162 mfspr r9,SPRN_SRR1; \
165 tovirt(r1,r11); /* set new kernel sp */ \
166 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
169 lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
170 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
172 SAVE_4GPRS(3, r11); \
176 * Note: code which follows this uses cr0.eq (set if from kernel),
177 * r11, r12 (SRR0), and r9 (SRR1).
179 * Note2: once we have set r1 we are in a position to take exceptions
180 * again, and we could thus set MSR:RI at that point.
186 #define EXCEPTION(n, label, hdlr, xfer) \
190 addi r3,r1,STACK_FRAME_OVERHEAD; \
193 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
195 stw r10,_TRAP(r11); \
203 #define COPY_EE(d, s) rlwimi d,s,0,16,16
206 #define EXC_XFER_STD(n, hdlr) \
207 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
208 ret_from_except_full)
210 #define EXC_XFER_LITE(n, hdlr) \
211 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
214 #define EXC_XFER_EE(n, hdlr) \
215 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
216 ret_from_except_full)
218 #define EXC_XFER_EE_LITE(n, hdlr) \
219 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
223 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
232 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
235 addi r3,r1,STACK_FRAME_OVERHEAD
236 EXC_XFER_STD(0x200, machine_check_exception)
238 /* Data access exception.
239 * This is "never generated" by the MPC8xx.
244 /* Instruction access exception.
245 * This is "never generated" by the MPC8xx.
250 /* External interrupt */
251 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
253 /* Alignment exception */
260 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
263 addi r3,r1,STACK_FRAME_OVERHEAD
264 EXC_XFER_EE(0x600, alignment_exception)
266 /* Program check exception */
267 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
269 /* No FPU on MPC8xx. This exception is not supposed to happen.
271 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
274 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
276 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
277 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
283 EXC_XFER_EE_LITE(0xc00, DoSyscall)
285 /* Single step - not used on 601 */
286 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
287 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
288 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
290 /* On the MPC8xx, this is a software emulation interrupt. It occurs
291 * for all unimplemented and illegal instructions.
293 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
295 /* Called from DataStoreTLBMiss when perf TLB misses events are activated */
296 #ifdef CONFIG_PERF_EVENTS
297 patch_site 0f, patch__dtlbmiss_perf
298 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
300 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
301 mfspr r10, SPRN_SPRG_SCRATCH0
302 mfspr r11, SPRN_SPRG_SCRATCH1
308 * For the MPC8xx, this is a software tablewalk to load the instruction
309 * TLB. The task switch loads the M_TWB register with the pointer to the first
311 * If we discover there is no second level table (value is zero) or if there
312 * is an invalid pte, we load that into the TLB, which causes another fault
313 * into the TLB Error interrupt where we can handle such problems.
314 * We have to use the MD_xxx registers for the tablewalk because the
315 * equivalent MI_xxx registers only perform the attribute functions.
318 #ifdef CONFIG_8xx_CPU15
319 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
320 addi addr, addr, PAGE_SIZE; \
322 addi addr, addr, -(PAGE_SIZE << 1); \
324 addi addr, addr, PAGE_SIZE
326 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
330 mtspr SPRN_SPRG_SCRATCH0, r10
331 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
332 mtspr SPRN_SPRG_SCRATCH1, r11
335 /* If we are faulting a kernel address, we have to use the
336 * kernel page tables.
338 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
339 INVALIDATE_ADJACENT_PAGES_CPU15(r10)
340 mtspr SPRN_MD_EPN, r10
341 /* Only modules will cause ITLB Misses as we always
342 * pin the first 8MB of kernel memory */
343 #ifdef ITLB_MISS_KERNEL
345 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
346 cmpi cr0, r10, 0 /* Address >= 0x80000000 */
348 rlwinm r10, r10, 16, 0xfff8
349 cmpli cr0, r10, PAGE_OFFSET@h
350 #ifndef CONFIG_PIN_TLB_TEXT
351 /* It is assumed that kernel code fits into the first 32M */
352 0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
353 patch_site 0b, patch__itlbmiss_linmem_top
357 mfspr r10, SPRN_M_TWB /* Get level 1 table */
358 #ifdef ITLB_MISS_KERNEL
359 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
364 #ifndef CONFIG_PIN_TLB_TEXT
365 blt cr7, ITLBMissLinear
367 rlwinm r10, r10, 0, 20, 31
368 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
371 lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
372 mtspr SPRN_MI_TWC, r10 /* Set segment attributes */
374 mtspr SPRN_MD_TWC, r10
375 mfspr r10, SPRN_MD_TWC
376 lwz r10, 0(r10) /* Get the pte */
377 #ifdef ITLB_MISS_KERNEL
381 rlwinm r11, r10, 32-5, _PAGE_PRESENT
383 rlwimi r10, r11, 0, _PAGE_PRESENT
385 /* The Linux PTE won't go exactly into the MMU TLB.
386 * Software indicator bits 20 and 23 must be clear.
387 * Software indicator bits 22, 24, 25, 26, and 27 must be
388 * set. All other Linux PTE bits control the behavior
391 rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
392 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
393 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
394 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
396 /* Restore registers */
397 0: mfspr r10, SPRN_SPRG_SCRATCH0
398 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
399 mfspr r11, SPRN_SPRG_SCRATCH1
402 patch_site 0b, patch__itlbmiss_exit_1
404 #ifdef CONFIG_PERF_EVENTS
405 patch_site 0f, patch__itlbmiss_perf
406 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
408 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
409 mfspr r10, SPRN_SPRG_SCRATCH0
410 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
411 mfspr r11, SPRN_SPRG_SCRATCH1
416 #ifndef CONFIG_PIN_TLB_TEXT
419 #if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23
420 patch_site 0f, patch__itlbmiss_linmem_top8
423 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
424 rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
425 ori r11, r11, MI_PS512K | MI_SVALID
426 rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
428 /* Set 8M byte page and mark it valid */
429 li r11, MI_PS8MEG | MI_SVALID
430 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
432 mtspr SPRN_MI_TWC, r11
433 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
435 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
437 0: mfspr r10, SPRN_SPRG_SCRATCH0
438 mfspr r11, SPRN_SPRG_SCRATCH1
440 patch_site 0b, patch__itlbmiss_exit_2
445 mtspr SPRN_SPRG_SCRATCH0, r10
446 mtspr SPRN_SPRG_SCRATCH1, r11
449 /* If we are faulting a kernel address, we have to use the
450 * kernel page tables.
452 mfspr r10, SPRN_MD_EPN
453 rlwinm r10, r10, 16, 0xfff8
454 cmpli cr0, r10, PAGE_OFFSET@h
455 #ifndef CONFIG_PIN_TLB_IMMR
456 cmpli cr6, r10, VIRT_IMMR_BASE@h
458 0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
459 patch_site 0b, patch__dtlbmiss_linmem_top
461 mfspr r10, SPRN_M_TWB /* Get level 1 table */
463 #ifndef CONFIG_PIN_TLB_IMMR
464 0: beq- cr6, DTLBMissIMMR
465 patch_site 0b, patch__dtlbmiss_immr_jmp
467 blt cr7, DTLBMissLinear
468 rlwinm r10, r10, 0, 20, 31
469 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
472 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
474 mtspr SPRN_MD_TWC, r11
475 mfspr r10, SPRN_MD_TWC
476 lwz r10, 0(r10) /* Get the pte */
478 /* Insert the Guarded flag into the TWC from the Linux PTE.
479 * It is bit 27 of both the Linux PTE and the TWC (at least
480 * I got that right :-). It will be better when we can put
481 * this into the Linux pgd/pmd and load it in the operation
484 rlwimi r11, r10, 0, _PAGE_GUARDED
485 mtspr SPRN_MD_TWC, r11
487 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
488 * We also need to know if the insn is a load/store, so:
489 * Clear _PAGE_PRESENT and load that which will
490 * trap into DTLB Error with store bit set accordinly.
492 /* PRESENT=0x1, ACCESSED=0x20
493 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
494 * r10 = (r10 & ~PRESENT) | r11;
497 rlwinm r11, r10, 32-5, _PAGE_PRESENT
499 rlwimi r10, r11, 0, _PAGE_PRESENT
501 /* The Linux PTE won't go exactly into the MMU TLB.
502 * Software indicator bits 24, 25, 26, and 27 must be
503 * set. All other Linux PTE bits control the behavior
507 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
508 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
510 /* Restore registers */
511 mtspr SPRN_DAR, r11 /* Tag DAR */
513 0: mfspr r10, SPRN_SPRG_SCRATCH0
514 mfspr r11, SPRN_SPRG_SCRATCH1
516 patch_site 0b, patch__dtlbmiss_exit_1
520 /* Set 512k byte guarded page and mark it valid */
521 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
522 mtspr SPRN_MD_TWC, r10
523 mfspr r10, SPRN_IMMR /* Get current IMMR */
524 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
525 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
526 _PAGE_PRESENT | _PAGE_NO_CACHE
527 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
530 mtspr SPRN_DAR, r11 /* Tag DAR */
532 0: mfspr r10, SPRN_SPRG_SCRATCH0
533 mfspr r11, SPRN_SPRG_SCRATCH1
535 patch_site 0b, patch__dtlbmiss_exit_2
539 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
540 #if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23
541 patch_site 0f, patch__dtlbmiss_romem_top8
543 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
544 rlwinm r11, r11, 0, 0xff800000
547 rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
548 ori r11, r11, MI_PS512K | MI_SVALID
549 mfspr r10, SPRN_MD_EPN
550 rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
552 /* Set 8M byte page and mark it valid */
553 li r11, MD_PS8MEG | MD_SVALID
555 mtspr SPRN_MD_TWC, r11
556 #ifdef CONFIG_STRICT_KERNEL_RWX
557 patch_site 0f, patch__dtlbmiss_romem_top
560 rlwimi r10, r11, 11, _PAGE_RO
562 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
564 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
567 mtspr SPRN_DAR, r11 /* Tag DAR */
569 0: mfspr r10, SPRN_SPRG_SCRATCH0
570 mfspr r11, SPRN_SPRG_SCRATCH1
572 patch_site 0b, patch__dtlbmiss_exit_3
574 /* This is an instruction TLB error on the MPC8xx. This could be due
575 * to many reasons, such as executing guarded memory or illegal instruction
576 * addresses. There is nothing to do but handle a big time error fault.
582 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
583 andis. r10,r9,SRR1_ISI_NOPT@h
586 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
588 EXC_XFER_LITE(0x400, handle_page_fault)
590 /* This is the data TLB error on the MPC8xx. This could be due to
591 * many reasons, including a dirty update to a pte. We bail out to
592 * a higher level function that can handle it.
596 mtspr SPRN_SPRG_SCRATCH0, r10
597 mtspr SPRN_SPRG_SCRATCH1, r11
601 cmpwi cr0, r11, RPN_PATTERN
602 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
603 DARFixed:/* Return from dcbx instruction bug workaround */
609 andis. r10,r5,DSISR_NOHPTE@h
614 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
615 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
616 EXC_XFER_LITE(0x300, handle_page_fault)
618 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
619 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
620 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
621 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
622 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
623 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
624 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
626 /* On the MPC8xx, these next four traps are used for development
627 * support of breakpoints and such. Someday I will get around to
632 mtspr SPRN_SPRG_SCRATCH0, r10
633 mtspr SPRN_SPRG_SCRATCH1, r11
636 cmplwi cr0, r11, (.Ldtlbie - PAGE_OFFSET)@l
637 cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l
642 addi r3,r1,STACK_FRAME_OVERHEAD
646 EXC_XFER_EE(0x1c00, do_break)
649 mfspr r10, SPRN_SPRG_SCRATCH0
650 mfspr r11, SPRN_SPRG_SCRATCH1
653 #ifdef CONFIG_PERF_EVENTS
655 InstructionBreakpoint:
656 mtspr SPRN_SPRG_SCRATCH0, r10
657 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
659 stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
662 mtspr SPRN_COUNTA, r10
663 mfspr r10, SPRN_SPRG_SCRATCH0
666 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
668 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
669 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
673 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
674 * by decoding the registers used by the dcbx instruction and adding them.
675 * DAR is set to the calculated address.
677 /* define if you don't want to use self modifying code */
678 #define NO_SELF_MODIFYING_CODE
679 FixupDAR:/* Entry point for dcbx workaround. */
681 /* fetch instruction from memory. */
683 mtspr SPRN_MD_EPN, r10
684 rlwinm r11, r10, 16, 0xfff8
685 cmpli cr0, r11, PAGE_OFFSET@h
686 mfspr r11, SPRN_M_TWB /* Get level 1 table */
688 rlwinm r11, r10, 16, 0xfff8
690 0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
691 patch_site 0b, patch__fixupdar_linmem_top
693 /* create physical page address from effective address */
696 mfspr r11, SPRN_M_TWB /* Get level 1 table */
697 rlwinm r11, r11, 0, 20, 31
698 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
700 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
701 mtspr SPRN_MD_TWC, r11
703 mfspr r11, SPRN_MD_TWC
704 lwz r11, 0(r11) /* Get the pte */
705 bt 28,200f /* bit 28 = Large page (8M) */
706 bt 29,202f /* bit 29 = Large page (8M or 512K) */
707 /* concat physical page address(r11) and page offset(r10) */
708 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
710 /* Check if it really is a dcbx instruction. */
711 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
712 * no need to include them here */
713 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
714 rlwinm r10, r10, 0, 21, 5
715 cmpwi cr0, r10, 2028 /* Is dcbz? */
717 cmpwi cr0, r10, 940 /* Is dcbi? */
719 cmpwi cr0, r10, 108 /* Is dcbst? */
720 beq+ 144f /* Fix up store bit! */
721 cmpwi cr0, r10, 172 /* Is dcbf? */
723 cmpwi cr0, r10, 1964 /* Is icbi? */
725 141: mfspr r10,SPRN_M_TW
726 b DARFixed /* Nope, go back to normal TLB processing */
729 /* concat physical page address(r11) and page offset(r10) */
730 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
734 /* concat physical page address(r11) and page offset(r10) */
735 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
738 144: mfspr r10, SPRN_DSISR
739 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
740 mtspr SPRN_DSISR, r10
741 142: /* continue, it was a dcbx, dcbi instruction. */
742 #ifndef NO_SELF_MODIFYING_CODE
743 andis. r10,r11,0x1f /* test if reg RA is r0 */
744 li r10,modified_instr@l
745 dcbtst r0,r10 /* touch for store */
746 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
747 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
749 stw r11,0(r10) /* store add/and instruction */
750 dcbf 0,r10 /* flush new instr. to memory. */
751 icbi 0,r10 /* invalidate instr. cache line */
752 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
753 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
754 isync /* Wait until new instr is loaded from memory */
756 .space 4 /* this is where the add instr. is stored */
758 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
759 143: mtdar r10 /* store faulting EA in DAR */
761 b DARFixed /* Go back to normal TLB handling */
764 mtdar r10 /* save ctr reg in DAR */
765 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
766 addi r10, r10, 150f@l /* add start of table */
767 mtctr r10 /* load ctr with jump address */
768 xor r10, r10, r10 /* sum starts at zero */
769 bctr /* jump into table */
771 add r10, r10, r0 ;b 151f
772 add r10, r10, r1 ;b 151f
773 add r10, r10, r2 ;b 151f
774 add r10, r10, r3 ;b 151f
775 add r10, r10, r4 ;b 151f
776 add r10, r10, r5 ;b 151f
777 add r10, r10, r6 ;b 151f
778 add r10, r10, r7 ;b 151f
779 add r10, r10, r8 ;b 151f
780 add r10, r10, r9 ;b 151f
781 mtctr r11 ;b 154f /* r10 needs special handling */
782 mtctr r11 ;b 153f /* r11 needs special handling */
783 add r10, r10, r12 ;b 151f
784 add r10, r10, r13 ;b 151f
785 add r10, r10, r14 ;b 151f
786 add r10, r10, r15 ;b 151f
787 add r10, r10, r16 ;b 151f
788 add r10, r10, r17 ;b 151f
789 add r10, r10, r18 ;b 151f
790 add r10, r10, r19 ;b 151f
791 add r10, r10, r20 ;b 151f
792 add r10, r10, r21 ;b 151f
793 add r10, r10, r22 ;b 151f
794 add r10, r10, r23 ;b 151f
795 add r10, r10, r24 ;b 151f
796 add r10, r10, r25 ;b 151f
797 add r10, r10, r26 ;b 151f
798 add r10, r10, r27 ;b 151f
799 add r10, r10, r28 ;b 151f
800 add r10, r10, r29 ;b 151f
801 add r10, r10, r30 ;b 151f
804 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
805 beq 152f /* if reg RA is zero, don't add it */
806 addi r11, r11, 150b@l /* add start of table */
807 mtctr r11 /* load ctr with jump address */
808 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
809 bctr /* jump into table */
812 mtctr r11 /* restore ctr reg from DAR */
813 mtdar r10 /* save fault EA to DAR */
815 b DARFixed /* Go back to normal TLB handling */
817 /* special handling for r10,r11 since these are modified already */
818 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
819 add r10, r10, r11 /* add it */
820 mfctr r11 /* restore r11 */
822 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
823 add r10, r10, r11 /* add it */
824 mfctr r11 /* restore r11 */
829 * This is where the main kernel code starts.
834 ori r2,r2,init_task@l
836 /* ptr to phys current thread */
838 addi r4,r4,THREAD /* init task's THREAD */
839 mtspr SPRN_SPRG_THREAD,r4
842 lis r1,init_thread_union@ha
843 addi r1,r1,init_thread_union@l
845 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
847 lis r6, swapper_pg_dir@ha
851 bl early_init /* We have to do this with MMU on */
854 * Decide what sort of machine this is and initialize the MMU.
862 * Go back to running unmapped so we can load up new values
863 * and change to using our exception vectors.
864 * On the 8xx, all we have to do is invalidate the TLB to clear
865 * the old 8M byte TLB mappings and load the page table base register.
867 /* The right way to do this would be to track it down through
868 * init's THREAD like the context switch code does, but this is
869 * easier......until someone changes init's static structures.
874 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
878 /* Load up the kernel context */
880 tlbia /* Clear all TLB entries */
881 sync /* wait for tlbia/tlbie to finish */
883 /* set up the PTE pointers for the Abatron bdiGDB.
885 lis r5, abatron_pteptrs@h
886 ori r5, r5, abatron_pteptrs@l
887 stw r5, 0xf0(0) /* Must match your Abatron config file */
889 lis r6, swapper_pg_dir@h
890 ori r6, r6, swapper_pg_dir@l
893 /* Now turn on the MMU for real! */
895 lis r3,start_kernel@h
896 ori r3,r3,start_kernel@l
899 rfi /* enable MMU and jump to start_kernel */
901 /* Set up the initial MMU state so we can do the first level of
902 * kernel initialization. This maps the first 8 MBytes of memory 1:1
903 * virtual to physical. Also, set the cache mode since that is defined
904 * by TLB entries and perform any additional mapping (like of the IMMR).
905 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
906 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
907 * these mappings is mapped by page tables.
911 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
912 lis r10, MD_RESETVAL@h
913 #ifndef CONFIG_8xx_COPYBACK
914 oris r10, r10, MD_WTDEF@h
916 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
918 tlbia /* Invalidate all TLB entries */
919 #ifdef CONFIG_PIN_TLB_DATA
920 oris r10, r10, MD_RSV4I@h
921 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
924 lis r8, MI_APG_INIT@h /* Set protection modes */
925 ori r8, r8, MI_APG_INIT@l
927 lis r8, MD_APG_INIT@h
928 ori r8, r8, MD_APG_INIT@l
931 /* Map a 512k page for the IMMR to get the processor
932 * internal registers (among other things).
934 #ifdef CONFIG_PIN_TLB_IMMR
935 oris r10, r10, MD_RSV4I@h
937 mtspr SPRN_MD_CTR, r10
939 mfspr r9, 638 /* Get current IMMR */
940 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
942 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
943 ori r8, r8, MD_EVALID /* Mark it valid */
944 mtspr SPRN_MD_EPN, r8
945 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
946 ori r8, r8, MD_SVALID /* Make it valid */
947 mtspr SPRN_MD_TWC, r8
948 mr r8, r9 /* Create paddr for TLB */
949 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
950 mtspr SPRN_MD_RPN, r8
953 /* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
954 #ifdef CONFIG_PIN_TLB_TEXT
958 li r9, 4 /* up to 4 pages of 8M */
960 lis r9, KERNELBASE@h /* Create vaddr for TLB */
961 li r10, MI_PS8MEG | MI_SVALID /* Set 8M byte page */
962 li r11, MI_BOOTINIT /* Create RPN for address 0 */
963 lis r12, _einittext@h
964 ori r12, r12, _einittext@l
966 #ifdef CONFIG_PIN_TLB_TEXT
967 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
971 ori r0, r9, MI_EVALID /* Mark it valid */
972 mtspr SPRN_MI_EPN, r0
973 mtspr SPRN_MI_TWC, r10
974 mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
981 /* Since the cache is enabled according to the information we
982 * just loaded into the TLB, invalidate and enable the caches here.
983 * We should probably check/set other modes....later.
986 mtspr SPRN_IC_CST, r8
987 mtspr SPRN_DC_CST, r8
989 mtspr SPRN_IC_CST, r8
990 #ifdef CONFIG_8xx_COPYBACK
991 mtspr SPRN_DC_CST, r8
993 /* For a debug option, I left this here to easily enable
994 * the write through cache mode
997 mtspr SPRN_DC_CST, r8
999 mtspr SPRN_DC_CST, r8
1001 /* Disable debug mode entry on breakpoints */
1003 #ifdef CONFIG_PERF_EVENTS
1004 rlwinm r8, r8, 0, ~0xc
1006 rlwinm r8, r8, 0, ~0x8
1013 * We put a few things here that have to be page-aligned.
1014 * This stuff goes at the beginning of the data segment,
1015 * which is page-aligned.
1020 .globl empty_zero_page
1024 EXPORT_SYMBOL(empty_zero_page)
1026 .globl swapper_pg_dir
1028 .space PGD_TABLE_SIZE
1030 /* Room for two PTE table poiners, usually the kernel and current user
1031 * pointer to their respective root page table (pgdir).
1033 .globl abatron_pteptrs