1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
21 #include <linux/threads.h>
22 #include <linux/init.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/head-64.h>
28 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/setup.h>
32 #include <asm/hvcall.h>
33 #include <asm/thread_info.h>
34 #include <asm/firmware.h>
35 #include <asm/page_64.h>
36 #include <asm/irqflags.h>
37 #include <asm/kvm_book3s_asm.h>
38 #include <asm/ptrace.h>
39 #include <asm/hw_irq.h>
40 #include <asm/cputhreads.h>
41 #include <asm/ppc-opcode.h>
42 #include <asm/export.h>
43 #include <asm/feature-fixups.h>
45 /* The physical memory is laid out such that the secondary processor
46 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
47 * using the layout described in exceptions-64s.S
51 * Entering into this code we make the following assumptions:
53 * For pSeries or server processors:
54 * 1. The MMU is off & open firmware is running in real mode.
55 * 2. The primary CPU enters at __start.
56 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
57 * CPUs will enter as directed by "start-cpu" RTAS call, which is
58 * generic_secondary_smp_init, with PIR in r3.
59 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
60 * directed by the "start-cpu" RTS call, with PIR in r3.
61 * -or- For OPAL entry:
62 * 1. The MMU is off, processor in HV mode.
63 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
64 * in r8, and entry in r9 for debugging purposes.
65 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
66 * is at generic_secondary_smp_init, with PIR in r3.
68 * For Book3E processors:
69 * 1. The MMU is on running in AS0 in a state defined in ePAPR
70 * 2. The kernel is entered at __start
73 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
74 USE_FIXED_SECTION(first_256B)
76 * Offsets are relative from the start of fixed section, and
77 * first_256B starts at 0. Offsets are a bit easier to use here
78 * than the fixed section entry macros.
82 /* NOP this out unconditionally */
85 b __start_initialization_multiplatform
88 /* Catch branch to 0 in real mode */
91 /* Secondary processors spin on this value until it becomes non-zero.
92 * When non-zero, it contains the real address of the function the cpu
96 .globl __secondary_hold_spinloop
97 __secondary_hold_spinloop:
100 /* Secondary processors write this value with their cpu # */
101 /* after they enter the spin loop immediately below. */
102 .globl __secondary_hold_acknowledge
103 __secondary_hold_acknowledge:
106 #ifdef CONFIG_RELOCATABLE
107 /* This flag is set to 1 by a loader if the kernel should run
108 * at the loaded address instead of the linked address. This
109 * is used by kexec-tools to keep the the kdump kernel in the
110 * crash_kernel region. The loader is responsible for
111 * observing the alignment requirement.
114 #ifdef CONFIG_RELOCATABLE_TEST
115 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
117 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
120 /* Do not move this variable as kexec-tools knows about it. */
124 DEFINE_FIXED_SYMBOL(__run_at_load)
125 .long RUN_AT_LOAD_DEFAULT
130 * The following code is used to hold secondary processors
131 * in a spin loop after they have entered the kernel, but
132 * before the bulk of the kernel has been relocated. This code
133 * is relocated to physical address 0x60 before prom_init is run.
134 * All of it must fit below the first exception vector at 0x100.
135 * Use .globl here not _GLOBAL because we want __secondary_hold
136 * to be the actual text address, not a descriptor.
138 .globl __secondary_hold
141 #ifndef CONFIG_PPC_BOOK3E
144 mtmsrd r24 /* RI on */
146 /* Grab our physical cpu number */
148 /* stash r4 for book3e */
151 /* Tell the master cpu we're here */
152 /* Relocation is off & we are located at an address less */
153 /* than 0x100, so only need to grab low order offset. */
154 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
158 #ifdef CONFIG_PPC_BOOK3E
161 /* All secondary cpus wait here until told to start. */
162 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
166 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
167 #ifdef CONFIG_PPC_BOOK3E
173 * it may be the case that other platforms have r4 right to
174 * begin with, this gives us some safety in case it is not
176 #ifdef CONFIG_PPC_BOOK3E
181 /* Make sure that patched code is visible */
186 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
188 CLOSE_FIXED_SECTION(first_256B)
190 /* This value is used to mark exception frames on the stack. */
193 .tc ID_72656773_68657265[TC],0x7265677368657265
197 * On server, we include the exception vectors code here as it
198 * relies on absolute addressing which is only possible within
199 * this compilation unit
201 #ifdef CONFIG_PPC_BOOK3S
202 #include "exceptions-64s.S"
204 OPEN_TEXT_SECTION(0x100)
209 #ifdef CONFIG_PPC_BOOK3E
211 * The booting_thread_hwid holds the thread id we want to boot in cpu
212 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
213 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
216 .globl booting_thread_hwid
218 .long INVALID_THREAD_HWID
221 * start a thread in the same core
223 * r3 = the thread physical id
224 * r4 = the entry point where thread starts
226 _GLOBAL(book3e_start_thread)
227 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
232 /* If the thread id is invalid, just exit. */
250 * stop a thread in the same core
252 * r3 = the thread physical id
254 _GLOBAL(book3e_stop_thread)
259 /* If the thread id is invalid, just exit. */
268 _GLOBAL(fsl_secondary_thread_init)
271 /* Enable branch prediction */
273 ori r3,r3,BUCSR_INIT@l
278 * Fix PIR to match the linear numbering in the device tree.
280 * On e6500, the reset value of PIR uses the low three bits for
281 * the thread within a core, and the upper bits for the core
282 * number. There are two threads per core, so shift everything
283 * but the low bit right by two bits so that the cpu numbering is
286 * If the old value of BUCSR is non-zero, this thread has run
287 * before. Thus, we assume we are coming from kexec or a similar
288 * scenario, and PIR is already set to the correct value. This
289 * is a bit of a hack, but there are limited opportunities for
290 * getting information into the thread and the alternatives
291 * seemed like they'd be overkill. We can't tell just by looking
292 * at the old PIR value which state it's in, since the same value
293 * could be valid for one thread out of reset and for a different
300 rlwimi r3, r3, 30, 2, 30
305 /* turn on 64-bit mode */
308 /* get a valid TOC pointer, wherever we're mapped at */
312 /* Book3E initialization */
314 bl book3e_secondary_thread_init
315 b generic_secondary_common_init
317 #endif /* CONFIG_PPC_BOOK3E */
320 * On pSeries and most other platforms, secondary processors spin
321 * in the following code.
322 * At entry, r3 = this processor's number (physical cpu id)
324 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
325 * this core already exists (setup via some other mechanism such
326 * as SCOM before entry).
328 _GLOBAL(generic_secondary_smp_init)
333 /* turn on 64-bit mode */
336 /* get a valid TOC pointer, wherever we're mapped at */
340 #ifdef CONFIG_PPC_BOOK3E
341 /* Book3E initialization */
344 bl book3e_secondary_core_init
347 * After common core init has finished, check if the current thread is the
348 * one we wanted to boot. If not, start the specified thread and stop the
351 LOAD_REG_ADDR(r4, booting_thread_hwid)
353 li r5, INVALID_THREAD_HWID
358 * The value of booting_thread_hwid has been stored in r3,
359 * so make it invalid.
364 * Get the current thread id and check if it is the one we wanted.
365 * If not, start the one specified in booting_thread_hwid and stop
366 * the current thread.
372 /* start the specified thread */
373 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
375 bl book3e_start_thread
377 /* stop the current thread */
379 bl book3e_stop_thread
385 generic_secondary_common_init:
386 /* Set up a paca value for this processor. Since we have the
387 * physical cpu id in r24, we need to search the pacas to find
388 * which logical id maps to our physical one.
391 b kexec_wait /* wait for next kernel if !SMP */
393 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
394 ld r8,0(r8) /* Get base vaddr of array */
395 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
396 lwz r7,0(r7) /* also the max paca allocated */
397 li r5,0 /* logical cpu id */
399 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
400 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
401 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
402 cmpw r6,r24 /* Compare to our id */
405 cmpw r5,r7 /* Check if more pacas exist */
408 mr r3,r24 /* not found, copy phys to r3 */
409 b kexec_wait /* next kernel might do better */
412 #ifdef CONFIG_PPC_BOOK3E
413 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
414 mtspr SPRN_SPRG_TLB_EXFRAME,r12
417 /* From now on, r24 is expected to be logical cpuid */
420 /* See if we need to call a cpu state restore handler */
421 LOAD_REG_ADDR(r23, cur_cpu_spec)
423 ld r12,CPU_SPEC_RESTORE(r23)
426 #ifdef PPC64_ELF_ABI_v1
432 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
440 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
443 beq 4b /* Loop until told to go */
445 sync /* order paca.run and cur_cpu_spec */
446 isync /* In case code patching happened */
448 /* Create a temp kernel stack for use before relocation is on. */
449 ld r1,PACAEMERGSP(r13)
450 subi r1,r1,STACK_FRAME_OVERHEAD
457 * Assumes we're mapped EA == RA if the MMU is on.
459 #ifdef CONFIG_PPC_BOOK3S
462 andi. r0,r3,MSR_IR|MSR_DR
470 b . /* prevent speculative execution */
475 * Here is our main kernel entry point. We support currently 2 kind of entries
476 * depending on the value of r5.
478 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
481 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
482 * DT block, r4 is a physical pointer to the kernel itself
485 __start_initialization_multiplatform:
486 /* Make sure we are running in 64 bits mode */
489 /* Get TOC pointer (current runtime address) */
492 /* find out where we are now */
494 0: mflr r26 /* r26 = runtime addr here */
495 addis r26,r26,(_stext - 0b)@ha
496 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
499 * Are we booted from a PROM Of-type client-interface ?
503 b __boot_from_prom /* yes -> prom */
505 /* Save parameters */
508 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
509 /* Save OPAL entry */
514 #ifdef CONFIG_PPC_BOOK3E
515 bl start_initialization_book3e
518 /* Setup some critical 970 SPRs before switching MMU off */
521 cmpwi r0,0x39 /* 970 */
523 cmpwi r0,0x3c /* 970FX */
525 cmpwi r0,0x44 /* 970MP */
527 cmpwi r0,0x45 /* 970GX */
529 1: bl __cpu_preinit_ppc970
532 /* Switch off MMU if not already off */
535 #endif /* CONFIG_PPC_BOOK3E */
539 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
540 /* Save parameters */
548 * Align the stack to 16-byte boundary
549 * Depending on the size and layout of the ELF sections in the initial
550 * boot binary, the stack pointer may be unaligned on PowerMac
554 #ifdef CONFIG_RELOCATABLE
555 /* Relocate code for where we are now */
560 /* Restore parameters */
567 /* Do all of the interaction with OF client interface */
570 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
572 /* We never return. We also hit that trap if trying to boot
573 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
578 #ifdef CONFIG_RELOCATABLE
579 /* process relocations for the final address of the kernel */
580 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
582 #if defined(CONFIG_PPC_BOOK3E)
583 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
585 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
586 #if defined(CONFIG_PPC_BOOK3E)
589 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
594 #if defined(CONFIG_PPC_BOOK3E)
595 /* IVPR needs to be set after relocation. */
601 * We need to run with _stext at physical address PHYSICAL_START.
602 * This will leave some code in the first 256B of
603 * real memory, which are reserved for software use.
605 * Note: This process overwrites the OF exception vectors.
607 li r3,0 /* target addr */
608 #ifdef CONFIG_PPC_BOOK3E
609 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
611 mr. r4,r26 /* In some cases the loader may */
612 #if defined(CONFIG_PPC_BOOK3E)
615 beq 9f /* have already put us at zero */
616 li r6,0x100 /* Start offset, the first 0x100 */
617 /* bytes were copied earlier. */
619 #ifdef CONFIG_RELOCATABLE
621 * Check if the kernel has to be running as relocatable kernel based on the
622 * variable __run_at_load, if it is set the kernel is treated as relocatable
623 * kernel, otherwise it will be moved to PHYSICAL_START
625 #if defined(CONFIG_PPC_BOOK3E)
626 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
628 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
632 #ifdef CONFIG_PPC_BOOK3E
633 LOAD_REG_ADDR(r5, __end_interrupts)
634 LOAD_REG_ADDR(r11, _stext)
637 /* just copy interrupts */
638 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
643 /* # bytes of memory to copy */
644 lis r5,(ABS_ADDR(copy_to_here))@ha
645 addi r5,r5,(ABS_ADDR(copy_to_here))@l
647 bl copy_and_flush /* copy the first n bytes */
648 /* this includes the code being */
650 /* Jump to the copy of this code that we just made */
651 addis r8,r3,(ABS_ADDR(4f))@ha
652 addi r12,r8,(ABS_ADDR(4f))@l
657 p_end: .8byte _end - copy_to_here
661 * Now copy the rest of the kernel up to _end, add
662 * _end - copy_to_here to the copy limit and run again.
664 addis r8,r26,(ABS_ADDR(p_end))@ha
665 ld r8,(ABS_ADDR(p_end))@l(r8)
667 5: bl copy_and_flush /* copy the rest */
669 9: b start_here_multiplatform
672 * Copy routine used to copy the kernel to start at physical address 0
673 * and flush and invalidate the caches as needed.
674 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
675 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
677 * Note: this routine *only* clobbers r0, r6 and lr
679 _GLOBAL(copy_and_flush)
682 4: li r0,8 /* Use the smallest common */
683 /* denominator cache line */
684 /* size. This results in */
685 /* extra cache line flushes */
686 /* but operation is correct. */
687 /* Can't get cache line size */
688 /* from NACA as it is being */
691 mtctr r0 /* put # words/line in ctr */
692 3: addi r6,r6,8 /* copy a cache line */
696 dcbst r6,r3 /* write it to memory */
698 icbi r6,r3 /* flush the icache line */
711 #ifdef CONFIG_PPC_PMAC
713 * On PowerMac, secondary processors starts from the reset vector, which
714 * is temporarily turned into a call to one of the functions below.
719 .globl __secondary_start_pmac_0
720 __secondary_start_pmac_0:
721 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
731 _GLOBAL(pmac_secondary_start)
732 /* turn on 64-bit mode */
737 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
744 /* get TOC pointer (real address) */
748 /* Copy some CPU settings from CPU 0 */
749 bl __restore_cpu_ppc970
751 /* pSeries do that early though I don't think we really need it */
754 mtmsrd r3 /* RI on */
756 /* Set up a paca value for this processor. */
757 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
758 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
759 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
760 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
761 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
763 /* Mark interrupts soft and hard disabled (they might be enabled
764 * in the PACA when doing hotplug)
767 stb r0,PACAIRQSOFTMASK(r13)
768 li r0,PACA_IRQ_HARD_DIS
769 stb r0,PACAIRQHAPPENED(r13)
771 /* Create a temp kernel stack for use before relocation is on. */
772 ld r1,PACAEMERGSP(r13)
773 subi r1,r1,STACK_FRAME_OVERHEAD
777 #endif /* CONFIG_PPC_PMAC */
780 * This function is called after the master CPU has released the
781 * secondary processors. The execution environment is relocation off.
782 * The paca for this processor has the following fields initialized at
784 * 1. Processor number
785 * 2. Segment table pointer (virtual address)
786 * On entry the following are set:
787 * r1 = stack pointer (real addr of temp stack)
788 * r24 = cpu# (in Linux terms)
789 * r13 = paca virtual address
790 * SPRG_PACA = paca virtual address
795 .globl __secondary_start
797 /* Set thread priority to MEDIUM */
801 * Do early setup for this CPU, in particular initialising the MMU so we
802 * can turn it on below. This is a call to C, which is OK, we're still
803 * running on the emergency stack.
805 bl early_setup_secondary
808 * The primary has initialized our kernel stack for us in the paca, grab
809 * it and put it in r1. We must *not* use it until we turn on the MMU
810 * below, because it may not be inside the RMO.
812 ld r1, PACAKSAVE(r13)
814 /* Clear backchain so we get nice backtraces */
818 /* Mark interrupts soft and hard disabled (they might be enabled
819 * in the PACA when doing hotplug)
822 stb r7,PACAIRQSOFTMASK(r13)
823 li r0,PACA_IRQ_HARD_DIS
824 stb r0,PACAIRQHAPPENED(r13)
826 /* enable MMU and jump to start_secondary */
827 LOAD_REG_ADDR(r3, start_secondary_prolog)
828 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
833 b . /* prevent speculative execution */
836 * Running with relocation on at this point. All we want to do is
837 * zero the stack back-chain pointer and get the TOC virtual address
838 * before going into C code.
840 start_secondary_prolog:
843 std r3,0(r1) /* Zero the stack frame pointer */
847 * Reset stack pointer and call start_secondary
848 * to continue with online operation when woken up
849 * from cede in cpu offline.
851 _GLOBAL(start_secondary_resume)
852 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
854 std r3,0(r1) /* Zero the stack frame pointer */
860 * This subroutine clobbers r11 and r12
863 mfmsr r11 /* grab the current MSR */
864 #ifdef CONFIG_PPC_BOOK3E
865 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
867 #else /* CONFIG_PPC_BOOK3E */
868 li r12,(MSR_64BIT | MSR_ISF)@highest
877 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
878 * by the toolchain). It computes the correct value for wherever we
879 * are running at the moment, using position-independent code.
881 * Note: The compiler constructs pointers using offsets from the
882 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
883 * the MMU is on we need our TOC to be a virtual address otherwise
884 * these pointers will be real addresses which may get stored and
885 * accessed later with the MMU on. We use tovirt() at the call
886 * sites to handle this.
888 _GLOBAL(relative_toc)
892 ld r2,(p_toc - 0b)(r11)
898 p_toc: .8byte __toc_start + 0x8000 - 0b
901 * This is where the main kernel code starts.
904 start_here_multiplatform:
909 /* Clear out the BSS. It may have been done in prom_init,
910 * already but that's irrelevant since prom_init will soon
911 * be detached from the kernel completely. Besides, we need
912 * to clear it now for kexec-style entry.
914 LOAD_REG_ADDR(r11,__bss_stop)
915 LOAD_REG_ADDR(r8,__bss_start)
916 sub r11,r11,r8 /* bss size */
917 addi r11,r11,7 /* round up to an even double word */
918 srdi. r11,r11,3 /* shift right by 3 */
922 mtctr r11 /* zero this many doublewords */
927 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
928 /* Setup OPAL entry */
929 LOAD_REG_ADDR(r11, opal)
934 #ifndef CONFIG_PPC_BOOK3E
937 mtmsrd r6 /* RI on */
940 #ifdef CONFIG_RELOCATABLE
941 /* Save the physical address we're running at in kernstart_addr */
942 LOAD_REG_ADDR(r4, kernstart_addr)
947 /* set up a stack pointer */
948 LOAD_REG_ADDR(r3,init_thread_union)
949 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
952 stdu r0,-STACK_FRAME_OVERHEAD(r1)
955 * Do very early kernel initializations, including initial hash table
956 * and SLB setup before we turn on relocation.
959 /* Restore parameters passed from prom_init/kexec */
961 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
963 bctrl /* also sets r13 and SPRG_PACA */
965 LOAD_REG_ADDR(r3, start_here_common)
970 b . /* prevent speculative execution */
972 /* This is where all platforms converge execution */
975 /* relocation is on at this point */
976 std r1,PACAKSAVE(r13)
978 /* Load the TOC (virtual address) */
981 /* Mark interrupts soft and hard disabled (they might be enabled
982 * in the PACA when doing hotplug)
985 stb r0,PACAIRQSOFTMASK(r13)
986 li r0,PACA_IRQ_HARD_DIS
987 stb r0,PACAIRQHAPPENED(r13)
989 /* Generic kernel entry */
994 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
998 * We put a few things here that have to be page-aligned.
999 * This stuff goes at the beginning of the bss, which is page-aligned.
1003 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
1004 * We will need to find a better way to fix this
1008 .globl swapper_pg_dir
1010 .space PGD_TABLE_SIZE
1012 .globl empty_zero_page
1015 EXPORT_SYMBOL(empty_zero_page)