1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
21 #include <linux/threads.h>
22 #include <linux/init.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/head-64.h>
28 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/setup.h>
32 #include <asm/hvcall.h>
33 #include <asm/thread_info.h>
34 #include <asm/firmware.h>
35 #include <asm/page_64.h>
36 #include <asm/irqflags.h>
37 #include <asm/kvm_book3s_asm.h>
38 #include <asm/ptrace.h>
39 #include <asm/hw_irq.h>
40 #include <asm/cputhreads.h>
41 #include <asm/ppc-opcode.h>
42 #include <asm/export.h>
43 #include <asm/feature-fixups.h>
45 /* The physical memory is laid out such that the secondary processor
46 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
47 * using the layout described in exceptions-64s.S
51 * Entering into this code we make the following assumptions:
53 * For pSeries or server processors:
54 * 1. The MMU is off & open firmware is running in real mode.
55 * 2. The primary CPU enters at __start.
56 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
57 * CPUs will enter as directed by "start-cpu" RTAS call, which is
58 * generic_secondary_smp_init, with PIR in r3.
59 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
60 * directed by the "start-cpu" RTS call, with PIR in r3.
61 * -or- For OPAL entry:
62 * 1. The MMU is off, processor in HV mode.
63 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
64 * in r8, and entry in r9 for debugging purposes.
65 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
66 * is at generic_secondary_smp_init, with PIR in r3.
68 * For Book3E processors:
69 * 1. The MMU is on running in AS0 in a state defined in ePAPR
70 * 2. The kernel is entered at __start
73 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
74 USE_FIXED_SECTION(first_256B)
76 * Offsets are relative from the start of fixed section, and
77 * first_256B starts at 0. Offsets are a bit easier to use here
78 * than the fixed section entry macros.
82 /* NOP this out unconditionally */
85 b __start_initialization_multiplatform
88 /* Catch branch to 0 in real mode */
91 /* Secondary processors spin on this value until it becomes non-zero.
92 * When non-zero, it contains the real address of the function the cpu
96 .globl __secondary_hold_spinloop
97 __secondary_hold_spinloop:
100 /* Secondary processors write this value with their cpu # */
101 /* after they enter the spin loop immediately below. */
102 .globl __secondary_hold_acknowledge
103 __secondary_hold_acknowledge:
106 #ifdef CONFIG_RELOCATABLE
107 /* This flag is set to 1 by a loader if the kernel should run
108 * at the loaded address instead of the linked address. This
109 * is used by kexec-tools to keep the the kdump kernel in the
110 * crash_kernel region. The loader is responsible for
111 * observing the alignment requirement.
114 #ifdef CONFIG_RELOCATABLE_TEST
115 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
117 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
120 /* Do not move this variable as kexec-tools knows about it. */
124 DEFINE_FIXED_SYMBOL(__run_at_load)
125 .long RUN_AT_LOAD_DEFAULT
130 * The following code is used to hold secondary processors
131 * in a spin loop after they have entered the kernel, but
132 * before the bulk of the kernel has been relocated. This code
133 * is relocated to physical address 0x60 before prom_init is run.
134 * All of it must fit below the first exception vector at 0x100.
135 * Use .globl here not _GLOBAL because we want __secondary_hold
136 * to be the actual text address, not a descriptor.
138 .globl __secondary_hold
141 #ifndef CONFIG_PPC_BOOK3E
144 mtmsrd r24 /* RI on */
146 /* Grab our physical cpu number */
148 /* stash r4 for book3e */
151 /* Tell the master cpu we're here */
152 /* Relocation is off & we are located at an address less */
153 /* than 0x100, so only need to grab low order offset. */
154 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
158 #ifdef CONFIG_PPC_BOOK3E
161 /* All secondary cpus wait here until told to start. */
162 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
166 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
167 #ifdef CONFIG_PPC_BOOK3E
173 * it may be the case that other platforms have r4 right to
174 * begin with, this gives us some safety in case it is not
176 #ifdef CONFIG_PPC_BOOK3E
181 /* Make sure that patched code is visible */
186 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
188 CLOSE_FIXED_SECTION(first_256B)
190 /* This value is used to mark exception frames on the stack. */
193 .tc ID_72656773_68657265[TC],0x7265677368657265
197 * On server, we include the exception vectors code here as it
198 * relies on absolute addressing which is only possible within
199 * this compilation unit
201 #ifdef CONFIG_PPC_BOOK3S
202 #include "exceptions-64s.S"
204 OPEN_TEXT_SECTION(0x100)
209 #ifdef CONFIG_PPC_BOOK3E
211 * The booting_thread_hwid holds the thread id we want to boot in cpu
212 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
213 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
216 .globl booting_thread_hwid
218 .long INVALID_THREAD_HWID
221 * start a thread in the same core
223 * r3 = the thread physical id
224 * r4 = the entry point where thread starts
226 _GLOBAL(book3e_start_thread)
227 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
232 /* If the thread id is invalid, just exit. */
250 * stop a thread in the same core
252 * r3 = the thread physical id
254 _GLOBAL(book3e_stop_thread)
259 /* If the thread id is invalid, just exit. */
268 _GLOBAL(fsl_secondary_thread_init)
271 /* Enable branch prediction */
273 ori r3,r3,BUCSR_INIT@l
278 * Fix PIR to match the linear numbering in the device tree.
280 * On e6500, the reset value of PIR uses the low three bits for
281 * the thread within a core, and the upper bits for the core
282 * number. There are two threads per core, so shift everything
283 * but the low bit right by two bits so that the cpu numbering is
286 * If the old value of BUCSR is non-zero, this thread has run
287 * before. Thus, we assume we are coming from kexec or a similar
288 * scenario, and PIR is already set to the correct value. This
289 * is a bit of a hack, but there are limited opportunities for
290 * getting information into the thread and the alternatives
291 * seemed like they'd be overkill. We can't tell just by looking
292 * at the old PIR value which state it's in, since the same value
293 * could be valid for one thread out of reset and for a different
300 rlwimi r3, r3, 30, 2, 30
305 _GLOBAL(generic_secondary_thread_init)
308 /* turn on 64-bit mode */
311 /* get a valid TOC pointer, wherever we're mapped at */
315 #ifdef CONFIG_PPC_BOOK3E
316 /* Book3E initialization */
318 bl book3e_secondary_thread_init
320 b generic_secondary_common_init
323 * On pSeries and most other platforms, secondary processors spin
324 * in the following code.
325 * At entry, r3 = this processor's number (physical cpu id)
327 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
328 * this core already exists (setup via some other mechanism such
329 * as SCOM before entry).
331 _GLOBAL(generic_secondary_smp_init)
336 /* turn on 64-bit mode */
339 /* get a valid TOC pointer, wherever we're mapped at */
343 #ifdef CONFIG_PPC_BOOK3E
344 /* Book3E initialization */
347 bl book3e_secondary_core_init
350 * After common core init has finished, check if the current thread is the
351 * one we wanted to boot. If not, start the specified thread and stop the
354 LOAD_REG_ADDR(r4, booting_thread_hwid)
356 li r5, INVALID_THREAD_HWID
361 * The value of booting_thread_hwid has been stored in r3,
362 * so make it invalid.
367 * Get the current thread id and check if it is the one we wanted.
368 * If not, start the one specified in booting_thread_hwid and stop
369 * the current thread.
375 /* start the specified thread */
376 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
378 bl book3e_start_thread
380 /* stop the current thread */
382 bl book3e_stop_thread
388 generic_secondary_common_init:
389 /* Set up a paca value for this processor. Since we have the
390 * physical cpu id in r24, we need to search the pacas to find
391 * which logical id maps to our physical one.
394 b kexec_wait /* wait for next kernel if !SMP */
396 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
397 ld r8,0(r8) /* Get base vaddr of array */
398 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
399 lwz r7,0(r7) /* also the max paca allocated */
400 li r5,0 /* logical cpu id */
402 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
403 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
404 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
405 cmpw r6,r24 /* Compare to our id */
408 cmpw r5,r7 /* Check if more pacas exist */
411 mr r3,r24 /* not found, copy phys to r3 */
412 b kexec_wait /* next kernel might do better */
415 #ifdef CONFIG_PPC_BOOK3E
416 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
417 mtspr SPRN_SPRG_TLB_EXFRAME,r12
420 /* From now on, r24 is expected to be logical cpuid */
423 /* See if we need to call a cpu state restore handler */
424 LOAD_REG_ADDR(r23, cur_cpu_spec)
426 ld r12,CPU_SPEC_RESTORE(r23)
429 #ifdef PPC64_ELF_ABI_v1
435 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
443 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
446 beq 4b /* Loop until told to go */
448 sync /* order paca.run and cur_cpu_spec */
449 isync /* In case code patching happened */
451 /* Create a temp kernel stack for use before relocation is on. */
452 ld r1,PACAEMERGSP(r13)
453 subi r1,r1,STACK_FRAME_OVERHEAD
460 * Assumes we're mapped EA == RA if the MMU is on.
462 #ifdef CONFIG_PPC_BOOK3S
465 andi. r0,r3,MSR_IR|MSR_DR
473 b . /* prevent speculative execution */
478 * Here is our main kernel entry point. We support currently 2 kind of entries
479 * depending on the value of r5.
481 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
484 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
485 * DT block, r4 is a physical pointer to the kernel itself
488 __start_initialization_multiplatform:
489 /* Make sure we are running in 64 bits mode */
492 /* Get TOC pointer (current runtime address) */
495 /* find out where we are now */
497 0: mflr r26 /* r26 = runtime addr here */
498 addis r26,r26,(_stext - 0b)@ha
499 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
502 * Are we booted from a PROM Of-type client-interface ?
506 b __boot_from_prom /* yes -> prom */
508 /* Save parameters */
511 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
512 /* Save OPAL entry */
517 #ifdef CONFIG_PPC_BOOK3E
518 bl start_initialization_book3e
521 /* Setup some critical 970 SPRs before switching MMU off */
524 cmpwi r0,0x39 /* 970 */
526 cmpwi r0,0x3c /* 970FX */
528 cmpwi r0,0x44 /* 970MP */
530 cmpwi r0,0x45 /* 970GX */
532 1: bl __cpu_preinit_ppc970
535 /* Switch off MMU if not already off */
538 #endif /* CONFIG_PPC_BOOK3E */
542 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
543 /* Save parameters */
551 * Align the stack to 16-byte boundary
552 * Depending on the size and layout of the ELF sections in the initial
553 * boot binary, the stack pointer may be unaligned on PowerMac
557 #ifdef CONFIG_RELOCATABLE
558 /* Relocate code for where we are now */
563 /* Restore parameters */
570 /* Do all of the interaction with OF client interface */
573 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
575 /* We never return. We also hit that trap if trying to boot
576 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
581 #ifdef CONFIG_RELOCATABLE
582 /* process relocations for the final address of the kernel */
583 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
585 #if defined(CONFIG_PPC_BOOK3E)
586 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
588 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
589 #if defined(CONFIG_PPC_BOOK3E)
592 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
597 #if defined(CONFIG_PPC_BOOK3E)
598 /* IVPR needs to be set after relocation. */
604 * We need to run with _stext at physical address PHYSICAL_START.
605 * This will leave some code in the first 256B of
606 * real memory, which are reserved for software use.
608 * Note: This process overwrites the OF exception vectors.
610 li r3,0 /* target addr */
611 #ifdef CONFIG_PPC_BOOK3E
612 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
614 mr. r4,r26 /* In some cases the loader may */
615 #if defined(CONFIG_PPC_BOOK3E)
618 beq 9f /* have already put us at zero */
619 li r6,0x100 /* Start offset, the first 0x100 */
620 /* bytes were copied earlier. */
622 #ifdef CONFIG_RELOCATABLE
624 * Check if the kernel has to be running as relocatable kernel based on the
625 * variable __run_at_load, if it is set the kernel is treated as relocatable
626 * kernel, otherwise it will be moved to PHYSICAL_START
628 #if defined(CONFIG_PPC_BOOK3E)
629 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
631 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
635 #ifdef CONFIG_PPC_BOOK3E
636 LOAD_REG_ADDR(r5, __end_interrupts)
637 LOAD_REG_ADDR(r11, _stext)
640 /* just copy interrupts */
641 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
646 /* # bytes of memory to copy */
647 lis r5,(ABS_ADDR(copy_to_here))@ha
648 addi r5,r5,(ABS_ADDR(copy_to_here))@l
650 bl copy_and_flush /* copy the first n bytes */
651 /* this includes the code being */
653 /* Jump to the copy of this code that we just made */
654 addis r8,r3,(ABS_ADDR(4f))@ha
655 addi r12,r8,(ABS_ADDR(4f))@l
660 p_end: .8byte _end - copy_to_here
664 * Now copy the rest of the kernel up to _end, add
665 * _end - copy_to_here to the copy limit and run again.
667 addis r8,r26,(ABS_ADDR(p_end))@ha
668 ld r8,(ABS_ADDR(p_end))@l(r8)
670 5: bl copy_and_flush /* copy the rest */
672 9: b start_here_multiplatform
675 * Copy routine used to copy the kernel to start at physical address 0
676 * and flush and invalidate the caches as needed.
677 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
678 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
680 * Note: this routine *only* clobbers r0, r6 and lr
682 _GLOBAL(copy_and_flush)
685 4: li r0,8 /* Use the smallest common */
686 /* denominator cache line */
687 /* size. This results in */
688 /* extra cache line flushes */
689 /* but operation is correct. */
690 /* Can't get cache line size */
691 /* from NACA as it is being */
694 mtctr r0 /* put # words/line in ctr */
695 3: addi r6,r6,8 /* copy a cache line */
699 dcbst r6,r3 /* write it to memory */
701 icbi r6,r3 /* flush the icache line */
714 #ifdef CONFIG_PPC_PMAC
716 * On PowerMac, secondary processors starts from the reset vector, which
717 * is temporarily turned into a call to one of the functions below.
722 .globl __secondary_start_pmac_0
723 __secondary_start_pmac_0:
724 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
734 _GLOBAL(pmac_secondary_start)
735 /* turn on 64-bit mode */
740 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
747 /* get TOC pointer (real address) */
751 /* Copy some CPU settings from CPU 0 */
752 bl __restore_cpu_ppc970
754 /* pSeries do that early though I don't think we really need it */
757 mtmsrd r3 /* RI on */
759 /* Set up a paca value for this processor. */
760 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
761 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
762 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
763 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
764 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
766 /* Mark interrupts soft and hard disabled (they might be enabled
767 * in the PACA when doing hotplug)
770 stb r0,PACAIRQSOFTMASK(r13)
771 li r0,PACA_IRQ_HARD_DIS
772 stb r0,PACAIRQHAPPENED(r13)
774 /* Create a temp kernel stack for use before relocation is on. */
775 ld r1,PACAEMERGSP(r13)
776 subi r1,r1,STACK_FRAME_OVERHEAD
780 #endif /* CONFIG_PPC_PMAC */
783 * This function is called after the master CPU has released the
784 * secondary processors. The execution environment is relocation off.
785 * The paca for this processor has the following fields initialized at
787 * 1. Processor number
788 * 2. Segment table pointer (virtual address)
789 * On entry the following are set:
790 * r1 = stack pointer (real addr of temp stack)
791 * r24 = cpu# (in Linux terms)
792 * r13 = paca virtual address
793 * SPRG_PACA = paca virtual address
798 .globl __secondary_start
800 /* Set thread priority to MEDIUM */
804 * Do early setup for this CPU, in particular initialising the MMU so we
805 * can turn it on below. This is a call to C, which is OK, we're still
806 * running on the emergency stack.
808 bl early_setup_secondary
811 * The primary has initialized our kernel stack for us in the paca, grab
812 * it and put it in r1. We must *not* use it until we turn on the MMU
813 * below, because it may not be inside the RMO.
815 ld r1, PACAKSAVE(r13)
817 /* Clear backchain so we get nice backtraces */
821 /* Mark interrupts soft and hard disabled (they might be enabled
822 * in the PACA when doing hotplug)
825 stb r7,PACAIRQSOFTMASK(r13)
826 li r0,PACA_IRQ_HARD_DIS
827 stb r0,PACAIRQHAPPENED(r13)
829 /* enable MMU and jump to start_secondary */
830 LOAD_REG_ADDR(r3, start_secondary_prolog)
831 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
836 b . /* prevent speculative execution */
839 * Running with relocation on at this point. All we want to do is
840 * zero the stack back-chain pointer and get the TOC virtual address
841 * before going into C code.
843 start_secondary_prolog:
846 std r3,0(r1) /* Zero the stack frame pointer */
850 * Reset stack pointer and call start_secondary
851 * to continue with online operation when woken up
852 * from cede in cpu offline.
854 _GLOBAL(start_secondary_resume)
855 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
857 std r3,0(r1) /* Zero the stack frame pointer */
863 * This subroutine clobbers r11 and r12
866 mfmsr r11 /* grab the current MSR */
867 #ifdef CONFIG_PPC_BOOK3E
868 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
870 #else /* CONFIG_PPC_BOOK3E */
871 li r12,(MSR_64BIT | MSR_ISF)@highest
880 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
881 * by the toolchain). It computes the correct value for wherever we
882 * are running at the moment, using position-independent code.
884 * Note: The compiler constructs pointers using offsets from the
885 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
886 * the MMU is on we need our TOC to be a virtual address otherwise
887 * these pointers will be real addresses which may get stored and
888 * accessed later with the MMU on. We use tovirt() at the call
889 * sites to handle this.
891 _GLOBAL(relative_toc)
895 ld r2,(p_toc - 0b)(r11)
901 p_toc: .8byte __toc_start + 0x8000 - 0b
904 * This is where the main kernel code starts.
907 start_here_multiplatform:
912 /* Clear out the BSS. It may have been done in prom_init,
913 * already but that's irrelevant since prom_init will soon
914 * be detached from the kernel completely. Besides, we need
915 * to clear it now for kexec-style entry.
917 LOAD_REG_ADDR(r11,__bss_stop)
918 LOAD_REG_ADDR(r8,__bss_start)
919 sub r11,r11,r8 /* bss size */
920 addi r11,r11,7 /* round up to an even double word */
921 srdi. r11,r11,3 /* shift right by 3 */
925 mtctr r11 /* zero this many doublewords */
930 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
931 /* Setup OPAL entry */
932 LOAD_REG_ADDR(r11, opal)
937 #ifndef CONFIG_PPC_BOOK3E
940 mtmsrd r6 /* RI on */
943 #ifdef CONFIG_RELOCATABLE
944 /* Save the physical address we're running at in kernstart_addr */
945 LOAD_REG_ADDR(r4, kernstart_addr)
950 /* set up a stack pointer */
951 LOAD_REG_ADDR(r3,init_thread_union)
952 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
955 stdu r0,-STACK_FRAME_OVERHEAD(r1)
958 * Do very early kernel initializations, including initial hash table
959 * and SLB setup before we turn on relocation.
962 /* Restore parameters passed from prom_init/kexec */
964 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
966 bctrl /* also sets r13 and SPRG_PACA */
968 LOAD_REG_ADDR(r3, start_here_common)
973 b . /* prevent speculative execution */
975 /* This is where all platforms converge execution */
978 /* relocation is on at this point */
979 std r1,PACAKSAVE(r13)
981 /* Load the TOC (virtual address) */
984 /* Mark interrupts soft and hard disabled (they might be enabled
985 * in the PACA when doing hotplug)
988 stb r0,PACAIRQSOFTMASK(r13)
989 li r0,PACA_IRQ_HARD_DIS
990 stb r0,PACAIRQHAPPENED(r13)
992 /* Generic kernel entry */
997 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1001 * We put a few things here that have to be page-aligned.
1002 * This stuff goes at the beginning of the bss, which is page-aligned.
1006 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
1007 * We will need to find a better way to fix this
1011 .globl swapper_pg_dir
1013 .space PGD_TABLE_SIZE
1015 .globl empty_zero_page
1018 EXPORT_SYMBOL(empty_zero_page)