2 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
3 * Initial PowerPC version.
4 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
7 * Low-level exception handers, MMU support, and rewrite.
8 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
9 * PowerPC 8xx modifications.
10 * Copyright (c) 1998-1999 TiVo, Inc.
11 * PowerPC 403GCX modifications.
12 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
13 * PowerPC 403GCX/405GP modifications.
14 * Copyright 2000 MontaVista Software Inc.
15 * PPC405 modifications
16 * PowerPC 403GCX/405GP modifications.
17 * Author: MontaVista Software, Inc.
18 * frank_rowand@mvista.com or source@mvista.com
19 * debbie_chu@mvista.com
22 * Module name: head_4xx.S
25 * Kernel execution entry point code.
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License
29 * as published by the Free Software Foundation; either version
30 * 2 of the License, or (at your option) any later version.
34 #include <linux/init.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/ptrace.h>
44 #include <asm/export.h>
45 #include <asm/asm-405.h>
49 /* As with the other PowerPC ports, it is expected that when code
50 * execution begins here, the following registers contain valid, yet
51 * optional, information:
53 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
54 * r4 - Starting address of the init RAM disk
55 * r5 - Ending address of the init RAM disk
56 * r6 - Start of kernel command line string (e.g. "mem=96m")
57 * r7 - End of kernel command line string
59 * This is all going to change RSN when we add bi_recs....... -- Dan
65 mr r31,r3 /* save device tree ptr */
67 /* We have to turn on the MMU right away so we get cache modes
72 /* We now have the lower 16 Meg mapped into TLB entries, and the caches
77 ori r0,r0,MSR_KERNEL@l
80 ori r0,r0,start_here@l
84 b . /* prevent prefetch past rfi */
87 * This area is used for temporarily saving registers during the
88 * critical exception prolog.
100 _ENTRY(saved_ksp_limit)
104 * Exception prolog for critical exceptions. This is a little different
105 * from the normal exception prolog above since a critical exception
106 * can potentially occur at any point during normal exception processing.
107 * Thus we cannot use the same SPRG registers as the normal prolog above.
108 * Instead we use a couple of words of memory at low physical addresses.
109 * This is OK since we don't support SMP on these processors.
111 #define CRITICAL_EXCEPTION_PROLOG \
112 stw r10,crit_r10@l(0); /* save two registers to work with */\
113 stw r11,crit_r11@l(0); \
114 mfcr r10; /* save CR in r10 for now */\
115 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\
116 andi. r11,r11,MSR_PR; \
117 lis r11,critirq_ctx@ha; \
119 lwz r11,critirq_ctx@l(r11); \
121 /* COMING FROM USER MODE */ \
122 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
123 lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\
124 1: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\
126 stw r10,_CCR(r11); /* save various registers */\
127 stw r12,GPR12(r11); \
130 stw r10,_LINK(r11); \
131 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
132 stw r12,_DEAR(r11); /* since they may have had stuff */\
133 mfspr r9,SPRN_ESR; /* in them at the point where the */\
134 stw r9,_ESR(r11); /* exception was taken */\
135 mfspr r12,SPRN_SRR2; \
137 mfspr r9,SPRN_SRR3; \
140 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
142 lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */\
143 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
145 SAVE_4GPRS(3, r11); \
149 * State at this point:
150 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
151 * r10 saved in crit_r10 and in stack frame, trashed
152 * r11 saved in crit_r11 and in stack frame,
153 * now phys stack/exception frame pointer
154 * r12 saved in stack frame, now saved SRR2
155 * CR saved in stack frame, CR0.EQ = !SRR3.PR
156 * LR, DEAR, ESR in stack frame
157 * r1 saved in stack frame, now virt stack/excframe pointer
158 * r0, r3-r8 saved in stack frame
164 #define CRITICAL_EXCEPTION(n, label, hdlr) \
165 START_EXCEPTION(n, label); \
166 CRITICAL_EXCEPTION_PROLOG; \
167 addi r3,r1,STACK_FRAME_OVERHEAD; \
168 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
169 crit_transfer_to_handler, ret_from_crit_exc)
172 * 0x0100 - Critical Interrupt Exception
174 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
177 * 0x0200 - Machine Check Exception
179 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
182 * 0x0300 - Data Storage Exception
183 * This happens for just a few reasons. U0 set (but we don't do that),
184 * or zone protection fault (user violation, write to protected page).
185 * If this is just an update of modified status, we do that quickly
186 * and exit. Otherwise, we call heavywight functions to do the work.
188 START_EXCEPTION(0x0300, DataStorage)
189 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
190 mtspr SPRN_SPRG_SCRATCH1, r11
199 mtspr SPRN_SPRG_SCRATCH3, r12
200 mtspr SPRN_SPRG_SCRATCH4, r9
203 mtspr SPRN_SPRG_SCRATCH6, r11
204 mtspr SPRN_SPRG_SCRATCH5, r12
207 /* First, check if it was a zone fault (which means a user
208 * tried to access a kernel or read-protected page - always
209 * a SEGV). All other faults here must be stores, so no
210 * need to check ESR_DST as well. */
212 andis. r10, r10, ESR_DIZ@h
215 mfspr r10, SPRN_DEAR /* Get faulting address */
217 /* If we are faulting a kernel address, we have to use the
218 * kernel page tables.
220 lis r11, PAGE_OFFSET@h
223 lis r11, swapper_pg_dir@h
224 ori r11, r11, swapper_pg_dir@l
226 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
229 /* Get the PGD for the current thread.
232 mfspr r11,SPRN_SPRG_THREAD
236 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
237 lwz r11, 0(r11) /* Get L1 entry */
238 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
239 beq 2f /* Bail if no table */
241 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
242 lwz r11, 0(r12) /* Get Linux PTE */
244 andi. r9, r11, _PAGE_RW /* Is it writeable? */
245 beq 2f /* Bail if not */
249 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
250 stw r11, 0(r12) /* Update Linux page table */
252 /* Most of the Linux PTE is ready to load into the TLB LO.
253 * We set ZSEL, where only the LS-bit determines user access.
254 * We set execute, because we don't have the granularity to
255 * properly set this at the page level (Linux problem).
256 * If shared is set, we cause a zero PID->TID load.
257 * Many of these bits are software only. Bits we don't set
258 * here we (properly should) assume have the appropriate value.
261 andc r11, r11, r12 /* Make sure 20, 21 are zero */
263 /* find the TLB index that caused the fault. It has to be here.
267 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
269 /* Done...restore registers and get out of here.
279 mfspr r12, SPRN_SPRG_SCRATCH5
280 mfspr r11, SPRN_SPRG_SCRATCH6
283 mfspr r9, SPRN_SPRG_SCRATCH4
284 mfspr r12, SPRN_SPRG_SCRATCH3
286 mfspr r11, SPRN_SPRG_SCRATCH1
287 mfspr r10, SPRN_SPRG_SCRATCH0
289 rfi /* Should sync shadow TLBs */
290 b . /* prevent prefetch past rfi */
293 /* The bailout. Restore registers to pre-exception conditions
294 * and call the heavyweights to help us out.
304 mfspr r12, SPRN_SPRG_SCRATCH5
305 mfspr r11, SPRN_SPRG_SCRATCH6
308 mfspr r9, SPRN_SPRG_SCRATCH4
309 mfspr r12, SPRN_SPRG_SCRATCH3
311 mfspr r11, SPRN_SPRG_SCRATCH1
312 mfspr r10, SPRN_SPRG_SCRATCH0
316 * 0x0400 - Instruction Storage Exception
317 * This is caused by a fetch from non-execute or guarded pages.
319 START_EXCEPTION(0x0400, InstructionAccess)
321 mr r4,r12 /* Pass SRR0 as arg2 */
322 li r5,0 /* Pass zero as arg3 */
323 EXC_XFER_LITE(0x400, handle_page_fault)
325 /* 0x0500 - External Interrupt Exception */
326 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
328 /* 0x0600 - Alignment Exception */
329 START_EXCEPTION(0x0600, Alignment)
331 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
333 addi r3,r1,STACK_FRAME_OVERHEAD
334 EXC_XFER_STD(0x600, alignment_exception)
336 /* 0x0700 - Program Exception */
337 START_EXCEPTION(0x0700, ProgramCheck)
339 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
341 addi r3,r1,STACK_FRAME_OVERHEAD
342 EXC_XFER_STD(0x700, program_check_exception)
344 EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD)
345 EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD)
346 EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD)
347 EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD)
349 /* 0x0C00 - System Call Exception */
350 START_EXCEPTION(0x0C00, SystemCall)
353 EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD)
354 EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD)
355 EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD)
357 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
361 /* 0x1010 - Fixed Interval Timer (FIT) Exception
366 /* 0x1020 - Watchdog Timer (WDT) Exception
371 /* 0x1100 - Data TLB Miss Exception
372 * As the name implies, translation is not in the MMU, so search the
373 * page tables and fix it. The only purpose of this function is to
374 * load TLB entries from the page table if they exist.
376 START_EXCEPTION(0x1100, DTLBMiss)
377 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
378 mtspr SPRN_SPRG_SCRATCH1, r11
387 mtspr SPRN_SPRG_SCRATCH3, r12
388 mtspr SPRN_SPRG_SCRATCH4, r9
391 mtspr SPRN_SPRG_SCRATCH6, r11
392 mtspr SPRN_SPRG_SCRATCH5, r12
394 mfspr r10, SPRN_DEAR /* Get faulting address */
396 /* If we are faulting a kernel address, we have to use the
397 * kernel page tables.
399 lis r11, PAGE_OFFSET@h
402 lis r11, swapper_pg_dir@h
403 ori r11, r11, swapper_pg_dir@l
405 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
408 /* Get the PGD for the current thread.
411 mfspr r11,SPRN_SPRG_THREAD
415 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
416 lwz r12, 0(r11) /* Get L1 entry */
417 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
418 beq 2f /* Bail if no table */
420 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
421 lwz r11, 0(r12) /* Get Linux PTE */
422 andi. r9, r11, _PAGE_PRESENT
425 ori r11, r11, _PAGE_ACCESSED
428 /* Create TLB tag. This is the faulting address plus a static
429 * set of bits. These are size, valid, E, U0.
432 rlwimi r10, r12, 0, 20, 31
436 2: /* Check for possible large-page pmd entry */
437 rlwinm. r9, r12, 2, 22, 24
440 /* Create TLB tag. This is the faulting address, plus a static
441 * set of bits (valid, E, U0) plus the size from the PMD.
444 rlwimi r10, r9, 0, 20, 31
450 /* The bailout. Restore registers to pre-exception conditions
451 * and call the heavyweights to help us out.
461 mfspr r12, SPRN_SPRG_SCRATCH5
462 mfspr r11, SPRN_SPRG_SCRATCH6
465 mfspr r9, SPRN_SPRG_SCRATCH4
466 mfspr r12, SPRN_SPRG_SCRATCH3
468 mfspr r11, SPRN_SPRG_SCRATCH1
469 mfspr r10, SPRN_SPRG_SCRATCH0
472 /* 0x1200 - Instruction TLB Miss Exception
473 * Nearly the same as above, except we get our information from different
474 * registers and bailout to a different point.
476 START_EXCEPTION(0x1200, ITLBMiss)
477 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
478 mtspr SPRN_SPRG_SCRATCH1, r11
487 mtspr SPRN_SPRG_SCRATCH3, r12
488 mtspr SPRN_SPRG_SCRATCH4, r9
491 mtspr SPRN_SPRG_SCRATCH6, r11
492 mtspr SPRN_SPRG_SCRATCH5, r12
494 mfspr r10, SPRN_SRR0 /* Get faulting address */
496 /* If we are faulting a kernel address, we have to use the
497 * kernel page tables.
499 lis r11, PAGE_OFFSET@h
502 lis r11, swapper_pg_dir@h
503 ori r11, r11, swapper_pg_dir@l
505 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
508 /* Get the PGD for the current thread.
511 mfspr r11,SPRN_SPRG_THREAD
515 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
516 lwz r12, 0(r11) /* Get L1 entry */
517 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
518 beq 2f /* Bail if no table */
520 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
521 lwz r11, 0(r12) /* Get Linux PTE */
522 andi. r9, r11, _PAGE_PRESENT
525 ori r11, r11, _PAGE_ACCESSED
528 /* Create TLB tag. This is the faulting address plus a static
529 * set of bits. These are size, valid, E, U0.
532 rlwimi r10, r12, 0, 20, 31
536 2: /* Check for possible large-page pmd entry */
537 rlwinm. r9, r12, 2, 22, 24
540 /* Create TLB tag. This is the faulting address, plus a static
541 * set of bits (valid, E, U0) plus the size from the PMD.
544 rlwimi r10, r9, 0, 20, 31
550 /* The bailout. Restore registers to pre-exception conditions
551 * and call the heavyweights to help us out.
561 mfspr r12, SPRN_SPRG_SCRATCH5
562 mfspr r11, SPRN_SPRG_SCRATCH6
565 mfspr r9, SPRN_SPRG_SCRATCH4
566 mfspr r12, SPRN_SPRG_SCRATCH3
568 mfspr r11, SPRN_SPRG_SCRATCH1
569 mfspr r10, SPRN_SPRG_SCRATCH0
572 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
573 EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD)
574 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
575 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD)
576 #ifdef CONFIG_IBM405_ERR51
577 /* 405GP errata 51 */
578 START_EXCEPTION(0x1700, Trap_17)
581 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD)
583 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
584 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
585 EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD)
586 EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD)
587 EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD)
588 EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD)
589 EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD)
590 EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD)
592 /* Check for a single step debug exception while in an exception
593 * handler before state has been saved. This is to catch the case
594 * where an instruction that we are trying to single step causes
595 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
596 * the exception handler generates a single step debug exception.
598 * If we get a debug trap on the first instruction of an exception handler,
599 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
600 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
601 * The exception handler was handling a non-critical interrupt, so it will
602 * save (and later restore) the MSR via SPRN_SRR1, which will still have
603 * the MSR_DE bit set.
605 /* 0x2000 - Debug Exception */
606 START_EXCEPTION(0x2000, DebugTrap)
607 CRITICAL_EXCEPTION_PROLOG
610 * If this is a single step or branch-taken exception in an
611 * exception entry sequence, it was probably meant to apply to
612 * the code where the exception occurred (since exception entry
613 * doesn't turn off DE automatically). We simulate the effect
614 * of turning off DE on entry to an exception handler by turning
615 * off DE in the SRR3 value and clearing the debug status.
617 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
618 andis. r10,r10,DBSR_IC@h
621 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
622 beq 1f /* branch and fix it up */
624 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
626 bgt+ 2f /* address above exception vectors */
628 /* here it looks like we got an inappropriate debug exception. */
629 1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */
630 lis r10,DBSR_IC@h /* clear the IC event */
632 /* restore state and get out */
641 lwz r10,crit_r10@l(0)
642 lwz r11,crit_r11@l(0)
647 /* continue normal handling for a critical exception... */
648 2: mfspr r4,SPRN_DBSR
649 addi r3,r1,STACK_FRAME_OVERHEAD
650 EXC_XFER_TEMPLATE(DebugException, 0x2002, \
651 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
652 crit_transfer_to_handler, ret_from_crit_exc)
654 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
658 mtspr SPRN_TSR,r0 /* Clear the PIT exception */
659 addi r3,r1,STACK_FRAME_OVERHEAD
660 EXC_XFER_LITE(0x1000, timer_interrupt)
662 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
665 addi r3,r1,STACK_FRAME_OVERHEAD;
666 EXC_XFER_STD(0x1010, unknown_exception)
668 /* Watchdog Timer (WDT) Exception. (from 0x1020) */
670 CRITICAL_EXCEPTION_PROLOG;
671 addi r3,r1,STACK_FRAME_OVERHEAD;
672 EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2,
673 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)),
674 crit_transfer_to_handler, ret_from_crit_exc)
677 * The other Data TLB exceptions bail out to this point
678 * if they can't resolve the lightweight TLB fault.
682 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
684 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
685 EXC_XFER_LITE(0x300, handle_page_fault)
687 /* Other PowerPC processors, namely those derived from the 6xx-series
688 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
689 * However, for the 4xx-series processors these are neither defined nor
693 /* Damn, I came up one instruction too many to fit into the
694 * exception space :-). Both the instruction and data TLB
695 * miss get to this point to load the TLB.
696 * r10 - TLB_TAG value
698 * r12, r9 - available to use
699 * PID - loaded with proper value when we get here
700 * Upon exit, we reload everything and RFI.
701 * Actually, it will fit now, but oh well.....a common place
707 /* load the next available TLB index.
709 lwz r9, tlb_4xx_index@l(0)
711 andi. r9, r9, (PPC40X_TLB_SIZE-1)
712 stw r9, tlb_4xx_index@l(0)
716 * Clear out the software-only bits in the PTE to generate the
717 * TLB_DATA value. These are the bottom 2 bits of the RPM, the
718 * top 3 bits of the zone field, and M.
723 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
724 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
726 /* Done...restore registers and get out of here.
736 mfspr r12, SPRN_SPRG_SCRATCH5
737 mfspr r11, SPRN_SPRG_SCRATCH6
740 mfspr r9, SPRN_SPRG_SCRATCH4
741 mfspr r12, SPRN_SPRG_SCRATCH3
743 mfspr r11, SPRN_SPRG_SCRATCH1
744 mfspr r10, SPRN_SPRG_SCRATCH0
746 rfi /* Should sync shadow TLBs */
747 b . /* prevent prefetch past rfi */
749 /* This is where the main kernel code starts.
755 ori r2,r2,init_task@l
757 /* ptr to phys current thread */
759 addi r4,r4,THREAD /* init task's THREAD */
760 mtspr SPRN_SPRG_THREAD,r4
763 lis r1,init_thread_union@ha
764 addi r1,r1,init_thread_union@l
766 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
768 bl early_init /* We have to do this with MMU on */
771 * Decide what sort of machine this is and initialize the MMU.
781 /* Go back to running unmapped so we can load up new values
782 * and change to using our exception vectors.
783 * On the 4xx, all we have to do is invalidate the TLB to clear
784 * the old 16M byte TLB mappings.
789 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
790 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
794 b . /* prevent prefetch past rfi */
796 /* Load up the kernel context */
798 sync /* Flush to memory before changing TLB */
800 isync /* Flush shadow TLBs */
802 /* set up the PTE pointers for the Abatron bdiGDB.
804 lis r6, swapper_pg_dir@h
805 ori r6, r6, swapper_pg_dir@l
806 lis r5, abatron_pteptrs@h
807 ori r5, r5, abatron_pteptrs@l
808 stw r5, 0xf0(r0) /* Must match your Abatron config file */
812 /* Now turn on the MMU for real! */
814 ori r4,r4,MSR_KERNEL@l
815 lis r3,start_kernel@h
816 ori r3,r3,start_kernel@l
819 rfi /* enable MMU and jump to start_kernel */
820 b . /* prevent prefetch past rfi */
822 /* Set up the initial MMU state so we can do the first level of
823 * kernel initialization. This maps the first 16 MBytes of memory 1:1
824 * virtual to physical and more importantly sets the cache mode.
827 tlbia /* Invalidate all TLB entries */
830 /* We should still be executing code at physical address 0x0000xxxx
831 * at this point. However, start_here is at virtual address
832 * 0xC000xxxx. So, set up a TLB mapping to cover this once
833 * translation is enabled.
836 lis r3,KERNELBASE@h /* Load the kernel virtual address */
837 ori r3,r3,KERNELBASE@l
838 tophys(r4,r3) /* Load the kernel physical address */
840 iccci r0,r3 /* Invalidate the i-cache before use */
842 /* Load the kernel PID.
848 /* Configure and load one entry into TLB slots 63 */
849 clrrwi r4,r4,10 /* Mask off the real page number */
850 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
852 clrrwi r3,r3,10 /* Mask off the effective page number */
853 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
855 li r0,63 /* TLB slot 63 */
857 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
858 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
862 /* Establish the exception vector base
864 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */
865 tophys(r0,r4) /* Use the physical address */
872 oris r13,r13,DBCR0_RST_SYSTEM@h
877 #ifdef CONFIG_BDI_SWITCH
878 /* Context switch the PTE pointer for the Abatron BDI2000.
879 * The PGDIR is the second parameter.
881 lis r5, abatron_pteptrs@ha
882 stw r4, abatron_pteptrs@l + 0x4(r5)
886 isync /* Need an isync to flush shadow */
887 /* TLBs after changing PID */
890 /* We put a few things here that have to be page-aligned. This stuff
891 * goes at the beginning of the data segment, which is page-aligned.
897 .globl empty_zero_page
900 EXPORT_SYMBOL(empty_zero_page)
901 .globl swapper_pg_dir
903 .space PGD_TABLE_SIZE
905 /* Room for two PTE pointers, usually the kernel and current user pointers
906 * to their respective root page table.