1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
4 * Initial PowerPC version.
5 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
8 * Low-level exception handers, MMU support, and rewrite.
9 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
10 * PowerPC 8xx modifications.
11 * Copyright (c) 1998-1999 TiVo, Inc.
12 * PowerPC 403GCX modifications.
13 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
14 * PowerPC 403GCX/405GP modifications.
15 * Copyright 2000 MontaVista Software Inc.
16 * PPC405 modifications
17 * PowerPC 403GCX/405GP modifications.
18 * Author: MontaVista Software, Inc.
19 * frank_rowand@mvista.com or source@mvista.com
20 * debbie_chu@mvista.com
22 * Module name: head_4xx.S
25 * Kernel execution entry point code.
28 #include <linux/init.h>
29 #include <asm/processor.h>
32 #include <asm/pgtable.h>
33 #include <asm/cputable.h>
34 #include <asm/thread_info.h>
35 #include <asm/ppc_asm.h>
36 #include <asm/asm-offsets.h>
37 #include <asm/ptrace.h>
38 #include <asm/export.h>
42 /* As with the other PowerPC ports, it is expected that when code
43 * execution begins here, the following registers contain valid, yet
44 * optional, information:
46 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
47 * r4 - Starting address of the init RAM disk
48 * r5 - Ending address of the init RAM disk
49 * r6 - Start of kernel command line string (e.g. "mem=96m")
50 * r7 - End of kernel command line string
52 * This is all going to change RSN when we add bi_recs....... -- Dan
58 mr r31,r3 /* save device tree ptr */
60 /* We have to turn on the MMU right away so we get cache modes
65 /* We now have the lower 16 Meg mapped into TLB entries, and the caches
70 ori r0,r0,MSR_KERNEL@l
73 ori r0,r0,start_here@l
77 b . /* prevent prefetch past rfi */
80 * This area is used for temporarily saving registers during the
81 * critical exception prolog.
93 _ENTRY(saved_ksp_limit)
97 * Exception prolog for critical exceptions. This is a little different
98 * from the normal exception prolog above since a critical exception
99 * can potentially occur at any point during normal exception processing.
100 * Thus we cannot use the same SPRG registers as the normal prolog above.
101 * Instead we use a couple of words of memory at low physical addresses.
102 * This is OK since we don't support SMP on these processors.
104 #define CRITICAL_EXCEPTION_PROLOG \
105 stw r10,crit_r10@l(0); /* save two registers to work with */\
106 stw r11,crit_r11@l(0); \
107 mfcr r10; /* save CR in r10 for now */\
108 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\
109 andi. r11,r11,MSR_PR; \
110 lis r11,critirq_ctx@ha; \
112 lwz r11,critirq_ctx@l(r11); \
114 /* COMING FROM USER MODE */ \
115 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
116 lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\
117 1: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\
119 stw r10,_CCR(r11); /* save various registers */\
120 stw r12,GPR12(r11); \
123 stw r10,_LINK(r11); \
124 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
125 stw r12,_DEAR(r11); /* since they may have had stuff */\
126 mfspr r9,SPRN_ESR; /* in them at the point where the */\
127 stw r9,_ESR(r11); /* exception was taken */\
128 mfspr r12,SPRN_SRR2; \
130 mfspr r9,SPRN_SRR3; \
133 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
135 lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */\
136 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
138 SAVE_4GPRS(3, r11); \
142 * State at this point:
143 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
144 * r10 saved in crit_r10 and in stack frame, trashed
145 * r11 saved in crit_r11 and in stack frame,
146 * now phys stack/exception frame pointer
147 * r12 saved in stack frame, now saved SRR2
148 * CR saved in stack frame, CR0.EQ = !SRR3.PR
149 * LR, DEAR, ESR in stack frame
150 * r1 saved in stack frame, now virt stack/excframe pointer
151 * r0, r3-r8 saved in stack frame
157 #define CRITICAL_EXCEPTION(n, label, hdlr) \
158 START_EXCEPTION(n, label); \
159 CRITICAL_EXCEPTION_PROLOG; \
160 addi r3,r1,STACK_FRAME_OVERHEAD; \
161 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
162 crit_transfer_to_handler, ret_from_crit_exc)
165 * 0x0100 - Critical Interrupt Exception
167 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
170 * 0x0200 - Machine Check Exception
172 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
175 * 0x0300 - Data Storage Exception
176 * This happens for just a few reasons. U0 set (but we don't do that),
177 * or zone protection fault (user violation, write to protected page).
178 * The other Data TLB exceptions bail out to this point
179 * if they can't resolve the lightweight TLB fault.
181 START_EXCEPTION(0x0300, DataStorage)
183 mfspr r5, SPRN_ESR /* Grab the ESR, save it, pass arg3 */
185 mfspr r4, SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
187 EXC_XFER_LITE(0x300, handle_page_fault)
190 * 0x0400 - Instruction Storage Exception
191 * This is caused by a fetch from non-execute or guarded pages.
193 START_EXCEPTION(0x0400, InstructionAccess)
195 mr r4,r12 /* Pass SRR0 as arg2 */
197 li r5,0 /* Pass zero as arg3 */
198 EXC_XFER_LITE(0x400, handle_page_fault)
200 /* 0x0500 - External Interrupt Exception */
201 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
203 /* 0x0600 - Alignment Exception */
204 START_EXCEPTION(0x0600, Alignment)
206 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
208 addi r3,r1,STACK_FRAME_OVERHEAD
209 EXC_XFER_STD(0x600, alignment_exception)
211 /* 0x0700 - Program Exception */
212 START_EXCEPTION(0x0700, ProgramCheck)
214 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
216 addi r3,r1,STACK_FRAME_OVERHEAD
217 EXC_XFER_STD(0x700, program_check_exception)
219 EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD)
220 EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD)
221 EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD)
222 EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD)
224 /* 0x0C00 - System Call Exception */
225 START_EXCEPTION(0x0C00, SystemCall)
227 /* Trap_0D is commented out to get more space for system call exception */
229 /* EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD) */
230 EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD)
231 EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD)
233 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
237 /* 0x1010 - Fixed Interval Timer (FIT) Exception
242 /* 0x1020 - Watchdog Timer (WDT) Exception
247 /* 0x1100 - Data TLB Miss Exception
248 * As the name implies, translation is not in the MMU, so search the
249 * page tables and fix it. The only purpose of this function is to
250 * load TLB entries from the page table if they exist.
252 START_EXCEPTION(0x1100, DTLBMiss)
253 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
254 mtspr SPRN_SPRG_SCRATCH1, r11
255 mtspr SPRN_SPRG_SCRATCH3, r12
256 mtspr SPRN_SPRG_SCRATCH4, r9
259 mtspr SPRN_SPRG_SCRATCH5, r9
260 mfspr r10, SPRN_DEAR /* Get faulting address */
262 /* If we are faulting a kernel address, we have to use the
263 * kernel page tables.
265 lis r11, PAGE_OFFSET@h
268 lis r11, swapper_pg_dir@h
269 ori r11, r11, swapper_pg_dir@l
271 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
274 /* Get the PGD for the current thread.
277 mfspr r11,SPRN_SPRG_THREAD
281 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
282 lwz r11, 0(r11) /* Get L1 entry */
283 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */
284 beq 2f /* Bail if no table */
286 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
287 lwz r11, 0(r11) /* Get Linux PTE */
289 li r9, _PAGE_PRESENT | _PAGE_ACCESSED
293 andc. r9, r9, r11 /* Check permission */
296 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
297 and r9, r9, r11 /* hwwrite = dirty & rw */
298 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
300 /* Create TLB tag. This is the faulting address plus a static
301 * set of bits. These are size, valid, E, U0.
304 rlwimi r10, r9, 0, 20, 31
308 2: /* Check for possible large-page pmd entry */
309 rlwinm. r9, r11, 2, 22, 24
312 /* Create TLB tag. This is the faulting address, plus a static
313 * set of bits (valid, E, U0) plus the size from the PMD.
316 rlwimi r10, r9, 0, 20, 31
321 /* The bailout. Restore registers to pre-exception conditions
322 * and call the heavyweights to help us out.
324 mfspr r9, SPRN_SPRG_SCRATCH5
327 mfspr r9, SPRN_SPRG_SCRATCH4
328 mfspr r12, SPRN_SPRG_SCRATCH3
329 mfspr r11, SPRN_SPRG_SCRATCH1
330 mfspr r10, SPRN_SPRG_SCRATCH0
333 /* 0x1200 - Instruction TLB Miss Exception
334 * Nearly the same as above, except we get our information from different
335 * registers and bailout to a different point.
337 START_EXCEPTION(0x1200, ITLBMiss)
338 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
339 mtspr SPRN_SPRG_SCRATCH1, r11
340 mtspr SPRN_SPRG_SCRATCH3, r12
341 mtspr SPRN_SPRG_SCRATCH4, r9
344 mtspr SPRN_SPRG_SCRATCH5, r9
345 mfspr r10, SPRN_SRR0 /* Get faulting address */
347 /* If we are faulting a kernel address, we have to use the
348 * kernel page tables.
350 lis r11, PAGE_OFFSET@h
353 lis r11, swapper_pg_dir@h
354 ori r11, r11, swapper_pg_dir@l
356 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
359 /* Get the PGD for the current thread.
362 mfspr r11,SPRN_SPRG_THREAD
366 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
367 lwz r11, 0(r11) /* Get L1 entry */
368 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */
369 beq 2f /* Bail if no table */
371 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
372 lwz r11, 0(r11) /* Get Linux PTE */
374 li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
376 li r9, _PAGE_PRESENT | _PAGE_EXEC
378 andc. r9, r9, r11 /* Check permission */
381 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
382 and r9, r9, r11 /* hwwrite = dirty & rw */
383 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
385 /* Create TLB tag. This is the faulting address plus a static
386 * set of bits. These are size, valid, E, U0.
389 rlwimi r10, r9, 0, 20, 31
393 2: /* Check for possible large-page pmd entry */
394 rlwinm. r9, r11, 2, 22, 24
397 /* Create TLB tag. This is the faulting address, plus a static
398 * set of bits (valid, E, U0) plus the size from the PMD.
401 rlwimi r10, r9, 0, 20, 31
406 /* The bailout. Restore registers to pre-exception conditions
407 * and call the heavyweights to help us out.
409 mfspr r9, SPRN_SPRG_SCRATCH5
412 mfspr r9, SPRN_SPRG_SCRATCH4
413 mfspr r12, SPRN_SPRG_SCRATCH3
414 mfspr r11, SPRN_SPRG_SCRATCH1
415 mfspr r10, SPRN_SPRG_SCRATCH0
418 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
419 EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD)
420 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
421 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD)
422 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD)
423 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
424 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
425 EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD)
426 EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD)
427 EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD)
428 EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD)
429 EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD)
430 EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD)
432 /* Check for a single step debug exception while in an exception
433 * handler before state has been saved. This is to catch the case
434 * where an instruction that we are trying to single step causes
435 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
436 * the exception handler generates a single step debug exception.
438 * If we get a debug trap on the first instruction of an exception handler,
439 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
440 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
441 * The exception handler was handling a non-critical interrupt, so it will
442 * save (and later restore) the MSR via SPRN_SRR1, which will still have
443 * the MSR_DE bit set.
445 /* 0x2000 - Debug Exception */
446 START_EXCEPTION(0x2000, DebugTrap)
447 CRITICAL_EXCEPTION_PROLOG
450 * If this is a single step or branch-taken exception in an
451 * exception entry sequence, it was probably meant to apply to
452 * the code where the exception occurred (since exception entry
453 * doesn't turn off DE automatically). We simulate the effect
454 * of turning off DE on entry to an exception handler by turning
455 * off DE in the SRR3 value and clearing the debug status.
457 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
458 andis. r10,r10,DBSR_IC@h
461 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
462 beq 1f /* branch and fix it up */
464 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
466 bgt+ 2f /* address above exception vectors */
468 /* here it looks like we got an inappropriate debug exception. */
469 1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */
470 lis r10,DBSR_IC@h /* clear the IC event */
472 /* restore state and get out */
481 lwz r10,crit_r10@l(0)
482 lwz r11,crit_r11@l(0)
486 /* continue normal handling for a critical exception... */
487 2: mfspr r4,SPRN_DBSR
488 addi r3,r1,STACK_FRAME_OVERHEAD
489 EXC_XFER_TEMPLATE(DebugException, 0x2002, \
490 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
491 crit_transfer_to_handler, ret_from_crit_exc)
493 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
497 mtspr SPRN_TSR,r0 /* Clear the PIT exception */
498 addi r3,r1,STACK_FRAME_OVERHEAD
499 EXC_XFER_LITE(0x1000, timer_interrupt)
501 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
504 addi r3,r1,STACK_FRAME_OVERHEAD;
505 EXC_XFER_STD(0x1010, unknown_exception)
507 /* Watchdog Timer (WDT) Exception. (from 0x1020) */
509 CRITICAL_EXCEPTION_PROLOG;
510 addi r3,r1,STACK_FRAME_OVERHEAD;
511 EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2,
512 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)),
513 crit_transfer_to_handler, ret_from_crit_exc)
515 /* Other PowerPC processors, namely those derived from the 6xx-series
516 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
517 * However, for the 4xx-series processors these are neither defined nor
521 /* Damn, I came up one instruction too many to fit into the
522 * exception space :-). Both the instruction and data TLB
523 * miss get to this point to load the TLB.
524 * r10 - TLB_TAG value
526 * r9 - available to use
527 * PID - loaded with proper value when we get here
528 * Upon exit, we reload everything and RFI.
529 * Actually, it will fit now, but oh well.....a common place
536 * Clear out the software-only bits in the PTE to generate the
537 * TLB_DATA value. These are the bottom 2 bits of the RPM, the
538 * top 3 bits of the zone field, and M.
543 /* load the next available TLB index. */
544 lwz r9, tlb_4xx_index@l(0)
546 andi. r9, r9, PPC40X_TLB_SIZE - 1
547 stw r9, tlb_4xx_index@l(0)
549 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
550 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
552 /* Done...restore registers and get out of here.
554 mfspr r9, SPRN_SPRG_SCRATCH5
557 mfspr r9, SPRN_SPRG_SCRATCH4
558 mfspr r12, SPRN_SPRG_SCRATCH3
559 mfspr r11, SPRN_SPRG_SCRATCH1
560 mfspr r10, SPRN_SPRG_SCRATCH0
561 rfi /* Should sync shadow TLBs */
562 b . /* prevent prefetch past rfi */
564 /* This is where the main kernel code starts.
570 ori r2,r2,init_task@l
572 /* ptr to phys current thread */
574 addi r4,r4,THREAD /* init task's THREAD */
575 mtspr SPRN_SPRG_THREAD,r4
578 lis r1,init_thread_union@ha
579 addi r1,r1,init_thread_union@l
581 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
583 bl early_init /* We have to do this with MMU on */
586 * Decide what sort of machine this is and initialize the MMU.
596 /* Go back to running unmapped so we can load up new values
597 * and change to using our exception vectors.
598 * On the 4xx, all we have to do is invalidate the TLB to clear
599 * the old 16M byte TLB mappings.
604 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
605 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
609 b . /* prevent prefetch past rfi */
611 /* Load up the kernel context */
613 sync /* Flush to memory before changing TLB */
615 isync /* Flush shadow TLBs */
617 /* set up the PTE pointers for the Abatron bdiGDB.
619 lis r6, swapper_pg_dir@h
620 ori r6, r6, swapper_pg_dir@l
621 lis r5, abatron_pteptrs@h
622 ori r5, r5, abatron_pteptrs@l
623 stw r5, 0xf0(r0) /* Must match your Abatron config file */
627 /* Now turn on the MMU for real! */
629 ori r4,r4,MSR_KERNEL@l
630 lis r3,start_kernel@h
631 ori r3,r3,start_kernel@l
634 rfi /* enable MMU and jump to start_kernel */
635 b . /* prevent prefetch past rfi */
637 /* Set up the initial MMU state so we can do the first level of
638 * kernel initialization. This maps the first 16 MBytes of memory 1:1
639 * virtual to physical and more importantly sets the cache mode.
642 tlbia /* Invalidate all TLB entries */
645 /* We should still be executing code at physical address 0x0000xxxx
646 * at this point. However, start_here is at virtual address
647 * 0xC000xxxx. So, set up a TLB mapping to cover this once
648 * translation is enabled.
651 lis r3,KERNELBASE@h /* Load the kernel virtual address */
652 ori r3,r3,KERNELBASE@l
653 tophys(r4,r3) /* Load the kernel physical address */
655 iccci r0,r3 /* Invalidate the i-cache before use */
657 /* Load the kernel PID.
663 /* Configure and load one entry into TLB slots 63 */
664 clrrwi r4,r4,10 /* Mask off the real page number */
665 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
667 clrrwi r3,r3,10 /* Mask off the effective page number */
668 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
670 li r0,63 /* TLB slot 63 */
672 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
673 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
677 /* Establish the exception vector base
679 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */
680 tophys(r0,r4) /* Use the physical address */
687 oris r13,r13,DBCR0_RST_SYSTEM@h
692 #ifdef CONFIG_BDI_SWITCH
693 /* Context switch the PTE pointer for the Abatron BDI2000.
694 * The PGDIR is the second parameter.
696 lis r5, abatron_pteptrs@ha
697 stw r4, abatron_pteptrs@l + 0x4(r5)
701 isync /* Need an isync to flush shadow */
702 /* TLBs after changing PID */
705 /* We put a few things here that have to be page-aligned. This stuff
706 * goes at the beginning of the data segment, which is page-aligned.
712 .globl empty_zero_page
715 EXPORT_SYMBOL(empty_zero_page)
716 .globl swapper_pg_dir
718 .space PGD_TABLE_SIZE
720 /* Room for two PTE pointers, usually the kernel and current user pointers
721 * to their respective root page table.