1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
25 * Following are fixed section helper macros.
27 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors
28 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors
29 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these)
30 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use)
31 * EXC_COMMON - After switching to virtual, relocated mode.
34 #define EXC_REAL_BEGIN(name, start, size) \
35 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
37 #define EXC_REAL_END(name, start, size) \
38 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
40 #define EXC_VIRT_BEGIN(name, start, size) \
41 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
43 #define EXC_VIRT_END(name, start, size) \
44 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
46 #define EXC_COMMON_BEGIN(name) \
48 .balign IFETCH_ALIGN_BYTES; \
50 _ASM_NOKPROBE_SYMBOL(name); \
51 DEFINE_FIXED_SYMBOL(name); \
54 #define TRAMP_REAL_BEGIN(name) \
55 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
57 #define TRAMP_VIRT_BEGIN(name) \
58 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
60 #define EXC_REAL_NONE(start, size) \
61 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
62 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
64 #define EXC_VIRT_NONE(start, size) \
65 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
66 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
69 * We're short on space and time in the exception prolog, so we can't
70 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
71 * Instead we get the base of the kernel from paca->kernelbase and or in the low
72 * part of label. This requires that the label be within 64KB of kernelbase, and
73 * that kernelbase be 64K aligned.
75 #define LOAD_HANDLER(reg, label) \
76 ld reg,PACAKBASE(r13); /* get high part of &label */ \
77 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
79 #define __LOAD_HANDLER(reg, label) \
80 ld reg,PACAKBASE(r13); \
81 ori reg,reg,(ABS_ADDR(label))@l
84 * Branches from unrelocated code (e.g., interrupts) to labels outside
85 * head-y require >64K offsets.
87 #define __LOAD_FAR_HANDLER(reg, label) \
88 ld reg,PACAKBASE(r13); \
89 ori reg,reg,(ABS_ADDR(label))@l; \
90 addis reg,reg,(ABS_ADDR(label))@h
93 * Branch to label using its 0xC000 address. This results in instruction
94 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
95 * on using mtmsr rather than rfid.
97 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
98 * load KBASE for a slight optimisation.
100 #define BRANCH_TO_C000(reg, label) \
101 __LOAD_FAR_HANDLER(reg, label); \
106 * Interrupt code generation macros
108 #define IVEC .L_IVEC_\name\() /* Interrupt vector address */
109 #define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */
110 #define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */
111 #define IAREA .L_IAREA_\name\() /* PACA save area */
112 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */
113 #define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */
114 #define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */
115 #define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */
116 #define ISET_RI .L_ISET_RI_\name\() /* Run common code w/ MSR[RI]=1 */
117 #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */
118 #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */
119 #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */
120 #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */
121 #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name
122 #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */
123 #define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */
124 #define __ISTACK(name) .L_ISTACK_ ## name
125 #define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */
127 #define INT_DEFINE_BEGIN(n) \
128 .macro int_define_ ## n name
130 #define INT_DEFINE_END(n) \
132 int_define_ ## n n ; \
135 .macro do_define_int name
137 .error "IVEC not defined"
142 .ifndef IHSRR_IF_HVMODE
163 .ifndef IBRANCH_TO_COMMON
166 .ifndef IREALMODE_COMMON
169 .if ! IBRANCH_TO_COMMON
170 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
191 * All interrupts which set HSRR registers, as well as SRESET and MCE and
192 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken,
193 * so they all generally need to test whether they were taken in guest context.
195 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be
196 * taken with MSR[HV]=0.
198 * Interrupts which set SRR registers (with the above exceptions) do not
199 * elevate to MSR[HV]=1 mode, though most can be taken when running with
200 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do
201 * not need to test whether a guest is running because they get delivered to
202 * the guest directly, including nested HV KVM guests.
204 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host
205 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
206 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
207 * delivered to the real-mode entry point, therefore such interrupts only test
208 * KVM in their real mode handlers, and only when PR KVM is possible.
210 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
211 * delivered in real-mode when the MMU is in hash mode because the MMU
212 * registers are not set appropriately to translate host addresses. In nested
213 * radix mode these can be delivered in virt-mode as the host translations are
214 * used implicitly (see: effective LPID, effective PID).
218 * If an interrupt is taken while a guest is running, it is immediately routed
222 .macro KVMTEST name handler
223 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
224 lbz r10,HSTATE_IN_GUEST(r13)
226 /* HSRR variants have the 0x2 bit added to their trap number */
232 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
243 * This is the BOOK3S interrupt entry code macro.
245 * This can result in one of several things happening:
246 * - Branch to the _common handler, relocated, in virtual mode.
247 * These are normal interrupts (synchronous and asynchronous) handled by
249 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
250 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
251 * / intended for host or guest kernel, but KVM must always be involved
252 * because the machine state is set for guest execution.
253 * - Branch to the masked handler, unrelocated.
254 * These occur when maskable asynchronous interrupts are taken with the
256 * - Branch to an "early" handler in real mode but relocated.
257 * This is done if early=1. MCE and HMI use these to handle errors in real
259 * - Fall through and continue executing in real, unrelocated mode.
260 * This is done if early=2.
263 .macro GEN_BRANCH_TO_COMMON name, virt
265 LOAD_HANDLER(r10, \name\()_common)
270 #ifndef CONFIG_RELOCATABLE
271 b \name\()_common_virt
273 LOAD_HANDLER(r10, \name\()_common_virt)
278 LOAD_HANDLER(r10, \name\()_common_real)
285 .macro GEN_INT_ENTRY name, virt, ool=0
286 SET_SCRATCH0(r13) /* save r13 */
288 std r9,IAREA+EX_R9(r13) /* save r9 */
291 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
293 std r10,IAREA+EX_R10(r13) /* save r10 - r12 */
296 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
301 TRAMP_REAL_BEGIN(tramp_real_\name)
305 TRAMP_VIRT_BEGIN(tramp_virt_\name)
310 std r9,IAREA+EX_PPR(r13)
311 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
313 std r10,IAREA+EX_CFAR(r13)
314 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
317 std r10,IAREA+EX_CTR(r13)
319 std r11,IAREA+EX_R11(r13)
320 std r12,IAREA+EX_R12(r13)
323 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
324 * because a d-side MCE will clobber those registers so is
325 * not recoverable if they are live.
328 std r10,IAREA+EX_R13(r13)
335 std r10,IAREA+EX_DAR(r13)
337 .if IDSISR && !IISIDE
339 mfspr r10,SPRN_HDSISR
343 stw r10,IAREA+EX_DSISR(r13)
348 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
349 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
351 mfspr r11,SPRN_SRR0 /* save SRR0 */
352 mfspr r12,SPRN_SRR1 /* and SRR1 */
353 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
355 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
356 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
358 mfspr r11,SPRN_SRR0 /* save SRR0 */
359 mfspr r12,SPRN_SRR1 /* and SRR1 */
362 .if IBRANCH_TO_COMMON
363 GEN_BRANCH_TO_COMMON \name \virt
372 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt
373 * entry, except in the case of the real-mode handlers which require
374 * __GEN_REALMODE_COMMON_ENTRY.
376 * This switches to virtual mode and sets MSR[RI].
378 .macro __GEN_COMMON_ENTRY name
379 DEFINE_FIXED_SYMBOL(\name\()_common_real)
380 \name\()_common_real:
382 KVMTEST \name kvm_interrupt
385 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
386 /* MSR[RI] is clear iff using SRR regs */
390 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
398 b 1f /* skip the virt test coming from real */
401 .balign IFETCH_ALIGN_BYTES
402 DEFINE_FIXED_SYMBOL(\name\()_common_virt)
403 \name\()_common_virt:
405 KVMTEST \name kvm_interrupt
412 * Don't switch to virt mode. Used for early MCE and HMI handlers that
413 * want to run in real mode.
415 .macro __GEN_REALMODE_COMMON_ENTRY name
416 DEFINE_FIXED_SYMBOL(\name\()_common_real)
417 \name\()_common_real:
419 KVMTEST \name kvm_interrupt
423 .macro __GEN_COMMON_BODY name
426 .error "No support for masked interrupt to use custom stack"
429 /* If coming from user, skip soft-mask tests. */
434 * Kernel code running below __end_soft_masked may be
435 * implicitly soft-masked if it is within the regions
436 * in the soft mask table.
438 LOAD_HANDLER(r10, __end_soft_masked)
442 /* SEARCH_SOFT_MASK_TABLE clobbers r9,r10,r12 */
444 stw r9,PACA_EXGEN+EX_CCR(r13)
445 SEARCH_SOFT_MASK_TABLE
447 mfctr r12 /* Restore r12 to SRR1 */
448 lwz r9,PACA_EXGEN+EX_CCR(r13)
449 beq 1f /* Not in soft-mask table */
451 b 2f /* In soft-mask table, always mask */
453 /* Test the soft mask state against our interrupt's bit */
454 1: lbz r10,PACAIRQSOFTMASK(r13)
455 2: andi. r10,r10,IMASK
456 /* Associate vector numbers with bits in paca->irq_happened */
457 .if IVEC == 0x500 || IVEC == 0xea0
459 .elseif IVEC == 0x900
461 .elseif IVEC == 0xa00 || IVEC == 0xe80
462 li r10,PACA_IRQ_DBELL
463 .elseif IVEC == 0xe60
465 .elseif IVEC == 0xf00
468 .abort "Bad maskable vector"
473 bne masked_Hinterrupt
476 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
478 bne masked_Hinterrupt
485 andi. r10,r12,MSR_PR /* See if coming from user */
486 3: mr r10,r1 /* Save r1 */
487 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */
489 ld r1,PACAKSAVE(r13) /* kernel stack to use */
490 100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */
491 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
494 std r9,_CCR(r1) /* save CR in stackframe */
495 std r11,_NIP(r1) /* save SRR0 in stackframe */
496 std r12,_MSR(r1) /* save SRR1 in stackframe */
497 std r10,0(r1) /* make stack chain pointer */
498 std r0,GPR0(r1) /* save r0 in stackframe */
499 std r10,GPR1(r1) /* save r1 in stackframe */
501 /* Mark our [H]SRRs valid for return */
505 stb r10,PACAHSRR_VALID(r13)
507 stb r10,PACASRR_VALID(r13)
508 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
510 stb r10,PACAHSRR_VALID(r13)
512 stb r10,PACASRR_VALID(r13)
517 mtmsrd r10,1 /* Set MSR_RI */
522 kuap_save_amr_and_lock r9, r10, cr1, cr0
524 beq 101f /* if from kernel mode */
526 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */
528 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
532 kuap_save_amr_and_lock r9, r10, cr1
536 /* Save original regs values from save area to stack frame. */
537 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */
538 ld r10,IAREA+EX_R10(r13)
541 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */
542 ld r10,IAREA+EX_R12(r13)
543 ld r11,IAREA+EX_R13(r13)
554 ld r10,IAREA+EX_DAR(r13)
562 lis r11,DSISR_SRR1_MATCH_64S@h
565 lwz r10,IAREA+EX_DSISR(r13)
571 ld r10,IAREA+EX_CFAR(r13)
572 std r10,ORIG_GPR3(r1)
573 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
574 ld r10,IAREA+EX_CTR(r13)
576 std r2,GPR2(r1) /* save r2 in stackframe */
577 SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */
578 SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */
579 mflr r9 /* Get LR, later save to stack */
580 ld r2,PACATOC(r13) /* get kernel TOC into r2 */
582 lbz r10,PACAIRQSOFTMASK(r13)
583 mfspr r11,SPRN_XER /* save XER in stackframe */
587 std r9,_TRAP(r1) /* set trap number */
589 ld r11,exception_marker@toc(r2)
590 std r10,RESULT(r1) /* clear regs->result */
591 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */
595 * On entry r13 points to the paca, r9-r13 are saved in the paca,
596 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
597 * SRR1, and relocation is on.
599 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
600 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
602 .macro GEN_COMMON name
603 __GEN_COMMON_ENTRY \name
604 __GEN_COMMON_BODY \name
607 .macro SEARCH_RESTART_TABLE
608 #ifdef CONFIG_RELOCATABLE
611 LOAD_REG_ADDR(r9, __start___restart_table)
612 LOAD_REG_ADDR(r10, __stop___restart_table)
615 LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___restart_table)
616 LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___restart_table)
637 .macro SEARCH_SOFT_MASK_TABLE
638 #ifdef CONFIG_RELOCATABLE
641 LOAD_REG_ADDR(r9, __start___soft_mask_table)
642 LOAD_REG_ADDR(r10, __stop___soft_mask_table)
645 LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___soft_mask_table)
646 LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___soft_mask_table)
668 * Restore all registers including H/SRR0/1 saved in a stack frame of a
669 * standard exception.
671 .macro EXCEPTION_RESTORE_REGS hsrr=0
672 /* Move original SRR0 and SRR1 into the respective regs */
677 stb r10,PACAHSRR_VALID(r13)
680 stb r10,PACASRR_VALID(r13)
699 /* restore original r1. */
704 * There are a few constraints to be concerned with.
705 * - Real mode exceptions code/data must be located at their physical location.
706 * - Virtual mode exceptions must be mapped at their 0xc000... location.
707 * - Fixed location code must not call directly beyond the __end_interrupts
708 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
710 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
712 * - Conditional branch targets must be within +/-32K of caller.
714 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
715 * therefore don't have to run in physically located code or rfid to
716 * virtual mode kernel code. However on relocatable kernels they do have
717 * to branch to KERNELBASE offset because the rest of the kernel (outside
718 * the exception vectors) may be located elsewhere.
720 * Virtual exceptions correspond with physical, except their entry points
721 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
722 * offset applied. Virtual exceptions are enabled with the Alternate
723 * Interrupt Location (AIL) bit set in the LPCR. However this does not
724 * guarantee they will be delivered virtually. Some conditions (see the ISA)
725 * cause exceptions to be delivered in real mode.
727 * The scv instructions are a special case. They get a 0x3000 offset applied.
728 * scv exceptions have unique reentrancy properties, see below.
730 * It's impossible to receive interrupts below 0x300 via AIL.
732 * KVM: None of the virtual exceptions are from the guest. Anything that
733 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
736 * We layout physical memory as follows:
737 * 0x0000 - 0x00ff : Secondary processor spin code
738 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
739 * 0x1900 - 0x2fff : Real mode trampolines
740 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
741 * 0x5900 - 0x6fff : Relon mode trampolines
742 * 0x7000 - 0x7fff : FWNMI data area
743 * 0x8000 - .... : Common interrupt handlers, remaining early
744 * setup code, rest of kernel.
746 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
747 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
750 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
751 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
752 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
753 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
755 #ifdef CONFIG_PPC_POWERNV
756 .globl start_real_trampolines
757 .globl end_real_trampolines
758 .globl start_virt_trampolines
759 .globl end_virt_trampolines
762 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
764 * Data area reserved for FWNMI option.
765 * This address (0x7000) is fixed by the RPA.
766 * pseries and powernv need to keep the whole page from
767 * 0x7000 to 0x8000 free for use by the firmware
769 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
770 OPEN_TEXT_SECTION(0x8000)
772 OPEN_TEXT_SECTION(0x7000)
775 USE_FIXED_SECTION(real_vectors)
778 * This is the start of the interrupt handlers for pSeries
779 * This code runs with relocation off.
780 * Code from here to __end_interrupts gets copied down to real
781 * address 0x100 when we are running a relocatable kernel.
782 * Therefore any relative branches in this section must only
783 * branch to labels in this section.
785 .globl __start_interrupts
789 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
790 * This is a synchronous interrupt invoked with the "scv" instruction. The
791 * system call does not alter the HV bit, so it is directed to the OS.
794 * scv instructions enter the kernel without changing EE, RI, ME, or HV.
795 * In particular, this means we can take a maskable interrupt at any point
796 * in the scv handler, which is unlike any other interrupt. This is solved
797 * by treating the instruction addresses in the handler as being soft-masked,
798 * by adding a SOFT_MASK_TABLE entry for them.
800 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
801 * ensure scv is never executed with relocation off, which means AIL-0
802 * should never happen.
804 * Before leaving the following inside-__end_soft_masked text, at least of the
805 * following must be true:
806 * - MSR[PR]=1 (i.e., return to userspace)
807 * - MSR_EE|MSR_RI is clear (no reentrant exceptions)
808 * - Standard kernel environment is set up (stack, paca, etc)
812 * syscall register convention is in Documentation/powerpc/syscall64-abi.rst
814 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
820 li r10,IRQS_ALL_DISABLED
821 stb r10,PACAIRQSOFTMASK(r13)
822 #ifdef CONFIG_RELOCATABLE
823 b system_call_vectored_tramp
825 b system_call_vectored_common
835 li r10,IRQS_ALL_DISABLED
836 stb r10,PACAIRQSOFTMASK(r13)
837 li r0,-1 /* cause failure */
838 #ifdef CONFIG_RELOCATABLE
839 b system_call_vectored_sigill_tramp
841 b system_call_vectored_sigill
844 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
846 // Treat scv vectors as soft-masked, see comment above.
847 // Use absolute values rather than labels here, so they don't get relocated,
848 // because this code runs unrelocated.
849 SOFT_MASK_TABLE(0xc000000000003000, 0xc000000000004000)
851 #ifdef CONFIG_RELOCATABLE
852 TRAMP_VIRT_BEGIN(system_call_vectored_tramp)
853 __LOAD_HANDLER(r10, system_call_vectored_common)
857 TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp)
858 __LOAD_HANDLER(r10, system_call_vectored_sigill)
864 /* No virt vectors corresponding with 0x0..0x100 */
865 EXC_VIRT_NONE(0x4000, 0x100)
869 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
870 * This is a non-maskable, asynchronous interrupt always taken in real-mode.
872 * - Wake from power-saving state, on powernv.
873 * - An NMI from another CPU, triggered by firmware or hypercall.
874 * - As crash/debug signal injected from BMC, firmware or hypervisor.
877 * Power-save wakeup is the only performance critical path, so this is
878 * determined quickly as possible first. In this case volatile registers
879 * can be discarded and SPRs like CFAR don't need to be read.
881 * If not a powersave wakeup, then it's run as a regular interrupt, however
882 * it uses its own stack and PACA save area to preserve the regular kernel
883 * environment for debugging.
885 * This interrupt is not maskable, so triggering it when MSR[RI] is clear,
886 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely
887 * correct to switch to virtual mode to run the regular interrupt handler
888 * because it might be interrupted when the MMU is in a bad state (e.g., SLB
892 * PAPR specifies a "fwnmi" facility which sends the sreset to a different
893 * entry point with a different register set up. Some hypervisors will
894 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
897 * Unlike most SRR interrupts, this may be taken by the host while executing
898 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest
899 * mode and then raise the sreset.
901 INT_DEFINE_BEGIN(system_reset)
904 IVIRT=0 /* no virt entry point */
906 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
907 * being used, so a nested NMI exception would corrupt it.
912 INT_DEFINE_END(system_reset)
914 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
915 #ifdef CONFIG_PPC_P7_NAP
917 * If running native on arch 2.06 or later, check if we are waking up
918 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
919 * bits 46:47. A non-0 value indicates that we are coming from a power
920 * saving state. The idle wakeup handler initially runs in real mode,
921 * but we branch to the 0xc000... address so we can turn on relocation
922 * with mtmsrd later, after SPRs are restored.
924 * Careful to minimise cost for the fast path (idle wakeup) while
925 * also avoiding clobbering CFAR for the debug path (non-idle).
927 * For the idle wake case volatile registers can be clobbered, which
928 * is why we use those initially. If it turns out to not be an idle
929 * wake, carefully put everything back the way it was, so we can use
930 * common exception macros to handle it.
935 std r3,PACA_EXNMI+0*8(r13)
936 std r4,PACA_EXNMI+1*8(r13)
937 std r5,PACA_EXNMI+2*8(r13)
940 rlwinm. r5,r3,47-31,30,31
941 bne+ system_reset_idle_wake
942 /* Not powersave wakeup. Restore regs for regular interrupt handler. */
944 ld r3,PACA_EXNMI+0*8(r13)
945 ld r4,PACA_EXNMI+1*8(r13)
946 ld r5,PACA_EXNMI+2*8(r13)
948 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
951 GEN_INT_ENTRY system_reset, virt=0
953 * In theory, we should not enable relocation here if it was disabled
954 * in SRR1, because the MMU may not be configured to support it (e.g.,
955 * SLB may have been cleared). In practice, there should only be a few
956 * small windows where that's the case, and sreset is considered to
957 * be dangerous anyway.
959 EXC_REAL_END(system_reset, 0x100, 0x100)
960 EXC_VIRT_NONE(0x4100, 0x100)
962 #ifdef CONFIG_PPC_P7_NAP
963 TRAMP_REAL_BEGIN(system_reset_idle_wake)
964 /* We are waking up from idle, so may clobber any volatile register */
966 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
967 BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss))
970 #ifdef CONFIG_PPC_PSERIES
972 * Vectors for the FWNMI option. Share common code.
974 TRAMP_REAL_BEGIN(system_reset_fwnmi)
975 GEN_INT_ENTRY system_reset, virt=0
977 #endif /* CONFIG_PPC_PSERIES */
979 EXC_COMMON_BEGIN(system_reset_common)
980 __GEN_COMMON_ENTRY system_reset
982 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
983 * to recover, but nested NMI will notice in_nmi and not recover
984 * because of the use of the NMI stack. in_nmi reentrancy is tested in
985 * system_reset_exception.
987 lhz r10,PACA_IN_NMI(r13)
989 sth r10,PACA_IN_NMI(r13)
994 ld r1,PACA_NMI_EMERG_SP(r13)
995 subi r1,r1,INT_FRAME_SIZE
996 __GEN_COMMON_BODY system_reset
998 addi r3,r1,STACK_FRAME_OVERHEAD
999 bl system_reset_exception
1001 /* Clear MSR_RI before setting SRR0 and SRR1. */
1006 * MSR_RI is clear, now we can decrement paca->in_nmi.
1008 lhz r10,PACA_IN_NMI(r13)
1010 sth r10,PACA_IN_NMI(r13)
1012 kuap_kernel_restore r9, r10
1013 EXCEPTION_RESTORE_REGS
1014 RFI_TO_USER_OR_KERNEL
1018 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1019 * This is a non-maskable interrupt always taken in real-mode. It can be
1020 * synchronous or asynchronous, caused by hardware or software, and it may be
1021 * taken in a power-saving state.
1024 * Similarly to system reset, this uses its own stack and PACA save area,
1025 * the difference is re-entrancy is allowed on the machine check stack.
1027 * machine_check_early is run in real mode, and carefully decodes the
1028 * machine check and tries to handle it (e.g., flush the SLB if there was an
1029 * error detected there), determines if it was recoverable and logs the
1032 * This early code does not "reconcile" irq soft-mask state like SRESET or
1033 * regular interrupts do, so irqs_disabled() among other things may not work
1034 * properly (irq disable/enable already doesn't work because irq tracing can
1035 * not work in real mode).
1037 * Then, depending on the execution context when the interrupt is taken, there
1038 * are 3 main actions:
1039 * - Executing in kernel mode. The event is queued with irq_work, which means
1040 * it is handled when it is next safe to do so (i.e., the kernel has enabled
1041 * interrupts), which could be immediately when the interrupt returns. This
1042 * avoids nasty issues like switching to virtual mode when the MMU is in a
1043 * bad state, or when executing OPAL code. (SRESET is exposed to such issues,
1044 * but it has different priorities). Check to see if the CPU was in power
1045 * save, and return via the wake up code if it was.
1047 * - Executing in user mode. machine_check_exception is run like a normal
1048 * interrupt handler, which processes the data generated by the early handler.
1050 * - Executing in guest mode. The interrupt is run with its KVM test, and
1051 * branches to KVM to deal with. KVM may queue the event for the host
1054 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear,
1055 * or SCRATCH0 is in use, it may cause a crash.
1060 INT_DEFINE_BEGIN(machine_check_early)
1063 IVIRT=0 /* no virt entry point */
1066 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
1067 * nested machine check corrupts it. machine_check_common enables
1074 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1075 INT_DEFINE_END(machine_check_early)
1077 INT_DEFINE_BEGIN(machine_check)
1080 IVIRT=0 /* no virt entry point */
1085 INT_DEFINE_END(machine_check)
1087 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1088 GEN_INT_ENTRY machine_check_early, virt=0
1089 EXC_REAL_END(machine_check, 0x200, 0x100)
1090 EXC_VIRT_NONE(0x4200, 0x100)
1092 #ifdef CONFIG_PPC_PSERIES
1093 TRAMP_REAL_BEGIN(machine_check_fwnmi)
1094 /* See comment at machine_check exception, don't turn on RI */
1095 GEN_INT_ENTRY machine_check_early, virt=0
1098 #define MACHINE_CHECK_HANDLER_WINDUP \
1099 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1101 mtmsrd r9,1; /* Clear MSR_RI */ \
1102 /* Decrement paca->in_mce now RI is clear. */ \
1103 lhz r12,PACA_IN_MCE(r13); \
1105 sth r12,PACA_IN_MCE(r13); \
1106 EXCEPTION_RESTORE_REGS
1108 EXC_COMMON_BEGIN(machine_check_early_common)
1109 __GEN_REALMODE_COMMON_ENTRY machine_check_early
1112 * Switch to mc_emergency stack and handle re-entrancy (we limit
1113 * the nested MCE upto level 4 to avoid stack overflow).
1114 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
1116 * We use paca->in_mce to check whether this is the first entry or
1117 * nested machine check. We increment paca->in_mce to track nested
1120 * If this is the first entry then set stack pointer to
1121 * paca->mc_emergency_sp, otherwise r1 is already pointing to
1122 * stack frame on mc_emergency stack.
1124 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1125 * checkstop if we get another machine check exception before we do
1126 * rfid with MSR_ME=1.
1128 * This interrupt can wake directly from idle. If that is the case,
1129 * the machine check is handled then the idle wakeup code is called
1132 lhz r10,PACA_IN_MCE(r13)
1133 cmpwi r10,0 /* Are we in nested machine check */
1134 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */
1135 addi r10,r10,1 /* increment paca->in_mce */
1136 sth r10,PACA_IN_MCE(r13)
1138 mr r10,r1 /* Save r1 */
1140 /* First machine check entry */
1141 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
1142 1: /* Limit nested MCE to level 4 to avoid stack overflow */
1143 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
1144 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1146 __GEN_COMMON_BODY machine_check_early
1149 bl enable_machine_check
1150 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1154 addi r3,r1,STACK_FRAME_OVERHEAD
1155 bl machine_check_early
1156 std r3,RESULT(r1) /* Save result */
1159 #ifdef CONFIG_PPC_P7_NAP
1161 * Check if thread was in power saving mode. We come here when any
1162 * of the following is true:
1163 * a. thread wasn't in power saving mode
1164 * b. thread was in power saving mode with no state loss,
1165 * supervisor state loss or hypervisor state loss.
1167 * Go back to nap/sleep/winkle mode again if (b) is true.
1170 rlwinm. r11,r12,47-31,30,31
1171 bne machine_check_idle_common
1172 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1175 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1177 * Check if we are coming from guest. If yes, then run the normal
1178 * exception handler which will take the
1179 * machine_check_kvm->kvm_interrupt branch to deliver the MC event
1182 lbz r11,HSTATE_IN_GUEST(r13)
1183 cmpwi r11,0 /* Check if coming from guest */
1184 bne mce_deliver /* continue if we are. */
1188 * Check if we are coming from userspace. If yes, then run the normal
1189 * exception handler which will deliver the MC event to this kernel.
1191 andi. r11,r12,MSR_PR /* See if coming from user. */
1192 bne mce_deliver /* continue in V mode if we are. */
1195 * At this point we are coming from kernel context.
1196 * Queue up the MCE event and return from the interrupt.
1197 * But before that, check if this is an un-recoverable exception.
1198 * If yes, then stay on emergency stack and panic.
1200 andi. r11,r12,MSR_RI
1201 beq unrecoverable_mce
1204 * Check if we have successfully handled/recovered from error, if not
1205 * then stay on emergency stack and panic.
1207 ld r3,RESULT(r1) /* Load result */
1208 cmpdi r3,0 /* see if we handled MCE successfully */
1209 beq unrecoverable_mce /* if !handled then panic */
1212 * Return from MC interrupt.
1213 * Queue up the MCE event so that we can log it later, while
1214 * returning from kernel or opal call.
1216 bl machine_check_queue_event
1217 MACHINE_CHECK_HANDLER_WINDUP
1222 * This is a host user or guest MCE. Restore all registers, then
1223 * run the "late" handler. For host user, this will run the
1224 * machine_check_exception handler in virtual mode like a normal
1225 * interrupt handler. For guest, this will trigger the KVM test
1226 * and branch to the KVM interrupt similarly to other interrupts.
1229 ld r10,ORIG_GPR3(r1)
1231 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1232 MACHINE_CHECK_HANDLER_WINDUP
1233 GEN_INT_ENTRY machine_check, virt=0
1235 EXC_COMMON_BEGIN(machine_check_common)
1237 * Machine check is different because we use a different
1238 * save area: PACA_EXMC instead of PACA_EXGEN.
1240 GEN_COMMON machine_check
1242 /* Enable MSR_RI when finished with PACA_EXMC */
1245 addi r3,r1,STACK_FRAME_OVERHEAD
1246 bl machine_check_exception
1247 b interrupt_return_srr
1250 #ifdef CONFIG_PPC_P7_NAP
1252 * This is an idle wakeup. Low level machine check has already been
1253 * done. Queue the event then call the idle code to do the wake up.
1255 EXC_COMMON_BEGIN(machine_check_idle_common)
1256 bl machine_check_queue_event
1259 * GPR-loss wakeups are relatively straightforward, because the
1260 * idle sleep code has saved all non-volatile registers on its
1261 * own stack, and r1 in PACAR1.
1263 * For no-loss wakeups the r1 and lr registers used by the
1264 * early machine check handler have to be restored first. r2 is
1265 * the kernel TOC, so no need to restore it.
1267 * Then decrement MCE nesting after finishing with the stack.
1273 lhz r11,PACA_IN_MCE(r13)
1275 sth r11,PACA_IN_MCE(r13)
1278 rlwinm r10,r3,47-31,30,31
1280 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1281 b idle_return_gpr_loss
1284 EXC_COMMON_BEGIN(unrecoverable_mce)
1286 * We are going down. But there are chances that we might get hit by
1287 * another MCE during panic path and we may run into unstable state
1288 * with no way out. Hence, turn ME bit off while going down, so that
1289 * when another MCE is hit during panic path, system will checkstop
1290 * and hypervisor will get restarted cleanly by SP.
1293 li r10,0 /* clear MSR_RI */
1295 bl disable_machine_check
1296 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1297 ld r10,PACAKMSR(r13)
1302 lhz r12,PACA_IN_MCE(r13)
1304 sth r12,PACA_IN_MCE(r13)
1306 /* Invoke machine_check_exception to print MCE event and panic. */
1307 addi r3,r1,STACK_FRAME_OVERHEAD
1308 bl machine_check_exception
1311 * We will not reach here. Even if we did, there is no way out.
1312 * Call unrecoverable_exception and die.
1314 addi r3,r1,STACK_FRAME_OVERHEAD
1315 bl unrecoverable_exception
1320 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1321 * This is a synchronous interrupt generated due to a data access exception,
1322 * e.g., a load orstore which does not have a valid page table entry with
1323 * permissions. DAWR matches also fault here, as do RC updates, and minor misc
1324 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc.
1328 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the
1329 * Linux page table. Hash faults can hit in kernel mode in a fairly
1330 * arbitrary state (e.g., interrupts disabled, locks held) when accessing
1331 * "non-bolted" regions, e.g., vmalloc space. However these should always be
1332 * backed by Linux page table entries.
1334 * If no entry is found the Linux page fault handler is invoked (by
1335 * do_hash_fault). Linux page faults can happen in kernel mode due to user
1336 * copy operations of course.
1338 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest
1339 * MMU context, which may cause a DSI in the host, which must go to the
1340 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will
1341 * always be used regardless of AIL setting.
1344 * The hardware loads from the Linux page table directly, so a fault goes
1345 * immediately to Linux page fault.
1347 * Conditions like DAWR match are handled on the way in to Linux page fault.
1349 INT_DEFINE_BEGIN(data_access)
1354 INT_DEFINE_END(data_access)
1356 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1357 GEN_INT_ENTRY data_access, virt=0
1358 EXC_REAL_END(data_access, 0x300, 0x80)
1359 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1360 GEN_INT_ENTRY data_access, virt=1
1361 EXC_VIRT_END(data_access, 0x4300, 0x80)
1362 EXC_COMMON_BEGIN(data_access_common)
1363 GEN_COMMON data_access
1365 addi r3,r1,STACK_FRAME_OVERHEAD
1366 andis. r0,r4,DSISR_DABRMATCH@h
1368 BEGIN_MMU_FTR_SECTION
1370 MMU_FTR_SECTION_ELSE
1372 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1373 b interrupt_return_srr
1377 * do_break() may have changed the NV GPRS while handling a breakpoint.
1378 * If so, we need to restore them with their updated values.
1381 b interrupt_return_srr
1385 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1386 * This is a synchronous interrupt in response to an MMU fault missing SLB
1387 * entry for HPT, or an address outside RPT translation range.
1391 * This refills the SLB, or reports an access fault similarly to a bad page
1392 * fault. When coming from user-mode, the SLB handler may access any kernel
1393 * data, though it may itself take a DSLB. When coming from kernel mode,
1394 * recursive faults must be avoided so access is restricted to the kernel
1395 * image text/data, kernel stack, and any data allocated below
1396 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping
1397 * on user-handler data structures.
1399 * KVM: Same as 0x300, DSLB must test for KVM guest.
1401 INT_DEFINE_BEGIN(data_access_slb)
1405 INT_DEFINE_END(data_access_slb)
1407 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1408 GEN_INT_ENTRY data_access_slb, virt=0
1409 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1410 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1411 GEN_INT_ENTRY data_access_slb, virt=1
1412 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1413 EXC_COMMON_BEGIN(data_access_slb_common)
1414 GEN_COMMON data_access_slb
1415 BEGIN_MMU_FTR_SECTION
1416 /* HPT case, do SLB fault */
1417 addi r3,r1,STACK_FRAME_OVERHEAD
1421 b fast_interrupt_return_srr
1423 MMU_FTR_SECTION_ELSE
1424 /* Radix case, access is outside page table range */
1426 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1428 addi r3,r1,STACK_FRAME_OVERHEAD
1430 b interrupt_return_srr
1434 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1435 * This is a synchronous interrupt in response to an MMU fault due to an
1436 * instruction fetch.
1439 * Similar to DSI, though in response to fetch. The faulting address is found
1440 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR).
1442 INT_DEFINE_BEGIN(instruction_access)
1447 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1450 INT_DEFINE_END(instruction_access)
1452 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1453 GEN_INT_ENTRY instruction_access, virt=0
1454 EXC_REAL_END(instruction_access, 0x400, 0x80)
1455 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1456 GEN_INT_ENTRY instruction_access, virt=1
1457 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1458 EXC_COMMON_BEGIN(instruction_access_common)
1459 GEN_COMMON instruction_access
1460 addi r3,r1,STACK_FRAME_OVERHEAD
1461 BEGIN_MMU_FTR_SECTION
1463 MMU_FTR_SECTION_ELSE
1465 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1466 b interrupt_return_srr
1470 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1471 * This is a synchronous interrupt in response to an MMU fault due to an
1472 * instruction fetch.
1475 * Similar to DSLB, though in response to fetch. The faulting address is found
1476 * in SRR0 (rather than DAR).
1478 INT_DEFINE_BEGIN(instruction_access_slb)
1482 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1485 INT_DEFINE_END(instruction_access_slb)
1487 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1488 GEN_INT_ENTRY instruction_access_slb, virt=0
1489 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1490 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1491 GEN_INT_ENTRY instruction_access_slb, virt=1
1492 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1493 EXC_COMMON_BEGIN(instruction_access_slb_common)
1494 GEN_COMMON instruction_access_slb
1495 BEGIN_MMU_FTR_SECTION
1496 /* HPT case, do SLB fault */
1497 addi r3,r1,STACK_FRAME_OVERHEAD
1501 b fast_interrupt_return_srr
1503 MMU_FTR_SECTION_ELSE
1504 /* Radix case, access is outside page table range */
1506 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1508 addi r3,r1,STACK_FRAME_OVERHEAD
1510 b interrupt_return_srr
1514 * Interrupt 0x500 - External Interrupt.
1515 * This is an asynchronous maskable interrupt in response to an "external
1516 * exception" from the interrupt controller or hypervisor (e.g., device
1517 * interrupt). It is maskable in hardware by clearing MSR[EE], and
1518 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()).
1520 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1521 * interrupts are delivered with HSRR registers, guests use SRRs, which
1522 * reqiures IHSRR_IF_HVMODE.
1524 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
1525 * external interrupts are delivered as Hypervisor Virtualization Interrupts
1526 * rather than External Interrupts.
1529 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead,
1530 * because registers at the time of the interrupt are not so important as it is
1533 * If soft masked, the masked handler will note the pending interrupt for
1534 * replay, and clear MSR[EE] in the interrupted context.
1536 INT_DEFINE_BEGIN(hardware_interrupt)
1542 INT_DEFINE_END(hardware_interrupt)
1544 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1545 GEN_INT_ENTRY hardware_interrupt, virt=0
1546 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1547 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1548 GEN_INT_ENTRY hardware_interrupt, virt=1
1549 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1550 EXC_COMMON_BEGIN(hardware_interrupt_common)
1551 GEN_COMMON hardware_interrupt
1552 addi r3,r1,STACK_FRAME_OVERHEAD
1555 b interrupt_return_hsrr
1557 b interrupt_return_srr
1558 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1562 * Interrupt 0x600 - Alignment Interrupt
1563 * This is a synchronous interrupt in response to data alignment fault.
1565 INT_DEFINE_BEGIN(alignment)
1569 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1572 INT_DEFINE_END(alignment)
1574 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1575 GEN_INT_ENTRY alignment, virt=0
1576 EXC_REAL_END(alignment, 0x600, 0x100)
1577 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1578 GEN_INT_ENTRY alignment, virt=1
1579 EXC_VIRT_END(alignment, 0x4600, 0x100)
1580 EXC_COMMON_BEGIN(alignment_common)
1581 GEN_COMMON alignment
1582 addi r3,r1,STACK_FRAME_OVERHEAD
1583 bl alignment_exception
1584 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1585 b interrupt_return_srr
1589 * Interrupt 0x700 - Program Interrupt (program check).
1590 * This is a synchronous interrupt in response to various instruction faults:
1591 * traps, privilege errors, TM errors, floating point exceptions.
1594 * This interrupt may use the "emergency stack" in some cases when being taken
1595 * from kernel context, which complicates handling.
1597 INT_DEFINE_BEGIN(program_check)
1599 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1602 INT_DEFINE_END(program_check)
1604 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1606 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1608 * There's a short window during boot where although the kernel is
1609 * running little endian, any exceptions will cause the CPU to switch
1610 * back to big endian. For example a WARN() boils down to a trap
1611 * instruction, which will cause a program check, and we end up here but
1612 * with the CPU in big endian mode. The first instruction of the program
1613 * check handler (in GEN_INT_ENTRY below) is an mtsprg, which when
1614 * executed in the wrong endian is an lhzu with a ~3GB displacement from
1615 * r3. The content of r3 is random, so that is a load from some random
1616 * location, and depending on the system can easily lead to a checkstop,
1617 * or an infinitely recursive page fault.
1619 * So to handle that case we have a trampoline here that can detect we
1620 * are in the wrong endian and flip us back to the correct endian. We
1621 * can't flip MSR[LE] using mtmsr, so we have to use rfid. That requires
1622 * backing up SRR0/1 as well as a GPR. To do that we use SPRG0/2/3, as
1623 * SPRG1 is already used for the paca. SPRG3 is user readable, but this
1624 * trampoline is only active very early in boot, and SPRG3 will be
1625 * reinitialised in vdso_getcpu_init() before userspace starts.
1628 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8
1629 b 1f // Skip trampoline if endian is correct
1630 .long 0xa643707d // mtsprg 0, r11 Backup r11
1631 .long 0xa6027a7d // mfsrr0 r11
1632 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2
1633 .long 0xa6027b7d // mfsrr1 r11
1634 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3
1635 .long 0xa600607d // mfmsr r11
1636 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE]
1637 .long 0xa6037b7d // mtsrr1 r11
1638 .long 0x34076039 // li r11, 0x734
1639 .long 0xa6037a7d // mtsrr0 r11
1640 .long 0x2400004c // rfid
1642 mtsrr1 r11 // Restore SRR1
1644 mtsrr0 r11 // Restore SRR0
1645 mfsprg r11, 0 // Restore r11
1647 END_FTR_SECTION(0, 1) // nop out after boot
1648 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1650 GEN_INT_ENTRY program_check, virt=0
1651 EXC_REAL_END(program_check, 0x700, 0x100)
1652 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1653 GEN_INT_ENTRY program_check, virt=1
1654 EXC_VIRT_END(program_check, 0x4700, 0x100)
1655 EXC_COMMON_BEGIN(program_check_common)
1656 __GEN_COMMON_ENTRY program_check
1659 * It's possible to receive a TM Bad Thing type program check with
1660 * userspace register values (in particular r1), but with SRR1 reporting
1661 * that we came from the kernel. Normally that would confuse the bad
1662 * stack logic, and we would report a bad kernel stack pointer. Instead
1663 * we switch to the emergency stack if we're taking a TM Bad Thing from
1667 andi. r10,r12,MSR_PR
1668 bne 2f /* If userspace, go normal path */
1670 andis. r10,r12,(SRR1_PROGTM)@h
1671 bne 1f /* If TM, emergency */
1673 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */
1674 blt 2f /* normal path if not */
1676 /* Use the emergency stack */
1677 1: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */
1678 /* 3 in EXCEPTION_PROLOG_COMMON */
1679 mr r10,r1 /* Save r1 */
1680 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1681 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1682 __ISTACK(program_check)=0
1683 __GEN_COMMON_BODY program_check
1686 __ISTACK(program_check)=1
1687 __GEN_COMMON_BODY program_check
1689 addi r3,r1,STACK_FRAME_OVERHEAD
1690 bl program_check_exception
1691 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1692 b interrupt_return_srr
1696 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1697 * This is a synchronous interrupt in response to executing an fp instruction
1701 * This will load FP registers and enable the FP bit if coming from userspace,
1702 * otherwise report a bad kernel use of FP.
1704 INT_DEFINE_BEGIN(fp_unavailable)
1706 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1709 INT_DEFINE_END(fp_unavailable)
1711 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1712 GEN_INT_ENTRY fp_unavailable, virt=0
1713 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1714 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1715 GEN_INT_ENTRY fp_unavailable, virt=1
1716 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1717 EXC_COMMON_BEGIN(fp_unavailable_common)
1718 GEN_COMMON fp_unavailable
1719 bne 1f /* if from user, just load it up */
1720 addi r3,r1,STACK_FRAME_OVERHEAD
1721 bl kernel_fp_unavailable_exception
1723 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1725 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1727 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1728 * transaction), go do TM stuff
1730 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1732 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1735 b fast_interrupt_return_srr
1736 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1737 2: /* User process was in a transaction */
1738 addi r3,r1,STACK_FRAME_OVERHEAD
1739 bl fp_unavailable_tm
1740 b interrupt_return_srr
1745 * Interrupt 0x900 - Decrementer Interrupt.
1746 * This is an asynchronous interrupt in response to a decrementer exception
1747 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing
1748 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e.,
1749 * local_irq_disable()).
1752 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1754 * If soft masked, the masked handler will note the pending interrupt for
1755 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled
1756 * in the interrupted context.
1757 * If PPC_WATCHDOG is configured, the soft masked handler will actually set
1758 * things back up to run soft_nmi_interrupt as a regular interrupt handler
1759 * on the emergency stack.
1761 INT_DEFINE_BEGIN(decrementer)
1764 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1767 INT_DEFINE_END(decrementer)
1769 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1770 GEN_INT_ENTRY decrementer, virt=0
1771 EXC_REAL_END(decrementer, 0x900, 0x80)
1772 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1773 GEN_INT_ENTRY decrementer, virt=1
1774 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1775 EXC_COMMON_BEGIN(decrementer_common)
1776 GEN_COMMON decrementer
1777 addi r3,r1,STACK_FRAME_OVERHEAD
1779 b interrupt_return_srr
1783 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1784 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1788 * Linux does not use this outside KVM where it's used to keep a host timer
1789 * while the guest is given control of DEC. It should normally be caught by
1790 * the KVM test and routed there.
1792 INT_DEFINE_BEGIN(hdecrementer)
1798 INT_DEFINE_END(hdecrementer)
1800 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1801 GEN_INT_ENTRY hdecrementer, virt=0
1802 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1803 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1804 GEN_INT_ENTRY hdecrementer, virt=1
1805 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1806 EXC_COMMON_BEGIN(hdecrementer_common)
1807 __GEN_COMMON_ENTRY hdecrementer
1809 * Hypervisor decrementer interrupts not caught by the KVM test
1810 * shouldn't occur but are sometimes left pending on exit from a KVM
1811 * guest. We don't need to do anything to clear them, as they are
1814 * Be careful to avoid touching the kernel stack.
1817 stb r10,PACAHSRR_VALID(r13)
1818 ld r10,PACA_EXGEN+EX_CTR(r13)
1821 ld r9,PACA_EXGEN+EX_R9(r13)
1822 ld r10,PACA_EXGEN+EX_R10(r13)
1823 ld r11,PACA_EXGEN+EX_R11(r13)
1824 ld r12,PACA_EXGEN+EX_R12(r13)
1825 ld r13,PACA_EXGEN+EX_R13(r13)
1830 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1831 * This is an asynchronous interrupt in response to a msgsndp doorbell.
1832 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
1833 * IRQS_DISABLED mask (i.e., local_irq_disable()).
1836 * Guests may use this for IPIs between threads in a core if the
1837 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1839 * If soft masked, the masked handler will note the pending interrupt for
1840 * replay, leaving MSR[EE] enabled in the interrupted context because the
1841 * doorbells are edge triggered.
1843 INT_DEFINE_BEGIN(doorbell_super)
1846 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1849 INT_DEFINE_END(doorbell_super)
1851 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1852 GEN_INT_ENTRY doorbell_super, virt=0
1853 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1854 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1855 GEN_INT_ENTRY doorbell_super, virt=1
1856 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1857 EXC_COMMON_BEGIN(doorbell_super_common)
1858 GEN_COMMON doorbell_super
1859 addi r3,r1,STACK_FRAME_OVERHEAD
1860 #ifdef CONFIG_PPC_DOORBELL
1861 bl doorbell_exception
1863 bl unknown_async_exception
1865 b interrupt_return_srr
1868 EXC_REAL_NONE(0xb00, 0x100)
1869 EXC_VIRT_NONE(0x4b00, 0x100)
1872 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1873 * This is a synchronous interrupt invoked with the "sc" instruction. The
1874 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1875 * is directed to the currently running OS. The hypercall is invoked with
1876 * "sc 1" and it sets HV=1, so it elevates to hypervisor.
1878 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1879 * 0x4c00 virtual mode.
1882 * If the KVM test fires then it was due to a hypercall and is accordingly
1883 * routed to KVM. Otherwise this executes a normal Linux system call.
1887 * syscall and hypercalls register conventions are documented in
1888 * Documentation/powerpc/syscall64-abi.rst and
1889 * Documentation/powerpc/papr_hcalls.rst respectively.
1891 * The intersection of volatile registers that don't contain possible
1892 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1893 * without saving, though xer is not a good idea to use, as hardware may
1894 * interpret some bits so it may be costly to change them.
1896 INT_DEFINE_BEGIN(system_call)
1900 INT_DEFINE_END(system_call)
1902 .macro SYSTEM_CALL virt
1903 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1905 * There is a little bit of juggling to get syscall and hcall
1906 * working well. Save r13 in ctr to avoid using SPRG scratch
1909 * Userspace syscalls have already saved the PPR, hcalls must save
1910 * it before setting HMT_MEDIUM.
1914 std r10,PACA_EXGEN+EX_R10(r13)
1916 KVMTEST system_call kvm_hcall /* uses r10, branch to kvm_hcall */
1924 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1928 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1931 /* We reach here with PACA in r13, r13 in r9. */
1938 __LOAD_HANDLER(r10, system_call_common_real)
1942 #ifdef CONFIG_RELOCATABLE
1943 __LOAD_HANDLER(r10, system_call_common)
1947 b system_call_common
1951 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1952 /* Fast LE/BE switch system call */
1953 1: mfspr r12,SPRN_SRR1
1957 RFI_TO_USER /* return to userspace */
1958 b . /* prevent speculative execution */
1962 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1964 EXC_REAL_END(system_call, 0xc00, 0x100)
1965 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1967 EXC_VIRT_END(system_call, 0x4c00, 0x100)
1969 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1970 TRAMP_REAL_BEGIN(kvm_hcall)
1971 std r9,PACA_EXGEN+EX_R9(r13)
1972 std r11,PACA_EXGEN+EX_R11(r13)
1973 std r12,PACA_EXGEN+EX_R12(r13)
1976 std r10,PACA_EXGEN+EX_R13(r13)
1978 std r10,PACA_EXGEN+EX_CFAR(r13)
1979 std r10,PACA_EXGEN+EX_CTR(r13)
1981 * Save the PPR (on systems that support it) before changing to
1982 * HMT_MEDIUM. That allows the KVM code to save that value into the
1983 * guest state (it is the guest's PPR value).
1987 std r10,PACA_EXGEN+EX_PPR(r13)
1988 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1992 #ifdef CONFIG_RELOCATABLE
1994 * Requires __LOAD_FAR_HANDLER beause kvmppc_hcall lives
1995 * outside the head section.
1997 __LOAD_FAR_HANDLER(r10, kvmppc_hcall)
2006 * Interrupt 0xd00 - Trace Interrupt.
2007 * This is a synchronous interrupt in response to instruction step or
2008 * breakpoint faults.
2010 INT_DEFINE_BEGIN(single_step)
2012 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2015 INT_DEFINE_END(single_step)
2017 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2018 GEN_INT_ENTRY single_step, virt=0
2019 EXC_REAL_END(single_step, 0xd00, 0x100)
2020 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2021 GEN_INT_ENTRY single_step, virt=1
2022 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2023 EXC_COMMON_BEGIN(single_step_common)
2024 GEN_COMMON single_step
2025 addi r3,r1,STACK_FRAME_OVERHEAD
2026 bl single_step_exception
2027 b interrupt_return_srr
2031 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2032 * This is a synchronous interrupt in response to an MMU fault caused by a
2033 * guest data access.
2036 * This should always get routed to KVM. In radix MMU mode, this is caused
2037 * by a guest nested radix access that can't be performed due to the
2038 * partition scope page table. In hash mode, this can be caused by guests
2039 * running with translation disabled (virtual real mode) or with VPM enabled.
2040 * KVM will update the page table structures or disallow the access.
2042 INT_DEFINE_BEGIN(h_data_storage)
2049 INT_DEFINE_END(h_data_storage)
2051 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2052 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2053 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2054 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2055 GEN_INT_ENTRY h_data_storage, virt=1, ool=1
2056 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2057 EXC_COMMON_BEGIN(h_data_storage_common)
2058 GEN_COMMON h_data_storage
2059 addi r3,r1,STACK_FRAME_OVERHEAD
2060 BEGIN_MMU_FTR_SECTION
2061 bl do_bad_page_fault_segv
2062 MMU_FTR_SECTION_ELSE
2063 bl unknown_exception
2064 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2065 b interrupt_return_hsrr
2069 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2070 * This is a synchronous interrupt in response to an MMU fault caused by a
2071 * guest instruction fetch, similar to HDSI.
2073 INT_DEFINE_BEGIN(h_instr_storage)
2078 INT_DEFINE_END(h_instr_storage)
2080 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2081 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2082 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2083 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2084 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1
2085 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2086 EXC_COMMON_BEGIN(h_instr_storage_common)
2087 GEN_COMMON h_instr_storage
2088 addi r3,r1,STACK_FRAME_OVERHEAD
2089 bl unknown_exception
2090 b interrupt_return_hsrr
2094 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2096 INT_DEFINE_BEGIN(emulation_assist)
2101 INT_DEFINE_END(emulation_assist)
2103 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2104 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2105 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2106 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2107 GEN_INT_ENTRY emulation_assist, virt=1, ool=1
2108 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2109 EXC_COMMON_BEGIN(emulation_assist_common)
2110 GEN_COMMON emulation_assist
2111 addi r3,r1,STACK_FRAME_OVERHEAD
2112 bl emulation_assist_interrupt
2113 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2114 b interrupt_return_hsrr
2118 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2119 * This is an asynchronous interrupt caused by a Hypervisor Maintenance
2120 * Exception. It is always taken in real mode but uses HSRR registers
2121 * unlike SRESET and MCE.
2123 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable
2124 * with IRQS_DISABLED mask (i.e., local_irq_disable()).
2127 * This is a special case, this is handled similarly to machine checks, with an
2128 * initial real mode handler that is not soft-masked, which attempts to fix the
2129 * problem. Then a regular handler which is soft-maskable and reports the
2132 * The emergency stack is used for the early real mode handler.
2134 * XXX: unclear why MCE and HMI schemes could not be made common, e.g.,
2135 * either use soft-masking for the MCE, or use irq_work for the HMI.
2138 * Unlike MCE, this calls into KVM without calling the real mode handler
2141 INT_DEFINE_BEGIN(hmi_exception_early)
2146 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2148 INT_DEFINE_END(hmi_exception_early)
2150 INT_DEFINE_BEGIN(hmi_exception)
2155 INT_DEFINE_END(hmi_exception)
2157 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2158 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2159 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2160 EXC_VIRT_NONE(0x4e60, 0x20)
2162 EXC_COMMON_BEGIN(hmi_exception_early_common)
2163 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early
2165 mr r10,r1 /* Save r1 */
2166 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
2167 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
2169 __GEN_COMMON_BODY hmi_exception_early
2171 addi r3,r1,STACK_FRAME_OVERHEAD
2172 bl hmi_exception_realmode
2176 EXCEPTION_RESTORE_REGS hsrr=1
2177 HRFI_TO_USER_OR_KERNEL
2181 * Go to virtual mode and pull the HMI event information from
2184 EXCEPTION_RESTORE_REGS hsrr=1
2185 GEN_INT_ENTRY hmi_exception, virt=0
2187 EXC_COMMON_BEGIN(hmi_exception_common)
2188 GEN_COMMON hmi_exception
2189 addi r3,r1,STACK_FRAME_OVERHEAD
2190 bl handle_hmi_exception
2191 b interrupt_return_hsrr
2195 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2196 * This is an asynchronous interrupt in response to a msgsnd doorbell.
2197 * Similar to the 0xa00 doorbell but for host rather than guest.
2199 INT_DEFINE_BEGIN(h_doorbell)
2205 INT_DEFINE_END(h_doorbell)
2207 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2208 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2209 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2210 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2211 GEN_INT_ENTRY h_doorbell, virt=1, ool=1
2212 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2213 EXC_COMMON_BEGIN(h_doorbell_common)
2214 GEN_COMMON h_doorbell
2215 addi r3,r1,STACK_FRAME_OVERHEAD
2216 #ifdef CONFIG_PPC_DOORBELL
2217 bl doorbell_exception
2219 bl unknown_async_exception
2221 b interrupt_return_hsrr
2225 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2226 * This is an asynchronous interrupt in response to an "external exception".
2227 * Similar to 0x500 but for host only.
2229 INT_DEFINE_BEGIN(h_virt_irq)
2235 INT_DEFINE_END(h_virt_irq)
2237 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2238 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2239 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2240 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2241 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1
2242 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2243 EXC_COMMON_BEGIN(h_virt_irq_common)
2244 GEN_COMMON h_virt_irq
2245 addi r3,r1,STACK_FRAME_OVERHEAD
2247 b interrupt_return_hsrr
2250 EXC_REAL_NONE(0xec0, 0x20)
2251 EXC_VIRT_NONE(0x4ec0, 0x20)
2252 EXC_REAL_NONE(0xee0, 0x20)
2253 EXC_VIRT_NONE(0x4ee0, 0x20)
2257 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2258 * This is an asynchronous interrupt in response to a PMU exception.
2259 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
2260 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()).
2263 * This calls into the perf subsystem.
2265 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it
2266 * runs under local_irq_disable. However it may be soft-masked in
2267 * powerpc-specific code.
2269 * If soft masked, the masked handler will note the pending interrupt for
2270 * replay, and clear MSR[EE] in the interrupted context.
2272 INT_DEFINE_BEGIN(performance_monitor)
2274 IMASK=IRQS_PMI_DISABLED
2275 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2278 INT_DEFINE_END(performance_monitor)
2280 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2281 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2282 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2283 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2284 GEN_INT_ENTRY performance_monitor, virt=1, ool=1
2285 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2286 EXC_COMMON_BEGIN(performance_monitor_common)
2287 GEN_COMMON performance_monitor
2288 addi r3,r1,STACK_FRAME_OVERHEAD
2289 bl performance_monitor_exception
2290 b interrupt_return_srr
2294 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2295 * This is a synchronous interrupt in response to
2296 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2297 * Similar to FP unavailable.
2299 INT_DEFINE_BEGIN(altivec_unavailable)
2301 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2304 INT_DEFINE_END(altivec_unavailable)
2306 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2307 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2308 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2309 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2310 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1
2311 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2312 EXC_COMMON_BEGIN(altivec_unavailable_common)
2313 GEN_COMMON altivec_unavailable
2314 #ifdef CONFIG_ALTIVEC
2317 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2318 BEGIN_FTR_SECTION_NESTED(69)
2319 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2320 * transaction), go do TM stuff
2322 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2324 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2327 b fast_interrupt_return_srr
2328 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2329 2: /* User process was in a transaction */
2330 addi r3,r1,STACK_FRAME_OVERHEAD
2331 bl altivec_unavailable_tm
2332 b interrupt_return_srr
2335 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2337 addi r3,r1,STACK_FRAME_OVERHEAD
2338 bl altivec_unavailable_exception
2339 b interrupt_return_srr
2343 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2344 * This is a synchronous interrupt in response to
2345 * executing a VSX instruction with MSR[VSX]=0.
2346 * Similar to FP unavailable.
2348 INT_DEFINE_BEGIN(vsx_unavailable)
2350 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2353 INT_DEFINE_END(vsx_unavailable)
2355 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2356 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2357 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2358 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2359 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1
2360 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2361 EXC_COMMON_BEGIN(vsx_unavailable_common)
2362 GEN_COMMON vsx_unavailable
2366 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2367 BEGIN_FTR_SECTION_NESTED(69)
2368 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2369 * transaction), go do TM stuff
2371 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2373 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2376 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2377 2: /* User process was in a transaction */
2378 addi r3,r1,STACK_FRAME_OVERHEAD
2379 bl vsx_unavailable_tm
2380 b interrupt_return_srr
2383 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2385 addi r3,r1,STACK_FRAME_OVERHEAD
2386 bl vsx_unavailable_exception
2387 b interrupt_return_srr
2391 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2392 * This is a synchronous interrupt in response to
2393 * executing an instruction without access to the facility that can be
2394 * resolved by the OS (e.g., FSCR, MSR).
2395 * Similar to FP unavailable.
2397 INT_DEFINE_BEGIN(facility_unavailable)
2399 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2402 INT_DEFINE_END(facility_unavailable)
2404 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2405 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2406 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2407 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2408 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1
2409 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2410 EXC_COMMON_BEGIN(facility_unavailable_common)
2411 GEN_COMMON facility_unavailable
2412 addi r3,r1,STACK_FRAME_OVERHEAD
2413 bl facility_unavailable_exception
2414 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2415 b interrupt_return_srr
2419 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2420 * This is a synchronous interrupt in response to
2421 * executing an instruction without access to the facility that can only
2422 * be resolved in HV mode (e.g., HFSCR).
2423 * Similar to FP unavailable.
2425 INT_DEFINE_BEGIN(h_facility_unavailable)
2430 INT_DEFINE_END(h_facility_unavailable)
2432 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2433 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2434 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2435 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2436 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1
2437 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2438 EXC_COMMON_BEGIN(h_facility_unavailable_common)
2439 GEN_COMMON h_facility_unavailable
2440 addi r3,r1,STACK_FRAME_OVERHEAD
2441 bl facility_unavailable_exception
2442 REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */
2443 b interrupt_return_hsrr
2446 EXC_REAL_NONE(0xfa0, 0x20)
2447 EXC_VIRT_NONE(0x4fa0, 0x20)
2448 EXC_REAL_NONE(0xfc0, 0x20)
2449 EXC_VIRT_NONE(0x4fc0, 0x20)
2450 EXC_REAL_NONE(0xfe0, 0x20)
2451 EXC_VIRT_NONE(0x4fe0, 0x20)
2453 EXC_REAL_NONE(0x1000, 0x100)
2454 EXC_VIRT_NONE(0x5000, 0x100)
2455 EXC_REAL_NONE(0x1100, 0x100)
2456 EXC_VIRT_NONE(0x5100, 0x100)
2458 #ifdef CONFIG_CBE_RAS
2459 INT_DEFINE_BEGIN(cbe_system_error)
2462 INT_DEFINE_END(cbe_system_error)
2464 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2465 GEN_INT_ENTRY cbe_system_error, virt=0
2466 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2467 EXC_VIRT_NONE(0x5200, 0x100)
2468 EXC_COMMON_BEGIN(cbe_system_error_common)
2469 GEN_COMMON cbe_system_error
2470 addi r3,r1,STACK_FRAME_OVERHEAD
2471 bl cbe_system_error_exception
2472 b interrupt_return_hsrr
2474 #else /* CONFIG_CBE_RAS */
2475 EXC_REAL_NONE(0x1200, 0x100)
2476 EXC_VIRT_NONE(0x5200, 0x100)
2480 * Interrupt 0x1300 - Instruction Address Breakpoint Interrupt.
2481 * This has been removed from the ISA before 2.01, which is the earliest
2482 * 64-bit BookS ISA supported, however the G5 / 970 implements this
2483 * interrupt with a non-architected feature available through the support
2484 * processor interface.
2486 INT_DEFINE_BEGIN(instruction_breakpoint)
2488 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2491 INT_DEFINE_END(instruction_breakpoint)
2493 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2494 GEN_INT_ENTRY instruction_breakpoint, virt=0
2495 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2496 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2497 GEN_INT_ENTRY instruction_breakpoint, virt=1
2498 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2499 EXC_COMMON_BEGIN(instruction_breakpoint_common)
2500 GEN_COMMON instruction_breakpoint
2501 addi r3,r1,STACK_FRAME_OVERHEAD
2502 bl instruction_breakpoint_exception
2503 b interrupt_return_srr
2506 EXC_REAL_NONE(0x1400, 0x100)
2507 EXC_VIRT_NONE(0x5400, 0x100)
2510 * Interrupt 0x1500 - Soft Patch Interrupt
2513 * This is an implementation specific interrupt which can be used for a
2514 * range of exceptions.
2516 * This interrupt handler is unique in that it runs the denormal assist
2517 * code even for guests (and even in guest context) without going to KVM,
2518 * for speed. POWER9 does not raise denorm exceptions, so this special case
2519 * could be phased out in future to reduce special cases.
2521 INT_DEFINE_BEGIN(denorm_exception)
2526 INT_DEFINE_END(denorm_exception)
2528 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2529 GEN_INT_ENTRY denorm_exception, virt=0
2530 #ifdef CONFIG_PPC_DENORMALISATION
2531 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2534 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2535 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2536 #ifdef CONFIG_PPC_DENORMALISATION
2537 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2538 GEN_INT_ENTRY denorm_exception, virt=1
2539 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2541 GEN_BRANCH_TO_COMMON denorm_exception, virt=1
2542 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2544 EXC_VIRT_NONE(0x5500, 0x100)
2547 #ifdef CONFIG_PPC_DENORMALISATION
2548 TRAMP_REAL_BEGIN(denorm_assist)
2551 * To denormalise we need to move a copy of the register to itself.
2552 * For POWER6 do that here for all FP regs.
2555 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2556 xori r10,r10,(MSR_FE0|MSR_FE1)
2568 * To denormalise we need to move a copy of the register to itself.
2569 * For POWER7 do that here for the first 32 VSX registers only.
2572 oris r10,r10,MSR_VSX@h
2578 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2582 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2586 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2588 * To denormalise we need to move a copy of the register to itself.
2589 * For POWER8 we need to do that for all 64 VSX registers
2593 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2598 mfspr r11,SPRN_HSRR0
2600 mtspr SPRN_HSRR0,r11
2602 ld r9,PACA_EXGEN+EX_R9(r13)
2604 ld r10,PACA_EXGEN+EX_PPR(r13)
2606 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2608 ld r10,PACA_EXGEN+EX_CFAR(r13)
2610 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2612 stb r10,PACAHSRR_VALID(r13)
2613 ld r10,PACA_EXGEN+EX_R10(r13)
2614 ld r11,PACA_EXGEN+EX_R11(r13)
2615 ld r12,PACA_EXGEN+EX_R12(r13)
2616 ld r13,PACA_EXGEN+EX_R13(r13)
2621 EXC_COMMON_BEGIN(denorm_exception_common)
2622 GEN_COMMON denorm_exception
2623 addi r3,r1,STACK_FRAME_OVERHEAD
2624 bl unknown_exception
2625 b interrupt_return_hsrr
2628 #ifdef CONFIG_CBE_RAS
2629 INT_DEFINE_BEGIN(cbe_maintenance)
2632 INT_DEFINE_END(cbe_maintenance)
2634 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2635 GEN_INT_ENTRY cbe_maintenance, virt=0
2636 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2637 EXC_VIRT_NONE(0x5600, 0x100)
2638 EXC_COMMON_BEGIN(cbe_maintenance_common)
2639 GEN_COMMON cbe_maintenance
2640 addi r3,r1,STACK_FRAME_OVERHEAD
2641 bl cbe_maintenance_exception
2642 b interrupt_return_hsrr
2644 #else /* CONFIG_CBE_RAS */
2645 EXC_REAL_NONE(0x1600, 0x100)
2646 EXC_VIRT_NONE(0x5600, 0x100)
2650 INT_DEFINE_BEGIN(altivec_assist)
2652 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2655 INT_DEFINE_END(altivec_assist)
2657 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2658 GEN_INT_ENTRY altivec_assist, virt=0
2659 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2660 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2661 GEN_INT_ENTRY altivec_assist, virt=1
2662 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2663 EXC_COMMON_BEGIN(altivec_assist_common)
2664 GEN_COMMON altivec_assist
2665 addi r3,r1,STACK_FRAME_OVERHEAD
2666 #ifdef CONFIG_ALTIVEC
2667 bl altivec_assist_exception
2668 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2670 bl unknown_exception
2672 b interrupt_return_srr
2675 #ifdef CONFIG_CBE_RAS
2676 INT_DEFINE_BEGIN(cbe_thermal)
2679 INT_DEFINE_END(cbe_thermal)
2681 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2682 GEN_INT_ENTRY cbe_thermal, virt=0
2683 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2684 EXC_VIRT_NONE(0x5800, 0x100)
2685 EXC_COMMON_BEGIN(cbe_thermal_common)
2686 GEN_COMMON cbe_thermal
2687 addi r3,r1,STACK_FRAME_OVERHEAD
2688 bl cbe_thermal_exception
2689 b interrupt_return_hsrr
2691 #else /* CONFIG_CBE_RAS */
2692 EXC_REAL_NONE(0x1800, 0x100)
2693 EXC_VIRT_NONE(0x5800, 0x100)
2697 #ifdef CONFIG_PPC_WATCHDOG
2699 INT_DEFINE_BEGIN(soft_nmi)
2702 INT_DEFINE_END(soft_nmi)
2705 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2706 * stack is one that is usable by maskable interrupts so long as MSR_EE
2707 * remains off. It is used for recovery when something has corrupted the
2708 * normal kernel stack, for example. The "soft NMI" must not use the process
2709 * stack because we want irq disabled sections to avoid touching the stack
2710 * at all (other than PMU interrupts), so use the emergency stack for this,
2711 * and run it entirely with interrupts hard disabled.
2713 EXC_COMMON_BEGIN(soft_nmi_common)
2715 ld r1,PACAEMERGSP(r13)
2716 subi r1,r1,INT_FRAME_SIZE
2717 __GEN_COMMON_BODY soft_nmi
2719 addi r3,r1,STACK_FRAME_OVERHEAD
2720 bl soft_nmi_interrupt
2722 /* Clear MSR_RI before setting SRR0 and SRR1. */
2726 kuap_kernel_restore r9, r10
2728 EXCEPTION_RESTORE_REGS hsrr=0
2731 #endif /* CONFIG_PPC_WATCHDOG */
2734 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2735 * - If it was a decrementer interrupt, we bump the dec to max and and return.
2736 * - If it was a doorbell we return immediately since doorbells are edge
2737 * triggered and won't automatically refire.
2738 * - If it was a HMI we return immediately since we handled it in realmode
2739 * and it won't refire.
2740 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2741 * This is called with r10 containing the value to OR to the paca field.
2743 .macro MASKED_INTERRUPT hsrr=0
2749 stw r9,PACA_EXGEN+EX_CCR(r13)
2750 lbz r9,PACAIRQHAPPENED(r13)
2752 stb r9,PACAIRQHAPPENED(r13)
2755 cmpwi r10,PACA_IRQ_DEC
2757 LOAD_REG_IMMEDIATE(r9, 0x7fffffff)
2759 #ifdef CONFIG_PPC_WATCHDOG
2760 lwz r9,PACA_EXGEN+EX_CCR(r13)
2767 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2769 xori r12,r12,MSR_EE /* clear MSR_EE */
2771 mtspr SPRN_HSRR1,r12
2775 ori r9,r9,PACA_IRQ_HARD_DIS
2776 stb r9,PACAIRQHAPPENED(r13)
2780 stb r9,PACAHSRR_VALID(r13)
2782 stb r9,PACASRR_VALID(r13)
2785 SEARCH_RESTART_TABLE
2789 mtspr SPRN_HSRR0,r12
2795 ld r9,PACA_EXGEN+EX_CTR(r13)
2797 lwz r9,PACA_EXGEN+EX_CCR(r13)
2800 ld r9,PACA_EXGEN+EX_R9(r13)
2801 ld r10,PACA_EXGEN+EX_R10(r13)
2802 ld r11,PACA_EXGEN+EX_R11(r13)
2803 ld r12,PACA_EXGEN+EX_R12(r13)
2804 ld r13,PACA_EXGEN+EX_R13(r13)
2805 /* May return to masked low address where r13 is not set up */
2814 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2815 std r9,PACA_EXRFI+EX_R9(r13)
2816 std r10,PACA_EXRFI+EX_R10(r13)
2818 ld r9,PACA_EXRFI+EX_R9(r13)
2819 ld r10,PACA_EXRFI+EX_R10(r13)
2827 /* Clobbers r10, r11, ctr */
2828 .macro L1D_DISPLACEMENT_FLUSH
2829 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2830 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2831 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2833 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2835 /* order ld/st prior to dcbt stop all streams with flushing */
2839 * The load addresses are at staggered offsets within cachelines,
2840 * which suits some pipelines better (on others it should not
2844 ld r11,(0x80 + 8)*0(r10)
2845 ld r11,(0x80 + 8)*1(r10)
2846 ld r11,(0x80 + 8)*2(r10)
2847 ld r11,(0x80 + 8)*3(r10)
2848 ld r11,(0x80 + 8)*4(r10)
2849 ld r11,(0x80 + 8)*5(r10)
2850 ld r11,(0x80 + 8)*6(r10)
2851 ld r11,(0x80 + 8)*7(r10)
2856 TRAMP_REAL_BEGIN(entry_flush_fallback)
2857 std r9,PACA_EXRFI+EX_R9(r13)
2858 std r10,PACA_EXRFI+EX_R10(r13)
2859 std r11,PACA_EXRFI+EX_R11(r13)
2861 L1D_DISPLACEMENT_FLUSH
2863 ld r9,PACA_EXRFI+EX_R9(r13)
2864 ld r10,PACA_EXRFI+EX_R10(r13)
2865 ld r11,PACA_EXRFI+EX_R11(r13)
2869 * The SCV entry flush happens with interrupts enabled, so it must disable
2870 * to prevent EXRFI being clobbered by NMIs (e.g., soft_nmi_common). r10
2871 * (containing LR) does not need to be preserved here because scv entry
2872 * puts 0 in the pt_regs, CTR can be clobbered for the same reason.
2874 TRAMP_REAL_BEGIN(scv_entry_flush_fallback)
2877 lbz r10,PACAIRQHAPPENED(r13)
2878 ori r10,r10,PACA_IRQ_HARD_DIS
2879 stb r10,PACAIRQHAPPENED(r13)
2880 std r11,PACA_EXRFI+EX_R11(r13)
2881 L1D_DISPLACEMENT_FLUSH
2882 ld r11,PACA_EXRFI+EX_R11(r13)
2887 TRAMP_REAL_BEGIN(rfi_flush_fallback)
2890 std r1,PACA_EXRFI+EX_R12(r13)
2891 ld r1,PACAKSAVE(r13)
2892 std r9,PACA_EXRFI+EX_R9(r13)
2893 std r10,PACA_EXRFI+EX_R10(r13)
2894 std r11,PACA_EXRFI+EX_R11(r13)
2896 L1D_DISPLACEMENT_FLUSH
2898 ld r9,PACA_EXRFI+EX_R9(r13)
2899 ld r10,PACA_EXRFI+EX_R10(r13)
2900 ld r11,PACA_EXRFI+EX_R11(r13)
2901 ld r1,PACA_EXRFI+EX_R12(r13)
2905 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2908 std r1,PACA_EXRFI+EX_R12(r13)
2909 ld r1,PACAKSAVE(r13)
2910 std r9,PACA_EXRFI+EX_R9(r13)
2911 std r10,PACA_EXRFI+EX_R10(r13)
2912 std r11,PACA_EXRFI+EX_R11(r13)
2914 L1D_DISPLACEMENT_FLUSH
2916 ld r9,PACA_EXRFI+EX_R9(r13)
2917 ld r10,PACA_EXRFI+EX_R10(r13)
2918 ld r11,PACA_EXRFI+EX_R11(r13)
2919 ld r1,PACA_EXRFI+EX_R12(r13)
2923 TRAMP_REAL_BEGIN(rfscv_flush_fallback)
2924 /* system call volatile */
2928 ld r1,PACAKSAVE(r13)
2930 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2931 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2932 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2934 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2936 /* order ld/st prior to dcbt stop all streams with flushing */
2940 * The load adresses are at staggered offsets within cachelines,
2941 * which suits some pipelines better (on others it should not
2945 ld r11,(0x80 + 8)*0(r10)
2946 ld r11,(0x80 + 8)*1(r10)
2947 ld r11,(0x80 + 8)*2(r10)
2948 ld r11,(0x80 + 8)*3(r10)
2949 ld r11,(0x80 + 8)*4(r10)
2950 ld r11,(0x80 + 8)*5(r10)
2951 ld r11,(0x80 + 8)*6(r10)
2952 ld r11,(0x80 + 8)*7(r10)
2966 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2969 * The conditional branch in KVMTEST can't reach all the way,
2975 _GLOBAL(do_uaccess_flush)
2976 UACCESS_FLUSH_FIXUP_SECTION
2981 L1D_DISPLACEMENT_FLUSH
2983 _ASM_NOKPROBE_SYMBOL(do_uaccess_flush)
2984 EXPORT_SYMBOL(do_uaccess_flush)
2988 MASKED_INTERRUPT hsrr=1
2991 * Relocation-on interrupts: A subset of the interrupts can be delivered
2992 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
2993 * it. Addresses are the same as the original interrupt addresses, but
2994 * offset by 0xc000000000004000.
2995 * It's impossible to receive interrupts below 0x300 via this mechanism.
2996 * KVM: None of these traps are from the guest ; anything that escalated
2997 * to HV=1 from HV=0 is delivered via real mode handlers.
3001 * This uses the standard macro, since the original 0x300 vector
3002 * only has extra guff for STAB-based processors -- which never
3006 USE_FIXED_SECTION(virt_trampolines)
3008 * All code below __end_soft_masked is treated as soft-masked. If
3009 * any code runs here with MSR[EE]=1, it must then cope with pending
3010 * soft interrupt being raised (i.e., by ensuring it is replayed).
3012 * The __end_interrupts marker must be past the out-of-line (OOL)
3013 * handlers, so that they are copied to real address 0x100 when running
3014 * a relocatable kernel. This ensures they can be reached from the short
3015 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3016 * directly, without using LOAD_HANDLER().
3019 .globl __end_interrupts
3021 DEFINE_FIXED_SYMBOL(__end_interrupts)
3023 CLOSE_FIXED_SECTION(real_vectors);
3024 CLOSE_FIXED_SECTION(real_trampolines);
3025 CLOSE_FIXED_SECTION(virt_vectors);
3026 CLOSE_FIXED_SECTION(virt_trampolines);
3030 /* MSR[RI] should be clear because this uses SRR[01] */
3031 enable_machine_check:
3035 addi r3,r3,(1f - 0b)
3044 /* MSR[RI] should be clear because this uses SRR[01] */
3045 disable_machine_check:
3049 addi r3,r3,(1f - 0b)