1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
24 /* PACA save area offsets (exgen, exmc, etc) */
37 .error "EX_SIZE is wrong"
41 * Following are fixed section helper macros.
43 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors
44 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors
45 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these)
46 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use)
47 * EXC_COMMON - After switching to virtual, relocated mode.
50 #define EXC_REAL_BEGIN(name, start, size) \
51 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
53 #define EXC_REAL_END(name, start, size) \
54 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
56 #define EXC_VIRT_BEGIN(name, start, size) \
57 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
59 #define EXC_VIRT_END(name, start, size) \
60 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
62 #define EXC_COMMON_BEGIN(name) \
64 .balign IFETCH_ALIGN_BYTES; \
66 _ASM_NOKPROBE_SYMBOL(name); \
67 DEFINE_FIXED_SYMBOL(name); \
70 #define TRAMP_REAL_BEGIN(name) \
71 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
73 #define TRAMP_VIRT_BEGIN(name) \
74 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
76 #define EXC_REAL_NONE(start, size) \
77 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
78 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
80 #define EXC_VIRT_NONE(start, size) \
81 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
82 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
85 * We're short on space and time in the exception prolog, so we can't
86 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
87 * Instead we get the base of the kernel from paca->kernelbase and or in the low
88 * part of label. This requires that the label be within 64KB of kernelbase, and
89 * that kernelbase be 64K aligned.
91 #define LOAD_HANDLER(reg, label) \
92 ld reg,PACAKBASE(r13); /* get high part of &label */ \
93 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
95 #define __LOAD_HANDLER(reg, label) \
96 ld reg,PACAKBASE(r13); \
97 ori reg,reg,(ABS_ADDR(label))@l
100 * Branches from unrelocated code (e.g., interrupts) to labels outside
101 * head-y require >64K offsets.
103 #define __LOAD_FAR_HANDLER(reg, label) \
104 ld reg,PACAKBASE(r13); \
105 ori reg,reg,(ABS_ADDR(label))@l; \
106 addis reg,reg,(ABS_ADDR(label))@h
109 * Branch to label using its 0xC000 address. This results in instruction
110 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
111 * on using mtmsr rather than rfid.
113 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
114 * load KBASE for a slight optimisation.
116 #define BRANCH_TO_C000(reg, label) \
117 __LOAD_FAR_HANDLER(reg, label); \
122 * Interrupt code generation macros
124 #define IVEC .L_IVEC_\name\() /* Interrupt vector address */
125 #define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */
126 #define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */
127 #define IAREA .L_IAREA_\name\() /* PACA save area */
128 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */
129 #define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */
130 #define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */
131 #define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */
132 #define ISET_RI .L_ISET_RI_\name\() /* Run common code w/ MSR[RI]=1 */
133 #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */
134 #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */
135 #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */
136 #define IKVM_SKIP .L_IKVM_SKIP_\name\() /* Generate KVM skip handler */
137 #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */
138 #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name
139 #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */
140 #define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */
141 #define __ISTACK(name) .L_ISTACK_ ## name
142 #define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */
144 #define INT_DEFINE_BEGIN(n) \
145 .macro int_define_ ## n name
147 #define INT_DEFINE_END(n) \
149 int_define_ ## n n ; \
152 .macro do_define_int name
154 .error "IVEC not defined"
159 .ifndef IHSRR_IF_HVMODE
180 .ifndef IBRANCH_TO_COMMON
183 .ifndef IREALMODE_COMMON
186 .if ! IBRANCH_TO_COMMON
187 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
210 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
211 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
213 * All interrupts which set HSRR registers, as well as SRESET and MCE and
214 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken,
215 * so they all generally need to test whether they were taken in guest context.
217 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be
218 * taken with MSR[HV]=0.
220 * Interrupts which set SRR registers (with the above exceptions) do not
221 * elevate to MSR[HV]=1 mode, though most can be taken when running with
222 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do
223 * not need to test whether a guest is running because they get delivered to
224 * the guest directly, including nested HV KVM guests.
226 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host
227 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
228 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
229 * delivered to the real-mode entry point, therefore such interrupts only test
230 * KVM in their real mode handlers, and only when PR KVM is possible.
232 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
233 * delivered in real-mode when the MMU is in hash mode because the MMU
234 * registers are not set appropriately to translate host addresses. In nested
235 * radix mode these can be delivered in virt-mode as the host translations are
236 * used implicitly (see: effective LPID, effective PID).
240 * If an interrupt is taken while a guest is running, it is immediately routed
241 * to KVM to handle. If both HV and PR KVM arepossible, KVM interrupts go first
242 * to kvmppc_interrupt_hv, which handles the PR guest case.
244 #define kvmppc_interrupt kvmppc_interrupt_hv
246 #define kvmppc_interrupt kvmppc_interrupt_pr
250 lbz r10,HSTATE_IN_GUEST(r13)
256 .balign IFETCH_ALIGN_BYTES
260 cmpwi r10,KVM_GUEST_MODE_SKIP
264 ld r10,IAREA+EX_CFAR(r13)
265 std r10,HSTATE_CFAR(r13)
266 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
269 ld r10,IAREA+EX_CTR(r13)
272 ld r10,IAREA+EX_PPR(r13)
273 std r10,HSTATE_PPR(r13)
274 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
275 ld r11,IAREA+EX_R11(r13)
276 ld r12,IAREA+EX_R12(r13)
277 std r12,HSTATE_SCRATCH0(r13)
279 ld r9,IAREA+EX_R9(r13)
280 ld r10,IAREA+EX_R10(r13)
281 /* HSRR variants have the 0x2 bit added to their trap number */
284 ori r12,r12,(IVEC + 0x2)
287 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
289 ori r12,r12,(IVEC+ 0x2)
297 ld r10,IAREA+EX_CTR(r13)
299 ld r9,IAREA+EX_R9(r13)
300 ld r10,IAREA+EX_R10(r13)
301 ld r11,IAREA+EX_R11(r13)
302 ld r12,IAREA+EX_R12(r13)
305 b kvmppc_skip_Hinterrupt
307 b kvmppc_skip_interrupt
308 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
310 b kvmppc_skip_Hinterrupt
312 b kvmppc_skip_interrupt
325 * This is the BOOK3S interrupt entry code macro.
327 * This can result in one of several things happening:
328 * - Branch to the _common handler, relocated, in virtual mode.
329 * These are normal interrupts (synchronous and asynchronous) handled by
331 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
332 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
333 * / intended for host or guest kernel, but KVM must always be involved
334 * because the machine state is set for guest execution.
335 * - Branch to the masked handler, unrelocated.
336 * These occur when maskable asynchronous interrupts are taken with the
338 * - Branch to an "early" handler in real mode but relocated.
339 * This is done if early=1. MCE and HMI use these to handle errors in real
341 * - Fall through and continue executing in real, unrelocated mode.
342 * This is done if early=2.
345 .macro GEN_BRANCH_TO_COMMON name, virt
347 LOAD_HANDLER(r10, \name\()_common)
352 #ifndef CONFIG_RELOCATABLE
353 b \name\()_common_virt
355 LOAD_HANDLER(r10, \name\()_common_virt)
360 LOAD_HANDLER(r10, \name\()_common_real)
367 .macro GEN_INT_ENTRY name, virt, ool=0
368 SET_SCRATCH0(r13) /* save r13 */
370 std r9,IAREA+EX_R9(r13) /* save r9 */
373 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
375 std r10,IAREA+EX_R10(r13) /* save r10 - r12 */
378 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
383 TRAMP_REAL_BEGIN(tramp_real_\name)
387 TRAMP_VIRT_BEGIN(tramp_virt_\name)
392 std r9,IAREA+EX_PPR(r13)
393 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
395 std r10,IAREA+EX_CFAR(r13)
396 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
399 std r10,IAREA+EX_CTR(r13)
401 std r11,IAREA+EX_R11(r13)
402 std r12,IAREA+EX_R12(r13)
405 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
406 * because a d-side MCE will clobber those registers so is
407 * not recoverable if they are live.
410 std r10,IAREA+EX_R13(r13)
417 std r10,IAREA+EX_DAR(r13)
419 .if IDSISR && !IISIDE
421 mfspr r10,SPRN_HDSISR
425 stw r10,IAREA+EX_DSISR(r13)
430 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
431 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
433 mfspr r11,SPRN_SRR0 /* save SRR0 */
434 mfspr r12,SPRN_SRR1 /* and SRR1 */
435 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
437 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
438 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
440 mfspr r11,SPRN_SRR0 /* save SRR0 */
441 mfspr r12,SPRN_SRR1 /* and SRR1 */
444 .if IBRANCH_TO_COMMON
445 GEN_BRANCH_TO_COMMON \name \virt
454 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt
455 * entry, except in the case of the real-mode handlers which require
456 * __GEN_REALMODE_COMMON_ENTRY.
458 * This switches to virtual mode and sets MSR[RI].
460 .macro __GEN_COMMON_ENTRY name
461 DEFINE_FIXED_SYMBOL(\name\()_common_real)
462 \name\()_common_real:
467 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
468 /* MSR[RI] is clear iff using SRR regs */
469 .if IHSRR == EXC_HV_OR_STD
472 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
480 b 1f /* skip the virt test coming from real */
483 .balign IFETCH_ALIGN_BYTES
484 DEFINE_FIXED_SYMBOL(\name\()_common_virt)
485 \name\()_common_virt:
494 * Don't switch to virt mode. Used for early MCE and HMI handlers that
495 * want to run in real mode.
497 .macro __GEN_REALMODE_COMMON_ENTRY name
498 DEFINE_FIXED_SYMBOL(\name\()_common_real)
499 \name\()_common_real:
505 .macro __GEN_COMMON_BODY name
508 .error "No support for masked interrupt to use custom stack"
511 /* If coming from user, skip soft-mask tests. */
515 /* Kernel code running below __end_interrupts is implicitly
517 LOAD_HANDLER(r10, __end_interrupts)
522 /* Test the soft mask state against our interrupt's bit */
523 lbz r10,PACAIRQSOFTMASK(r13)
524 1: andi. r10,r10,IMASK
525 /* Associate vector numbers with bits in paca->irq_happened */
526 .if IVEC == 0x500 || IVEC == 0xea0
528 .elseif IVEC == 0x900
530 .elseif IVEC == 0xa00 || IVEC == 0xe80
531 li r10,PACA_IRQ_DBELL
532 .elseif IVEC == 0xe60
534 .elseif IVEC == 0xf00
537 .abort "Bad maskable vector"
542 bne masked_Hinterrupt
545 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
547 bne masked_Hinterrupt
554 andi. r10,r12,MSR_PR /* See if coming from user */
555 2: mr r10,r1 /* Save r1 */
556 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */
558 ld r1,PACAKSAVE(r13) /* kernel stack to use */
559 100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */
560 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
563 std r9,_CCR(r1) /* save CR in stackframe */
564 std r11,_NIP(r1) /* save SRR0 in stackframe */
565 std r12,_MSR(r1) /* save SRR1 in stackframe */
566 std r10,0(r1) /* make stack chain pointer */
567 std r0,GPR0(r1) /* save r0 in stackframe */
568 std r10,GPR1(r1) /* save r1 in stackframe */
572 mtmsrd r10,1 /* Set MSR_RI */
577 kuap_save_amr_and_lock r9, r10, cr1, cr0
579 beq 101f /* if from kernel mode */
581 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */
583 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
587 kuap_save_amr_and_lock r9, r10, cr1
591 /* Save original regs values from save area to stack frame. */
592 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */
593 ld r10,IAREA+EX_R10(r13)
596 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */
597 ld r10,IAREA+EX_R12(r13)
598 ld r11,IAREA+EX_R13(r13)
609 ld r10,IAREA+EX_DAR(r13)
617 lis r11,DSISR_SRR1_MATCH_64S@h
620 lwz r10,IAREA+EX_DSISR(r13)
626 ld r10,IAREA+EX_CFAR(r13)
627 std r10,ORIG_GPR3(r1)
628 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
629 ld r10,IAREA+EX_CTR(r13)
631 std r2,GPR2(r1) /* save r2 in stackframe */
632 SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */
633 SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */
634 mflr r9 /* Get LR, later save to stack */
635 ld r2,PACATOC(r13) /* get kernel TOC into r2 */
637 lbz r10,PACAIRQSOFTMASK(r13)
638 mfspr r11,SPRN_XER /* save XER in stackframe */
642 std r9,_TRAP(r1) /* set trap number */
644 ld r11,exception_marker@toc(r2)
645 std r10,RESULT(r1) /* clear regs->result */
646 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */
650 * On entry r13 points to the paca, r9-r13 are saved in the paca,
651 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
652 * SRR1, and relocation is on.
654 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
655 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
657 .macro GEN_COMMON name
658 __GEN_COMMON_ENTRY \name
659 __GEN_COMMON_BODY \name
663 * Restore all registers including H/SRR0/1 saved in a stack frame of a
664 * standard exception.
666 .macro EXCEPTION_RESTORE_REGS hsrr=0
667 /* Move original SRR0 and SRR1 into the respective regs */
691 /* restore original r1. */
695 #define RUNLATCH_ON \
697 ld r3, PACA_THREAD_INFO(r13); \
698 ld r4,TI_LOCAL_FLAGS(r3); \
699 andi. r0,r4,_TLF_RUNLATCH; \
700 beql ppc64_runlatch_on_trampoline; \
701 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
704 * When the idle code in power4_idle puts the CPU into NAP mode,
705 * it has to do so in a loop, and relies on the external interrupt
706 * and decrementer interrupt entry code to get it out of the loop.
707 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
708 * to signal that it is in the loop and needs help to get out.
710 #ifdef CONFIG_PPC_970_NAP
713 ld r11, PACA_THREAD_INFO(r13); \
714 ld r9,TI_LOCAL_FLAGS(r11); \
715 andi. r10,r9,_TLF_NAPPING; \
716 bnel power4_fixup_nap; \
717 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
723 * There are a few constraints to be concerned with.
724 * - Real mode exceptions code/data must be located at their physical location.
725 * - Virtual mode exceptions must be mapped at their 0xc000... location.
726 * - Fixed location code must not call directly beyond the __end_interrupts
727 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
729 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
731 * - Conditional branch targets must be within +/-32K of caller.
733 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
734 * therefore don't have to run in physically located code or rfid to
735 * virtual mode kernel code. However on relocatable kernels they do have
736 * to branch to KERNELBASE offset because the rest of the kernel (outside
737 * the exception vectors) may be located elsewhere.
739 * Virtual exceptions correspond with physical, except their entry points
740 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
741 * offset applied. Virtual exceptions are enabled with the Alternate
742 * Interrupt Location (AIL) bit set in the LPCR. However this does not
743 * guarantee they will be delivered virtually. Some conditions (see the ISA)
744 * cause exceptions to be delivered in real mode.
746 * The scv instructions are a special case. They get a 0x3000 offset applied.
747 * scv exceptions have unique reentrancy properties, see below.
749 * It's impossible to receive interrupts below 0x300 via AIL.
751 * KVM: None of the virtual exceptions are from the guest. Anything that
752 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
755 * We layout physical memory as follows:
756 * 0x0000 - 0x00ff : Secondary processor spin code
757 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
758 * 0x1900 - 0x2fff : Real mode trampolines
759 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
760 * 0x5900 - 0x6fff : Relon mode trampolines
761 * 0x7000 - 0x7fff : FWNMI data area
762 * 0x8000 - .... : Common interrupt handlers, remaining early
763 * setup code, rest of kernel.
765 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
766 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
769 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
770 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
771 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
772 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
774 #ifdef CONFIG_PPC_POWERNV
775 .globl start_real_trampolines
776 .globl end_real_trampolines
777 .globl start_virt_trampolines
778 .globl end_virt_trampolines
781 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
783 * Data area reserved for FWNMI option.
784 * This address (0x7000) is fixed by the RPA.
785 * pseries and powernv need to keep the whole page from
786 * 0x7000 to 0x8000 free for use by the firmware
788 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
789 OPEN_TEXT_SECTION(0x8000)
791 OPEN_TEXT_SECTION(0x7000)
794 USE_FIXED_SECTION(real_vectors)
797 * This is the start of the interrupt handlers for pSeries
798 * This code runs with relocation off.
799 * Code from here to __end_interrupts gets copied down to real
800 * address 0x100 when we are running a relocatable kernel.
801 * Therefore any relative branches in this section must only
802 * branch to labels in this section.
804 .globl __start_interrupts
808 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
809 * This is a synchronous interrupt invoked with the "scv" instruction. The
810 * system call does not alter the HV bit, so it is directed to the OS.
813 * scv instructions enter the kernel without changing EE, RI, ME, or HV.
814 * In particular, this means we can take a maskable interrupt at any point
815 * in the scv handler, which is unlike any other interrupt. This is solved
816 * by treating the instruction addresses below __end_interrupts as being
819 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
820 * ensure scv is never executed with relocation off, which means AIL-0
821 * should never happen.
823 * Before leaving the below __end_interrupts text, at least of the following
825 * - MSR[PR]=1 (i.e., return to userspace)
826 * - MSR_EE|MSR_RI is set (no reentrant exceptions)
827 * - Standard kernel environment is set up (stack, paca, etc)
831 * syscall register convention is in Documentation/powerpc/syscall64-abi.rst
833 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
839 li r10,IRQS_ALL_DISABLED
840 stb r10,PACAIRQSOFTMASK(r13)
841 #ifdef CONFIG_RELOCATABLE
842 b system_call_vectored_tramp
844 b system_call_vectored_common
854 li r10,IRQS_ALL_DISABLED
855 stb r10,PACAIRQSOFTMASK(r13)
856 li r0,-1 /* cause failure */
857 #ifdef CONFIG_RELOCATABLE
858 b system_call_vectored_sigill_tramp
860 b system_call_vectored_sigill
863 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
865 #ifdef CONFIG_RELOCATABLE
866 TRAMP_VIRT_BEGIN(system_call_vectored_tramp)
867 __LOAD_HANDLER(r10, system_call_vectored_common)
871 TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp)
872 __LOAD_HANDLER(r10, system_call_vectored_sigill)
878 /* No virt vectors corresponding with 0x0..0x100 */
879 EXC_VIRT_NONE(0x4000, 0x100)
883 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
884 * This is a non-maskable, asynchronous interrupt always taken in real-mode.
886 * - Wake from power-saving state, on powernv.
887 * - An NMI from another CPU, triggered by firmware or hypercall.
888 * - As crash/debug signal injected from BMC, firmware or hypervisor.
891 * Power-save wakeup is the only performance critical path, so this is
892 * determined quickly as possible first. In this case volatile registers
893 * can be discarded and SPRs like CFAR don't need to be read.
895 * If not a powersave wakeup, then it's run as a regular interrupt, however
896 * it uses its own stack and PACA save area to preserve the regular kernel
897 * environment for debugging.
899 * This interrupt is not maskable, so triggering it when MSR[RI] is clear,
900 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely
901 * correct to switch to virtual mode to run the regular interrupt handler
902 * because it might be interrupted when the MMU is in a bad state (e.g., SLB
906 * PAPR specifies a "fwnmi" facility which sends the sreset to a different
907 * entry point with a different register set up. Some hypervisors will
908 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
911 * Unlike most SRR interrupts, this may be taken by the host while executing
912 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest
913 * mode and then raise the sreset.
915 INT_DEFINE_BEGIN(system_reset)
918 IVIRT=0 /* no virt entry point */
920 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
921 * being used, so a nested NMI exception would corrupt it.
926 INT_DEFINE_END(system_reset)
928 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
929 #ifdef CONFIG_PPC_P7_NAP
931 * If running native on arch 2.06 or later, check if we are waking up
932 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
933 * bits 46:47. A non-0 value indicates that we are coming from a power
934 * saving state. The idle wakeup handler initially runs in real mode,
935 * but we branch to the 0xc000... address so we can turn on relocation
936 * with mtmsrd later, after SPRs are restored.
938 * Careful to minimise cost for the fast path (idle wakeup) while
939 * also avoiding clobbering CFAR for the debug path (non-idle).
941 * For the idle wake case volatile registers can be clobbered, which
942 * is why we use those initially. If it turns out to not be an idle
943 * wake, carefully put everything back the way it was, so we can use
944 * common exception macros to handle it.
949 std r3,PACA_EXNMI+0*8(r13)
950 std r4,PACA_EXNMI+1*8(r13)
951 std r5,PACA_EXNMI+2*8(r13)
954 rlwinm. r5,r3,47-31,30,31
955 bne+ system_reset_idle_wake
956 /* Not powersave wakeup. Restore regs for regular interrupt handler. */
958 ld r3,PACA_EXNMI+0*8(r13)
959 ld r4,PACA_EXNMI+1*8(r13)
960 ld r5,PACA_EXNMI+2*8(r13)
962 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
965 GEN_INT_ENTRY system_reset, virt=0
967 * In theory, we should not enable relocation here if it was disabled
968 * in SRR1, because the MMU may not be configured to support it (e.g.,
969 * SLB may have been cleared). In practice, there should only be a few
970 * small windows where that's the case, and sreset is considered to
971 * be dangerous anyway.
973 EXC_REAL_END(system_reset, 0x100, 0x100)
974 EXC_VIRT_NONE(0x4100, 0x100)
976 #ifdef CONFIG_PPC_P7_NAP
977 TRAMP_REAL_BEGIN(system_reset_idle_wake)
978 /* We are waking up from idle, so may clobber any volatile register */
980 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
981 BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss))
984 #ifdef CONFIG_PPC_PSERIES
986 * Vectors for the FWNMI option. Share common code.
988 TRAMP_REAL_BEGIN(system_reset_fwnmi)
989 GEN_INT_ENTRY system_reset, virt=0
991 #endif /* CONFIG_PPC_PSERIES */
993 EXC_COMMON_BEGIN(system_reset_common)
994 __GEN_COMMON_ENTRY system_reset
996 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
997 * to recover, but nested NMI will notice in_nmi and not recover
998 * because of the use of the NMI stack. in_nmi reentrancy is tested in
999 * system_reset_exception.
1001 lhz r10,PACA_IN_NMI(r13)
1003 sth r10,PACA_IN_NMI(r13)
1008 ld r1,PACA_NMI_EMERG_SP(r13)
1009 subi r1,r1,INT_FRAME_SIZE
1010 __GEN_COMMON_BODY system_reset
1012 * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does
1013 * the right thing. We do not want to reconcile because that goes
1014 * through irq tracing which we don't want in NMI.
1016 * Save PACAIRQHAPPENED to RESULT (otherwise unused), and set HARD_DIS
1017 * as we are running with MSR[EE]=0.
1019 li r10,IRQS_ALL_DISABLED
1020 stb r10,PACAIRQSOFTMASK(r13)
1021 lbz r10,PACAIRQHAPPENED(r13)
1023 ori r10,r10,PACA_IRQ_HARD_DIS
1024 stb r10,PACAIRQHAPPENED(r13)
1026 addi r3,r1,STACK_FRAME_OVERHEAD
1027 bl system_reset_exception
1029 /* Clear MSR_RI before setting SRR0 and SRR1. */
1034 * MSR_RI is clear, now we can decrement paca->in_nmi.
1036 lhz r10,PACA_IN_NMI(r13)
1038 sth r10,PACA_IN_NMI(r13)
1041 * Restore soft mask settings.
1044 stb r10,PACAIRQHAPPENED(r13)
1046 stb r10,PACAIRQSOFTMASK(r13)
1048 kuap_kernel_restore r9, r10
1049 EXCEPTION_RESTORE_REGS
1050 RFI_TO_USER_OR_KERNEL
1052 GEN_KVM system_reset
1056 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1057 * This is a non-maskable interrupt always taken in real-mode. It can be
1058 * synchronous or asynchronous, caused by hardware or software, and it may be
1059 * taken in a power-saving state.
1062 * Similarly to system reset, this uses its own stack and PACA save area,
1063 * the difference is re-entrancy is allowed on the machine check stack.
1065 * machine_check_early is run in real mode, and carefully decodes the
1066 * machine check and tries to handle it (e.g., flush the SLB if there was an
1067 * error detected there), determines if it was recoverable and logs the
1070 * This early code does not "reconcile" irq soft-mask state like SRESET or
1071 * regular interrupts do, so irqs_disabled() among other things may not work
1072 * properly (irq disable/enable already doesn't work because irq tracing can
1073 * not work in real mode).
1075 * Then, depending on the execution context when the interrupt is taken, there
1076 * are 3 main actions:
1077 * - Executing in kernel mode. The event is queued with irq_work, which means
1078 * it is handled when it is next safe to do so (i.e., the kernel has enabled
1079 * interrupts), which could be immediately when the interrupt returns. This
1080 * avoids nasty issues like switching to virtual mode when the MMU is in a
1081 * bad state, or when executing OPAL code. (SRESET is exposed to such issues,
1082 * but it has different priorities). Check to see if the CPU was in power
1083 * save, and return via the wake up code if it was.
1085 * - Executing in user mode. machine_check_exception is run like a normal
1086 * interrupt handler, which processes the data generated by the early handler.
1088 * - Executing in guest mode. The interrupt is run with its KVM test, and
1089 * branches to KVM to deal with. KVM may queue the event for the host
1092 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear,
1093 * or SCRATCH0 is in use, it may cause a crash.
1098 INT_DEFINE_BEGIN(machine_check_early)
1101 IVIRT=0 /* no virt entry point */
1104 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
1105 * nested machine check corrupts it. machine_check_common enables
1112 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1113 INT_DEFINE_END(machine_check_early)
1115 INT_DEFINE_BEGIN(machine_check)
1118 IVIRT=0 /* no virt entry point */
1124 INT_DEFINE_END(machine_check)
1126 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1127 GEN_INT_ENTRY machine_check_early, virt=0
1128 EXC_REAL_END(machine_check, 0x200, 0x100)
1129 EXC_VIRT_NONE(0x4200, 0x100)
1131 #ifdef CONFIG_PPC_PSERIES
1132 TRAMP_REAL_BEGIN(machine_check_fwnmi)
1133 /* See comment at machine_check exception, don't turn on RI */
1134 GEN_INT_ENTRY machine_check_early, virt=0
1137 #define MACHINE_CHECK_HANDLER_WINDUP \
1138 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1140 mtmsrd r9,1; /* Clear MSR_RI */ \
1141 /* Decrement paca->in_mce now RI is clear. */ \
1142 lhz r12,PACA_IN_MCE(r13); \
1144 sth r12,PACA_IN_MCE(r13); \
1145 EXCEPTION_RESTORE_REGS
1147 EXC_COMMON_BEGIN(machine_check_early_common)
1148 __GEN_REALMODE_COMMON_ENTRY machine_check_early
1151 * Switch to mc_emergency stack and handle re-entrancy (we limit
1152 * the nested MCE upto level 4 to avoid stack overflow).
1153 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
1155 * We use paca->in_mce to check whether this is the first entry or
1156 * nested machine check. We increment paca->in_mce to track nested
1159 * If this is the first entry then set stack pointer to
1160 * paca->mc_emergency_sp, otherwise r1 is already pointing to
1161 * stack frame on mc_emergency stack.
1163 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1164 * checkstop if we get another machine check exception before we do
1165 * rfid with MSR_ME=1.
1167 * This interrupt can wake directly from idle. If that is the case,
1168 * the machine check is handled then the idle wakeup code is called
1171 lhz r10,PACA_IN_MCE(r13)
1172 cmpwi r10,0 /* Are we in nested machine check */
1173 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */
1174 addi r10,r10,1 /* increment paca->in_mce */
1175 sth r10,PACA_IN_MCE(r13)
1177 mr r10,r1 /* Save r1 */
1179 /* First machine check entry */
1180 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
1181 1: /* Limit nested MCE to level 4 to avoid stack overflow */
1182 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
1183 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1185 __GEN_COMMON_BODY machine_check_early
1188 bl enable_machine_check
1189 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1194 * Set IRQS_ALL_DISABLED and save PACAIRQHAPPENED (see
1195 * system_reset_common)
1197 li r10,IRQS_ALL_DISABLED
1198 stb r10,PACAIRQSOFTMASK(r13)
1199 lbz r10,PACAIRQHAPPENED(r13)
1201 ori r10,r10,PACA_IRQ_HARD_DIS
1202 stb r10,PACAIRQHAPPENED(r13)
1204 addi r3,r1,STACK_FRAME_OVERHEAD
1205 bl machine_check_early
1206 std r3,RESULT(r1) /* Save result */
1210 * Restore soft mask settings.
1213 stb r10,PACAIRQHAPPENED(r13)
1215 stb r10,PACAIRQSOFTMASK(r13)
1217 #ifdef CONFIG_PPC_P7_NAP
1219 * Check if thread was in power saving mode. We come here when any
1220 * of the following is true:
1221 * a. thread wasn't in power saving mode
1222 * b. thread was in power saving mode with no state loss,
1223 * supervisor state loss or hypervisor state loss.
1225 * Go back to nap/sleep/winkle mode again if (b) is true.
1228 rlwinm. r11,r12,47-31,30,31
1229 bne machine_check_idle_common
1230 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1233 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1235 * Check if we are coming from guest. If yes, then run the normal
1236 * exception handler which will take the
1237 * machine_check_kvm->kvmppc_interrupt branch to deliver the MC event
1240 lbz r11,HSTATE_IN_GUEST(r13)
1241 cmpwi r11,0 /* Check if coming from guest */
1242 bne mce_deliver /* continue if we are. */
1246 * Check if we are coming from userspace. If yes, then run the normal
1247 * exception handler which will deliver the MC event to this kernel.
1249 andi. r11,r12,MSR_PR /* See if coming from user. */
1250 bne mce_deliver /* continue in V mode if we are. */
1253 * At this point we are coming from kernel context.
1254 * Queue up the MCE event and return from the interrupt.
1255 * But before that, check if this is an un-recoverable exception.
1256 * If yes, then stay on emergency stack and panic.
1258 andi. r11,r12,MSR_RI
1259 beq unrecoverable_mce
1262 * Check if we have successfully handled/recovered from error, if not
1263 * then stay on emergency stack and panic.
1265 ld r3,RESULT(r1) /* Load result */
1266 cmpdi r3,0 /* see if we handled MCE successfully */
1267 beq unrecoverable_mce /* if !handled then panic */
1270 * Return from MC interrupt.
1271 * Queue up the MCE event so that we can log it later, while
1272 * returning from kernel or opal call.
1274 bl machine_check_queue_event
1275 MACHINE_CHECK_HANDLER_WINDUP
1280 * This is a host user or guest MCE. Restore all registers, then
1281 * run the "late" handler. For host user, this will run the
1282 * machine_check_exception handler in virtual mode like a normal
1283 * interrupt handler. For guest, this will trigger the KVM test
1284 * and branch to the KVM interrupt similarly to other interrupts.
1287 ld r10,ORIG_GPR3(r1)
1289 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1290 MACHINE_CHECK_HANDLER_WINDUP
1291 GEN_INT_ENTRY machine_check, virt=0
1293 EXC_COMMON_BEGIN(machine_check_common)
1295 * Machine check is different because we use a different
1296 * save area: PACA_EXMC instead of PACA_EXGEN.
1298 GEN_COMMON machine_check
1301 /* Enable MSR_RI when finished with PACA_EXMC */
1304 addi r3,r1,STACK_FRAME_OVERHEAD
1305 bl machine_check_exception
1308 GEN_KVM machine_check
1311 #ifdef CONFIG_PPC_P7_NAP
1313 * This is an idle wakeup. Low level machine check has already been
1314 * done. Queue the event then call the idle code to do the wake up.
1316 EXC_COMMON_BEGIN(machine_check_idle_common)
1317 bl machine_check_queue_event
1320 * GPR-loss wakeups are relatively straightforward, because the
1321 * idle sleep code has saved all non-volatile registers on its
1322 * own stack, and r1 in PACAR1.
1324 * For no-loss wakeups the r1 and lr registers used by the
1325 * early machine check handler have to be restored first. r2 is
1326 * the kernel TOC, so no need to restore it.
1328 * Then decrement MCE nesting after finishing with the stack.
1334 lhz r11,PACA_IN_MCE(r13)
1336 sth r11,PACA_IN_MCE(r13)
1339 rlwinm r10,r3,47-31,30,31
1341 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1342 b idle_return_gpr_loss
1345 EXC_COMMON_BEGIN(unrecoverable_mce)
1347 * We are going down. But there are chances that we might get hit by
1348 * another MCE during panic path and we may run into unstable state
1349 * with no way out. Hence, turn ME bit off while going down, so that
1350 * when another MCE is hit during panic path, system will checkstop
1351 * and hypervisor will get restarted cleanly by SP.
1354 li r10,0 /* clear MSR_RI */
1356 bl disable_machine_check
1357 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1358 ld r10,PACAKMSR(r13)
1363 lhz r12,PACA_IN_MCE(r13)
1365 sth r12,PACA_IN_MCE(r13)
1367 /* Invoke machine_check_exception to print MCE event and panic. */
1368 addi r3,r1,STACK_FRAME_OVERHEAD
1369 bl machine_check_exception
1372 * We will not reach here. Even if we did, there is no way out.
1373 * Call unrecoverable_exception and die.
1375 addi r3,r1,STACK_FRAME_OVERHEAD
1376 bl unrecoverable_exception
1381 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1382 * This is a synchronous interrupt generated due to a data access exception,
1383 * e.g., a load orstore which does not have a valid page table entry with
1384 * permissions. DAWR matches also fault here, as do RC updates, and minor misc
1385 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc.
1389 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the
1390 * Linux page table. Hash faults can hit in kernel mode in a fairly
1391 * arbitrary state (e.g., interrupts disabled, locks held) when accessing
1392 * "non-bolted" regions, e.g., vmalloc space. However these should always be
1393 * backed by Linux page table entries.
1395 * If no entry is found the Linux page fault handler is invoked (by
1396 * do_hash_fault). Linux page faults can happen in kernel mode due to user
1397 * copy operations of course.
1399 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest
1400 * MMU context, which may cause a DSI in the host, which must go to the
1401 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will
1402 * always be used regardless of AIL setting.
1405 * The hardware loads from the Linux page table directly, so a fault goes
1406 * immediately to Linux page fault.
1408 * Conditions like DAWR match are handled on the way in to Linux page fault.
1410 INT_DEFINE_BEGIN(data_access)
1416 INT_DEFINE_END(data_access)
1418 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1419 GEN_INT_ENTRY data_access, virt=0
1420 EXC_REAL_END(data_access, 0x300, 0x80)
1421 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1422 GEN_INT_ENTRY data_access, virt=1
1423 EXC_VIRT_END(data_access, 0x4300, 0x80)
1424 EXC_COMMON_BEGIN(data_access_common)
1425 GEN_COMMON data_access
1427 addi r3,r1,STACK_FRAME_OVERHEAD
1428 andis. r0,r4,DSISR_DABRMATCH@h
1430 BEGIN_MMU_FTR_SECTION
1432 MMU_FTR_SECTION_ELSE
1434 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1439 * do_break() may have changed the NV GPRS while handling a breakpoint.
1440 * If so, we need to restore them with their updated values.
1449 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1450 * This is a synchronous interrupt in response to an MMU fault missing SLB
1451 * entry for HPT, or an address outside RPT translation range.
1455 * This refills the SLB, or reports an access fault similarly to a bad page
1456 * fault. When coming from user-mode, the SLB handler may access any kernel
1457 * data, though it may itself take a DSLB. When coming from kernel mode,
1458 * recursive faults must be avoided so access is restricted to the kernel
1459 * image text/data, kernel stack, and any data allocated below
1460 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping
1461 * on user-handler data structures.
1463 * KVM: Same as 0x300, DSLB must test for KVM guest.
1465 * A dedicated save area EXSLB is used (XXX: but it actually need not be
1466 * these days, we could use EXGEN).
1468 INT_DEFINE_BEGIN(data_access_slb)
1474 INT_DEFINE_END(data_access_slb)
1476 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1477 GEN_INT_ENTRY data_access_slb, virt=0
1478 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1479 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1480 GEN_INT_ENTRY data_access_slb, virt=1
1481 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1482 EXC_COMMON_BEGIN(data_access_slb_common)
1483 GEN_COMMON data_access_slb
1484 BEGIN_MMU_FTR_SECTION
1485 /* HPT case, do SLB fault */
1486 addi r3,r1,STACK_FRAME_OVERHEAD
1490 b fast_interrupt_return
1492 MMU_FTR_SECTION_ELSE
1493 /* Radix case, access is outside page table range */
1495 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1497 addi r3,r1,STACK_FRAME_OVERHEAD
1501 GEN_KVM data_access_slb
1505 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1506 * This is a synchronous interrupt in response to an MMU fault due to an
1507 * instruction fetch.
1510 * Similar to DSI, though in response to fetch. The faulting address is found
1511 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR).
1513 INT_DEFINE_BEGIN(instruction_access)
1518 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1521 INT_DEFINE_END(instruction_access)
1523 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1524 GEN_INT_ENTRY instruction_access, virt=0
1525 EXC_REAL_END(instruction_access, 0x400, 0x80)
1526 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1527 GEN_INT_ENTRY instruction_access, virt=1
1528 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1529 EXC_COMMON_BEGIN(instruction_access_common)
1530 GEN_COMMON instruction_access
1531 addi r3,r1,STACK_FRAME_OVERHEAD
1532 BEGIN_MMU_FTR_SECTION
1534 MMU_FTR_SECTION_ELSE
1536 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1539 GEN_KVM instruction_access
1543 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1544 * This is a synchronous interrupt in response to an MMU fault due to an
1545 * instruction fetch.
1548 * Similar to DSLB, though in response to fetch. The faulting address is found
1549 * in SRR0 (rather than DAR).
1551 INT_DEFINE_BEGIN(instruction_access_slb)
1556 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1559 INT_DEFINE_END(instruction_access_slb)
1561 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1562 GEN_INT_ENTRY instruction_access_slb, virt=0
1563 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1564 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1565 GEN_INT_ENTRY instruction_access_slb, virt=1
1566 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1567 EXC_COMMON_BEGIN(instruction_access_slb_common)
1568 GEN_COMMON instruction_access_slb
1569 BEGIN_MMU_FTR_SECTION
1570 /* HPT case, do SLB fault */
1571 addi r3,r1,STACK_FRAME_OVERHEAD
1575 b fast_interrupt_return
1577 MMU_FTR_SECTION_ELSE
1578 /* Radix case, access is outside page table range */
1580 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1582 addi r3,r1,STACK_FRAME_OVERHEAD
1586 GEN_KVM instruction_access_slb
1590 * Interrupt 0x500 - External Interrupt.
1591 * This is an asynchronous maskable interrupt in response to an "external
1592 * exception" from the interrupt controller or hypervisor (e.g., device
1593 * interrupt). It is maskable in hardware by clearing MSR[EE], and
1594 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()).
1596 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1597 * interrupts are delivered with HSRR registers, guests use SRRs, which
1598 * reqiures IHSRR_IF_HVMODE.
1600 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
1601 * external interrupts are delivered as Hypervisor Virtualization Interrupts
1602 * rather than External Interrupts.
1605 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead,
1606 * because registers at the time of the interrupt are not so important as it is
1609 * If soft masked, the masked handler will note the pending interrupt for
1610 * replay, and clear MSR[EE] in the interrupted context.
1612 INT_DEFINE_BEGIN(hardware_interrupt)
1618 INT_DEFINE_END(hardware_interrupt)
1620 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1621 GEN_INT_ENTRY hardware_interrupt, virt=0
1622 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1623 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1624 GEN_INT_ENTRY hardware_interrupt, virt=1
1625 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1626 EXC_COMMON_BEGIN(hardware_interrupt_common)
1627 GEN_COMMON hardware_interrupt
1630 addi r3,r1,STACK_FRAME_OVERHEAD
1634 GEN_KVM hardware_interrupt
1638 * Interrupt 0x600 - Alignment Interrupt
1639 * This is a synchronous interrupt in response to data alignment fault.
1641 INT_DEFINE_BEGIN(alignment)
1645 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1648 INT_DEFINE_END(alignment)
1650 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1651 GEN_INT_ENTRY alignment, virt=0
1652 EXC_REAL_END(alignment, 0x600, 0x100)
1653 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1654 GEN_INT_ENTRY alignment, virt=1
1655 EXC_VIRT_END(alignment, 0x4600, 0x100)
1656 EXC_COMMON_BEGIN(alignment_common)
1657 GEN_COMMON alignment
1658 addi r3,r1,STACK_FRAME_OVERHEAD
1659 bl alignment_exception
1660 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1667 * Interrupt 0x700 - Program Interrupt (program check).
1668 * This is a synchronous interrupt in response to various instruction faults:
1669 * traps, privilege errors, TM errors, floating point exceptions.
1672 * This interrupt may use the "emergency stack" in some cases when being taken
1673 * from kernel context, which complicates handling.
1675 INT_DEFINE_BEGIN(program_check)
1677 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1680 INT_DEFINE_END(program_check)
1682 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1683 GEN_INT_ENTRY program_check, virt=0
1684 EXC_REAL_END(program_check, 0x700, 0x100)
1685 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1686 GEN_INT_ENTRY program_check, virt=1
1687 EXC_VIRT_END(program_check, 0x4700, 0x100)
1688 EXC_COMMON_BEGIN(program_check_common)
1689 __GEN_COMMON_ENTRY program_check
1692 * It's possible to receive a TM Bad Thing type program check with
1693 * userspace register values (in particular r1), but with SRR1 reporting
1694 * that we came from the kernel. Normally that would confuse the bad
1695 * stack logic, and we would report a bad kernel stack pointer. Instead
1696 * we switch to the emergency stack if we're taking a TM Bad Thing from
1700 andi. r10,r12,MSR_PR
1701 bne 2f /* If userspace, go normal path */
1703 andis. r10,r12,(SRR1_PROGTM)@h
1704 bne 1f /* If TM, emergency */
1706 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */
1707 blt 2f /* normal path if not */
1709 /* Use the emergency stack */
1710 1: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */
1711 /* 3 in EXCEPTION_PROLOG_COMMON */
1712 mr r10,r1 /* Save r1 */
1713 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1714 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1715 __ISTACK(program_check)=0
1716 __GEN_COMMON_BODY program_check
1719 __ISTACK(program_check)=1
1720 __GEN_COMMON_BODY program_check
1722 addi r3,r1,STACK_FRAME_OVERHEAD
1723 bl program_check_exception
1724 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1727 GEN_KVM program_check
1731 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1732 * This is a synchronous interrupt in response to executing an fp instruction
1736 * This will load FP registers and enable the FP bit if coming from userspace,
1737 * otherwise report a bad kernel use of FP.
1739 INT_DEFINE_BEGIN(fp_unavailable)
1741 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1744 INT_DEFINE_END(fp_unavailable)
1746 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1747 GEN_INT_ENTRY fp_unavailable, virt=0
1748 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1749 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1750 GEN_INT_ENTRY fp_unavailable, virt=1
1751 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1752 EXC_COMMON_BEGIN(fp_unavailable_common)
1753 GEN_COMMON fp_unavailable
1754 bne 1f /* if from user, just load it up */
1755 addi r3,r1,STACK_FRAME_OVERHEAD
1756 bl kernel_fp_unavailable_exception
1758 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1760 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1762 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1763 * transaction), go do TM stuff
1765 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1767 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1770 b fast_interrupt_return
1771 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1772 2: /* User process was in a transaction */
1773 addi r3,r1,STACK_FRAME_OVERHEAD
1774 bl fp_unavailable_tm
1778 GEN_KVM fp_unavailable
1782 * Interrupt 0x900 - Decrementer Interrupt.
1783 * This is an asynchronous interrupt in response to a decrementer exception
1784 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing
1785 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e.,
1786 * local_irq_disable()).
1789 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1791 * If soft masked, the masked handler will note the pending interrupt for
1792 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled
1793 * in the interrupted context.
1794 * If PPC_WATCHDOG is configured, the soft masked handler will actually set
1795 * things back up to run soft_nmi_interrupt as a regular interrupt handler
1796 * on the emergency stack.
1798 INT_DEFINE_BEGIN(decrementer)
1801 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1804 INT_DEFINE_END(decrementer)
1806 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1807 GEN_INT_ENTRY decrementer, virt=0
1808 EXC_REAL_END(decrementer, 0x900, 0x80)
1809 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1810 GEN_INT_ENTRY decrementer, virt=1
1811 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1812 EXC_COMMON_BEGIN(decrementer_common)
1813 GEN_COMMON decrementer
1816 addi r3,r1,STACK_FRAME_OVERHEAD
1824 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1825 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1829 * Linux does not use this outside KVM where it's used to keep a host timer
1830 * while the guest is given control of DEC. It should normally be caught by
1831 * the KVM test and routed there.
1833 INT_DEFINE_BEGIN(hdecrementer)
1839 INT_DEFINE_END(hdecrementer)
1841 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1842 GEN_INT_ENTRY hdecrementer, virt=0
1843 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1844 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1845 GEN_INT_ENTRY hdecrementer, virt=1
1846 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1847 EXC_COMMON_BEGIN(hdecrementer_common)
1848 __GEN_COMMON_ENTRY hdecrementer
1850 * Hypervisor decrementer interrupts not caught by the KVM test
1851 * shouldn't occur but are sometimes left pending on exit from a KVM
1852 * guest. We don't need to do anything to clear them, as they are
1855 * Be careful to avoid touching the kernel stack.
1857 ld r10,PACA_EXGEN+EX_CTR(r13)
1860 ld r9,PACA_EXGEN+EX_R9(r13)
1861 ld r10,PACA_EXGEN+EX_R10(r13)
1862 ld r11,PACA_EXGEN+EX_R11(r13)
1863 ld r12,PACA_EXGEN+EX_R12(r13)
1864 ld r13,PACA_EXGEN+EX_R13(r13)
1867 GEN_KVM hdecrementer
1871 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1872 * This is an asynchronous interrupt in response to a msgsndp doorbell.
1873 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
1874 * IRQS_DISABLED mask (i.e., local_irq_disable()).
1877 * Guests may use this for IPIs between threads in a core if the
1878 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1880 * If soft masked, the masked handler will note the pending interrupt for
1881 * replay, leaving MSR[EE] enabled in the interrupted context because the
1882 * doorbells are edge triggered.
1884 INT_DEFINE_BEGIN(doorbell_super)
1887 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1890 INT_DEFINE_END(doorbell_super)
1892 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1893 GEN_INT_ENTRY doorbell_super, virt=0
1894 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1895 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1896 GEN_INT_ENTRY doorbell_super, virt=1
1897 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1898 EXC_COMMON_BEGIN(doorbell_super_common)
1899 GEN_COMMON doorbell_super
1902 addi r3,r1,STACK_FRAME_OVERHEAD
1903 #ifdef CONFIG_PPC_DOORBELL
1904 bl doorbell_exception
1906 bl unknown_async_exception
1910 GEN_KVM doorbell_super
1913 EXC_REAL_NONE(0xb00, 0x100)
1914 EXC_VIRT_NONE(0x4b00, 0x100)
1917 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1918 * This is a synchronous interrupt invoked with the "sc" instruction. The
1919 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1920 * is directed to the currently running OS. The hypercall is invoked with
1921 * "sc 1" and it sets HV=1, so it elevates to hypervisor.
1923 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1924 * 0x4c00 virtual mode.
1927 * If the KVM test fires then it was due to a hypercall and is accordingly
1928 * routed to KVM. Otherwise this executes a normal Linux system call.
1932 * syscall and hypercalls register conventions are documented in
1933 * Documentation/powerpc/syscall64-abi.rst and
1934 * Documentation/powerpc/papr_hcalls.rst respectively.
1936 * The intersection of volatile registers that don't contain possible
1937 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1938 * without saving, though xer is not a good idea to use, as hardware may
1939 * interpret some bits so it may be costly to change them.
1941 INT_DEFINE_BEGIN(system_call)
1945 INT_DEFINE_END(system_call)
1947 .macro SYSTEM_CALL virt
1948 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1950 * There is a little bit of juggling to get syscall and hcall
1951 * working well. Save r13 in ctr to avoid using SPRG scratch
1954 * Userspace syscalls have already saved the PPR, hcalls must save
1955 * it before setting HMT_MEDIUM.
1959 std r10,PACA_EXGEN+EX_R10(r13)
1961 KVMTEST system_call /* uses r10, branch to system_call_kvm */
1969 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1973 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1976 /* We reach here with PACA in r13, r13 in r9. */
1983 __LOAD_HANDLER(r10, system_call_common)
1985 ld r10,PACAKMSR(r13)
1988 b . /* prevent speculative execution */
1991 mtmsrd r10,1 /* Set RI (EE=0) */
1992 #ifdef CONFIG_RELOCATABLE
1993 __LOAD_HANDLER(r10, system_call_common)
1997 b system_call_common
2001 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
2002 /* Fast LE/BE switch system call */
2003 1: mfspr r12,SPRN_SRR1
2007 RFI_TO_USER /* return to userspace */
2008 b . /* prevent speculative execution */
2012 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
2014 EXC_REAL_END(system_call, 0xc00, 0x100)
2015 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2017 EXC_VIRT_END(system_call, 0x4c00, 0x100)
2019 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2020 TRAMP_REAL_BEGIN(system_call_kvm)
2022 * This is a hcall, so register convention is as above, with these
2026 * orig r10 saved in PACA
2029 * Save the PPR (on systems that support it) before changing to
2030 * HMT_MEDIUM. That allows the KVM code to save that value into the
2031 * guest state (it is the guest's PPR value).
2035 std r10,HSTATE_PPR(r13)
2036 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2041 std r12,HSTATE_SCRATCH0(r13)
2044 #ifdef CONFIG_RELOCATABLE
2046 * Requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives
2047 * outside the head section.
2049 __LOAD_FAR_HANDLER(r10, kvmppc_interrupt)
2051 ld r10,PACA_EXGEN+EX_R10(r13)
2054 ld r10,PACA_EXGEN+EX_R10(r13)
2061 * Interrupt 0xd00 - Trace Interrupt.
2062 * This is a synchronous interrupt in response to instruction step or
2063 * breakpoint faults.
2065 INT_DEFINE_BEGIN(single_step)
2067 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2070 INT_DEFINE_END(single_step)
2072 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2073 GEN_INT_ENTRY single_step, virt=0
2074 EXC_REAL_END(single_step, 0xd00, 0x100)
2075 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2076 GEN_INT_ENTRY single_step, virt=1
2077 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2078 EXC_COMMON_BEGIN(single_step_common)
2079 GEN_COMMON single_step
2080 addi r3,r1,STACK_FRAME_OVERHEAD
2081 bl single_step_exception
2088 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2089 * This is a synchronous interrupt in response to an MMU fault caused by a
2090 * guest data access.
2093 * This should always get routed to KVM. In radix MMU mode, this is caused
2094 * by a guest nested radix access that can't be performed due to the
2095 * partition scope page table. In hash mode, this can be caused by guests
2096 * running with translation disabled (virtual real mode) or with VPM enabled.
2097 * KVM will update the page table structures or disallow the access.
2099 INT_DEFINE_BEGIN(h_data_storage)
2107 INT_DEFINE_END(h_data_storage)
2109 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2110 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2111 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2112 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2113 GEN_INT_ENTRY h_data_storage, virt=1, ool=1
2114 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2115 EXC_COMMON_BEGIN(h_data_storage_common)
2116 GEN_COMMON h_data_storage
2117 addi r3,r1,STACK_FRAME_OVERHEAD
2118 BEGIN_MMU_FTR_SECTION
2119 bl do_bad_page_fault_segv
2120 MMU_FTR_SECTION_ELSE
2121 bl unknown_exception
2122 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2125 GEN_KVM h_data_storage
2129 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2130 * This is a synchronous interrupt in response to an MMU fault caused by a
2131 * guest instruction fetch, similar to HDSI.
2133 INT_DEFINE_BEGIN(h_instr_storage)
2138 INT_DEFINE_END(h_instr_storage)
2140 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2141 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2142 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2143 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2144 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1
2145 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2146 EXC_COMMON_BEGIN(h_instr_storage_common)
2147 GEN_COMMON h_instr_storage
2148 addi r3,r1,STACK_FRAME_OVERHEAD
2149 bl unknown_exception
2152 GEN_KVM h_instr_storage
2156 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2158 INT_DEFINE_BEGIN(emulation_assist)
2163 INT_DEFINE_END(emulation_assist)
2165 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2166 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2167 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2168 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2169 GEN_INT_ENTRY emulation_assist, virt=1, ool=1
2170 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2171 EXC_COMMON_BEGIN(emulation_assist_common)
2172 GEN_COMMON emulation_assist
2173 addi r3,r1,STACK_FRAME_OVERHEAD
2174 bl emulation_assist_interrupt
2175 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2178 GEN_KVM emulation_assist
2182 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2183 * This is an asynchronous interrupt caused by a Hypervisor Maintenance
2184 * Exception. It is always taken in real mode but uses HSRR registers
2185 * unlike SRESET and MCE.
2187 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable
2188 * with IRQS_DISABLED mask (i.e., local_irq_disable()).
2191 * This is a special case, this is handled similarly to machine checks, with an
2192 * initial real mode handler that is not soft-masked, which attempts to fix the
2193 * problem. Then a regular handler which is soft-maskable and reports the
2196 * The emergency stack is used for the early real mode handler.
2198 * XXX: unclear why MCE and HMI schemes could not be made common, e.g.,
2199 * either use soft-masking for the MCE, or use irq_work for the HMI.
2202 * Unlike MCE, this calls into KVM without calling the real mode handler
2205 INT_DEFINE_BEGIN(hmi_exception_early)
2210 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2212 INT_DEFINE_END(hmi_exception_early)
2214 INT_DEFINE_BEGIN(hmi_exception)
2219 INT_DEFINE_END(hmi_exception)
2221 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2222 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2223 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2224 EXC_VIRT_NONE(0x4e60, 0x20)
2226 EXC_COMMON_BEGIN(hmi_exception_early_common)
2227 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early
2229 mr r10,r1 /* Save r1 */
2230 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
2231 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
2233 __GEN_COMMON_BODY hmi_exception_early
2235 addi r3,r1,STACK_FRAME_OVERHEAD
2236 bl hmi_exception_realmode
2240 EXCEPTION_RESTORE_REGS hsrr=1
2241 HRFI_TO_USER_OR_KERNEL
2245 * Go to virtual mode and pull the HMI event information from
2248 EXCEPTION_RESTORE_REGS hsrr=1
2249 GEN_INT_ENTRY hmi_exception, virt=0
2251 GEN_KVM hmi_exception_early
2253 EXC_COMMON_BEGIN(hmi_exception_common)
2254 GEN_COMMON hmi_exception
2257 addi r3,r1,STACK_FRAME_OVERHEAD
2258 bl handle_hmi_exception
2261 GEN_KVM hmi_exception
2265 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2266 * This is an asynchronous interrupt in response to a msgsnd doorbell.
2267 * Similar to the 0xa00 doorbell but for host rather than guest.
2269 INT_DEFINE_BEGIN(h_doorbell)
2275 INT_DEFINE_END(h_doorbell)
2277 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2278 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2279 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2280 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2281 GEN_INT_ENTRY h_doorbell, virt=1, ool=1
2282 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2283 EXC_COMMON_BEGIN(h_doorbell_common)
2284 GEN_COMMON h_doorbell
2287 addi r3,r1,STACK_FRAME_OVERHEAD
2288 #ifdef CONFIG_PPC_DOORBELL
2289 bl doorbell_exception
2291 bl unknown_async_exception
2299 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2300 * This is an asynchronous interrupt in response to an "external exception".
2301 * Similar to 0x500 but for host only.
2303 INT_DEFINE_BEGIN(h_virt_irq)
2309 INT_DEFINE_END(h_virt_irq)
2311 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2312 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2313 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2314 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2315 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1
2316 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2317 EXC_COMMON_BEGIN(h_virt_irq_common)
2318 GEN_COMMON h_virt_irq
2321 addi r3,r1,STACK_FRAME_OVERHEAD
2328 EXC_REAL_NONE(0xec0, 0x20)
2329 EXC_VIRT_NONE(0x4ec0, 0x20)
2330 EXC_REAL_NONE(0xee0, 0x20)
2331 EXC_VIRT_NONE(0x4ee0, 0x20)
2335 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2336 * This is an asynchronous interrupt in response to a PMU exception.
2337 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
2338 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()).
2341 * This calls into the perf subsystem.
2343 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it
2344 * runs under local_irq_disable. However it may be soft-masked in
2345 * powerpc-specific code.
2347 * If soft masked, the masked handler will note the pending interrupt for
2348 * replay, and clear MSR[EE] in the interrupted context.
2350 INT_DEFINE_BEGIN(performance_monitor)
2352 IMASK=IRQS_PMI_DISABLED
2353 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2356 INT_DEFINE_END(performance_monitor)
2358 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2359 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2360 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2361 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2362 GEN_INT_ENTRY performance_monitor, virt=1, ool=1
2363 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2364 EXC_COMMON_BEGIN(performance_monitor_common)
2365 GEN_COMMON performance_monitor
2368 addi r3,r1,STACK_FRAME_OVERHEAD
2369 bl performance_monitor_exception
2372 GEN_KVM performance_monitor
2376 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2377 * This is a synchronous interrupt in response to
2378 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2379 * Similar to FP unavailable.
2381 INT_DEFINE_BEGIN(altivec_unavailable)
2383 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2386 INT_DEFINE_END(altivec_unavailable)
2388 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2389 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2390 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2391 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2392 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1
2393 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2394 EXC_COMMON_BEGIN(altivec_unavailable_common)
2395 GEN_COMMON altivec_unavailable
2396 #ifdef CONFIG_ALTIVEC
2399 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2400 BEGIN_FTR_SECTION_NESTED(69)
2401 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2402 * transaction), go do TM stuff
2404 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2406 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2409 b fast_interrupt_return
2410 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2411 2: /* User process was in a transaction */
2412 addi r3,r1,STACK_FRAME_OVERHEAD
2413 bl altivec_unavailable_tm
2417 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2419 addi r3,r1,STACK_FRAME_OVERHEAD
2420 bl altivec_unavailable_exception
2423 GEN_KVM altivec_unavailable
2427 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2428 * This is a synchronous interrupt in response to
2429 * executing a VSX instruction with MSR[VSX]=0.
2430 * Similar to FP unavailable.
2432 INT_DEFINE_BEGIN(vsx_unavailable)
2434 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2437 INT_DEFINE_END(vsx_unavailable)
2439 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2440 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2441 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2442 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2443 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1
2444 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2445 EXC_COMMON_BEGIN(vsx_unavailable_common)
2446 GEN_COMMON vsx_unavailable
2450 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2451 BEGIN_FTR_SECTION_NESTED(69)
2452 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2453 * transaction), go do TM stuff
2455 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2457 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2460 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2461 2: /* User process was in a transaction */
2462 addi r3,r1,STACK_FRAME_OVERHEAD
2463 bl vsx_unavailable_tm
2467 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2469 addi r3,r1,STACK_FRAME_OVERHEAD
2470 bl vsx_unavailable_exception
2473 GEN_KVM vsx_unavailable
2477 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2478 * This is a synchronous interrupt in response to
2479 * executing an instruction without access to the facility that can be
2480 * resolved by the OS (e.g., FSCR, MSR).
2481 * Similar to FP unavailable.
2483 INT_DEFINE_BEGIN(facility_unavailable)
2485 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2488 INT_DEFINE_END(facility_unavailable)
2490 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2491 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2492 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2493 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2494 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1
2495 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2496 EXC_COMMON_BEGIN(facility_unavailable_common)
2497 GEN_COMMON facility_unavailable
2498 addi r3,r1,STACK_FRAME_OVERHEAD
2499 bl facility_unavailable_exception
2500 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2503 GEN_KVM facility_unavailable
2507 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2508 * This is a synchronous interrupt in response to
2509 * executing an instruction without access to the facility that can only
2510 * be resolved in HV mode (e.g., HFSCR).
2511 * Similar to FP unavailable.
2513 INT_DEFINE_BEGIN(h_facility_unavailable)
2518 INT_DEFINE_END(h_facility_unavailable)
2520 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2521 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2522 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2523 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2524 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1
2525 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2526 EXC_COMMON_BEGIN(h_facility_unavailable_common)
2527 GEN_COMMON h_facility_unavailable
2528 addi r3,r1,STACK_FRAME_OVERHEAD
2529 bl facility_unavailable_exception
2530 REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */
2533 GEN_KVM h_facility_unavailable
2536 EXC_REAL_NONE(0xfa0, 0x20)
2537 EXC_VIRT_NONE(0x4fa0, 0x20)
2538 EXC_REAL_NONE(0xfc0, 0x20)
2539 EXC_VIRT_NONE(0x4fc0, 0x20)
2540 EXC_REAL_NONE(0xfe0, 0x20)
2541 EXC_VIRT_NONE(0x4fe0, 0x20)
2543 EXC_REAL_NONE(0x1000, 0x100)
2544 EXC_VIRT_NONE(0x5000, 0x100)
2545 EXC_REAL_NONE(0x1100, 0x100)
2546 EXC_VIRT_NONE(0x5100, 0x100)
2548 #ifdef CONFIG_CBE_RAS
2549 INT_DEFINE_BEGIN(cbe_system_error)
2554 INT_DEFINE_END(cbe_system_error)
2556 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2557 GEN_INT_ENTRY cbe_system_error, virt=0
2558 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2559 EXC_VIRT_NONE(0x5200, 0x100)
2560 EXC_COMMON_BEGIN(cbe_system_error_common)
2561 GEN_COMMON cbe_system_error
2562 addi r3,r1,STACK_FRAME_OVERHEAD
2563 bl cbe_system_error_exception
2566 GEN_KVM cbe_system_error
2568 #else /* CONFIG_CBE_RAS */
2569 EXC_REAL_NONE(0x1200, 0x100)
2570 EXC_VIRT_NONE(0x5200, 0x100)
2574 INT_DEFINE_BEGIN(instruction_breakpoint)
2576 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2580 INT_DEFINE_END(instruction_breakpoint)
2582 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2583 GEN_INT_ENTRY instruction_breakpoint, virt=0
2584 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2585 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2586 GEN_INT_ENTRY instruction_breakpoint, virt=1
2587 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2588 EXC_COMMON_BEGIN(instruction_breakpoint_common)
2589 GEN_COMMON instruction_breakpoint
2590 addi r3,r1,STACK_FRAME_OVERHEAD
2591 bl instruction_breakpoint_exception
2594 GEN_KVM instruction_breakpoint
2597 EXC_REAL_NONE(0x1400, 0x100)
2598 EXC_VIRT_NONE(0x5400, 0x100)
2601 * Interrupt 0x1500 - Soft Patch Interrupt
2604 * This is an implementation specific interrupt which can be used for a
2605 * range of exceptions.
2607 * This interrupt handler is unique in that it runs the denormal assist
2608 * code even for guests (and even in guest context) without going to KVM,
2609 * for speed. POWER9 does not raise denorm exceptions, so this special case
2610 * could be phased out in future to reduce special cases.
2612 INT_DEFINE_BEGIN(denorm_exception)
2617 INT_DEFINE_END(denorm_exception)
2619 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2620 GEN_INT_ENTRY denorm_exception, virt=0
2621 #ifdef CONFIG_PPC_DENORMALISATION
2622 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2625 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2626 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2627 #ifdef CONFIG_PPC_DENORMALISATION
2628 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2629 GEN_INT_ENTRY denorm_exception, virt=1
2630 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2632 GEN_BRANCH_TO_COMMON denorm_exception, virt=1
2633 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2635 EXC_VIRT_NONE(0x5500, 0x100)
2638 #ifdef CONFIG_PPC_DENORMALISATION
2639 TRAMP_REAL_BEGIN(denorm_assist)
2642 * To denormalise we need to move a copy of the register to itself.
2643 * For POWER6 do that here for all FP regs.
2646 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2647 xori r10,r10,(MSR_FE0|MSR_FE1)
2659 * To denormalise we need to move a copy of the register to itself.
2660 * For POWER7 do that here for the first 32 VSX registers only.
2663 oris r10,r10,MSR_VSX@h
2669 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2673 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2677 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2679 * To denormalise we need to move a copy of the register to itself.
2680 * For POWER8 we need to do that for all 64 VSX registers
2684 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2689 mfspr r11,SPRN_HSRR0
2691 mtspr SPRN_HSRR0,r11
2693 ld r9,PACA_EXGEN+EX_R9(r13)
2695 ld r10,PACA_EXGEN+EX_PPR(r13)
2697 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2699 ld r10,PACA_EXGEN+EX_CFAR(r13)
2701 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2702 ld r10,PACA_EXGEN+EX_R10(r13)
2703 ld r11,PACA_EXGEN+EX_R11(r13)
2704 ld r12,PACA_EXGEN+EX_R12(r13)
2705 ld r13,PACA_EXGEN+EX_R13(r13)
2710 EXC_COMMON_BEGIN(denorm_exception_common)
2711 GEN_COMMON denorm_exception
2712 addi r3,r1,STACK_FRAME_OVERHEAD
2713 bl unknown_exception
2716 GEN_KVM denorm_exception
2719 #ifdef CONFIG_CBE_RAS
2720 INT_DEFINE_BEGIN(cbe_maintenance)
2725 INT_DEFINE_END(cbe_maintenance)
2727 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2728 GEN_INT_ENTRY cbe_maintenance, virt=0
2729 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2730 EXC_VIRT_NONE(0x5600, 0x100)
2731 EXC_COMMON_BEGIN(cbe_maintenance_common)
2732 GEN_COMMON cbe_maintenance
2733 addi r3,r1,STACK_FRAME_OVERHEAD
2734 bl cbe_maintenance_exception
2737 GEN_KVM cbe_maintenance
2739 #else /* CONFIG_CBE_RAS */
2740 EXC_REAL_NONE(0x1600, 0x100)
2741 EXC_VIRT_NONE(0x5600, 0x100)
2745 INT_DEFINE_BEGIN(altivec_assist)
2747 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2750 INT_DEFINE_END(altivec_assist)
2752 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2753 GEN_INT_ENTRY altivec_assist, virt=0
2754 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2755 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2756 GEN_INT_ENTRY altivec_assist, virt=1
2757 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2758 EXC_COMMON_BEGIN(altivec_assist_common)
2759 GEN_COMMON altivec_assist
2760 addi r3,r1,STACK_FRAME_OVERHEAD
2761 #ifdef CONFIG_ALTIVEC
2762 bl altivec_assist_exception
2763 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2765 bl unknown_exception
2769 GEN_KVM altivec_assist
2772 #ifdef CONFIG_CBE_RAS
2773 INT_DEFINE_BEGIN(cbe_thermal)
2778 INT_DEFINE_END(cbe_thermal)
2780 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2781 GEN_INT_ENTRY cbe_thermal, virt=0
2782 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2783 EXC_VIRT_NONE(0x5800, 0x100)
2784 EXC_COMMON_BEGIN(cbe_thermal_common)
2785 GEN_COMMON cbe_thermal
2786 addi r3,r1,STACK_FRAME_OVERHEAD
2787 bl cbe_thermal_exception
2792 #else /* CONFIG_CBE_RAS */
2793 EXC_REAL_NONE(0x1800, 0x100)
2794 EXC_VIRT_NONE(0x5800, 0x100)
2798 #ifdef CONFIG_PPC_WATCHDOG
2800 INT_DEFINE_BEGIN(soft_nmi)
2803 INT_DEFINE_END(soft_nmi)
2806 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2807 * stack is one that is usable by maskable interrupts so long as MSR_EE
2808 * remains off. It is used for recovery when something has corrupted the
2809 * normal kernel stack, for example. The "soft NMI" must not use the process
2810 * stack because we want irq disabled sections to avoid touching the stack
2811 * at all (other than PMU interrupts), so use the emergency stack for this,
2812 * and run it entirely with interrupts hard disabled.
2814 EXC_COMMON_BEGIN(soft_nmi_common)
2817 ld r1,PACAEMERGSP(r13)
2818 subi r1,r1,INT_FRAME_SIZE
2819 __GEN_COMMON_BODY soft_nmi
2822 * Set IRQS_ALL_DISABLED and save PACAIRQHAPPENED (see
2823 * system_reset_common)
2825 li r10,IRQS_ALL_DISABLED
2826 stb r10,PACAIRQSOFTMASK(r13)
2827 lbz r10,PACAIRQHAPPENED(r13)
2829 ori r10,r10,PACA_IRQ_HARD_DIS
2830 stb r10,PACAIRQHAPPENED(r13)
2832 addi r3,r1,STACK_FRAME_OVERHEAD
2833 bl soft_nmi_interrupt
2835 /* Clear MSR_RI before setting SRR0 and SRR1. */
2840 * Restore soft mask settings.
2843 stb r10,PACAIRQHAPPENED(r13)
2845 stb r10,PACAIRQSOFTMASK(r13)
2847 kuap_kernel_restore r9, r10
2848 EXCEPTION_RESTORE_REGS hsrr=0
2851 #endif /* CONFIG_PPC_WATCHDOG */
2854 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2855 * - If it was a decrementer interrupt, we bump the dec to max and and return.
2856 * - If it was a doorbell we return immediately since doorbells are edge
2857 * triggered and won't automatically refire.
2858 * - If it was a HMI we return immediately since we handled it in realmode
2859 * and it won't refire.
2860 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2861 * This is called with r10 containing the value to OR to the paca field.
2863 .macro MASKED_INTERRUPT hsrr=0
2869 lbz r11,PACAIRQHAPPENED(r13)
2871 stb r11,PACAIRQHAPPENED(r13)
2872 cmpwi r10,PACA_IRQ_DEC
2877 #ifdef CONFIG_PPC_WATCHDOG
2882 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2884 xori r12,r12,MSR_EE /* clear MSR_EE */
2886 mtspr SPRN_HSRR1,r12
2890 ori r11,r11,PACA_IRQ_HARD_DIS
2891 stb r11,PACAIRQHAPPENED(r13)
2893 ld r10,PACA_EXGEN+EX_CTR(r13)
2897 ld r9,PACA_EXGEN+EX_R9(r13)
2898 ld r10,PACA_EXGEN+EX_R10(r13)
2899 ld r11,PACA_EXGEN+EX_R11(r13)
2900 ld r12,PACA_EXGEN+EX_R12(r13)
2901 ld r13,PACA_EXGEN+EX_R13(r13)
2902 /* May return to masked low address where r13 is not set up */
2911 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2912 std r9,PACA_EXRFI+EX_R9(r13)
2913 std r10,PACA_EXRFI+EX_R10(r13)
2915 ld r9,PACA_EXRFI+EX_R9(r13)
2916 ld r10,PACA_EXRFI+EX_R10(r13)
2924 /* Clobbers r10, r11, ctr */
2925 .macro L1D_DISPLACEMENT_FLUSH
2926 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2927 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2928 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2930 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2932 /* order ld/st prior to dcbt stop all streams with flushing */
2936 * The load addresses are at staggered offsets within cachelines,
2937 * which suits some pipelines better (on others it should not
2941 ld r11,(0x80 + 8)*0(r10)
2942 ld r11,(0x80 + 8)*1(r10)
2943 ld r11,(0x80 + 8)*2(r10)
2944 ld r11,(0x80 + 8)*3(r10)
2945 ld r11,(0x80 + 8)*4(r10)
2946 ld r11,(0x80 + 8)*5(r10)
2947 ld r11,(0x80 + 8)*6(r10)
2948 ld r11,(0x80 + 8)*7(r10)
2953 TRAMP_REAL_BEGIN(entry_flush_fallback)
2954 std r9,PACA_EXRFI+EX_R9(r13)
2955 std r10,PACA_EXRFI+EX_R10(r13)
2956 std r11,PACA_EXRFI+EX_R11(r13)
2958 L1D_DISPLACEMENT_FLUSH
2960 ld r9,PACA_EXRFI+EX_R9(r13)
2961 ld r10,PACA_EXRFI+EX_R10(r13)
2962 ld r11,PACA_EXRFI+EX_R11(r13)
2965 TRAMP_REAL_BEGIN(rfi_flush_fallback)
2968 std r1,PACA_EXRFI+EX_R12(r13)
2969 ld r1,PACAKSAVE(r13)
2970 std r9,PACA_EXRFI+EX_R9(r13)
2971 std r10,PACA_EXRFI+EX_R10(r13)
2972 std r11,PACA_EXRFI+EX_R11(r13)
2974 L1D_DISPLACEMENT_FLUSH
2976 ld r9,PACA_EXRFI+EX_R9(r13)
2977 ld r10,PACA_EXRFI+EX_R10(r13)
2978 ld r11,PACA_EXRFI+EX_R11(r13)
2979 ld r1,PACA_EXRFI+EX_R12(r13)
2983 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2986 std r1,PACA_EXRFI+EX_R12(r13)
2987 ld r1,PACAKSAVE(r13)
2988 std r9,PACA_EXRFI+EX_R9(r13)
2989 std r10,PACA_EXRFI+EX_R10(r13)
2990 std r11,PACA_EXRFI+EX_R11(r13)
2992 L1D_DISPLACEMENT_FLUSH
2994 ld r9,PACA_EXRFI+EX_R9(r13)
2995 ld r10,PACA_EXRFI+EX_R10(r13)
2996 ld r11,PACA_EXRFI+EX_R11(r13)
2997 ld r1,PACA_EXRFI+EX_R12(r13)
3001 TRAMP_REAL_BEGIN(rfscv_flush_fallback)
3002 /* system call volatile */
3006 ld r1,PACAKSAVE(r13)
3008 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
3009 ld r11,PACA_L1D_FLUSH_SIZE(r13)
3010 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
3012 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
3014 /* order ld/st prior to dcbt stop all streams with flushing */
3018 * The load adresses are at staggered offsets within cachelines,
3019 * which suits some pipelines better (on others it should not
3023 ld r11,(0x80 + 8)*0(r10)
3024 ld r11,(0x80 + 8)*1(r10)
3025 ld r11,(0x80 + 8)*2(r10)
3026 ld r11,(0x80 + 8)*3(r10)
3027 ld r11,(0x80 + 8)*4(r10)
3028 ld r11,(0x80 + 8)*5(r10)
3029 ld r11,(0x80 + 8)*6(r10)
3030 ld r11,(0x80 + 8)*7(r10)
3044 _GLOBAL(do_uaccess_flush)
3045 UACCESS_FLUSH_FIXUP_SECTION
3050 L1D_DISPLACEMENT_FLUSH
3052 _ASM_NOKPROBE_SYMBOL(do_uaccess_flush)
3053 EXPORT_SYMBOL(do_uaccess_flush)
3057 MASKED_INTERRUPT hsrr=1
3059 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
3060 kvmppc_skip_interrupt:
3062 * Here all GPRs are unchanged from when the interrupt happened
3063 * except for r13, which is saved in SPRG_SCRATCH0.
3065 mfspr r13, SPRN_SRR0
3067 mtspr SPRN_SRR0, r13
3072 kvmppc_skip_Hinterrupt:
3074 * Here all GPRs are unchanged from when the interrupt happened
3075 * except for r13, which is saved in SPRG_SCRATCH0.
3077 mfspr r13, SPRN_HSRR0
3079 mtspr SPRN_HSRR0, r13
3086 * Relocation-on interrupts: A subset of the interrupts can be delivered
3087 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
3088 * it. Addresses are the same as the original interrupt addresses, but
3089 * offset by 0xc000000000004000.
3090 * It's impossible to receive interrupts below 0x300 via this mechanism.
3091 * KVM: None of these traps are from the guest ; anything that escalated
3092 * to HV=1 from HV=0 is delivered via real mode handlers.
3096 * This uses the standard macro, since the original 0x300 vector
3097 * only has extra guff for STAB-based processors -- which never
3101 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
3102 b __ppc64_runlatch_on
3104 USE_FIXED_SECTION(virt_trampolines)
3106 * All code below __end_interrupts is treated as soft-masked. If
3107 * any code runs here with MSR[EE]=1, it must then cope with pending
3108 * soft interrupt being raised (i.e., by ensuring it is replayed).
3110 * The __end_interrupts marker must be past the out-of-line (OOL)
3111 * handlers, so that they are copied to real address 0x100 when running
3112 * a relocatable kernel. This ensures they can be reached from the short
3113 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3114 * directly, without using LOAD_HANDLER().
3117 .globl __end_interrupts
3119 DEFINE_FIXED_SYMBOL(__end_interrupts)
3121 #ifdef CONFIG_PPC_970_NAP
3123 * Called by exception entry code if _TLF_NAPPING was set, this clears
3124 * the NAPPING flag, and redirects the exception exit to
3125 * power4_fixup_nap_return.
3127 .globl power4_fixup_nap
3128 EXC_COMMON_BEGIN(power4_fixup_nap)
3130 std r9,TI_LOCAL_FLAGS(r11)
3131 LOAD_REG_ADDR(r10, power4_idle_nap_return)
3135 power4_idle_nap_return:
3139 CLOSE_FIXED_SECTION(real_vectors);
3140 CLOSE_FIXED_SECTION(real_trampolines);
3141 CLOSE_FIXED_SECTION(virt_vectors);
3142 CLOSE_FIXED_SECTION(virt_trampolines);
3146 /* MSR[RI] should be clear because this uses SRR[01] */
3147 enable_machine_check:
3151 addi r3,r3,(1f - 0b)
3160 /* MSR[RI] should be clear because this uses SRR[01] */
3161 disable_machine_check:
3165 addi r3,r3,(1f - 0b)