1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
24 /* PACA save area offsets (exgen, exmc, etc) */
37 .error "EX_SIZE is wrong"
41 * Following are fixed section helper macros.
43 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors
44 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors
45 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these)
46 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use)
47 * EXC_COMMON - After switching to virtual, relocated mode.
50 #define EXC_REAL_BEGIN(name, start, size) \
51 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
53 #define EXC_REAL_END(name, start, size) \
54 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
56 #define EXC_VIRT_BEGIN(name, start, size) \
57 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
59 #define EXC_VIRT_END(name, start, size) \
60 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
62 #define EXC_COMMON_BEGIN(name) \
64 .balign IFETCH_ALIGN_BYTES; \
66 _ASM_NOKPROBE_SYMBOL(name); \
67 DEFINE_FIXED_SYMBOL(name); \
70 #define TRAMP_REAL_BEGIN(name) \
71 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
73 #define TRAMP_VIRT_BEGIN(name) \
74 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
76 #define EXC_REAL_NONE(start, size) \
77 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
78 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
80 #define EXC_VIRT_NONE(start, size) \
81 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
82 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
85 * We're short on space and time in the exception prolog, so we can't
86 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
87 * Instead we get the base of the kernel from paca->kernelbase and or in the low
88 * part of label. This requires that the label be within 64KB of kernelbase, and
89 * that kernelbase be 64K aligned.
91 #define LOAD_HANDLER(reg, label) \
92 ld reg,PACAKBASE(r13); /* get high part of &label */ \
93 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
95 #define __LOAD_HANDLER(reg, label) \
96 ld reg,PACAKBASE(r13); \
97 ori reg,reg,(ABS_ADDR(label))@l
100 * Branches from unrelocated code (e.g., interrupts) to labels outside
101 * head-y require >64K offsets.
103 #define __LOAD_FAR_HANDLER(reg, label) \
104 ld reg,PACAKBASE(r13); \
105 ori reg,reg,(ABS_ADDR(label))@l; \
106 addis reg,reg,(ABS_ADDR(label))@h
109 * Branch to label using its 0xC000 address. This results in instruction
110 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
111 * on using mtmsr rather than rfid.
113 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
114 * load KBASE for a slight optimisation.
116 #define BRANCH_TO_C000(reg, label) \
117 __LOAD_FAR_HANDLER(reg, label); \
122 * Interrupt code generation macros
124 #define IVEC .L_IVEC_\name\() /* Interrupt vector address */
125 #define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */
126 #define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */
127 #define IAREA .L_IAREA_\name\() /* PACA save area */
128 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */
129 #define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */
130 #define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */
131 #define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */
132 #define ISET_RI .L_ISET_RI_\name\() /* Run common code w/ MSR[RI]=1 */
133 #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */
134 #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */
135 #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */
136 #define IKVM_SKIP .L_IKVM_SKIP_\name\() /* Generate KVM skip handler */
137 #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */
138 #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name
139 #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */
140 #define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */
141 #define __ISTACK(name) .L_ISTACK_ ## name
142 #define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */
144 #define INT_DEFINE_BEGIN(n) \
145 .macro int_define_ ## n name
147 #define INT_DEFINE_END(n) \
149 int_define_ ## n n ; \
152 .macro do_define_int name
154 .error "IVEC not defined"
159 .ifndef IHSRR_IF_HVMODE
180 .ifndef IBRANCH_TO_COMMON
183 .ifndef IREALMODE_COMMON
186 .if ! IBRANCH_TO_COMMON
187 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
210 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
211 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
213 * All interrupts which set HSRR registers, as well as SRESET and MCE and
214 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken,
215 * so they all generally need to test whether they were taken in guest context.
217 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be
218 * taken with MSR[HV]=0.
220 * Interrupts which set SRR registers (with the above exceptions) do not
221 * elevate to MSR[HV]=1 mode, though most can be taken when running with
222 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do
223 * not need to test whether a guest is running because they get delivered to
224 * the guest directly, including nested HV KVM guests.
226 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host
227 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
228 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
229 * delivered to the real-mode entry point, therefore such interrupts only test
230 * KVM in their real mode handlers, and only when PR KVM is possible.
232 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
233 * delivered in real-mode when the MMU is in hash mode because the MMU
234 * registers are not set appropriately to translate host addresses. In nested
235 * radix mode these can be delivered in virt-mode as the host translations are
236 * used implicitly (see: effective LPID, effective PID).
240 * If an interrupt is taken while a guest is running, it is immediately routed
241 * to KVM to handle. If both HV and PR KVM arepossible, KVM interrupts go first
242 * to kvmppc_interrupt_hv, which handles the PR guest case.
244 #define kvmppc_interrupt kvmppc_interrupt_hv
246 #define kvmppc_interrupt kvmppc_interrupt_pr
250 lbz r10,HSTATE_IN_GUEST(r13)
256 .balign IFETCH_ALIGN_BYTES
260 cmpwi r10,KVM_GUEST_MODE_SKIP
264 ld r10,IAREA+EX_CFAR(r13)
265 std r10,HSTATE_CFAR(r13)
266 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
269 ld r10,IAREA+EX_CTR(r13)
272 ld r10,IAREA+EX_PPR(r13)
273 std r10,HSTATE_PPR(r13)
274 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
275 ld r11,IAREA+EX_R11(r13)
276 ld r12,IAREA+EX_R12(r13)
277 std r12,HSTATE_SCRATCH0(r13)
279 ld r9,IAREA+EX_R9(r13)
280 ld r10,IAREA+EX_R10(r13)
281 /* HSRR variants have the 0x2 bit added to their trap number */
284 ori r12,r12,(IVEC + 0x2)
287 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
289 ori r12,r12,(IVEC+ 0x2)
297 ld r10,IAREA+EX_CTR(r13)
299 ld r9,IAREA+EX_R9(r13)
300 ld r10,IAREA+EX_R10(r13)
301 ld r11,IAREA+EX_R11(r13)
302 ld r12,IAREA+EX_R12(r13)
305 b kvmppc_skip_Hinterrupt
307 b kvmppc_skip_interrupt
308 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
310 b kvmppc_skip_Hinterrupt
312 b kvmppc_skip_interrupt
325 * This is the BOOK3S interrupt entry code macro.
327 * This can result in one of several things happening:
328 * - Branch to the _common handler, relocated, in virtual mode.
329 * These are normal interrupts (synchronous and asynchronous) handled by
331 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
332 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
333 * / intended for host or guest kernel, but KVM must always be involved
334 * because the machine state is set for guest execution.
335 * - Branch to the masked handler, unrelocated.
336 * These occur when maskable asynchronous interrupts are taken with the
338 * - Branch to an "early" handler in real mode but relocated.
339 * This is done if early=1. MCE and HMI use these to handle errors in real
341 * - Fall through and continue executing in real, unrelocated mode.
342 * This is done if early=2.
345 .macro GEN_BRANCH_TO_COMMON name, virt
347 LOAD_HANDLER(r10, \name\()_common)
352 #ifndef CONFIG_RELOCATABLE
353 b \name\()_common_virt
355 LOAD_HANDLER(r10, \name\()_common_virt)
360 LOAD_HANDLER(r10, \name\()_common_real)
367 .macro GEN_INT_ENTRY name, virt, ool=0
368 SET_SCRATCH0(r13) /* save r13 */
370 std r9,IAREA+EX_R9(r13) /* save r9 */
373 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
375 std r10,IAREA+EX_R10(r13) /* save r10 - r12 */
378 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
383 TRAMP_REAL_BEGIN(tramp_real_\name)
387 TRAMP_VIRT_BEGIN(tramp_virt_\name)
392 std r9,IAREA+EX_PPR(r13)
393 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
395 std r10,IAREA+EX_CFAR(r13)
396 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
399 std r10,IAREA+EX_CTR(r13)
401 std r11,IAREA+EX_R11(r13)
402 std r12,IAREA+EX_R12(r13)
405 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
406 * because a d-side MCE will clobber those registers so is
407 * not recoverable if they are live.
410 std r10,IAREA+EX_R13(r13)
417 std r10,IAREA+EX_DAR(r13)
419 .if IDSISR && !IISIDE
421 mfspr r10,SPRN_HDSISR
425 stw r10,IAREA+EX_DSISR(r13)
430 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
431 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
433 mfspr r11,SPRN_SRR0 /* save SRR0 */
434 mfspr r12,SPRN_SRR1 /* and SRR1 */
435 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
437 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
438 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
440 mfspr r11,SPRN_SRR0 /* save SRR0 */
441 mfspr r12,SPRN_SRR1 /* and SRR1 */
444 .if IBRANCH_TO_COMMON
445 GEN_BRANCH_TO_COMMON \name \virt
454 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt
455 * entry, except in the case of the real-mode handlers which require
456 * __GEN_REALMODE_COMMON_ENTRY.
458 * This switches to virtual mode and sets MSR[RI].
460 .macro __GEN_COMMON_ENTRY name
461 DEFINE_FIXED_SYMBOL(\name\()_common_real)
462 \name\()_common_real:
467 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
468 /* MSR[RI] is clear iff using SRR regs */
469 .if IHSRR == EXC_HV_OR_STD
472 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
480 b 1f /* skip the virt test coming from real */
483 .balign IFETCH_ALIGN_BYTES
484 DEFINE_FIXED_SYMBOL(\name\()_common_virt)
485 \name\()_common_virt:
494 * Don't switch to virt mode. Used for early MCE and HMI handlers that
495 * want to run in real mode.
497 .macro __GEN_REALMODE_COMMON_ENTRY name
498 DEFINE_FIXED_SYMBOL(\name\()_common_real)
499 \name\()_common_real:
505 .macro __GEN_COMMON_BODY name
508 .error "No support for masked interrupt to use custom stack"
511 /* If coming from user, skip soft-mask tests. */
515 /* Kernel code running below __end_interrupts is implicitly
517 LOAD_HANDLER(r10, __end_interrupts)
522 /* Test the soft mask state against our interrupt's bit */
523 lbz r10,PACAIRQSOFTMASK(r13)
524 1: andi. r10,r10,IMASK
525 /* Associate vector numbers with bits in paca->irq_happened */
526 .if IVEC == 0x500 || IVEC == 0xea0
528 .elseif IVEC == 0x900
530 .elseif IVEC == 0xa00 || IVEC == 0xe80
531 li r10,PACA_IRQ_DBELL
532 .elseif IVEC == 0xe60
534 .elseif IVEC == 0xf00
537 .abort "Bad maskable vector"
542 bne masked_Hinterrupt
545 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
547 bne masked_Hinterrupt
554 andi. r10,r12,MSR_PR /* See if coming from user */
555 2: mr r10,r1 /* Save r1 */
556 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */
558 ld r1,PACAKSAVE(r13) /* kernel stack to use */
559 100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */
560 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
563 std r9,_CCR(r1) /* save CR in stackframe */
564 std r11,_NIP(r1) /* save SRR0 in stackframe */
565 std r12,_MSR(r1) /* save SRR1 in stackframe */
566 std r10,0(r1) /* make stack chain pointer */
567 std r0,GPR0(r1) /* save r0 in stackframe */
568 std r10,GPR1(r1) /* save r1 in stackframe */
572 mtmsrd r10,1 /* Set MSR_RI */
577 kuap_save_amr_and_lock r9, r10, cr1, cr0
579 beq 101f /* if from kernel mode */
581 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */
583 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
587 kuap_save_amr_and_lock r9, r10, cr1
591 /* Save original regs values from save area to stack frame. */
592 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */
593 ld r10,IAREA+EX_R10(r13)
596 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */
597 ld r10,IAREA+EX_R12(r13)
598 ld r11,IAREA+EX_R13(r13)
609 ld r10,IAREA+EX_DAR(r13)
617 lis r11,DSISR_SRR1_MATCH_64S@h
620 lwz r10,IAREA+EX_DSISR(r13)
626 ld r10,IAREA+EX_CFAR(r13)
627 std r10,ORIG_GPR3(r1)
628 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
629 ld r10,IAREA+EX_CTR(r13)
631 std r2,GPR2(r1) /* save r2 in stackframe */
632 SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */
633 SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */
634 mflr r9 /* Get LR, later save to stack */
635 ld r2,PACATOC(r13) /* get kernel TOC into r2 */
637 lbz r10,PACAIRQSOFTMASK(r13)
638 mfspr r11,SPRN_XER /* save XER in stackframe */
642 std r9,_TRAP(r1) /* set trap number */
644 ld r11,exception_marker@toc(r2)
645 std r10,RESULT(r1) /* clear regs->result */
646 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */
650 * On entry r13 points to the paca, r9-r13 are saved in the paca,
651 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
652 * SRR1, and relocation is on.
654 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
655 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
657 .macro GEN_COMMON name
658 __GEN_COMMON_ENTRY \name
659 __GEN_COMMON_BODY \name
663 * Restore all registers including H/SRR0/1 saved in a stack frame of a
664 * standard exception.
666 .macro EXCEPTION_RESTORE_REGS hsrr=0
667 /* Move original SRR0 and SRR1 into the respective regs */
691 /* restore original r1. */
696 * When the idle code in power4_idle puts the CPU into NAP mode,
697 * it has to do so in a loop, and relies on the external interrupt
698 * and decrementer interrupt entry code to get it out of the loop.
699 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
700 * to signal that it is in the loop and needs help to get out.
702 #ifdef CONFIG_PPC_970_NAP
705 ld r11, PACA_THREAD_INFO(r13); \
706 ld r9,TI_LOCAL_FLAGS(r11); \
707 andi. r10,r9,_TLF_NAPPING; \
708 bnel power4_fixup_nap; \
709 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
715 * There are a few constraints to be concerned with.
716 * - Real mode exceptions code/data must be located at their physical location.
717 * - Virtual mode exceptions must be mapped at their 0xc000... location.
718 * - Fixed location code must not call directly beyond the __end_interrupts
719 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
721 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
723 * - Conditional branch targets must be within +/-32K of caller.
725 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
726 * therefore don't have to run in physically located code or rfid to
727 * virtual mode kernel code. However on relocatable kernels they do have
728 * to branch to KERNELBASE offset because the rest of the kernel (outside
729 * the exception vectors) may be located elsewhere.
731 * Virtual exceptions correspond with physical, except their entry points
732 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
733 * offset applied. Virtual exceptions are enabled with the Alternate
734 * Interrupt Location (AIL) bit set in the LPCR. However this does not
735 * guarantee they will be delivered virtually. Some conditions (see the ISA)
736 * cause exceptions to be delivered in real mode.
738 * The scv instructions are a special case. They get a 0x3000 offset applied.
739 * scv exceptions have unique reentrancy properties, see below.
741 * It's impossible to receive interrupts below 0x300 via AIL.
743 * KVM: None of the virtual exceptions are from the guest. Anything that
744 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
747 * We layout physical memory as follows:
748 * 0x0000 - 0x00ff : Secondary processor spin code
749 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
750 * 0x1900 - 0x2fff : Real mode trampolines
751 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
752 * 0x5900 - 0x6fff : Relon mode trampolines
753 * 0x7000 - 0x7fff : FWNMI data area
754 * 0x8000 - .... : Common interrupt handlers, remaining early
755 * setup code, rest of kernel.
757 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
758 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
761 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
762 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
763 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
764 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
766 #ifdef CONFIG_PPC_POWERNV
767 .globl start_real_trampolines
768 .globl end_real_trampolines
769 .globl start_virt_trampolines
770 .globl end_virt_trampolines
773 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
775 * Data area reserved for FWNMI option.
776 * This address (0x7000) is fixed by the RPA.
777 * pseries and powernv need to keep the whole page from
778 * 0x7000 to 0x8000 free for use by the firmware
780 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
781 OPEN_TEXT_SECTION(0x8000)
783 OPEN_TEXT_SECTION(0x7000)
786 USE_FIXED_SECTION(real_vectors)
789 * This is the start of the interrupt handlers for pSeries
790 * This code runs with relocation off.
791 * Code from here to __end_interrupts gets copied down to real
792 * address 0x100 when we are running a relocatable kernel.
793 * Therefore any relative branches in this section must only
794 * branch to labels in this section.
796 .globl __start_interrupts
800 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
801 * This is a synchronous interrupt invoked with the "scv" instruction. The
802 * system call does not alter the HV bit, so it is directed to the OS.
805 * scv instructions enter the kernel without changing EE, RI, ME, or HV.
806 * In particular, this means we can take a maskable interrupt at any point
807 * in the scv handler, which is unlike any other interrupt. This is solved
808 * by treating the instruction addresses below __end_interrupts as being
811 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
812 * ensure scv is never executed with relocation off, which means AIL-0
813 * should never happen.
815 * Before leaving the below __end_interrupts text, at least of the following
817 * - MSR[PR]=1 (i.e., return to userspace)
818 * - MSR_EE|MSR_RI is set (no reentrant exceptions)
819 * - Standard kernel environment is set up (stack, paca, etc)
823 * syscall register convention is in Documentation/powerpc/syscall64-abi.rst
825 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
831 li r10,IRQS_ALL_DISABLED
832 stb r10,PACAIRQSOFTMASK(r13)
833 #ifdef CONFIG_RELOCATABLE
834 b system_call_vectored_tramp
836 b system_call_vectored_common
846 li r10,IRQS_ALL_DISABLED
847 stb r10,PACAIRQSOFTMASK(r13)
848 li r0,-1 /* cause failure */
849 #ifdef CONFIG_RELOCATABLE
850 b system_call_vectored_sigill_tramp
852 b system_call_vectored_sigill
855 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
857 #ifdef CONFIG_RELOCATABLE
858 TRAMP_VIRT_BEGIN(system_call_vectored_tramp)
859 __LOAD_HANDLER(r10, system_call_vectored_common)
863 TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp)
864 __LOAD_HANDLER(r10, system_call_vectored_sigill)
870 /* No virt vectors corresponding with 0x0..0x100 */
871 EXC_VIRT_NONE(0x4000, 0x100)
875 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
876 * This is a non-maskable, asynchronous interrupt always taken in real-mode.
878 * - Wake from power-saving state, on powernv.
879 * - An NMI from another CPU, triggered by firmware or hypercall.
880 * - As crash/debug signal injected from BMC, firmware or hypervisor.
883 * Power-save wakeup is the only performance critical path, so this is
884 * determined quickly as possible first. In this case volatile registers
885 * can be discarded and SPRs like CFAR don't need to be read.
887 * If not a powersave wakeup, then it's run as a regular interrupt, however
888 * it uses its own stack and PACA save area to preserve the regular kernel
889 * environment for debugging.
891 * This interrupt is not maskable, so triggering it when MSR[RI] is clear,
892 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely
893 * correct to switch to virtual mode to run the regular interrupt handler
894 * because it might be interrupted when the MMU is in a bad state (e.g., SLB
898 * PAPR specifies a "fwnmi" facility which sends the sreset to a different
899 * entry point with a different register set up. Some hypervisors will
900 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
903 * Unlike most SRR interrupts, this may be taken by the host while executing
904 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest
905 * mode and then raise the sreset.
907 INT_DEFINE_BEGIN(system_reset)
910 IVIRT=0 /* no virt entry point */
912 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
913 * being used, so a nested NMI exception would corrupt it.
918 INT_DEFINE_END(system_reset)
920 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
921 #ifdef CONFIG_PPC_P7_NAP
923 * If running native on arch 2.06 or later, check if we are waking up
924 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
925 * bits 46:47. A non-0 value indicates that we are coming from a power
926 * saving state. The idle wakeup handler initially runs in real mode,
927 * but we branch to the 0xc000... address so we can turn on relocation
928 * with mtmsrd later, after SPRs are restored.
930 * Careful to minimise cost for the fast path (idle wakeup) while
931 * also avoiding clobbering CFAR for the debug path (non-idle).
933 * For the idle wake case volatile registers can be clobbered, which
934 * is why we use those initially. If it turns out to not be an idle
935 * wake, carefully put everything back the way it was, so we can use
936 * common exception macros to handle it.
941 std r3,PACA_EXNMI+0*8(r13)
942 std r4,PACA_EXNMI+1*8(r13)
943 std r5,PACA_EXNMI+2*8(r13)
946 rlwinm. r5,r3,47-31,30,31
947 bne+ system_reset_idle_wake
948 /* Not powersave wakeup. Restore regs for regular interrupt handler. */
950 ld r3,PACA_EXNMI+0*8(r13)
951 ld r4,PACA_EXNMI+1*8(r13)
952 ld r5,PACA_EXNMI+2*8(r13)
954 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
957 GEN_INT_ENTRY system_reset, virt=0
959 * In theory, we should not enable relocation here if it was disabled
960 * in SRR1, because the MMU may not be configured to support it (e.g.,
961 * SLB may have been cleared). In practice, there should only be a few
962 * small windows where that's the case, and sreset is considered to
963 * be dangerous anyway.
965 EXC_REAL_END(system_reset, 0x100, 0x100)
966 EXC_VIRT_NONE(0x4100, 0x100)
968 #ifdef CONFIG_PPC_P7_NAP
969 TRAMP_REAL_BEGIN(system_reset_idle_wake)
970 /* We are waking up from idle, so may clobber any volatile register */
972 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
973 BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss))
976 #ifdef CONFIG_PPC_PSERIES
978 * Vectors for the FWNMI option. Share common code.
980 TRAMP_REAL_BEGIN(system_reset_fwnmi)
981 GEN_INT_ENTRY system_reset, virt=0
983 #endif /* CONFIG_PPC_PSERIES */
985 EXC_COMMON_BEGIN(system_reset_common)
986 __GEN_COMMON_ENTRY system_reset
988 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
989 * to recover, but nested NMI will notice in_nmi and not recover
990 * because of the use of the NMI stack. in_nmi reentrancy is tested in
991 * system_reset_exception.
993 lhz r10,PACA_IN_NMI(r13)
995 sth r10,PACA_IN_NMI(r13)
1000 ld r1,PACA_NMI_EMERG_SP(r13)
1001 subi r1,r1,INT_FRAME_SIZE
1002 __GEN_COMMON_BODY system_reset
1004 addi r3,r1,STACK_FRAME_OVERHEAD
1005 bl system_reset_exception
1007 /* Clear MSR_RI before setting SRR0 and SRR1. */
1012 * MSR_RI is clear, now we can decrement paca->in_nmi.
1014 lhz r10,PACA_IN_NMI(r13)
1016 sth r10,PACA_IN_NMI(r13)
1018 kuap_kernel_restore r9, r10
1019 EXCEPTION_RESTORE_REGS
1020 RFI_TO_USER_OR_KERNEL
1022 GEN_KVM system_reset
1026 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1027 * This is a non-maskable interrupt always taken in real-mode. It can be
1028 * synchronous or asynchronous, caused by hardware or software, and it may be
1029 * taken in a power-saving state.
1032 * Similarly to system reset, this uses its own stack and PACA save area,
1033 * the difference is re-entrancy is allowed on the machine check stack.
1035 * machine_check_early is run in real mode, and carefully decodes the
1036 * machine check and tries to handle it (e.g., flush the SLB if there was an
1037 * error detected there), determines if it was recoverable and logs the
1040 * This early code does not "reconcile" irq soft-mask state like SRESET or
1041 * regular interrupts do, so irqs_disabled() among other things may not work
1042 * properly (irq disable/enable already doesn't work because irq tracing can
1043 * not work in real mode).
1045 * Then, depending on the execution context when the interrupt is taken, there
1046 * are 3 main actions:
1047 * - Executing in kernel mode. The event is queued with irq_work, which means
1048 * it is handled when it is next safe to do so (i.e., the kernel has enabled
1049 * interrupts), which could be immediately when the interrupt returns. This
1050 * avoids nasty issues like switching to virtual mode when the MMU is in a
1051 * bad state, or when executing OPAL code. (SRESET is exposed to such issues,
1052 * but it has different priorities). Check to see if the CPU was in power
1053 * save, and return via the wake up code if it was.
1055 * - Executing in user mode. machine_check_exception is run like a normal
1056 * interrupt handler, which processes the data generated by the early handler.
1058 * - Executing in guest mode. The interrupt is run with its KVM test, and
1059 * branches to KVM to deal with. KVM may queue the event for the host
1062 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear,
1063 * or SCRATCH0 is in use, it may cause a crash.
1068 INT_DEFINE_BEGIN(machine_check_early)
1071 IVIRT=0 /* no virt entry point */
1074 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
1075 * nested machine check corrupts it. machine_check_common enables
1082 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1083 INT_DEFINE_END(machine_check_early)
1085 INT_DEFINE_BEGIN(machine_check)
1088 IVIRT=0 /* no virt entry point */
1094 INT_DEFINE_END(machine_check)
1096 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1097 GEN_INT_ENTRY machine_check_early, virt=0
1098 EXC_REAL_END(machine_check, 0x200, 0x100)
1099 EXC_VIRT_NONE(0x4200, 0x100)
1101 #ifdef CONFIG_PPC_PSERIES
1102 TRAMP_REAL_BEGIN(machine_check_fwnmi)
1103 /* See comment at machine_check exception, don't turn on RI */
1104 GEN_INT_ENTRY machine_check_early, virt=0
1107 #define MACHINE_CHECK_HANDLER_WINDUP \
1108 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1110 mtmsrd r9,1; /* Clear MSR_RI */ \
1111 /* Decrement paca->in_mce now RI is clear. */ \
1112 lhz r12,PACA_IN_MCE(r13); \
1114 sth r12,PACA_IN_MCE(r13); \
1115 EXCEPTION_RESTORE_REGS
1117 EXC_COMMON_BEGIN(machine_check_early_common)
1118 __GEN_REALMODE_COMMON_ENTRY machine_check_early
1121 * Switch to mc_emergency stack and handle re-entrancy (we limit
1122 * the nested MCE upto level 4 to avoid stack overflow).
1123 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
1125 * We use paca->in_mce to check whether this is the first entry or
1126 * nested machine check. We increment paca->in_mce to track nested
1129 * If this is the first entry then set stack pointer to
1130 * paca->mc_emergency_sp, otherwise r1 is already pointing to
1131 * stack frame on mc_emergency stack.
1133 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1134 * checkstop if we get another machine check exception before we do
1135 * rfid with MSR_ME=1.
1137 * This interrupt can wake directly from idle. If that is the case,
1138 * the machine check is handled then the idle wakeup code is called
1141 lhz r10,PACA_IN_MCE(r13)
1142 cmpwi r10,0 /* Are we in nested machine check */
1143 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */
1144 addi r10,r10,1 /* increment paca->in_mce */
1145 sth r10,PACA_IN_MCE(r13)
1147 mr r10,r1 /* Save r1 */
1149 /* First machine check entry */
1150 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
1151 1: /* Limit nested MCE to level 4 to avoid stack overflow */
1152 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
1153 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1155 __GEN_COMMON_BODY machine_check_early
1158 bl enable_machine_check
1159 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1163 addi r3,r1,STACK_FRAME_OVERHEAD
1164 bl machine_check_early
1165 std r3,RESULT(r1) /* Save result */
1168 #ifdef CONFIG_PPC_P7_NAP
1170 * Check if thread was in power saving mode. We come here when any
1171 * of the following is true:
1172 * a. thread wasn't in power saving mode
1173 * b. thread was in power saving mode with no state loss,
1174 * supervisor state loss or hypervisor state loss.
1176 * Go back to nap/sleep/winkle mode again if (b) is true.
1179 rlwinm. r11,r12,47-31,30,31
1180 bne machine_check_idle_common
1181 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1184 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1186 * Check if we are coming from guest. If yes, then run the normal
1187 * exception handler which will take the
1188 * machine_check_kvm->kvmppc_interrupt branch to deliver the MC event
1191 lbz r11,HSTATE_IN_GUEST(r13)
1192 cmpwi r11,0 /* Check if coming from guest */
1193 bne mce_deliver /* continue if we are. */
1197 * Check if we are coming from userspace. If yes, then run the normal
1198 * exception handler which will deliver the MC event to this kernel.
1200 andi. r11,r12,MSR_PR /* See if coming from user. */
1201 bne mce_deliver /* continue in V mode if we are. */
1204 * At this point we are coming from kernel context.
1205 * Queue up the MCE event and return from the interrupt.
1206 * But before that, check if this is an un-recoverable exception.
1207 * If yes, then stay on emergency stack and panic.
1209 andi. r11,r12,MSR_RI
1210 beq unrecoverable_mce
1213 * Check if we have successfully handled/recovered from error, if not
1214 * then stay on emergency stack and panic.
1216 ld r3,RESULT(r1) /* Load result */
1217 cmpdi r3,0 /* see if we handled MCE successfully */
1218 beq unrecoverable_mce /* if !handled then panic */
1221 * Return from MC interrupt.
1222 * Queue up the MCE event so that we can log it later, while
1223 * returning from kernel or opal call.
1225 bl machine_check_queue_event
1226 MACHINE_CHECK_HANDLER_WINDUP
1231 * This is a host user or guest MCE. Restore all registers, then
1232 * run the "late" handler. For host user, this will run the
1233 * machine_check_exception handler in virtual mode like a normal
1234 * interrupt handler. For guest, this will trigger the KVM test
1235 * and branch to the KVM interrupt similarly to other interrupts.
1238 ld r10,ORIG_GPR3(r1)
1240 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1241 MACHINE_CHECK_HANDLER_WINDUP
1242 GEN_INT_ENTRY machine_check, virt=0
1244 EXC_COMMON_BEGIN(machine_check_common)
1246 * Machine check is different because we use a different
1247 * save area: PACA_EXMC instead of PACA_EXGEN.
1249 GEN_COMMON machine_check
1252 /* Enable MSR_RI when finished with PACA_EXMC */
1255 addi r3,r1,STACK_FRAME_OVERHEAD
1256 bl machine_check_exception
1259 GEN_KVM machine_check
1262 #ifdef CONFIG_PPC_P7_NAP
1264 * This is an idle wakeup. Low level machine check has already been
1265 * done. Queue the event then call the idle code to do the wake up.
1267 EXC_COMMON_BEGIN(machine_check_idle_common)
1268 bl machine_check_queue_event
1271 * GPR-loss wakeups are relatively straightforward, because the
1272 * idle sleep code has saved all non-volatile registers on its
1273 * own stack, and r1 in PACAR1.
1275 * For no-loss wakeups the r1 and lr registers used by the
1276 * early machine check handler have to be restored first. r2 is
1277 * the kernel TOC, so no need to restore it.
1279 * Then decrement MCE nesting after finishing with the stack.
1285 lhz r11,PACA_IN_MCE(r13)
1287 sth r11,PACA_IN_MCE(r13)
1290 rlwinm r10,r3,47-31,30,31
1292 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1293 b idle_return_gpr_loss
1296 EXC_COMMON_BEGIN(unrecoverable_mce)
1298 * We are going down. But there are chances that we might get hit by
1299 * another MCE during panic path and we may run into unstable state
1300 * with no way out. Hence, turn ME bit off while going down, so that
1301 * when another MCE is hit during panic path, system will checkstop
1302 * and hypervisor will get restarted cleanly by SP.
1305 li r10,0 /* clear MSR_RI */
1307 bl disable_machine_check
1308 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1309 ld r10,PACAKMSR(r13)
1314 lhz r12,PACA_IN_MCE(r13)
1316 sth r12,PACA_IN_MCE(r13)
1318 /* Invoke machine_check_exception to print MCE event and panic. */
1319 addi r3,r1,STACK_FRAME_OVERHEAD
1320 bl machine_check_exception
1323 * We will not reach here. Even if we did, there is no way out.
1324 * Call unrecoverable_exception and die.
1326 addi r3,r1,STACK_FRAME_OVERHEAD
1327 bl unrecoverable_exception
1332 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1333 * This is a synchronous interrupt generated due to a data access exception,
1334 * e.g., a load orstore which does not have a valid page table entry with
1335 * permissions. DAWR matches also fault here, as do RC updates, and minor misc
1336 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc.
1340 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the
1341 * Linux page table. Hash faults can hit in kernel mode in a fairly
1342 * arbitrary state (e.g., interrupts disabled, locks held) when accessing
1343 * "non-bolted" regions, e.g., vmalloc space. However these should always be
1344 * backed by Linux page table entries.
1346 * If no entry is found the Linux page fault handler is invoked (by
1347 * do_hash_fault). Linux page faults can happen in kernel mode due to user
1348 * copy operations of course.
1350 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest
1351 * MMU context, which may cause a DSI in the host, which must go to the
1352 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will
1353 * always be used regardless of AIL setting.
1356 * The hardware loads from the Linux page table directly, so a fault goes
1357 * immediately to Linux page fault.
1359 * Conditions like DAWR match are handled on the way in to Linux page fault.
1361 INT_DEFINE_BEGIN(data_access)
1367 INT_DEFINE_END(data_access)
1369 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1370 GEN_INT_ENTRY data_access, virt=0
1371 EXC_REAL_END(data_access, 0x300, 0x80)
1372 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1373 GEN_INT_ENTRY data_access, virt=1
1374 EXC_VIRT_END(data_access, 0x4300, 0x80)
1375 EXC_COMMON_BEGIN(data_access_common)
1376 GEN_COMMON data_access
1378 addi r3,r1,STACK_FRAME_OVERHEAD
1379 andis. r0,r4,DSISR_DABRMATCH@h
1381 BEGIN_MMU_FTR_SECTION
1383 MMU_FTR_SECTION_ELSE
1385 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1390 * do_break() may have changed the NV GPRS while handling a breakpoint.
1391 * If so, we need to restore them with their updated values.
1400 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1401 * This is a synchronous interrupt in response to an MMU fault missing SLB
1402 * entry for HPT, or an address outside RPT translation range.
1406 * This refills the SLB, or reports an access fault similarly to a bad page
1407 * fault. When coming from user-mode, the SLB handler may access any kernel
1408 * data, though it may itself take a DSLB. When coming from kernel mode,
1409 * recursive faults must be avoided so access is restricted to the kernel
1410 * image text/data, kernel stack, and any data allocated below
1411 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping
1412 * on user-handler data structures.
1414 * KVM: Same as 0x300, DSLB must test for KVM guest.
1416 INT_DEFINE_BEGIN(data_access_slb)
1421 INT_DEFINE_END(data_access_slb)
1423 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1424 GEN_INT_ENTRY data_access_slb, virt=0
1425 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1426 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1427 GEN_INT_ENTRY data_access_slb, virt=1
1428 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1429 EXC_COMMON_BEGIN(data_access_slb_common)
1430 GEN_COMMON data_access_slb
1431 BEGIN_MMU_FTR_SECTION
1432 /* HPT case, do SLB fault */
1433 addi r3,r1,STACK_FRAME_OVERHEAD
1437 b fast_interrupt_return
1439 MMU_FTR_SECTION_ELSE
1440 /* Radix case, access is outside page table range */
1442 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1444 addi r3,r1,STACK_FRAME_OVERHEAD
1448 GEN_KVM data_access_slb
1452 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1453 * This is a synchronous interrupt in response to an MMU fault due to an
1454 * instruction fetch.
1457 * Similar to DSI, though in response to fetch. The faulting address is found
1458 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR).
1460 INT_DEFINE_BEGIN(instruction_access)
1465 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1468 INT_DEFINE_END(instruction_access)
1470 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1471 GEN_INT_ENTRY instruction_access, virt=0
1472 EXC_REAL_END(instruction_access, 0x400, 0x80)
1473 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1474 GEN_INT_ENTRY instruction_access, virt=1
1475 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1476 EXC_COMMON_BEGIN(instruction_access_common)
1477 GEN_COMMON instruction_access
1478 addi r3,r1,STACK_FRAME_OVERHEAD
1479 BEGIN_MMU_FTR_SECTION
1481 MMU_FTR_SECTION_ELSE
1483 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1486 GEN_KVM instruction_access
1490 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1491 * This is a synchronous interrupt in response to an MMU fault due to an
1492 * instruction fetch.
1495 * Similar to DSLB, though in response to fetch. The faulting address is found
1496 * in SRR0 (rather than DAR).
1498 INT_DEFINE_BEGIN(instruction_access_slb)
1502 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1505 INT_DEFINE_END(instruction_access_slb)
1507 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1508 GEN_INT_ENTRY instruction_access_slb, virt=0
1509 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1510 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1511 GEN_INT_ENTRY instruction_access_slb, virt=1
1512 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1513 EXC_COMMON_BEGIN(instruction_access_slb_common)
1514 GEN_COMMON instruction_access_slb
1515 BEGIN_MMU_FTR_SECTION
1516 /* HPT case, do SLB fault */
1517 addi r3,r1,STACK_FRAME_OVERHEAD
1521 b fast_interrupt_return
1523 MMU_FTR_SECTION_ELSE
1524 /* Radix case, access is outside page table range */
1526 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1528 addi r3,r1,STACK_FRAME_OVERHEAD
1532 GEN_KVM instruction_access_slb
1536 * Interrupt 0x500 - External Interrupt.
1537 * This is an asynchronous maskable interrupt in response to an "external
1538 * exception" from the interrupt controller or hypervisor (e.g., device
1539 * interrupt). It is maskable in hardware by clearing MSR[EE], and
1540 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()).
1542 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1543 * interrupts are delivered with HSRR registers, guests use SRRs, which
1544 * reqiures IHSRR_IF_HVMODE.
1546 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
1547 * external interrupts are delivered as Hypervisor Virtualization Interrupts
1548 * rather than External Interrupts.
1551 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead,
1552 * because registers at the time of the interrupt are not so important as it is
1555 * If soft masked, the masked handler will note the pending interrupt for
1556 * replay, and clear MSR[EE] in the interrupted context.
1558 INT_DEFINE_BEGIN(hardware_interrupt)
1564 INT_DEFINE_END(hardware_interrupt)
1566 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1567 GEN_INT_ENTRY hardware_interrupt, virt=0
1568 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1569 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1570 GEN_INT_ENTRY hardware_interrupt, virt=1
1571 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1572 EXC_COMMON_BEGIN(hardware_interrupt_common)
1573 GEN_COMMON hardware_interrupt
1575 addi r3,r1,STACK_FRAME_OVERHEAD
1579 GEN_KVM hardware_interrupt
1583 * Interrupt 0x600 - Alignment Interrupt
1584 * This is a synchronous interrupt in response to data alignment fault.
1586 INT_DEFINE_BEGIN(alignment)
1590 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1593 INT_DEFINE_END(alignment)
1595 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1596 GEN_INT_ENTRY alignment, virt=0
1597 EXC_REAL_END(alignment, 0x600, 0x100)
1598 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1599 GEN_INT_ENTRY alignment, virt=1
1600 EXC_VIRT_END(alignment, 0x4600, 0x100)
1601 EXC_COMMON_BEGIN(alignment_common)
1602 GEN_COMMON alignment
1603 addi r3,r1,STACK_FRAME_OVERHEAD
1604 bl alignment_exception
1605 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1612 * Interrupt 0x700 - Program Interrupt (program check).
1613 * This is a synchronous interrupt in response to various instruction faults:
1614 * traps, privilege errors, TM errors, floating point exceptions.
1617 * This interrupt may use the "emergency stack" in some cases when being taken
1618 * from kernel context, which complicates handling.
1620 INT_DEFINE_BEGIN(program_check)
1622 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1625 INT_DEFINE_END(program_check)
1627 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1629 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1631 * There's a short window during boot where although the kernel is
1632 * running little endian, any exceptions will cause the CPU to switch
1633 * back to big endian. For example a WARN() boils down to a trap
1634 * instruction, which will cause a program check, and we end up here but
1635 * with the CPU in big endian mode. The first instruction of the program
1636 * check handler (in GEN_INT_ENTRY below) is an mtsprg, which when
1637 * executed in the wrong endian is an lhzu with a ~3GB displacement from
1638 * r3. The content of r3 is random, so that is a load from some random
1639 * location, and depending on the system can easily lead to a checkstop,
1640 * or an infinitely recursive page fault.
1642 * So to handle that case we have a trampoline here that can detect we
1643 * are in the wrong endian and flip us back to the correct endian. We
1644 * can't flip MSR[LE] using mtmsr, so we have to use rfid. That requires
1645 * backing up SRR0/1 as well as a GPR. To do that we use SPRG0/2/3, as
1646 * SPRG1 is already used for the paca. SPRG3 is user readable, but this
1647 * trampoline is only active very early in boot, and SPRG3 will be
1648 * reinitialised in vdso_getcpu_init() before userspace starts.
1651 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8
1652 b 1f // Skip trampoline if endian is correct
1653 .long 0xa643707d // mtsprg 0, r11 Backup r11
1654 .long 0xa6027a7d // mfsrr0 r11
1655 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2
1656 .long 0xa6027b7d // mfsrr1 r11
1657 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3
1658 .long 0xa600607d // mfmsr r11
1659 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE]
1660 .long 0xa6037b7d // mtsrr1 r11
1661 .long 0x34076039 // li r11, 0x734
1662 .long 0xa6037a7d // mtsrr0 r11
1663 .long 0x2400004c // rfid
1665 mtsrr1 r11 // Restore SRR1
1667 mtsrr0 r11 // Restore SRR0
1668 mfsprg r11, 0 // Restore r11
1670 END_FTR_SECTION(0, 1) // nop out after boot
1671 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
1673 GEN_INT_ENTRY program_check, virt=0
1674 EXC_REAL_END(program_check, 0x700, 0x100)
1675 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1676 GEN_INT_ENTRY program_check, virt=1
1677 EXC_VIRT_END(program_check, 0x4700, 0x100)
1678 EXC_COMMON_BEGIN(program_check_common)
1679 __GEN_COMMON_ENTRY program_check
1682 * It's possible to receive a TM Bad Thing type program check with
1683 * userspace register values (in particular r1), but with SRR1 reporting
1684 * that we came from the kernel. Normally that would confuse the bad
1685 * stack logic, and we would report a bad kernel stack pointer. Instead
1686 * we switch to the emergency stack if we're taking a TM Bad Thing from
1690 andi. r10,r12,MSR_PR
1691 bne 2f /* If userspace, go normal path */
1693 andis. r10,r12,(SRR1_PROGTM)@h
1694 bne 1f /* If TM, emergency */
1696 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */
1697 blt 2f /* normal path if not */
1699 /* Use the emergency stack */
1700 1: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */
1701 /* 3 in EXCEPTION_PROLOG_COMMON */
1702 mr r10,r1 /* Save r1 */
1703 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1704 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1705 __ISTACK(program_check)=0
1706 __GEN_COMMON_BODY program_check
1709 __ISTACK(program_check)=1
1710 __GEN_COMMON_BODY program_check
1712 addi r3,r1,STACK_FRAME_OVERHEAD
1713 bl program_check_exception
1714 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1717 GEN_KVM program_check
1721 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1722 * This is a synchronous interrupt in response to executing an fp instruction
1726 * This will load FP registers and enable the FP bit if coming from userspace,
1727 * otherwise report a bad kernel use of FP.
1729 INT_DEFINE_BEGIN(fp_unavailable)
1731 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1734 INT_DEFINE_END(fp_unavailable)
1736 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1737 GEN_INT_ENTRY fp_unavailable, virt=0
1738 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1739 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1740 GEN_INT_ENTRY fp_unavailable, virt=1
1741 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1742 EXC_COMMON_BEGIN(fp_unavailable_common)
1743 GEN_COMMON fp_unavailable
1744 bne 1f /* if from user, just load it up */
1745 addi r3,r1,STACK_FRAME_OVERHEAD
1746 bl kernel_fp_unavailable_exception
1748 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1750 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1752 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1753 * transaction), go do TM stuff
1755 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1757 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1760 b fast_interrupt_return
1761 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1762 2: /* User process was in a transaction */
1763 addi r3,r1,STACK_FRAME_OVERHEAD
1764 bl fp_unavailable_tm
1768 GEN_KVM fp_unavailable
1772 * Interrupt 0x900 - Decrementer Interrupt.
1773 * This is an asynchronous interrupt in response to a decrementer exception
1774 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing
1775 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e.,
1776 * local_irq_disable()).
1779 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1781 * If soft masked, the masked handler will note the pending interrupt for
1782 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled
1783 * in the interrupted context.
1784 * If PPC_WATCHDOG is configured, the soft masked handler will actually set
1785 * things back up to run soft_nmi_interrupt as a regular interrupt handler
1786 * on the emergency stack.
1788 INT_DEFINE_BEGIN(decrementer)
1791 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1794 INT_DEFINE_END(decrementer)
1796 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1797 GEN_INT_ENTRY decrementer, virt=0
1798 EXC_REAL_END(decrementer, 0x900, 0x80)
1799 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1800 GEN_INT_ENTRY decrementer, virt=1
1801 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1802 EXC_COMMON_BEGIN(decrementer_common)
1803 GEN_COMMON decrementer
1805 addi r3,r1,STACK_FRAME_OVERHEAD
1813 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1814 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1818 * Linux does not use this outside KVM where it's used to keep a host timer
1819 * while the guest is given control of DEC. It should normally be caught by
1820 * the KVM test and routed there.
1822 INT_DEFINE_BEGIN(hdecrementer)
1828 INT_DEFINE_END(hdecrementer)
1830 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1831 GEN_INT_ENTRY hdecrementer, virt=0
1832 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1833 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1834 GEN_INT_ENTRY hdecrementer, virt=1
1835 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1836 EXC_COMMON_BEGIN(hdecrementer_common)
1837 __GEN_COMMON_ENTRY hdecrementer
1839 * Hypervisor decrementer interrupts not caught by the KVM test
1840 * shouldn't occur but are sometimes left pending on exit from a KVM
1841 * guest. We don't need to do anything to clear them, as they are
1844 * Be careful to avoid touching the kernel stack.
1846 ld r10,PACA_EXGEN+EX_CTR(r13)
1849 ld r9,PACA_EXGEN+EX_R9(r13)
1850 ld r10,PACA_EXGEN+EX_R10(r13)
1851 ld r11,PACA_EXGEN+EX_R11(r13)
1852 ld r12,PACA_EXGEN+EX_R12(r13)
1853 ld r13,PACA_EXGEN+EX_R13(r13)
1856 GEN_KVM hdecrementer
1860 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1861 * This is an asynchronous interrupt in response to a msgsndp doorbell.
1862 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
1863 * IRQS_DISABLED mask (i.e., local_irq_disable()).
1866 * Guests may use this for IPIs between threads in a core if the
1867 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1869 * If soft masked, the masked handler will note the pending interrupt for
1870 * replay, leaving MSR[EE] enabled in the interrupted context because the
1871 * doorbells are edge triggered.
1873 INT_DEFINE_BEGIN(doorbell_super)
1876 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1879 INT_DEFINE_END(doorbell_super)
1881 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1882 GEN_INT_ENTRY doorbell_super, virt=0
1883 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1884 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1885 GEN_INT_ENTRY doorbell_super, virt=1
1886 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1887 EXC_COMMON_BEGIN(doorbell_super_common)
1888 GEN_COMMON doorbell_super
1890 addi r3,r1,STACK_FRAME_OVERHEAD
1891 #ifdef CONFIG_PPC_DOORBELL
1892 bl doorbell_exception
1894 bl unknown_async_exception
1898 GEN_KVM doorbell_super
1901 EXC_REAL_NONE(0xb00, 0x100)
1902 EXC_VIRT_NONE(0x4b00, 0x100)
1905 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1906 * This is a synchronous interrupt invoked with the "sc" instruction. The
1907 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1908 * is directed to the currently running OS. The hypercall is invoked with
1909 * "sc 1" and it sets HV=1, so it elevates to hypervisor.
1911 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1912 * 0x4c00 virtual mode.
1915 * If the KVM test fires then it was due to a hypercall and is accordingly
1916 * routed to KVM. Otherwise this executes a normal Linux system call.
1920 * syscall and hypercalls register conventions are documented in
1921 * Documentation/powerpc/syscall64-abi.rst and
1922 * Documentation/powerpc/papr_hcalls.rst respectively.
1924 * The intersection of volatile registers that don't contain possible
1925 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1926 * without saving, though xer is not a good idea to use, as hardware may
1927 * interpret some bits so it may be costly to change them.
1929 INT_DEFINE_BEGIN(system_call)
1933 INT_DEFINE_END(system_call)
1935 .macro SYSTEM_CALL virt
1936 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1938 * There is a little bit of juggling to get syscall and hcall
1939 * working well. Save r13 in ctr to avoid using SPRG scratch
1942 * Userspace syscalls have already saved the PPR, hcalls must save
1943 * it before setting HMT_MEDIUM.
1947 std r10,PACA_EXGEN+EX_R10(r13)
1949 KVMTEST system_call /* uses r10, branch to system_call_kvm */
1957 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1961 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1964 /* We reach here with PACA in r13, r13 in r9. */
1971 __LOAD_HANDLER(r10, system_call_common_real)
1976 mtmsrd r10,1 /* Set RI (EE=0) */
1977 #ifdef CONFIG_RELOCATABLE
1978 __LOAD_HANDLER(r10, system_call_common)
1982 b system_call_common
1986 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1987 /* Fast LE/BE switch system call */
1988 1: mfspr r12,SPRN_SRR1
1992 RFI_TO_USER /* return to userspace */
1993 b . /* prevent speculative execution */
1997 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1999 EXC_REAL_END(system_call, 0xc00, 0x100)
2000 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2002 EXC_VIRT_END(system_call, 0x4c00, 0x100)
2004 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2005 TRAMP_REAL_BEGIN(system_call_kvm)
2007 * This is a hcall, so register convention is as above, with these
2011 * orig r10 saved in PACA
2014 * Save the PPR (on systems that support it) before changing to
2015 * HMT_MEDIUM. That allows the KVM code to save that value into the
2016 * guest state (it is the guest's PPR value).
2020 std r10,HSTATE_PPR(r13)
2021 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2026 std r12,HSTATE_SCRATCH0(r13)
2029 #ifdef CONFIG_RELOCATABLE
2031 * Requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives
2032 * outside the head section.
2034 __LOAD_FAR_HANDLER(r10, kvmppc_interrupt)
2036 ld r10,PACA_EXGEN+EX_R10(r13)
2039 ld r10,PACA_EXGEN+EX_R10(r13)
2046 * Interrupt 0xd00 - Trace Interrupt.
2047 * This is a synchronous interrupt in response to instruction step or
2048 * breakpoint faults.
2050 INT_DEFINE_BEGIN(single_step)
2052 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2055 INT_DEFINE_END(single_step)
2057 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2058 GEN_INT_ENTRY single_step, virt=0
2059 EXC_REAL_END(single_step, 0xd00, 0x100)
2060 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2061 GEN_INT_ENTRY single_step, virt=1
2062 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2063 EXC_COMMON_BEGIN(single_step_common)
2064 GEN_COMMON single_step
2065 addi r3,r1,STACK_FRAME_OVERHEAD
2066 bl single_step_exception
2073 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2074 * This is a synchronous interrupt in response to an MMU fault caused by a
2075 * guest data access.
2078 * This should always get routed to KVM. In radix MMU mode, this is caused
2079 * by a guest nested radix access that can't be performed due to the
2080 * partition scope page table. In hash mode, this can be caused by guests
2081 * running with translation disabled (virtual real mode) or with VPM enabled.
2082 * KVM will update the page table structures or disallow the access.
2084 INT_DEFINE_BEGIN(h_data_storage)
2092 INT_DEFINE_END(h_data_storage)
2094 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2095 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2096 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2097 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2098 GEN_INT_ENTRY h_data_storage, virt=1, ool=1
2099 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2100 EXC_COMMON_BEGIN(h_data_storage_common)
2101 GEN_COMMON h_data_storage
2102 addi r3,r1,STACK_FRAME_OVERHEAD
2103 BEGIN_MMU_FTR_SECTION
2104 bl do_bad_page_fault_segv
2105 MMU_FTR_SECTION_ELSE
2106 bl unknown_exception
2107 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2110 GEN_KVM h_data_storage
2114 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2115 * This is a synchronous interrupt in response to an MMU fault caused by a
2116 * guest instruction fetch, similar to HDSI.
2118 INT_DEFINE_BEGIN(h_instr_storage)
2123 INT_DEFINE_END(h_instr_storage)
2125 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2126 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2127 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2128 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2129 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1
2130 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2131 EXC_COMMON_BEGIN(h_instr_storage_common)
2132 GEN_COMMON h_instr_storage
2133 addi r3,r1,STACK_FRAME_OVERHEAD
2134 bl unknown_exception
2137 GEN_KVM h_instr_storage
2141 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2143 INT_DEFINE_BEGIN(emulation_assist)
2148 INT_DEFINE_END(emulation_assist)
2150 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2151 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2152 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2153 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2154 GEN_INT_ENTRY emulation_assist, virt=1, ool=1
2155 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2156 EXC_COMMON_BEGIN(emulation_assist_common)
2157 GEN_COMMON emulation_assist
2158 addi r3,r1,STACK_FRAME_OVERHEAD
2159 bl emulation_assist_interrupt
2160 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2163 GEN_KVM emulation_assist
2167 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2168 * This is an asynchronous interrupt caused by a Hypervisor Maintenance
2169 * Exception. It is always taken in real mode but uses HSRR registers
2170 * unlike SRESET and MCE.
2172 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable
2173 * with IRQS_DISABLED mask (i.e., local_irq_disable()).
2176 * This is a special case, this is handled similarly to machine checks, with an
2177 * initial real mode handler that is not soft-masked, which attempts to fix the
2178 * problem. Then a regular handler which is soft-maskable and reports the
2181 * The emergency stack is used for the early real mode handler.
2183 * XXX: unclear why MCE and HMI schemes could not be made common, e.g.,
2184 * either use soft-masking for the MCE, or use irq_work for the HMI.
2187 * Unlike MCE, this calls into KVM without calling the real mode handler
2190 INT_DEFINE_BEGIN(hmi_exception_early)
2195 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2197 INT_DEFINE_END(hmi_exception_early)
2199 INT_DEFINE_BEGIN(hmi_exception)
2204 INT_DEFINE_END(hmi_exception)
2206 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2207 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2208 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2209 EXC_VIRT_NONE(0x4e60, 0x20)
2211 EXC_COMMON_BEGIN(hmi_exception_early_common)
2212 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early
2214 mr r10,r1 /* Save r1 */
2215 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
2216 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
2218 __GEN_COMMON_BODY hmi_exception_early
2220 addi r3,r1,STACK_FRAME_OVERHEAD
2221 bl hmi_exception_realmode
2225 EXCEPTION_RESTORE_REGS hsrr=1
2226 HRFI_TO_USER_OR_KERNEL
2230 * Go to virtual mode and pull the HMI event information from
2233 EXCEPTION_RESTORE_REGS hsrr=1
2234 GEN_INT_ENTRY hmi_exception, virt=0
2236 GEN_KVM hmi_exception_early
2238 EXC_COMMON_BEGIN(hmi_exception_common)
2239 GEN_COMMON hmi_exception
2241 addi r3,r1,STACK_FRAME_OVERHEAD
2242 bl handle_hmi_exception
2245 GEN_KVM hmi_exception
2249 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2250 * This is an asynchronous interrupt in response to a msgsnd doorbell.
2251 * Similar to the 0xa00 doorbell but for host rather than guest.
2253 INT_DEFINE_BEGIN(h_doorbell)
2259 INT_DEFINE_END(h_doorbell)
2261 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2262 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2263 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2264 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2265 GEN_INT_ENTRY h_doorbell, virt=1, ool=1
2266 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2267 EXC_COMMON_BEGIN(h_doorbell_common)
2268 GEN_COMMON h_doorbell
2270 addi r3,r1,STACK_FRAME_OVERHEAD
2271 #ifdef CONFIG_PPC_DOORBELL
2272 bl doorbell_exception
2274 bl unknown_async_exception
2282 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2283 * This is an asynchronous interrupt in response to an "external exception".
2284 * Similar to 0x500 but for host only.
2286 INT_DEFINE_BEGIN(h_virt_irq)
2292 INT_DEFINE_END(h_virt_irq)
2294 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2295 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2296 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2297 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2298 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1
2299 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2300 EXC_COMMON_BEGIN(h_virt_irq_common)
2301 GEN_COMMON h_virt_irq
2303 addi r3,r1,STACK_FRAME_OVERHEAD
2310 EXC_REAL_NONE(0xec0, 0x20)
2311 EXC_VIRT_NONE(0x4ec0, 0x20)
2312 EXC_REAL_NONE(0xee0, 0x20)
2313 EXC_VIRT_NONE(0x4ee0, 0x20)
2317 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2318 * This is an asynchronous interrupt in response to a PMU exception.
2319 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
2320 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()).
2323 * This calls into the perf subsystem.
2325 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it
2326 * runs under local_irq_disable. However it may be soft-masked in
2327 * powerpc-specific code.
2329 * If soft masked, the masked handler will note the pending interrupt for
2330 * replay, and clear MSR[EE] in the interrupted context.
2332 INT_DEFINE_BEGIN(performance_monitor)
2334 IMASK=IRQS_PMI_DISABLED
2335 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2338 INT_DEFINE_END(performance_monitor)
2340 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2341 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2342 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2343 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2344 GEN_INT_ENTRY performance_monitor, virt=1, ool=1
2345 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2346 EXC_COMMON_BEGIN(performance_monitor_common)
2347 GEN_COMMON performance_monitor
2349 addi r3,r1,STACK_FRAME_OVERHEAD
2350 bl performance_monitor_exception
2353 GEN_KVM performance_monitor
2357 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2358 * This is a synchronous interrupt in response to
2359 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2360 * Similar to FP unavailable.
2362 INT_DEFINE_BEGIN(altivec_unavailable)
2364 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2367 INT_DEFINE_END(altivec_unavailable)
2369 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2370 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2371 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2372 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2373 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1
2374 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2375 EXC_COMMON_BEGIN(altivec_unavailable_common)
2376 GEN_COMMON altivec_unavailable
2377 #ifdef CONFIG_ALTIVEC
2380 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2381 BEGIN_FTR_SECTION_NESTED(69)
2382 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2383 * transaction), go do TM stuff
2385 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2387 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2390 b fast_interrupt_return
2391 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2392 2: /* User process was in a transaction */
2393 addi r3,r1,STACK_FRAME_OVERHEAD
2394 bl altivec_unavailable_tm
2398 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2400 addi r3,r1,STACK_FRAME_OVERHEAD
2401 bl altivec_unavailable_exception
2404 GEN_KVM altivec_unavailable
2408 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2409 * This is a synchronous interrupt in response to
2410 * executing a VSX instruction with MSR[VSX]=0.
2411 * Similar to FP unavailable.
2413 INT_DEFINE_BEGIN(vsx_unavailable)
2415 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2418 INT_DEFINE_END(vsx_unavailable)
2420 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2421 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2422 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2423 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2424 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1
2425 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2426 EXC_COMMON_BEGIN(vsx_unavailable_common)
2427 GEN_COMMON vsx_unavailable
2431 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2432 BEGIN_FTR_SECTION_NESTED(69)
2433 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2434 * transaction), go do TM stuff
2436 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2438 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2441 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2442 2: /* User process was in a transaction */
2443 addi r3,r1,STACK_FRAME_OVERHEAD
2444 bl vsx_unavailable_tm
2448 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2450 addi r3,r1,STACK_FRAME_OVERHEAD
2451 bl vsx_unavailable_exception
2454 GEN_KVM vsx_unavailable
2458 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2459 * This is a synchronous interrupt in response to
2460 * executing an instruction without access to the facility that can be
2461 * resolved by the OS (e.g., FSCR, MSR).
2462 * Similar to FP unavailable.
2464 INT_DEFINE_BEGIN(facility_unavailable)
2466 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2469 INT_DEFINE_END(facility_unavailable)
2471 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2472 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2473 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2474 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2475 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1
2476 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2477 EXC_COMMON_BEGIN(facility_unavailable_common)
2478 GEN_COMMON facility_unavailable
2479 addi r3,r1,STACK_FRAME_OVERHEAD
2480 bl facility_unavailable_exception
2481 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2484 GEN_KVM facility_unavailable
2488 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2489 * This is a synchronous interrupt in response to
2490 * executing an instruction without access to the facility that can only
2491 * be resolved in HV mode (e.g., HFSCR).
2492 * Similar to FP unavailable.
2494 INT_DEFINE_BEGIN(h_facility_unavailable)
2499 INT_DEFINE_END(h_facility_unavailable)
2501 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2502 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2503 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2504 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2505 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1
2506 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2507 EXC_COMMON_BEGIN(h_facility_unavailable_common)
2508 GEN_COMMON h_facility_unavailable
2509 addi r3,r1,STACK_FRAME_OVERHEAD
2510 bl facility_unavailable_exception
2511 REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */
2514 GEN_KVM h_facility_unavailable
2517 EXC_REAL_NONE(0xfa0, 0x20)
2518 EXC_VIRT_NONE(0x4fa0, 0x20)
2519 EXC_REAL_NONE(0xfc0, 0x20)
2520 EXC_VIRT_NONE(0x4fc0, 0x20)
2521 EXC_REAL_NONE(0xfe0, 0x20)
2522 EXC_VIRT_NONE(0x4fe0, 0x20)
2524 EXC_REAL_NONE(0x1000, 0x100)
2525 EXC_VIRT_NONE(0x5000, 0x100)
2526 EXC_REAL_NONE(0x1100, 0x100)
2527 EXC_VIRT_NONE(0x5100, 0x100)
2529 #ifdef CONFIG_CBE_RAS
2530 INT_DEFINE_BEGIN(cbe_system_error)
2535 INT_DEFINE_END(cbe_system_error)
2537 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2538 GEN_INT_ENTRY cbe_system_error, virt=0
2539 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2540 EXC_VIRT_NONE(0x5200, 0x100)
2541 EXC_COMMON_BEGIN(cbe_system_error_common)
2542 GEN_COMMON cbe_system_error
2543 addi r3,r1,STACK_FRAME_OVERHEAD
2544 bl cbe_system_error_exception
2547 GEN_KVM cbe_system_error
2549 #else /* CONFIG_CBE_RAS */
2550 EXC_REAL_NONE(0x1200, 0x100)
2551 EXC_VIRT_NONE(0x5200, 0x100)
2555 INT_DEFINE_BEGIN(instruction_breakpoint)
2557 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2561 INT_DEFINE_END(instruction_breakpoint)
2563 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2564 GEN_INT_ENTRY instruction_breakpoint, virt=0
2565 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2566 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2567 GEN_INT_ENTRY instruction_breakpoint, virt=1
2568 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2569 EXC_COMMON_BEGIN(instruction_breakpoint_common)
2570 GEN_COMMON instruction_breakpoint
2571 addi r3,r1,STACK_FRAME_OVERHEAD
2572 bl instruction_breakpoint_exception
2575 GEN_KVM instruction_breakpoint
2578 EXC_REAL_NONE(0x1400, 0x100)
2579 EXC_VIRT_NONE(0x5400, 0x100)
2582 * Interrupt 0x1500 - Soft Patch Interrupt
2585 * This is an implementation specific interrupt which can be used for a
2586 * range of exceptions.
2588 * This interrupt handler is unique in that it runs the denormal assist
2589 * code even for guests (and even in guest context) without going to KVM,
2590 * for speed. POWER9 does not raise denorm exceptions, so this special case
2591 * could be phased out in future to reduce special cases.
2593 INT_DEFINE_BEGIN(denorm_exception)
2598 INT_DEFINE_END(denorm_exception)
2600 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2601 GEN_INT_ENTRY denorm_exception, virt=0
2602 #ifdef CONFIG_PPC_DENORMALISATION
2603 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2606 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2607 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2608 #ifdef CONFIG_PPC_DENORMALISATION
2609 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2610 GEN_INT_ENTRY denorm_exception, virt=1
2611 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2613 GEN_BRANCH_TO_COMMON denorm_exception, virt=1
2614 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2616 EXC_VIRT_NONE(0x5500, 0x100)
2619 #ifdef CONFIG_PPC_DENORMALISATION
2620 TRAMP_REAL_BEGIN(denorm_assist)
2623 * To denormalise we need to move a copy of the register to itself.
2624 * For POWER6 do that here for all FP regs.
2627 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2628 xori r10,r10,(MSR_FE0|MSR_FE1)
2640 * To denormalise we need to move a copy of the register to itself.
2641 * For POWER7 do that here for the first 32 VSX registers only.
2644 oris r10,r10,MSR_VSX@h
2650 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2654 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2658 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2660 * To denormalise we need to move a copy of the register to itself.
2661 * For POWER8 we need to do that for all 64 VSX registers
2665 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2670 mfspr r11,SPRN_HSRR0
2672 mtspr SPRN_HSRR0,r11
2674 ld r9,PACA_EXGEN+EX_R9(r13)
2676 ld r10,PACA_EXGEN+EX_PPR(r13)
2678 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2680 ld r10,PACA_EXGEN+EX_CFAR(r13)
2682 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2683 ld r10,PACA_EXGEN+EX_R10(r13)
2684 ld r11,PACA_EXGEN+EX_R11(r13)
2685 ld r12,PACA_EXGEN+EX_R12(r13)
2686 ld r13,PACA_EXGEN+EX_R13(r13)
2691 EXC_COMMON_BEGIN(denorm_exception_common)
2692 GEN_COMMON denorm_exception
2693 addi r3,r1,STACK_FRAME_OVERHEAD
2694 bl unknown_exception
2697 GEN_KVM denorm_exception
2700 #ifdef CONFIG_CBE_RAS
2701 INT_DEFINE_BEGIN(cbe_maintenance)
2706 INT_DEFINE_END(cbe_maintenance)
2708 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2709 GEN_INT_ENTRY cbe_maintenance, virt=0
2710 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2711 EXC_VIRT_NONE(0x5600, 0x100)
2712 EXC_COMMON_BEGIN(cbe_maintenance_common)
2713 GEN_COMMON cbe_maintenance
2714 addi r3,r1,STACK_FRAME_OVERHEAD
2715 bl cbe_maintenance_exception
2718 GEN_KVM cbe_maintenance
2720 #else /* CONFIG_CBE_RAS */
2721 EXC_REAL_NONE(0x1600, 0x100)
2722 EXC_VIRT_NONE(0x5600, 0x100)
2726 INT_DEFINE_BEGIN(altivec_assist)
2728 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2731 INT_DEFINE_END(altivec_assist)
2733 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2734 GEN_INT_ENTRY altivec_assist, virt=0
2735 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2736 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2737 GEN_INT_ENTRY altivec_assist, virt=1
2738 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2739 EXC_COMMON_BEGIN(altivec_assist_common)
2740 GEN_COMMON altivec_assist
2741 addi r3,r1,STACK_FRAME_OVERHEAD
2742 #ifdef CONFIG_ALTIVEC
2743 bl altivec_assist_exception
2744 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2746 bl unknown_exception
2750 GEN_KVM altivec_assist
2753 #ifdef CONFIG_CBE_RAS
2754 INT_DEFINE_BEGIN(cbe_thermal)
2759 INT_DEFINE_END(cbe_thermal)
2761 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2762 GEN_INT_ENTRY cbe_thermal, virt=0
2763 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2764 EXC_VIRT_NONE(0x5800, 0x100)
2765 EXC_COMMON_BEGIN(cbe_thermal_common)
2766 GEN_COMMON cbe_thermal
2767 addi r3,r1,STACK_FRAME_OVERHEAD
2768 bl cbe_thermal_exception
2773 #else /* CONFIG_CBE_RAS */
2774 EXC_REAL_NONE(0x1800, 0x100)
2775 EXC_VIRT_NONE(0x5800, 0x100)
2779 #ifdef CONFIG_PPC_WATCHDOG
2781 INT_DEFINE_BEGIN(soft_nmi)
2784 INT_DEFINE_END(soft_nmi)
2787 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2788 * stack is one that is usable by maskable interrupts so long as MSR_EE
2789 * remains off. It is used for recovery when something has corrupted the
2790 * normal kernel stack, for example. The "soft NMI" must not use the process
2791 * stack because we want irq disabled sections to avoid touching the stack
2792 * at all (other than PMU interrupts), so use the emergency stack for this,
2793 * and run it entirely with interrupts hard disabled.
2795 EXC_COMMON_BEGIN(soft_nmi_common)
2798 ld r1,PACAEMERGSP(r13)
2799 subi r1,r1,INT_FRAME_SIZE
2800 __GEN_COMMON_BODY soft_nmi
2802 addi r3,r1,STACK_FRAME_OVERHEAD
2803 bl soft_nmi_interrupt
2805 /* Clear MSR_RI before setting SRR0 and SRR1. */
2809 kuap_kernel_restore r9, r10
2810 EXCEPTION_RESTORE_REGS hsrr=0
2813 #endif /* CONFIG_PPC_WATCHDOG */
2816 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2817 * - If it was a decrementer interrupt, we bump the dec to max and and return.
2818 * - If it was a doorbell we return immediately since doorbells are edge
2819 * triggered and won't automatically refire.
2820 * - If it was a HMI we return immediately since we handled it in realmode
2821 * and it won't refire.
2822 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2823 * This is called with r10 containing the value to OR to the paca field.
2825 .macro MASKED_INTERRUPT hsrr=0
2831 lbz r11,PACAIRQHAPPENED(r13)
2833 stb r11,PACAIRQHAPPENED(r13)
2834 cmpwi r10,PACA_IRQ_DEC
2839 #ifdef CONFIG_PPC_WATCHDOG
2844 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2846 xori r12,r12,MSR_EE /* clear MSR_EE */
2848 mtspr SPRN_HSRR1,r12
2852 ori r11,r11,PACA_IRQ_HARD_DIS
2853 stb r11,PACAIRQHAPPENED(r13)
2855 ld r10,PACA_EXGEN+EX_CTR(r13)
2859 ld r9,PACA_EXGEN+EX_R9(r13)
2860 ld r10,PACA_EXGEN+EX_R10(r13)
2861 ld r11,PACA_EXGEN+EX_R11(r13)
2862 ld r12,PACA_EXGEN+EX_R12(r13)
2863 ld r13,PACA_EXGEN+EX_R13(r13)
2864 /* May return to masked low address where r13 is not set up */
2873 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2874 std r9,PACA_EXRFI+EX_R9(r13)
2875 std r10,PACA_EXRFI+EX_R10(r13)
2877 ld r9,PACA_EXRFI+EX_R9(r13)
2878 ld r10,PACA_EXRFI+EX_R10(r13)
2886 /* Clobbers r10, r11, ctr */
2887 .macro L1D_DISPLACEMENT_FLUSH
2888 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2889 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2890 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2892 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2894 /* order ld/st prior to dcbt stop all streams with flushing */
2898 * The load addresses are at staggered offsets within cachelines,
2899 * which suits some pipelines better (on others it should not
2903 ld r11,(0x80 + 8)*0(r10)
2904 ld r11,(0x80 + 8)*1(r10)
2905 ld r11,(0x80 + 8)*2(r10)
2906 ld r11,(0x80 + 8)*3(r10)
2907 ld r11,(0x80 + 8)*4(r10)
2908 ld r11,(0x80 + 8)*5(r10)
2909 ld r11,(0x80 + 8)*6(r10)
2910 ld r11,(0x80 + 8)*7(r10)
2915 TRAMP_REAL_BEGIN(entry_flush_fallback)
2916 std r9,PACA_EXRFI+EX_R9(r13)
2917 std r10,PACA_EXRFI+EX_R10(r13)
2918 std r11,PACA_EXRFI+EX_R11(r13)
2920 L1D_DISPLACEMENT_FLUSH
2922 ld r9,PACA_EXRFI+EX_R9(r13)
2923 ld r10,PACA_EXRFI+EX_R10(r13)
2924 ld r11,PACA_EXRFI+EX_R11(r13)
2928 * The SCV entry flush happens with interrupts enabled, so it must disable
2929 * to prevent EXRFI being clobbered by NMIs (e.g., soft_nmi_common). r10
2930 * (containing LR) does not need to be preserved here because scv entry
2931 * puts 0 in the pt_regs, CTR can be clobbered for the same reason.
2933 TRAMP_REAL_BEGIN(scv_entry_flush_fallback)
2936 lbz r10,PACAIRQHAPPENED(r13)
2937 ori r10,r10,PACA_IRQ_HARD_DIS
2938 stb r10,PACAIRQHAPPENED(r13)
2939 std r11,PACA_EXRFI+EX_R11(r13)
2940 L1D_DISPLACEMENT_FLUSH
2941 ld r11,PACA_EXRFI+EX_R11(r13)
2946 TRAMP_REAL_BEGIN(rfi_flush_fallback)
2949 std r1,PACA_EXRFI+EX_R12(r13)
2950 ld r1,PACAKSAVE(r13)
2951 std r9,PACA_EXRFI+EX_R9(r13)
2952 std r10,PACA_EXRFI+EX_R10(r13)
2953 std r11,PACA_EXRFI+EX_R11(r13)
2955 L1D_DISPLACEMENT_FLUSH
2957 ld r9,PACA_EXRFI+EX_R9(r13)
2958 ld r10,PACA_EXRFI+EX_R10(r13)
2959 ld r11,PACA_EXRFI+EX_R11(r13)
2960 ld r1,PACA_EXRFI+EX_R12(r13)
2964 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2967 std r1,PACA_EXRFI+EX_R12(r13)
2968 ld r1,PACAKSAVE(r13)
2969 std r9,PACA_EXRFI+EX_R9(r13)
2970 std r10,PACA_EXRFI+EX_R10(r13)
2971 std r11,PACA_EXRFI+EX_R11(r13)
2973 L1D_DISPLACEMENT_FLUSH
2975 ld r9,PACA_EXRFI+EX_R9(r13)
2976 ld r10,PACA_EXRFI+EX_R10(r13)
2977 ld r11,PACA_EXRFI+EX_R11(r13)
2978 ld r1,PACA_EXRFI+EX_R12(r13)
2982 TRAMP_REAL_BEGIN(rfscv_flush_fallback)
2983 /* system call volatile */
2987 ld r1,PACAKSAVE(r13)
2989 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2990 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2991 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2993 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2995 /* order ld/st prior to dcbt stop all streams with flushing */
2999 * The load adresses are at staggered offsets within cachelines,
3000 * which suits some pipelines better (on others it should not
3004 ld r11,(0x80 + 8)*0(r10)
3005 ld r11,(0x80 + 8)*1(r10)
3006 ld r11,(0x80 + 8)*2(r10)
3007 ld r11,(0x80 + 8)*3(r10)
3008 ld r11,(0x80 + 8)*4(r10)
3009 ld r11,(0x80 + 8)*5(r10)
3010 ld r11,(0x80 + 8)*6(r10)
3011 ld r11,(0x80 + 8)*7(r10)
3025 _GLOBAL(do_uaccess_flush)
3026 UACCESS_FLUSH_FIXUP_SECTION
3031 L1D_DISPLACEMENT_FLUSH
3033 _ASM_NOKPROBE_SYMBOL(do_uaccess_flush)
3034 EXPORT_SYMBOL(do_uaccess_flush)
3038 MASKED_INTERRUPT hsrr=1
3040 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
3041 kvmppc_skip_interrupt:
3043 * Here all GPRs are unchanged from when the interrupt happened
3044 * except for r13, which is saved in SPRG_SCRATCH0.
3046 mfspr r13, SPRN_SRR0
3048 mtspr SPRN_SRR0, r13
3053 kvmppc_skip_Hinterrupt:
3055 * Here all GPRs are unchanged from when the interrupt happened
3056 * except for r13, which is saved in SPRG_SCRATCH0.
3058 mfspr r13, SPRN_HSRR0
3060 mtspr SPRN_HSRR0, r13
3067 * Relocation-on interrupts: A subset of the interrupts can be delivered
3068 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
3069 * it. Addresses are the same as the original interrupt addresses, but
3070 * offset by 0xc000000000004000.
3071 * It's impossible to receive interrupts below 0x300 via this mechanism.
3072 * KVM: None of these traps are from the guest ; anything that escalated
3073 * to HV=1 from HV=0 is delivered via real mode handlers.
3077 * This uses the standard macro, since the original 0x300 vector
3078 * only has extra guff for STAB-based processors -- which never
3082 USE_FIXED_SECTION(virt_trampolines)
3084 * All code below __end_interrupts is treated as soft-masked. If
3085 * any code runs here with MSR[EE]=1, it must then cope with pending
3086 * soft interrupt being raised (i.e., by ensuring it is replayed).
3088 * The __end_interrupts marker must be past the out-of-line (OOL)
3089 * handlers, so that they are copied to real address 0x100 when running
3090 * a relocatable kernel. This ensures they can be reached from the short
3091 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3092 * directly, without using LOAD_HANDLER().
3095 .globl __end_interrupts
3097 DEFINE_FIXED_SYMBOL(__end_interrupts)
3099 #ifdef CONFIG_PPC_970_NAP
3101 * Called by exception entry code if _TLF_NAPPING was set, this clears
3102 * the NAPPING flag, and redirects the exception exit to
3103 * power4_fixup_nap_return.
3105 .globl power4_fixup_nap
3106 EXC_COMMON_BEGIN(power4_fixup_nap)
3108 std r9,TI_LOCAL_FLAGS(r11)
3109 LOAD_REG_ADDR(r10, power4_idle_nap_return)
3113 power4_idle_nap_return:
3117 CLOSE_FIXED_SECTION(real_vectors);
3118 CLOSE_FIXED_SECTION(real_trampolines);
3119 CLOSE_FIXED_SECTION(virt_vectors);
3120 CLOSE_FIXED_SECTION(virt_trampolines);
3124 /* MSR[RI] should be clear because this uses SRR[01] */
3125 enable_machine_check:
3129 addi r3,r3,(1f - 0b)
3138 /* MSR[RI] should be clear because this uses SRR[01] */
3139 disable_machine_check:
3143 addi r3,r3,(1f - 0b)