1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
23 * There are a few constraints to be concerned with.
24 * - Real mode exceptions code/data must be located at their physical location.
25 * - Virtual mode exceptions must be mapped at their 0xc000... location.
26 * - Fixed location code must not call directly beyond the __end_interrupts
27 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
29 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
31 * - Conditional branch targets must be within +/-32K of caller.
33 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
34 * therefore don't have to run in physically located code or rfid to
35 * virtual mode kernel code. However on relocatable kernels they do have
36 * to branch to KERNELBASE offset because the rest of the kernel (outside
37 * the exception vectors) may be located elsewhere.
39 * Virtual exceptions correspond with physical, except their entry points
40 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
41 * offset applied. Virtual exceptions are enabled with the Alternate
42 * Interrupt Location (AIL) bit set in the LPCR. However this does not
43 * guarantee they will be delivered virtually. Some conditions (see the ISA)
44 * cause exceptions to be delivered in real mode.
46 * It's impossible to receive interrupts below 0x300 via AIL.
48 * KVM: None of the virtual exceptions are from the guest. Anything that
49 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
52 * We layout physical memory as follows:
53 * 0x0000 - 0x00ff : Secondary processor spin code
54 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
55 * 0x1900 - 0x3fff : Real mode trampolines
56 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
57 * 0x5900 - 0x6fff : Relon mode trampolines
58 * 0x7000 - 0x7fff : FWNMI data area
59 * 0x8000 - .... : Common interrupt handlers, remaining early
60 * setup code, rest of kernel.
62 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
63 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
66 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
67 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
68 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
69 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
70 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
72 * Data area reserved for FWNMI option.
73 * This address (0x7000) is fixed by the RPA.
74 * pseries and powernv need to keep the whole page from
75 * 0x7000 to 0x8000 free for use by the firmware
77 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
78 OPEN_TEXT_SECTION(0x8000)
80 OPEN_TEXT_SECTION(0x7000)
83 USE_FIXED_SECTION(real_vectors)
86 * This is the start of the interrupt handlers for pSeries
87 * This code runs with relocation off.
88 * Code from here to __end_interrupts gets copied down to real
89 * address 0x100 when we are running a relocatable kernel.
90 * Therefore any relative branches in this section must only
91 * branch to labels in this section.
93 .globl __start_interrupts
96 /* No virt vectors corresponding with 0x0..0x100 */
97 EXC_VIRT_NONE(0x4000, 0x100)
100 #ifdef CONFIG_PPC_P7_NAP
102 * If running native on arch 2.06 or later, check if we are waking up
103 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
104 * bits 46:47. A non-0 value indicates that we are coming from a power
105 * saving state. The idle wakeup handler initially runs in real mode,
106 * but we branch to the 0xc000... address so we can turn on relocation
109 #define IDLETEST(n) \
110 BEGIN_FTR_SECTION ; \
111 mfspr r10,SPRN_SRR1 ; \
112 rlwinm. r10,r10,47-31,30,31 ; \
115 BRANCH_TO_C000(r10, system_reset_idle_common) ; \
118 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
120 #define IDLETEST NOTEST
123 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
126 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
127 * being used, so a nested NMI exception would corrupt it.
129 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
132 EXC_REAL_END(system_reset, 0x100, 0x100)
133 EXC_VIRT_NONE(0x4100, 0x100)
134 TRAMP_KVM(PACA_EXNMI, 0x100)
136 #ifdef CONFIG_PPC_P7_NAP
137 EXC_COMMON_BEGIN(system_reset_idle_common)
139 b pnv_powersave_wakeup
143 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
144 * the right thing. We do not want to reconcile because that goes
145 * through irq tracing which we don't want in NMI.
147 * Save PACAIRQHAPPENED because some code will do a hard disable
148 * (e.g., xmon). So we want to restore this back to where it was
149 * when we return. DAR is unused in the stack, so save it there.
151 #define ADD_RECONCILE_NMI \
152 li r10,IRQS_ALL_DISABLED; \
153 stb r10,PACAIRQSOFTMASK(r13); \
154 lbz r10,PACAIRQHAPPENED(r13); \
157 EXC_COMMON_BEGIN(system_reset_common)
159 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
160 * to recover, but nested NMI will notice in_nmi and not recover
161 * because of the use of the NMI stack. in_nmi reentrancy is tested in
162 * system_reset_exception.
164 lhz r10,PACA_IN_NMI(r13)
166 sth r10,PACA_IN_NMI(r13)
171 ld r1,PACA_NMI_EMERG_SP(r13)
172 subi r1,r1,INT_FRAME_SIZE
173 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
174 system_reset, system_reset_exception,
175 ADD_NVGPRS;ADD_RECONCILE_NMI)
177 /* This (and MCE) can be simplified with mtmsrd L=1 */
178 /* Clear MSR_RI before setting SRR0 and SRR1. */
185 * MSR_RI is clear, now we can decrement paca->in_nmi.
187 lhz r10,PACA_IN_NMI(r13)
189 sth r10,PACA_IN_NMI(r13)
192 * Restore soft mask settings.
195 stb r10,PACAIRQHAPPENED(r13)
197 stb r10,PACAIRQSOFTMASK(r13)
200 * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
201 * Should share common bits...
204 /* Move original SRR0 and SRR1 into the respective regs */
222 /* restore original r1. */
224 RFI_TO_USER_OR_KERNEL
226 #ifdef CONFIG_PPC_PSERIES
228 * Vectors for the FWNMI option. Share common code.
230 TRAMP_REAL_BEGIN(system_reset_fwnmi)
231 SET_SCRATCH0(r13) /* save r13 */
232 /* See comment at system_reset exception */
233 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
234 EXC_STD, NOTEST, 0x100)
235 #endif /* CONFIG_PPC_PSERIES */
238 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
239 /* This is moved out of line as it can be patched by FW, but
240 * some code path might still want to branch into the original
243 SET_SCRATCH0(r13) /* save r13 */
244 EXCEPTION_PROLOG_0(PACA_EXMC)
246 b machine_check_powernv_early
248 b machine_check_pSeries_0
249 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
250 EXC_REAL_END(machine_check, 0x200, 0x100)
251 EXC_VIRT_NONE(0x4200, 0x100)
252 TRAMP_REAL_BEGIN(machine_check_powernv_early)
254 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
259 * Original R9 to R13 is saved on PACA_EXMC
261 * Switch to mc_emergency stack and handle re-entrancy (we limit
262 * the nested MCE upto level 4 to avoid stack overflow).
263 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
265 * We use paca->in_mce to check whether this is the first entry or
266 * nested machine check. We increment paca->in_mce to track nested
269 * If this is the first entry then set stack pointer to
270 * paca->mc_emergency_sp, otherwise r1 is already pointing to
271 * stack frame on mc_emergency stack.
273 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
274 * checkstop if we get another machine check exception before we do
275 * rfid with MSR_ME=1.
277 * This interrupt can wake directly from idle. If that is the case,
278 * the machine check is handled then the idle wakeup code is called
281 mr r11,r1 /* Save r1 */
282 lhz r10,PACA_IN_MCE(r13)
283 cmpwi r10,0 /* Are we in nested machine check */
284 bne 0f /* Yes, we are. */
285 /* First machine check entry */
286 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
287 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
288 addi r10,r10,1 /* increment paca->in_mce */
289 sth r10,PACA_IN_MCE(r13)
290 /* Limit nested MCE to level 4 to avoid stack overflow */
291 cmpwi r10,MAX_MCE_DEPTH
292 bgt 2f /* Check if we hit limit of 4 */
293 std r11,GPR1(r1) /* Save r1 on the stack. */
294 std r11,0(r1) /* make stack chain pointer */
295 mfspr r11,SPRN_SRR0 /* Save SRR0 */
297 mfspr r11,SPRN_SRR1 /* Save SRR1 */
299 mfspr r11,SPRN_DAR /* Save DAR */
301 mfspr r11,SPRN_DSISR /* Save DSISR */
303 std r9,_CCR(r1) /* Save CR in stackframe */
304 /* Save r9 through r13 from EXMC save area to stack frame. */
305 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
306 mfmsr r11 /* get MSR value */
307 ori r11,r11,MSR_ME /* turn on ME bit */
308 ori r11,r11,MSR_RI /* turn on RI bit */
309 LOAD_HANDLER(r12, machine_check_handle_early)
310 1: mtspr SPRN_SRR0,r12
313 b . /* prevent speculative execution */
315 /* Stack overflow. Stay on emergency stack and panic.
316 * Keep the ME bit off while panic-ing, so that if we hit
317 * another machine check we checkstop.
319 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
321 LOAD_HANDLER(r12, unrecover_mce)
323 andc r11,r11,r10 /* Turn off MSR_ME */
325 b . /* prevent speculative execution */
326 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
328 TRAMP_REAL_BEGIN(machine_check_pSeries)
329 .globl machine_check_fwnmi
331 SET_SCRATCH0(r13) /* save r13 */
332 EXCEPTION_PROLOG_0(PACA_EXMC)
333 machine_check_pSeries_0:
334 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
336 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
337 * nested machine check corrupts it. machine_check_common enables
340 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
342 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
344 EXC_COMMON_BEGIN(machine_check_common)
346 * Machine check is different because we use a different
347 * save area: PACA_EXMC instead of PACA_EXGEN.
350 std r10,PACA_EXMC+EX_DAR(r13)
352 stw r10,PACA_EXMC+EX_DSISR(r13)
353 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
355 RECONCILE_IRQ_STATE(r10, r11)
356 ld r3,PACA_EXMC+EX_DAR(r13)
357 lwz r4,PACA_EXMC+EX_DSISR(r13)
358 /* Enable MSR_RI when finished with PACA_EXMC */
364 addi r3,r1,STACK_FRAME_OVERHEAD
365 bl machine_check_exception
368 #define MACHINE_CHECK_HANDLER_WINDUP \
369 /* Clear MSR_RI before setting SRR0 and SRR1. */\
371 mfmsr r9; /* get MSR value */ \
373 mtmsrd r9,1; /* Clear MSR_RI */ \
374 /* Move original SRR0 and SRR1 into the respective regs */ \
376 mtspr SPRN_SRR1,r9; \
378 mtspr SPRN_SRR0,r3; \
390 /* Decrement paca->in_mce. */ \
391 lhz r12,PACA_IN_MCE(r13); \
393 sth r12,PACA_IN_MCE(r13); \
395 REST_2GPRS(12, r1); \
396 /* restore original r1. */ \
399 #ifdef CONFIG_PPC_P7_NAP
401 * This is an idle wakeup. Low level machine check has already been
402 * done. Queue the event then call the idle code to do the wake up.
404 EXC_COMMON_BEGIN(machine_check_idle_common)
405 bl machine_check_queue_event
408 * We have not used any non-volatile GPRs here, and as a rule
409 * most exception code including machine check does not.
410 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
411 * wakeup will restore volatile registers.
413 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
415 * Then decrement MCE nesting after finishing with the stack.
419 lhz r11,PACA_IN_MCE(r13)
421 sth r11,PACA_IN_MCE(r13)
423 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
424 /* Recoverability could be improved by reducing the use of SRR1. */
428 b pnv_powersave_wakeup_mce
431 * Handle machine check early in real mode. We come here with
432 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
434 EXC_COMMON_BEGIN(machine_check_handle_early)
435 std r0,GPR0(r1) /* Save r0 */
436 EXCEPTION_PROLOG_COMMON_3(0x200)
438 addi r3,r1,STACK_FRAME_OVERHEAD
439 bl machine_check_early
440 std r3,RESULT(r1) /* Save result */
443 #ifdef CONFIG_PPC_P7_NAP
445 * Check if thread was in power saving mode. We come here when any
446 * of the following is true:
447 * a. thread wasn't in power saving mode
448 * b. thread was in power saving mode with no state loss,
449 * supervisor state loss or hypervisor state loss.
451 * Go back to nap/sleep/winkle mode again if (b) is true.
454 rlwinm. r11,r12,47-31,30,31
455 bne machine_check_idle_common
456 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
460 * Check if we are coming from hypervisor userspace. If yes then we
461 * continue in host kernel in V mode to deliver the MC event.
463 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
465 andi. r11,r12,MSR_PR /* See if coming from user. */
466 bne 9f /* continue in V mode if we are. */
469 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
471 * We are coming from kernel context. Check if we are coming from
472 * guest. if yes, then we can continue. We will fall through
473 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
475 lbz r11,HSTATE_IN_GUEST(r13)
476 cmpwi r11,0 /* Check if coming from guest */
477 bne 9f /* continue if we are. */
480 * At this point we are not sure about what context we come from.
481 * Queue up the MCE event and return from the interrupt.
482 * But before that, check if this is an un-recoverable exception.
483 * If yes, then stay on emergency stack and panic.
487 1: mfspr r11,SPRN_SRR0
488 LOAD_HANDLER(r10,unrecover_mce)
492 * We are going down. But there are chances that we might get hit by
493 * another MCE during panic path and we may run into unstable state
494 * with no way out. Hence, turn ME bit off while going down, so that
495 * when another MCE is hit during panic path, system will checkstop
496 * and hypervisor will get restarted cleanly by SP.
499 andc r10,r10,r3 /* Turn off MSR_ME */
505 * Check if we have successfully handled/recovered from error, if not
506 * then stay on emergency stack and panic.
508 ld r3,RESULT(r1) /* Load result */
509 cmpdi r3,0 /* see if we handled MCE successfully */
511 beq 1b /* if !handled then panic */
513 * Return from MC interrupt.
514 * Queue up the MCE event so that we can log it later, while
515 * returning from kernel or opal call.
517 bl machine_check_queue_event
518 MACHINE_CHECK_HANDLER_WINDUP
519 RFI_TO_USER_OR_KERNEL
521 /* Deliver the machine check to host kernel in V mode. */
522 MACHINE_CHECK_HANDLER_WINDUP
523 b machine_check_pSeries
525 EXC_COMMON_BEGIN(unrecover_mce)
526 /* Invoke machine_check_exception to print MCE event and panic. */
527 addi r3,r1,STACK_FRAME_OVERHEAD
528 bl machine_check_exception
530 * We will not reach here. Even if we did, there is no way out. Call
531 * unrecoverable_exception and die.
533 1: addi r3,r1,STACK_FRAME_OVERHEAD
534 bl unrecoverable_exception
538 EXC_REAL(data_access, 0x300, 0x80)
539 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
540 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
542 EXC_COMMON_BEGIN(data_access_common)
544 * Here r13 points to the paca, r9 contains the saved CR,
545 * SRR0 and SRR1 are saved in r11 and r12,
546 * r9 - r13 are saved in paca->exgen.
549 std r10,PACA_EXGEN+EX_DAR(r13)
551 stw r10,PACA_EXGEN+EX_DSISR(r13)
552 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
553 RECONCILE_IRQ_STATE(r10, r11)
555 ld r3,PACA_EXGEN+EX_DAR(r13)
556 lwz r4,PACA_EXGEN+EX_DSISR(r13)
560 BEGIN_MMU_FTR_SECTION
561 b do_hash_page /* Try to handle as hpte fault */
564 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
567 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
569 EXCEPTION_PROLOG_0(PACA_EXSLB)
570 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
571 mr r12,r3 /* save r3 */
575 BRANCH_TO_COMMON(r10, slb_miss_common)
576 EXC_REAL_END(data_access_slb, 0x380, 0x80)
578 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
580 EXCEPTION_PROLOG_0(PACA_EXSLB)
581 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
582 mr r12,r3 /* save r3 */
586 BRANCH_TO_COMMON(r10, slb_miss_common)
587 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
588 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
591 EXC_REAL(instruction_access, 0x400, 0x80)
592 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
593 TRAMP_KVM(PACA_EXGEN, 0x400)
595 EXC_COMMON_BEGIN(instruction_access_common)
596 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
597 RECONCILE_IRQ_STATE(r10, r11)
600 andis. r4,r12,DSISR_SRR1_MATCH_64S@h
604 BEGIN_MMU_FTR_SECTION
605 b do_hash_page /* Try to handle as hpte fault */
608 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
611 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
613 EXCEPTION_PROLOG_0(PACA_EXSLB)
614 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
615 mr r12,r3 /* save r3 */
616 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
619 BRANCH_TO_COMMON(r10, slb_miss_common)
620 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
622 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
624 EXCEPTION_PROLOG_0(PACA_EXSLB)
625 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
626 mr r12,r3 /* save r3 */
627 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
630 BRANCH_TO_COMMON(r10, slb_miss_common)
631 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
632 TRAMP_KVM(PACA_EXSLB, 0x480)
636 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as
637 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled.
639 EXC_COMMON_BEGIN(slb_miss_common)
641 * r13 points to the PACA, r9 contains the saved CR,
642 * r12 contains the saved r3,
643 * r11 contain the saved SRR1, SRR0 is still ready for return
644 * r3 has the faulting address
645 * r9 - r13 are saved in paca->exslb.
646 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
647 * We assume we aren't going to take any exceptions during this
651 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
652 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
654 andi. r9,r11,MSR_PR // Check for exception from userspace
655 cmpdi cr4,r9,MSR_PR // And save the result in CR4 for later
658 * Test MSR_RI before calling slb_allocate_realmode, because the
659 * MSR in r11 gets clobbered. However we still want to allocate
660 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
661 * recursive SLB faults. So use cr5 for this, which is preserved.
663 andi. r11,r11,MSR_RI /* check for unrecoverable exception */
667 #ifdef CONFIG_PPC_BOOK3S_64
668 BEGIN_MMU_FTR_SECTION
670 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
673 ld r10,PACA_EXSLB+EX_LR(r13)
674 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
678 * Large address, check whether we have to allocate new contexts.
682 bne- cr5,2f /* if unrecoverable exception, oops */
684 /* All done -- return from exception. */
686 bne cr4,1f /* returning to kernel */
689 mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */
690 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
691 mtcrf 0x02,r9 /* I/D indication is in cr6 */
692 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
694 RESTORE_CTR(r9, PACA_EXSLB)
695 RESTORE_PPR_PACA(PACA_EXSLB, r9)
697 ld r9,PACA_EXSLB+EX_R9(r13)
698 ld r10,PACA_EXSLB+EX_R10(r13)
699 ld r11,PACA_EXSLB+EX_R11(r13)
700 ld r12,PACA_EXSLB+EX_R12(r13)
701 ld r13,PACA_EXSLB+EX_R13(r13)
703 b . /* prevent speculative execution */
706 mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */
707 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
708 mtcrf 0x02,r9 /* I/D indication is in cr6 */
709 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
711 RESTORE_CTR(r9, PACA_EXSLB)
712 RESTORE_PPR_PACA(PACA_EXSLB, r9)
714 ld r9,PACA_EXSLB+EX_R9(r13)
715 ld r10,PACA_EXSLB+EX_R10(r13)
716 ld r11,PACA_EXSLB+EX_R11(r13)
717 ld r12,PACA_EXSLB+EX_R12(r13)
718 ld r13,PACA_EXSLB+EX_R13(r13)
720 b . /* prevent speculative execution */
723 2: std r3,PACA_EXSLB+EX_DAR(r13)
727 LOAD_HANDLER(r10,unrecov_slb)
734 8: std r3,PACA_EXSLB+EX_DAR(r13)
738 LOAD_HANDLER(r10, large_addr_slb)
745 EXC_COMMON_BEGIN(unrecov_slb)
746 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
747 RECONCILE_IRQ_STATE(r10, r11)
749 1: addi r3,r1,STACK_FRAME_OVERHEAD
750 bl unrecoverable_exception
753 EXC_COMMON_BEGIN(large_addr_slb)
754 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
755 RECONCILE_IRQ_STATE(r10, r11)
756 ld r3, PACA_EXSLB+EX_DAR(r13)
759 li r10, 0x481 /* fix trap number for I-SLB miss */
762 addi r3, r1, STACK_FRAME_OVERHEAD
763 bl slb_miss_large_addr
766 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
767 .globl hardware_interrupt_hv;
768 hardware_interrupt_hv:
770 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
771 EXC_HV, SOFTEN_TEST_HV,
774 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
775 EXC_STD, SOFTEN_TEST_PR,
777 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
778 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
780 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
781 .globl hardware_interrupt_relon_hv;
782 hardware_interrupt_relon_hv:
784 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
785 EXC_HV, SOFTEN_TEST_HV,
788 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
789 EXC_STD, SOFTEN_TEST_PR,
791 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
792 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
794 TRAMP_KVM(PACA_EXGEN, 0x500)
795 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
796 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
799 EXC_REAL(alignment, 0x600, 0x100)
800 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
801 TRAMP_KVM(PACA_EXGEN, 0x600)
802 EXC_COMMON_BEGIN(alignment_common)
804 std r10,PACA_EXGEN+EX_DAR(r13)
806 stw r10,PACA_EXGEN+EX_DSISR(r13)
807 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
808 ld r3,PACA_EXGEN+EX_DAR(r13)
809 lwz r4,PACA_EXGEN+EX_DSISR(r13)
813 RECONCILE_IRQ_STATE(r10, r11)
814 addi r3,r1,STACK_FRAME_OVERHEAD
815 bl alignment_exception
819 EXC_REAL(program_check, 0x700, 0x100)
820 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
821 TRAMP_KVM(PACA_EXGEN, 0x700)
822 EXC_COMMON_BEGIN(program_check_common)
824 * It's possible to receive a TM Bad Thing type program check with
825 * userspace register values (in particular r1), but with SRR1 reporting
826 * that we came from the kernel. Normally that would confuse the bad
827 * stack logic, and we would report a bad kernel stack pointer. Instead
828 * we switch to the emergency stack if we're taking a TM Bad Thing from
831 li r10,MSR_PR /* Build a mask of MSR_PR .. */
832 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
833 and r10,r10,r12 /* Mask SRR1 with that. */
834 srdi r10,r10,8 /* Shift it so we can compare */
835 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
836 bne 1f /* If != go to normal path. */
838 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
839 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
840 /* 3 in EXCEPTION_PROLOG_COMMON */
841 mr r10,r1 /* Save r1 */
842 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
843 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
844 b 3f /* Jump into the macro !! */
845 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
847 RECONCILE_IRQ_STATE(r10, r11)
848 addi r3,r1,STACK_FRAME_OVERHEAD
849 bl program_check_exception
853 EXC_REAL(fp_unavailable, 0x800, 0x100)
854 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
855 TRAMP_KVM(PACA_EXGEN, 0x800)
856 EXC_COMMON_BEGIN(fp_unavailable_common)
857 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
858 bne 1f /* if from user, just load it up */
860 RECONCILE_IRQ_STATE(r10, r11)
861 addi r3,r1,STACK_FRAME_OVERHEAD
862 bl kernel_fp_unavailable_exception
865 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
867 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
868 * transaction), go do TM stuff
870 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
872 END_FTR_SECTION_IFSET(CPU_FTR_TM)
875 b fast_exception_return
876 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
877 2: /* User process was in a transaction */
879 RECONCILE_IRQ_STATE(r10, r11)
880 addi r3,r1,STACK_FRAME_OVERHEAD
886 EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
887 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
888 TRAMP_KVM(PACA_EXGEN, 0x900)
889 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
892 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
893 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
894 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
895 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
898 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
899 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
900 TRAMP_KVM(PACA_EXGEN, 0xa00)
901 #ifdef CONFIG_PPC_DOORBELL
902 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
904 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
908 EXC_REAL(trap_0b, 0xb00, 0x100)
909 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
910 TRAMP_KVM(PACA_EXGEN, 0xb00)
911 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
914 * system call / hypercall (0xc00, 0x4c00)
916 * The system call exception is invoked with "sc 0" and does not alter HV bit.
917 * There is support for kernel code to invoke system calls but there are no
920 * The hypercall is invoked with "sc 1" and sets HV=1.
922 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
923 * 0x4c00 virtual mode.
927 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
929 * For hypercalls, the register convention is as follows:
932 * r3 volatile parameter and return value for status
933 * r4-r10 volatile input and output value
934 * r11 volatile hypercall number and output value
935 * r12 volatile input and output value
936 * r13-r31 nonvolatile
940 * CR0-1 CR5-7 volatile
942 * Other registers nonvolatile
944 * The intersection of volatile registers that don't contain possible
945 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
946 * without saving, though xer is not a good idea to use, as hardware may
947 * interpret some bits so it may be costly to change them.
949 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
951 * There is a little bit of juggling to get syscall and hcall
952 * working well. Save r13 in ctr to avoid using SPRG scratch
955 * Userspace syscalls have already saved the PPR, hcalls must save
956 * it before setting HMT_MEDIUM.
958 #define SYSCALL_KVMTEST \
961 std r10,PACA_EXGEN+EX_R10(r13); \
962 INTERRUPT_TO_KERNEL; \
963 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
968 #define SYSCALL_KVMTEST \
975 #define LOAD_SYSCALL_HANDLER(reg) \
976 __LOAD_HANDLER(reg, system_call_common)
979 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
982 #define SYSCALL_REAL \
983 mfspr r11,SPRN_SRR0 ; \
984 mfspr r12,SPRN_SRR1 ; \
985 LOAD_SYSCALL_HANDLER(r10) ; \
986 mtspr SPRN_SRR0,r10 ; \
987 ld r10,PACAKMSR(r13) ; \
988 mtspr SPRN_SRR1,r10 ; \
990 b . ; /* prevent speculative execution */
992 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
993 #define SYSCALL_FASTENDIAN_TEST \
997 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
999 #define SYSCALL_FASTENDIAN \
1000 /* Fast LE/BE switch system call */ \
1001 1: mfspr r12,SPRN_SRR1 ; \
1002 xori r12,r12,MSR_LE ; \
1003 mtspr SPRN_SRR1,r12 ; \
1005 RFI_TO_USER ; /* return to userspace */ \
1006 b . ; /* prevent speculative execution */
1008 #define SYSCALL_FASTENDIAN_TEST
1009 #define SYSCALL_FASTENDIAN
1010 #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */
1012 #if defined(CONFIG_RELOCATABLE)
1014 * We can't branch directly so we do it via the CTR which
1015 * is volatile across system calls.
1017 #define SYSCALL_VIRT \
1018 LOAD_SYSCALL_HANDLER(r10) ; \
1020 mfspr r11,SPRN_SRR0 ; \
1021 mfspr r12,SPRN_SRR1 ; \
1026 /* We can branch directly */
1027 #define SYSCALL_VIRT \
1028 mfspr r11,SPRN_SRR0 ; \
1029 mfspr r12,SPRN_SRR1 ; \
1031 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
1032 b system_call_common ;
1035 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1036 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1037 SYSCALL_FASTENDIAN_TEST
1040 EXC_REAL_END(system_call, 0xc00, 0x100)
1042 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1043 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1044 SYSCALL_FASTENDIAN_TEST
1047 EXC_VIRT_END(system_call, 0x4c00, 0x100)
1049 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1051 * This is a hcall, so register convention is as above, with these
1055 * orig r10 saved in PACA
1057 TRAMP_KVM_BEGIN(do_kvm_0xc00)
1059 * Save the PPR (on systems that support it) before changing to
1060 * HMT_MEDIUM. That allows the KVM code to save that value into the
1061 * guest state (it is the guest's PPR value).
1063 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1065 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1068 std r9,PACA_EXGEN+EX_R9(r13)
1070 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
1074 EXC_REAL(single_step, 0xd00, 0x100)
1075 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
1076 TRAMP_KVM(PACA_EXGEN, 0xd00)
1077 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1079 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1080 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1081 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1082 EXC_COMMON_BEGIN(h_data_storage_common)
1084 std r10,PACA_EXGEN+EX_DAR(r13)
1085 mfspr r10,SPRN_HDSISR
1086 stw r10,PACA_EXGEN+EX_DSISR(r13)
1087 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1089 RECONCILE_IRQ_STATE(r10, r11)
1090 addi r3,r1,STACK_FRAME_OVERHEAD
1091 bl unknown_exception
1095 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1096 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1097 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1098 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1101 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1102 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1103 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1104 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1108 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1109 * first, and then eventaully from there to the trampoline to get into virtual
1112 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1113 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1114 EXC_VIRT_NONE(0x4e60, 0x20)
1115 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1116 TRAMP_REAL_BEGIN(hmi_exception_early)
1117 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1118 mr r10,r1 /* Save r1 */
1119 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1120 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1121 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1122 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1123 EXCEPTION_PROLOG_COMMON_1()
1124 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1125 EXCEPTION_PROLOG_COMMON_3(0xe60)
1126 addi r3,r1,STACK_FRAME_OVERHEAD
1127 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1130 /* Windup the stack. */
1131 /* Move original HSRR0 and HSRR1 into the respective regs */
1151 HRFI_TO_USER_OR_KERNEL
1158 * Go to virtual mode and pull the HMI event information from
1161 .globl hmi_exception_after_realmode
1162 hmi_exception_after_realmode:
1164 EXCEPTION_PROLOG_0(PACA_EXGEN)
1165 b tramp_real_hmi_exception
1167 EXC_COMMON_BEGIN(hmi_exception_common)
1168 EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception,
1169 ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON)
1171 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1172 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1173 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1174 #ifdef CONFIG_PPC_DOORBELL
1175 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1177 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1181 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1182 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1183 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1184 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1187 EXC_REAL_NONE(0xec0, 0x20)
1188 EXC_VIRT_NONE(0x4ec0, 0x20)
1189 EXC_REAL_NONE(0xee0, 0x20)
1190 EXC_VIRT_NONE(0x4ee0, 0x20)
1193 EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1194 EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1195 TRAMP_KVM(PACA_EXGEN, 0xf00)
1196 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1199 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1200 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1201 TRAMP_KVM(PACA_EXGEN, 0xf20)
1202 EXC_COMMON_BEGIN(altivec_unavailable_common)
1203 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1204 #ifdef CONFIG_ALTIVEC
1207 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1208 BEGIN_FTR_SECTION_NESTED(69)
1209 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1210 * transaction), go do TM stuff
1212 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1214 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1217 b fast_exception_return
1218 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1219 2: /* User process was in a transaction */
1221 RECONCILE_IRQ_STATE(r10, r11)
1222 addi r3,r1,STACK_FRAME_OVERHEAD
1223 bl altivec_unavailable_tm
1227 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1230 RECONCILE_IRQ_STATE(r10, r11)
1231 addi r3,r1,STACK_FRAME_OVERHEAD
1232 bl altivec_unavailable_exception
1236 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1237 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1238 TRAMP_KVM(PACA_EXGEN, 0xf40)
1239 EXC_COMMON_BEGIN(vsx_unavailable_common)
1240 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1244 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1245 BEGIN_FTR_SECTION_NESTED(69)
1246 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1247 * transaction), go do TM stuff
1249 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1251 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1254 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1255 2: /* User process was in a transaction */
1257 RECONCILE_IRQ_STATE(r10, r11)
1258 addi r3,r1,STACK_FRAME_OVERHEAD
1259 bl vsx_unavailable_tm
1263 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1266 RECONCILE_IRQ_STATE(r10, r11)
1267 addi r3,r1,STACK_FRAME_OVERHEAD
1268 bl vsx_unavailable_exception
1272 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1273 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1274 TRAMP_KVM(PACA_EXGEN, 0xf60)
1275 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1278 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1279 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1280 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1281 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1284 EXC_REAL_NONE(0xfa0, 0x20)
1285 EXC_VIRT_NONE(0x4fa0, 0x20)
1286 EXC_REAL_NONE(0xfc0, 0x20)
1287 EXC_VIRT_NONE(0x4fc0, 0x20)
1288 EXC_REAL_NONE(0xfe0, 0x20)
1289 EXC_VIRT_NONE(0x4fe0, 0x20)
1291 EXC_REAL_NONE(0x1000, 0x100)
1292 EXC_VIRT_NONE(0x5000, 0x100)
1293 EXC_REAL_NONE(0x1100, 0x100)
1294 EXC_VIRT_NONE(0x5100, 0x100)
1296 #ifdef CONFIG_CBE_RAS
1297 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1298 EXC_VIRT_NONE(0x5200, 0x100)
1299 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1300 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1301 #else /* CONFIG_CBE_RAS */
1302 EXC_REAL_NONE(0x1200, 0x100)
1303 EXC_VIRT_NONE(0x5200, 0x100)
1307 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1308 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1309 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1310 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1312 EXC_REAL_NONE(0x1400, 0x100)
1313 EXC_VIRT_NONE(0x5400, 0x100)
1315 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1316 mtspr SPRN_SPRG_HSCRATCH0,r13
1317 EXCEPTION_PROLOG_0(PACA_EXGEN)
1318 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1320 #ifdef CONFIG_PPC_DENORMALISATION
1321 mfspr r10,SPRN_HSRR1
1322 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1323 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1324 addi r11,r11,-4 /* HSRR0 is next instruction */
1329 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1330 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1332 #ifdef CONFIG_PPC_DENORMALISATION
1333 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1334 b exc_real_0x1500_denorm_exception_hv
1335 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1337 EXC_VIRT_NONE(0x5500, 0x100)
1340 TRAMP_KVM_HV(PACA_EXGEN, 0x1500)
1342 #ifdef CONFIG_PPC_DENORMALISATION
1343 TRAMP_REAL_BEGIN(denorm_assist)
1346 * To denormalise we need to move a copy of the register to itself.
1347 * For POWER6 do that here for all FP regs.
1350 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1351 xori r10,r10,(MSR_FE0|MSR_FE1)
1355 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1356 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1357 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1358 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1359 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1364 * To denormalise we need to move a copy of the register to itself.
1365 * For POWER7 do that here for the first 32 VSX registers only.
1368 oris r10,r10,MSR_VSX@h
1372 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1373 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1374 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1375 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1376 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1379 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1383 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1385 * To denormalise we need to move a copy of the register to itself.
1386 * For POWER8 we need to do that for all 64 VSX registers
1390 mtspr SPRN_HSRR0,r11
1392 ld r9,PACA_EXGEN+EX_R9(r13)
1393 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1395 ld r10,PACA_EXGEN+EX_CFAR(r13)
1397 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1398 ld r10,PACA_EXGEN+EX_R10(r13)
1399 ld r11,PACA_EXGEN+EX_R11(r13)
1400 ld r12,PACA_EXGEN+EX_R12(r13)
1401 ld r13,PACA_EXGEN+EX_R13(r13)
1406 EXC_COMMON(denorm_common, 0x1500, unknown_exception)
1409 #ifdef CONFIG_CBE_RAS
1410 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1411 EXC_VIRT_NONE(0x5600, 0x100)
1412 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1413 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1414 #else /* CONFIG_CBE_RAS */
1415 EXC_REAL_NONE(0x1600, 0x100)
1416 EXC_VIRT_NONE(0x5600, 0x100)
1420 EXC_REAL(altivec_assist, 0x1700, 0x100)
1421 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1422 TRAMP_KVM(PACA_EXGEN, 0x1700)
1423 #ifdef CONFIG_ALTIVEC
1424 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1426 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1430 #ifdef CONFIG_CBE_RAS
1431 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1432 EXC_VIRT_NONE(0x5800, 0x100)
1433 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1434 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1435 #else /* CONFIG_CBE_RAS */
1436 EXC_REAL_NONE(0x1800, 0x100)
1437 EXC_VIRT_NONE(0x5800, 0x100)
1440 #ifdef CONFIG_PPC_WATCHDOG
1442 #define MASKED_DEC_HANDLER_LABEL 3f
1444 #define MASKED_DEC_HANDLER(_H) \
1446 std r12,PACA_EXGEN+EX_R12(r13); \
1447 GET_SCRATCH0(r10); \
1448 std r10,PACA_EXGEN+EX_R13(r13); \
1449 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
1452 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1453 * stack is one that is usable by maskable interrupts so long as MSR_EE
1454 * remains off. It is used for recovery when something has corrupted the
1455 * normal kernel stack, for example. The "soft NMI" must not use the process
1456 * stack because we want irq disabled sections to avoid touching the stack
1457 * at all (other than PMU interrupts), so use the emergency stack for this,
1458 * and run it entirely with interrupts hard disabled.
1460 EXC_COMMON_BEGIN(soft_nmi_common)
1462 ld r1,PACAEMERGSP(r13)
1463 subi r1,r1,INT_FRAME_SIZE
1464 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1465 system_reset, soft_nmi_interrupt,
1466 ADD_NVGPRS;ADD_RECONCILE)
1469 #else /* CONFIG_PPC_WATCHDOG */
1470 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1471 #define MASKED_DEC_HANDLER(_H)
1472 #endif /* CONFIG_PPC_WATCHDOG */
1475 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1476 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1477 * - If it was a doorbell we return immediately since doorbells are edge
1478 * triggered and won't automatically refire.
1479 * - If it was a HMI we return immediately since we handled it in realmode
1480 * and it won't refire.
1481 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
1482 * This is called with r10 containing the value to OR to the paca field.
1484 #define MASKED_INTERRUPT(_H) \
1485 masked_##_H##interrupt: \
1486 std r11,PACA_EXGEN+EX_R11(r13); \
1487 lbz r11,PACAIRQHAPPENED(r13); \
1489 stb r11,PACAIRQHAPPENED(r13); \
1490 cmpwi r10,PACA_IRQ_DEC; \
1493 ori r10,r10,0xffff; \
1494 mtspr SPRN_DEC,r10; \
1495 b MASKED_DEC_HANDLER_LABEL; \
1496 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK; \
1498 mfspr r10,SPRN_##_H##SRR1; \
1499 xori r10,r10,MSR_EE; /* clear MSR_EE */ \
1500 mtspr SPRN_##_H##SRR1,r10; \
1501 ori r11,r11,PACA_IRQ_HARD_DIS; \
1502 stb r11,PACAIRQHAPPENED(r13); \
1505 std r1,PACAR1(r13); \
1506 ld r9,PACA_EXGEN+EX_R9(r13); \
1507 ld r10,PACA_EXGEN+EX_R10(r13); \
1508 ld r11,PACA_EXGEN+EX_R11(r13); \
1509 /* returns to kernel where r13 must be set up, so don't restore it */ \
1510 ##_H##RFI_TO_KERNEL; \
1512 MASKED_DEC_HANDLER(_H)
1514 TRAMP_REAL_BEGIN(stf_barrier_fallback)
1515 std r9,PACA_EXRFI+EX_R9(r13)
1516 std r10,PACA_EXRFI+EX_R10(r13)
1518 ld r9,PACA_EXRFI+EX_R9(r13)
1519 ld r10,PACA_EXRFI+EX_R10(r13)
1527 TRAMP_REAL_BEGIN(rfi_flush_fallback)
1530 std r9,PACA_EXRFI+EX_R9(r13)
1531 std r10,PACA_EXRFI+EX_R10(r13)
1532 std r11,PACA_EXRFI+EX_R11(r13)
1534 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1535 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1536 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1538 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1540 /* order ld/st prior to dcbt stop all streams with flushing */
1544 * The load adresses are at staggered offsets within cachelines,
1545 * which suits some pipelines better (on others it should not
1549 ld r11,(0x80 + 8)*0(r10)
1550 ld r11,(0x80 + 8)*1(r10)
1551 ld r11,(0x80 + 8)*2(r10)
1552 ld r11,(0x80 + 8)*3(r10)
1553 ld r11,(0x80 + 8)*4(r10)
1554 ld r11,(0x80 + 8)*5(r10)
1555 ld r11,(0x80 + 8)*6(r10)
1556 ld r11,(0x80 + 8)*7(r10)
1561 ld r9,PACA_EXRFI+EX_R9(r13)
1562 ld r10,PACA_EXRFI+EX_R10(r13)
1563 ld r11,PACA_EXRFI+EX_R11(r13)
1567 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
1570 std r9,PACA_EXRFI+EX_R9(r13)
1571 std r10,PACA_EXRFI+EX_R10(r13)
1572 std r11,PACA_EXRFI+EX_R11(r13)
1574 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1575 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1576 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1578 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1580 /* order ld/st prior to dcbt stop all streams with flushing */
1584 * The load adresses are at staggered offsets within cachelines,
1585 * which suits some pipelines better (on others it should not
1589 ld r11,(0x80 + 8)*0(r10)
1590 ld r11,(0x80 + 8)*1(r10)
1591 ld r11,(0x80 + 8)*2(r10)
1592 ld r11,(0x80 + 8)*3(r10)
1593 ld r11,(0x80 + 8)*4(r10)
1594 ld r11,(0x80 + 8)*5(r10)
1595 ld r11,(0x80 + 8)*6(r10)
1596 ld r11,(0x80 + 8)*7(r10)
1601 ld r9,PACA_EXRFI+EX_R9(r13)
1602 ld r10,PACA_EXRFI+EX_R10(r13)
1603 ld r11,PACA_EXRFI+EX_R11(r13)
1608 * Real mode exceptions actually use this too, but alternate
1609 * instruction code patches (which end up in the common .text area)
1610 * cannot reach these if they are put there.
1612 USE_FIXED_SECTION(virt_trampolines)
1616 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1617 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1619 * Here all GPRs are unchanged from when the interrupt happened
1620 * except for r13, which is saved in SPRG_SCRATCH0.
1622 mfspr r13, SPRN_SRR0
1624 mtspr SPRN_SRR0, r13
1629 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1631 * Here all GPRs are unchanged from when the interrupt happened
1632 * except for r13, which is saved in SPRG_SCRATCH0.
1634 mfspr r13, SPRN_HSRR0
1636 mtspr SPRN_HSRR0, r13
1643 * Ensure that any handlers that get invoked from the exception prologs
1644 * above are below the first 64KB (0x10000) of the kernel image because
1645 * the prologs assemble the addresses of these handlers using the
1646 * LOAD_HANDLER macro, which uses an ori instruction.
1649 /*** Common interrupt handlers ***/
1653 * Relocation-on interrupts: A subset of the interrupts can be delivered
1654 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1655 * it. Addresses are the same as the original interrupt addresses, but
1656 * offset by 0xc000000000004000.
1657 * It's impossible to receive interrupts below 0x300 via this mechanism.
1658 * KVM: None of these traps are from the guest ; anything that escalated
1659 * to HV=1 from HV=0 is delivered via real mode handlers.
1663 * This uses the standard macro, since the original 0x300 vector
1664 * only has extra guff for STAB-based processors -- which never
1668 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1669 b __ppc64_runlatch_on
1671 USE_FIXED_SECTION(virt_trampolines)
1673 * The __end_interrupts marker must be past the out-of-line (OOL)
1674 * handlers, so that they are copied to real address 0x100 when running
1675 * a relocatable kernel. This ensures they can be reached from the short
1676 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1677 * directly, without using LOAD_HANDLER().
1680 .globl __end_interrupts
1682 DEFINE_FIXED_SYMBOL(__end_interrupts)
1684 #ifdef CONFIG_PPC_970_NAP
1685 EXC_COMMON_BEGIN(power4_fixup_nap)
1687 std r9,TI_LOCAL_FLAGS(r11)
1688 ld r10,_LINK(r1) /* make idle task do the */
1689 std r10,_NIP(r1) /* equivalent of a blr */
1693 CLOSE_FIXED_SECTION(real_vectors);
1694 CLOSE_FIXED_SECTION(real_trampolines);
1695 CLOSE_FIXED_SECTION(virt_vectors);
1696 CLOSE_FIXED_SECTION(virt_trampolines);
1703 .balign IFETCH_ALIGN_BYTES
1705 #ifdef CONFIG_PPC_BOOK3S_64
1706 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
1707 ori r0,r0,DSISR_BAD_FAULT_64S@l
1708 and. r0,r4,r0 /* weird error? */
1709 bne- handle_page_fault /* if not, try to insert a HPTE */
1710 CURRENT_THREAD_INFO(r11, r1)
1711 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1712 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1713 bne 77f /* then don't call hash_page now */
1716 * r3 contains the faulting address
1718 * r5 contains the trap number
1721 * at return r3 = 0 for success, 1 for page fault, negative for error
1725 bl __hash_page /* build HPTE if possible */
1726 cmpdi r3,0 /* see if __hash_page succeeded */
1729 beq fast_exc_return_irq /* Return from exception on success */
1734 /* Reload DSISR into r4 for the DABR check below */
1736 #endif /* CONFIG_PPC_BOOK3S_64 */
1738 /* Here we have a page fault that hash_page can't handle. */
1740 11: andis. r0,r4,DSISR_DABRMATCH@h
1741 bne- handle_dabr_fault
1744 addi r3,r1,STACK_FRAME_OVERHEAD
1750 addi r3,r1,STACK_FRAME_OVERHEAD
1755 /* We have a data breakpoint exception - handle it */
1760 addi r3,r1,STACK_FRAME_OVERHEAD
1762 12: b ret_from_except_lite
1765 #ifdef CONFIG_PPC_BOOK3S_64
1766 /* We have a page fault that hash_page could handle but HV refused
1771 addi r3,r1,STACK_FRAME_OVERHEAD
1778 * We come here as a result of a DSI at a point where we don't want
1779 * to call hash_page, such as when we are accessing memory (possibly
1780 * user memory) inside a PMU interrupt that occurred while interrupts
1781 * were soft-disabled. We want to invoke the exception handler for
1782 * the access, or panic if there isn't a handler.
1786 addi r3,r1,STACK_FRAME_OVERHEAD
1792 * Here we have detected that the kernel stack pointer is bad.
1793 * R9 contains the saved CR, r13 points to the paca,
1794 * r10 contains the (bad) kernel stack pointer,
1795 * r11 and r12 contain the saved SRR0 and SRR1.
1796 * We switch to using an emergency stack, save the registers there,
1797 * and call kernel_bad_stack(), which panics.
1800 ld r1,PACAEMERGSP(r13)
1801 subi r1,r1,64+INT_FRAME_SIZE
1807 mfspr r12,SPRN_DSISR
1833 std r10,ORIG_GPR3(r1)
1834 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1837 lhz r12,PACA_TRAP_SAVE(r13)
1839 addi r11,r1,INT_FRAME_SIZE
1844 ld r11,exception_marker@toc(r2)
1846 std r11,STACK_FRAME_OVERHEAD-16(r1)
1847 1: addi r3,r1,STACK_FRAME_OVERHEAD
1850 _ASM_NOKPROBE_SYMBOL(bad_stack);
1853 * When doorbell is triggered from system reset wakeup, the message is
1854 * not cleared, so it would fire again when EE is enabled.
1856 * When coming from local_irq_enable, there may be the same problem if
1857 * we were hard disabled.
1859 * Execute msgclr to clear pending exceptions before handling it.
1861 h_doorbell_common_msgclr:
1862 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1866 doorbell_super_common_msgclr:
1867 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1869 b doorbell_super_common
1872 * Called from arch_local_irq_enable when an interrupt needs
1873 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1874 * which kind of interrupt. MSR:EE is already off. We generate a
1875 * stackframe like if a real interrupt had happened.
1877 * Note: While MSR:EE is off, we need to make sure that _MSR
1878 * in the generated frame has EE set to 1 or the exception
1879 * handler will not properly re-enable them.
1881 * Note that we don't specify LR as the NIP (return address) for
1882 * the interrupt because that would unbalance the return branch
1885 _GLOBAL(__replay_interrupt)
1886 /* We are going to jump to the exception common code which
1887 * will retrieve various register values from the PACA which
1888 * we don't give a damn about, so we don't bother storing them.
1891 LOAD_REG_ADDR(r11, replay_interrupt_return)
1895 beq decrementer_common
1898 beq h_virt_irq_common
1900 beq hardware_interrupt_common
1901 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
1903 beq performance_monitor_common
1906 beq h_doorbell_common_msgclr
1908 beq hmi_exception_common
1911 beq doorbell_super_common_msgclr
1912 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1913 replay_interrupt_return:
1916 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)