1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
24 /* PACA save area offsets (exgen, exmc, etc) */
37 .error "EX_SIZE is wrong"
41 * Following are fixed section helper macros.
43 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors
44 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors
45 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these)
46 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use)
47 * EXC_COMMON - After switching to virtual, relocated mode.
50 #define EXC_REAL_BEGIN(name, start, size) \
51 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
53 #define EXC_REAL_END(name, start, size) \
54 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
56 #define EXC_VIRT_BEGIN(name, start, size) \
57 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
59 #define EXC_VIRT_END(name, start, size) \
60 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
62 #define EXC_COMMON_BEGIN(name) \
64 .balign IFETCH_ALIGN_BYTES; \
66 _ASM_NOKPROBE_SYMBOL(name); \
67 DEFINE_FIXED_SYMBOL(name); \
70 #define TRAMP_REAL_BEGIN(name) \
71 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
73 #define TRAMP_VIRT_BEGIN(name) \
74 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
76 #define EXC_REAL_NONE(start, size) \
77 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
78 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
80 #define EXC_VIRT_NONE(start, size) \
81 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
82 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
85 * We're short on space and time in the exception prolog, so we can't
86 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
87 * Instead we get the base of the kernel from paca->kernelbase and or in the low
88 * part of label. This requires that the label be within 64KB of kernelbase, and
89 * that kernelbase be 64K aligned.
91 #define LOAD_HANDLER(reg, label) \
92 ld reg,PACAKBASE(r13); /* get high part of &label */ \
93 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
95 #define __LOAD_HANDLER(reg, label) \
96 ld reg,PACAKBASE(r13); \
97 ori reg,reg,(ABS_ADDR(label))@l
100 * Branches from unrelocated code (e.g., interrupts) to labels outside
101 * head-y require >64K offsets.
103 #define __LOAD_FAR_HANDLER(reg, label) \
104 ld reg,PACAKBASE(r13); \
105 ori reg,reg,(ABS_ADDR(label))@l; \
106 addis reg,reg,(ABS_ADDR(label))@h
109 * Branch to label using its 0xC000 address. This results in instruction
110 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
111 * on using mtmsr rather than rfid.
113 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
114 * load KBASE for a slight optimisation.
116 #define BRANCH_TO_C000(reg, label) \
117 __LOAD_FAR_HANDLER(reg, label); \
122 * Interrupt code generation macros
124 #define IVEC .L_IVEC_\name\() /* Interrupt vector address */
125 #define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */
126 #define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */
127 #define IAREA .L_IAREA_\name\() /* PACA save area */
128 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */
129 #define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */
130 #define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */
131 #define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */
132 #define ISET_RI .L_ISET_RI_\name\() /* Run common code w/ MSR[RI]=1 */
133 #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */
134 #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */
135 #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */
136 #define IKVM_SKIP .L_IKVM_SKIP_\name\() /* Generate KVM skip handler */
137 #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */
138 #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name
139 #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */
140 #define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */
141 #define __ISTACK(name) .L_ISTACK_ ## name
142 #define IRECONCILE .L_IRECONCILE_\name\() /* Do RECONCILE_IRQ_STATE */
143 #define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */
145 #define INT_DEFINE_BEGIN(n) \
146 .macro int_define_ ## n name
148 #define INT_DEFINE_END(n) \
150 int_define_ ## n n ; \
153 .macro do_define_int name
155 .error "IVEC not defined"
160 .ifndef IHSRR_IF_HVMODE
181 .ifndef IBRANCH_TO_COMMON
184 .ifndef IREALMODE_COMMON
187 .if ! IBRANCH_TO_COMMON
188 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
214 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
215 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
217 * All interrupts which set HSRR registers, as well as SRESET and MCE and
218 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken,
219 * so they all generally need to test whether they were taken in guest context.
221 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be
222 * taken with MSR[HV]=0.
224 * Interrupts which set SRR registers (with the above exceptions) do not
225 * elevate to MSR[HV]=1 mode, though most can be taken when running with
226 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do
227 * not need to test whether a guest is running because they get delivered to
228 * the guest directly, including nested HV KVM guests.
230 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host
231 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
232 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
233 * delivered to the real-mode entry point, therefore such interrupts only test
234 * KVM in their real mode handlers, and only when PR KVM is possible.
236 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
237 * delivered in real-mode when the MMU is in hash mode because the MMU
238 * registers are not set appropriately to translate host addresses. In nested
239 * radix mode these can be delivered in virt-mode as the host translations are
240 * used implicitly (see: effective LPID, effective PID).
244 * If an interrupt is taken while a guest is running, it is immediately routed
245 * to KVM to handle. If both HV and PR KVM arepossible, KVM interrupts go first
246 * to kvmppc_interrupt_hv, which handles the PR guest case.
248 #define kvmppc_interrupt kvmppc_interrupt_hv
250 #define kvmppc_interrupt kvmppc_interrupt_pr
254 lbz r10,HSTATE_IN_GUEST(r13)
260 .balign IFETCH_ALIGN_BYTES
264 cmpwi r10,KVM_GUEST_MODE_SKIP
268 ld r10,IAREA+EX_CFAR(r13)
269 std r10,HSTATE_CFAR(r13)
270 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
273 ld r10,IAREA+EX_CTR(r13)
276 ld r10,IAREA+EX_PPR(r13)
277 std r10,HSTATE_PPR(r13)
278 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
279 ld r11,IAREA+EX_R11(r13)
280 ld r12,IAREA+EX_R12(r13)
281 std r12,HSTATE_SCRATCH0(r13)
283 ld r9,IAREA+EX_R9(r13)
284 ld r10,IAREA+EX_R10(r13)
285 /* HSRR variants have the 0x2 bit added to their trap number */
288 ori r12,r12,(IVEC + 0x2)
291 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
293 ori r12,r12,(IVEC+ 0x2)
301 ld r10,IAREA+EX_CTR(r13)
303 ld r9,IAREA+EX_R9(r13)
304 ld r10,IAREA+EX_R10(r13)
305 ld r11,IAREA+EX_R11(r13)
306 ld r12,IAREA+EX_R12(r13)
309 b kvmppc_skip_Hinterrupt
311 b kvmppc_skip_interrupt
312 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
314 b kvmppc_skip_Hinterrupt
316 b kvmppc_skip_interrupt
329 * This is the BOOK3S interrupt entry code macro.
331 * This can result in one of several things happening:
332 * - Branch to the _common handler, relocated, in virtual mode.
333 * These are normal interrupts (synchronous and asynchronous) handled by
335 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
336 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
337 * / intended for host or guest kernel, but KVM must always be involved
338 * because the machine state is set for guest execution.
339 * - Branch to the masked handler, unrelocated.
340 * These occur when maskable asynchronous interrupts are taken with the
342 * - Branch to an "early" handler in real mode but relocated.
343 * This is done if early=1. MCE and HMI use these to handle errors in real
345 * - Fall through and continue executing in real, unrelocated mode.
346 * This is done if early=2.
349 .macro GEN_BRANCH_TO_COMMON name, virt
351 LOAD_HANDLER(r10, \name\()_common)
356 #ifndef CONFIG_RELOCATABLE
357 b \name\()_common_virt
359 LOAD_HANDLER(r10, \name\()_common_virt)
364 LOAD_HANDLER(r10, \name\()_common_real)
371 .macro GEN_INT_ENTRY name, virt, ool=0
372 SET_SCRATCH0(r13) /* save r13 */
374 std r9,IAREA+EX_R9(r13) /* save r9 */
377 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
379 std r10,IAREA+EX_R10(r13) /* save r10 - r12 */
382 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
387 TRAMP_REAL_BEGIN(tramp_real_\name)
391 TRAMP_VIRT_BEGIN(tramp_virt_\name)
396 std r9,IAREA+EX_PPR(r13)
397 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
399 std r10,IAREA+EX_CFAR(r13)
400 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
403 std r10,IAREA+EX_CTR(r13)
405 std r11,IAREA+EX_R11(r13)
406 std r12,IAREA+EX_R12(r13)
409 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
410 * because a d-side MCE will clobber those registers so is
411 * not recoverable if they are live.
414 std r10,IAREA+EX_R13(r13)
421 std r10,IAREA+EX_DAR(r13)
423 .if IDSISR && !IISIDE
425 mfspr r10,SPRN_HDSISR
429 stw r10,IAREA+EX_DSISR(r13)
434 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
435 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
437 mfspr r11,SPRN_SRR0 /* save SRR0 */
438 mfspr r12,SPRN_SRR1 /* and SRR1 */
439 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
441 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
442 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
444 mfspr r11,SPRN_SRR0 /* save SRR0 */
445 mfspr r12,SPRN_SRR1 /* and SRR1 */
448 .if IBRANCH_TO_COMMON
449 GEN_BRANCH_TO_COMMON \name \virt
458 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt
459 * entry, except in the case of the real-mode handlers which require
460 * __GEN_REALMODE_COMMON_ENTRY.
462 * This switches to virtual mode and sets MSR[RI].
464 .macro __GEN_COMMON_ENTRY name
465 DEFINE_FIXED_SYMBOL(\name\()_common_real)
466 \name\()_common_real:
471 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
472 /* MSR[RI] is clear iff using SRR regs */
473 .if IHSRR == EXC_HV_OR_STD
476 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
484 b 1f /* skip the virt test coming from real */
487 .balign IFETCH_ALIGN_BYTES
488 DEFINE_FIXED_SYMBOL(\name\()_common_virt)
489 \name\()_common_virt:
498 * Don't switch to virt mode. Used for early MCE and HMI handlers that
499 * want to run in real mode.
501 .macro __GEN_REALMODE_COMMON_ENTRY name
502 DEFINE_FIXED_SYMBOL(\name\()_common_real)
503 \name\()_common_real:
509 .macro __GEN_COMMON_BODY name
512 .error "No support for masked interrupt to use custom stack"
515 /* If coming from user, skip soft-mask tests. */
519 /* Kernel code running below __end_interrupts is implicitly
521 LOAD_HANDLER(r10, __end_interrupts)
526 /* Test the soft mask state against our interrupt's bit */
527 lbz r10,PACAIRQSOFTMASK(r13)
528 1: andi. r10,r10,IMASK
529 /* Associate vector numbers with bits in paca->irq_happened */
530 .if IVEC == 0x500 || IVEC == 0xea0
532 .elseif IVEC == 0x900
534 .elseif IVEC == 0xa00 || IVEC == 0xe80
535 li r10,PACA_IRQ_DBELL
536 .elseif IVEC == 0xe60
538 .elseif IVEC == 0xf00
541 .abort "Bad maskable vector"
546 bne masked_Hinterrupt
549 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
551 bne masked_Hinterrupt
558 andi. r10,r12,MSR_PR /* See if coming from user */
559 2: mr r10,r1 /* Save r1 */
560 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */
562 ld r1,PACAKSAVE(r13) /* kernel stack to use */
563 100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */
564 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
567 std r9,_CCR(r1) /* save CR in stackframe */
568 std r11,_NIP(r1) /* save SRR0 in stackframe */
569 std r12,_MSR(r1) /* save SRR1 in stackframe */
570 std r10,0(r1) /* make stack chain pointer */
571 std r0,GPR0(r1) /* save r0 in stackframe */
572 std r10,GPR1(r1) /* save r1 in stackframe */
576 mtmsrd r10,1 /* Set MSR_RI */
581 kuap_save_amr_and_lock r9, r10, cr1, cr0
583 beq 101f /* if from kernel mode */
584 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10)
586 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */
588 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
592 kuap_save_amr_and_lock r9, r10, cr1
596 /* Save original regs values from save area to stack frame. */
597 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */
598 ld r10,IAREA+EX_R10(r13)
601 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */
602 ld r10,IAREA+EX_R12(r13)
603 ld r11,IAREA+EX_R13(r13)
614 ld r10,IAREA+EX_DAR(r13)
622 lis r11,DSISR_SRR1_MATCH_64S@h
625 lwz r10,IAREA+EX_DSISR(r13)
631 ld r10,IAREA+EX_CFAR(r13)
632 std r10,ORIG_GPR3(r1)
633 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
634 ld r10,IAREA+EX_CTR(r13)
636 std r2,GPR2(r1) /* save r2 in stackframe */
637 SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */
638 SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */
639 mflr r9 /* Get LR, later save to stack */
640 ld r2,PACATOC(r13) /* get kernel TOC into r2 */
642 lbz r10,PACAIRQSOFTMASK(r13)
643 mfspr r11,SPRN_XER /* save XER in stackframe */
647 std r9,_TRAP(r1) /* set trap number */
649 ld r11,exception_marker@toc(r2)
650 std r10,RESULT(r1) /* clear regs->result */
651 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */
658 RECONCILE_IRQ_STATE(r10, r11)
663 * On entry r13 points to the paca, r9-r13 are saved in the paca,
664 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
665 * SRR1, and relocation is on.
667 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
668 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
670 .macro GEN_COMMON name
671 __GEN_COMMON_ENTRY \name
672 __GEN_COMMON_BODY \name
676 * Restore all registers including H/SRR0/1 saved in a stack frame of a
677 * standard exception.
679 .macro EXCEPTION_RESTORE_REGS hsrr=0
680 /* Move original SRR0 and SRR1 into the respective regs */
704 /* restore original r1. */
708 #define RUNLATCH_ON \
710 ld r3, PACA_THREAD_INFO(r13); \
711 ld r4,TI_LOCAL_FLAGS(r3); \
712 andi. r0,r4,_TLF_RUNLATCH; \
713 beql ppc64_runlatch_on_trampoline; \
714 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
717 * When the idle code in power4_idle puts the CPU into NAP mode,
718 * it has to do so in a loop, and relies on the external interrupt
719 * and decrementer interrupt entry code to get it out of the loop.
720 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
721 * to signal that it is in the loop and needs help to get out.
723 #ifdef CONFIG_PPC_970_NAP
726 ld r11, PACA_THREAD_INFO(r13); \
727 ld r9,TI_LOCAL_FLAGS(r11); \
728 andi. r10,r9,_TLF_NAPPING; \
729 bnel power4_fixup_nap; \
730 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
736 * There are a few constraints to be concerned with.
737 * - Real mode exceptions code/data must be located at their physical location.
738 * - Virtual mode exceptions must be mapped at their 0xc000... location.
739 * - Fixed location code must not call directly beyond the __end_interrupts
740 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
742 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
744 * - Conditional branch targets must be within +/-32K of caller.
746 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
747 * therefore don't have to run in physically located code or rfid to
748 * virtual mode kernel code. However on relocatable kernels they do have
749 * to branch to KERNELBASE offset because the rest of the kernel (outside
750 * the exception vectors) may be located elsewhere.
752 * Virtual exceptions correspond with physical, except their entry points
753 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
754 * offset applied. Virtual exceptions are enabled with the Alternate
755 * Interrupt Location (AIL) bit set in the LPCR. However this does not
756 * guarantee they will be delivered virtually. Some conditions (see the ISA)
757 * cause exceptions to be delivered in real mode.
759 * The scv instructions are a special case. They get a 0x3000 offset applied.
760 * scv exceptions have unique reentrancy properties, see below.
762 * It's impossible to receive interrupts below 0x300 via AIL.
764 * KVM: None of the virtual exceptions are from the guest. Anything that
765 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
768 * We layout physical memory as follows:
769 * 0x0000 - 0x00ff : Secondary processor spin code
770 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
771 * 0x1900 - 0x2fff : Real mode trampolines
772 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
773 * 0x5900 - 0x6fff : Relon mode trampolines
774 * 0x7000 - 0x7fff : FWNMI data area
775 * 0x8000 - .... : Common interrupt handlers, remaining early
776 * setup code, rest of kernel.
778 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
779 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
782 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
783 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
784 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
785 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
787 #ifdef CONFIG_PPC_POWERNV
788 .globl start_real_trampolines
789 .globl end_real_trampolines
790 .globl start_virt_trampolines
791 .globl end_virt_trampolines
794 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
796 * Data area reserved for FWNMI option.
797 * This address (0x7000) is fixed by the RPA.
798 * pseries and powernv need to keep the whole page from
799 * 0x7000 to 0x8000 free for use by the firmware
801 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
802 OPEN_TEXT_SECTION(0x8000)
804 OPEN_TEXT_SECTION(0x7000)
807 USE_FIXED_SECTION(real_vectors)
810 * This is the start of the interrupt handlers for pSeries
811 * This code runs with relocation off.
812 * Code from here to __end_interrupts gets copied down to real
813 * address 0x100 when we are running a relocatable kernel.
814 * Therefore any relative branches in this section must only
815 * branch to labels in this section.
817 .globl __start_interrupts
821 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
822 * This is a synchronous interrupt invoked with the "scv" instruction. The
823 * system call does not alter the HV bit, so it is directed to the OS.
826 * scv instructions enter the kernel without changing EE, RI, ME, or HV.
827 * In particular, this means we can take a maskable interrupt at any point
828 * in the scv handler, which is unlike any other interrupt. This is solved
829 * by treating the instruction addresses below __end_interrupts as being
832 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
833 * ensure scv is never executed with relocation off, which means AIL-0
834 * should never happen.
836 * Before leaving the below __end_interrupts text, at least of the following
838 * - MSR[PR]=1 (i.e., return to userspace)
839 * - MSR_EE|MSR_RI is set (no reentrant exceptions)
840 * - Standard kernel environment is set up (stack, paca, etc)
844 * syscall register convention is in Documentation/powerpc/syscall64-abi.rst
846 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
852 li r10,IRQS_ALL_DISABLED
853 stb r10,PACAIRQSOFTMASK(r13)
854 #ifdef CONFIG_RELOCATABLE
855 b system_call_vectored_tramp
857 b system_call_vectored_common
867 li r10,IRQS_ALL_DISABLED
868 stb r10,PACAIRQSOFTMASK(r13)
869 li r0,-1 /* cause failure */
870 #ifdef CONFIG_RELOCATABLE
871 b system_call_vectored_sigill_tramp
873 b system_call_vectored_sigill
876 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
878 #ifdef CONFIG_RELOCATABLE
879 TRAMP_VIRT_BEGIN(system_call_vectored_tramp)
880 __LOAD_HANDLER(r10, system_call_vectored_common)
884 TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp)
885 __LOAD_HANDLER(r10, system_call_vectored_sigill)
891 /* No virt vectors corresponding with 0x0..0x100 */
892 EXC_VIRT_NONE(0x4000, 0x100)
896 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
897 * This is a non-maskable, asynchronous interrupt always taken in real-mode.
899 * - Wake from power-saving state, on powernv.
900 * - An NMI from another CPU, triggered by firmware or hypercall.
901 * - As crash/debug signal injected from BMC, firmware or hypervisor.
904 * Power-save wakeup is the only performance critical path, so this is
905 * determined quickly as possible first. In this case volatile registers
906 * can be discarded and SPRs like CFAR don't need to be read.
908 * If not a powersave wakeup, then it's run as a regular interrupt, however
909 * it uses its own stack and PACA save area to preserve the regular kernel
910 * environment for debugging.
912 * This interrupt is not maskable, so triggering it when MSR[RI] is clear,
913 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely
914 * correct to switch to virtual mode to run the regular interrupt handler
915 * because it might be interrupted when the MMU is in a bad state (e.g., SLB
919 * PAPR specifies a "fwnmi" facility which sends the sreset to a different
920 * entry point with a different register set up. Some hypervisors will
921 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
924 * Unlike most SRR interrupts, this may be taken by the host while executing
925 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest
926 * mode and then raise the sreset.
928 INT_DEFINE_BEGIN(system_reset)
931 IVIRT=0 /* no virt entry point */
933 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
934 * being used, so a nested NMI exception would corrupt it.
940 INT_DEFINE_END(system_reset)
942 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
943 #ifdef CONFIG_PPC_P7_NAP
945 * If running native on arch 2.06 or later, check if we are waking up
946 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
947 * bits 46:47. A non-0 value indicates that we are coming from a power
948 * saving state. The idle wakeup handler initially runs in real mode,
949 * but we branch to the 0xc000... address so we can turn on relocation
950 * with mtmsrd later, after SPRs are restored.
952 * Careful to minimise cost for the fast path (idle wakeup) while
953 * also avoiding clobbering CFAR for the debug path (non-idle).
955 * For the idle wake case volatile registers can be clobbered, which
956 * is why we use those initially. If it turns out to not be an idle
957 * wake, carefully put everything back the way it was, so we can use
958 * common exception macros to handle it.
963 std r3,PACA_EXNMI+0*8(r13)
964 std r4,PACA_EXNMI+1*8(r13)
965 std r5,PACA_EXNMI+2*8(r13)
968 rlwinm. r5,r3,47-31,30,31
969 bne+ system_reset_idle_wake
970 /* Not powersave wakeup. Restore regs for regular interrupt handler. */
972 ld r3,PACA_EXNMI+0*8(r13)
973 ld r4,PACA_EXNMI+1*8(r13)
974 ld r5,PACA_EXNMI+2*8(r13)
976 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
979 GEN_INT_ENTRY system_reset, virt=0
981 * In theory, we should not enable relocation here if it was disabled
982 * in SRR1, because the MMU may not be configured to support it (e.g.,
983 * SLB may have been cleared). In practice, there should only be a few
984 * small windows where that's the case, and sreset is considered to
985 * be dangerous anyway.
987 EXC_REAL_END(system_reset, 0x100, 0x100)
988 EXC_VIRT_NONE(0x4100, 0x100)
990 #ifdef CONFIG_PPC_P7_NAP
991 TRAMP_REAL_BEGIN(system_reset_idle_wake)
992 /* We are waking up from idle, so may clobber any volatile register */
994 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
995 BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss))
998 #ifdef CONFIG_PPC_PSERIES
1000 * Vectors for the FWNMI option. Share common code.
1002 TRAMP_REAL_BEGIN(system_reset_fwnmi)
1003 GEN_INT_ENTRY system_reset, virt=0
1005 #endif /* CONFIG_PPC_PSERIES */
1007 EXC_COMMON_BEGIN(system_reset_common)
1008 __GEN_COMMON_ENTRY system_reset
1010 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
1011 * to recover, but nested NMI will notice in_nmi and not recover
1012 * because of the use of the NMI stack. in_nmi reentrancy is tested in
1013 * system_reset_exception.
1015 lhz r10,PACA_IN_NMI(r13)
1017 sth r10,PACA_IN_NMI(r13)
1022 ld r1,PACA_NMI_EMERG_SP(r13)
1023 subi r1,r1,INT_FRAME_SIZE
1024 __GEN_COMMON_BODY system_reset
1026 * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does
1027 * the right thing. We do not want to reconcile because that goes
1028 * through irq tracing which we don't want in NMI.
1030 * Save PACAIRQHAPPENED to RESULT (otherwise unused), and set HARD_DIS
1031 * as we are running with MSR[EE]=0.
1033 li r10,IRQS_ALL_DISABLED
1034 stb r10,PACAIRQSOFTMASK(r13)
1035 lbz r10,PACAIRQHAPPENED(r13)
1037 ori r10,r10,PACA_IRQ_HARD_DIS
1038 stb r10,PACAIRQHAPPENED(r13)
1040 addi r3,r1,STACK_FRAME_OVERHEAD
1041 bl system_reset_exception
1043 /* Clear MSR_RI before setting SRR0 and SRR1. */
1048 * MSR_RI is clear, now we can decrement paca->in_nmi.
1050 lhz r10,PACA_IN_NMI(r13)
1052 sth r10,PACA_IN_NMI(r13)
1055 * Restore soft mask settings.
1058 stb r10,PACAIRQHAPPENED(r13)
1060 stb r10,PACAIRQSOFTMASK(r13)
1062 kuap_restore_amr r9, r10
1063 EXCEPTION_RESTORE_REGS
1064 RFI_TO_USER_OR_KERNEL
1066 GEN_KVM system_reset
1070 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1071 * This is a non-maskable interrupt always taken in real-mode. It can be
1072 * synchronous or asynchronous, caused by hardware or software, and it may be
1073 * taken in a power-saving state.
1076 * Similarly to system reset, this uses its own stack and PACA save area,
1077 * the difference is re-entrancy is allowed on the machine check stack.
1079 * machine_check_early is run in real mode, and carefully decodes the
1080 * machine check and tries to handle it (e.g., flush the SLB if there was an
1081 * error detected there), determines if it was recoverable and logs the
1084 * This early code does not "reconcile" irq soft-mask state like SRESET or
1085 * regular interrupts do, so irqs_disabled() among other things may not work
1086 * properly (irq disable/enable already doesn't work because irq tracing can
1087 * not work in real mode).
1089 * Then, depending on the execution context when the interrupt is taken, there
1090 * are 3 main actions:
1091 * - Executing in kernel mode. The event is queued with irq_work, which means
1092 * it is handled when it is next safe to do so (i.e., the kernel has enabled
1093 * interrupts), which could be immediately when the interrupt returns. This
1094 * avoids nasty issues like switching to virtual mode when the MMU is in a
1095 * bad state, or when executing OPAL code. (SRESET is exposed to such issues,
1096 * but it has different priorities). Check to see if the CPU was in power
1097 * save, and return via the wake up code if it was.
1099 * - Executing in user mode. machine_check_exception is run like a normal
1100 * interrupt handler, which processes the data generated by the early handler.
1102 * - Executing in guest mode. The interrupt is run with its KVM test, and
1103 * branches to KVM to deal with. KVM may queue the event for the host
1106 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear,
1107 * or SCRATCH0 is in use, it may cause a crash.
1112 INT_DEFINE_BEGIN(machine_check_early)
1115 IVIRT=0 /* no virt entry point */
1118 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
1119 * nested machine check corrupts it. machine_check_common enables
1127 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1128 INT_DEFINE_END(machine_check_early)
1130 INT_DEFINE_BEGIN(machine_check)
1133 IVIRT=0 /* no virt entry point */
1139 INT_DEFINE_END(machine_check)
1141 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1142 GEN_INT_ENTRY machine_check_early, virt=0
1143 EXC_REAL_END(machine_check, 0x200, 0x100)
1144 EXC_VIRT_NONE(0x4200, 0x100)
1146 #ifdef CONFIG_PPC_PSERIES
1147 TRAMP_REAL_BEGIN(machine_check_fwnmi)
1148 /* See comment at machine_check exception, don't turn on RI */
1149 GEN_INT_ENTRY machine_check_early, virt=0
1152 #define MACHINE_CHECK_HANDLER_WINDUP \
1153 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1155 mtmsrd r9,1; /* Clear MSR_RI */ \
1156 /* Decrement paca->in_mce now RI is clear. */ \
1157 lhz r12,PACA_IN_MCE(r13); \
1159 sth r12,PACA_IN_MCE(r13); \
1160 EXCEPTION_RESTORE_REGS
1162 EXC_COMMON_BEGIN(machine_check_early_common)
1163 __GEN_REALMODE_COMMON_ENTRY machine_check_early
1166 * Switch to mc_emergency stack and handle re-entrancy (we limit
1167 * the nested MCE upto level 4 to avoid stack overflow).
1168 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
1170 * We use paca->in_mce to check whether this is the first entry or
1171 * nested machine check. We increment paca->in_mce to track nested
1174 * If this is the first entry then set stack pointer to
1175 * paca->mc_emergency_sp, otherwise r1 is already pointing to
1176 * stack frame on mc_emergency stack.
1178 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1179 * checkstop if we get another machine check exception before we do
1180 * rfid with MSR_ME=1.
1182 * This interrupt can wake directly from idle. If that is the case,
1183 * the machine check is handled then the idle wakeup code is called
1186 lhz r10,PACA_IN_MCE(r13)
1187 cmpwi r10,0 /* Are we in nested machine check */
1188 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */
1189 addi r10,r10,1 /* increment paca->in_mce */
1190 sth r10,PACA_IN_MCE(r13)
1192 mr r10,r1 /* Save r1 */
1194 /* First machine check entry */
1195 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
1196 1: /* Limit nested MCE to level 4 to avoid stack overflow */
1197 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
1198 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1200 __GEN_COMMON_BODY machine_check_early
1203 bl enable_machine_check
1204 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1209 * Set IRQS_ALL_DISABLED and save PACAIRQHAPPENED (see
1210 * system_reset_common)
1212 li r10,IRQS_ALL_DISABLED
1213 stb r10,PACAIRQSOFTMASK(r13)
1214 lbz r10,PACAIRQHAPPENED(r13)
1216 ori r10,r10,PACA_IRQ_HARD_DIS
1217 stb r10,PACAIRQHAPPENED(r13)
1219 addi r3,r1,STACK_FRAME_OVERHEAD
1220 bl machine_check_early
1221 std r3,RESULT(r1) /* Save result */
1225 * Restore soft mask settings.
1228 stb r10,PACAIRQHAPPENED(r13)
1230 stb r10,PACAIRQSOFTMASK(r13)
1232 #ifdef CONFIG_PPC_P7_NAP
1234 * Check if thread was in power saving mode. We come here when any
1235 * of the following is true:
1236 * a. thread wasn't in power saving mode
1237 * b. thread was in power saving mode with no state loss,
1238 * supervisor state loss or hypervisor state loss.
1240 * Go back to nap/sleep/winkle mode again if (b) is true.
1243 rlwinm. r11,r12,47-31,30,31
1244 bne machine_check_idle_common
1245 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1248 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1250 * Check if we are coming from guest. If yes, then run the normal
1251 * exception handler which will take the
1252 * machine_check_kvm->kvmppc_interrupt branch to deliver the MC event
1255 lbz r11,HSTATE_IN_GUEST(r13)
1256 cmpwi r11,0 /* Check if coming from guest */
1257 bne mce_deliver /* continue if we are. */
1261 * Check if we are coming from userspace. If yes, then run the normal
1262 * exception handler which will deliver the MC event to this kernel.
1264 andi. r11,r12,MSR_PR /* See if coming from user. */
1265 bne mce_deliver /* continue in V mode if we are. */
1268 * At this point we are coming from kernel context.
1269 * Queue up the MCE event and return from the interrupt.
1270 * But before that, check if this is an un-recoverable exception.
1271 * If yes, then stay on emergency stack and panic.
1273 andi. r11,r12,MSR_RI
1274 beq unrecoverable_mce
1277 * Check if we have successfully handled/recovered from error, if not
1278 * then stay on emergency stack and panic.
1280 ld r3,RESULT(r1) /* Load result */
1281 cmpdi r3,0 /* see if we handled MCE successfully */
1282 beq unrecoverable_mce /* if !handled then panic */
1285 * Return from MC interrupt.
1286 * Queue up the MCE event so that we can log it later, while
1287 * returning from kernel or opal call.
1289 bl machine_check_queue_event
1290 MACHINE_CHECK_HANDLER_WINDUP
1295 * This is a host user or guest MCE. Restore all registers, then
1296 * run the "late" handler. For host user, this will run the
1297 * machine_check_exception handler in virtual mode like a normal
1298 * interrupt handler. For guest, this will trigger the KVM test
1299 * and branch to the KVM interrupt similarly to other interrupts.
1302 ld r10,ORIG_GPR3(r1)
1304 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1305 MACHINE_CHECK_HANDLER_WINDUP
1306 GEN_INT_ENTRY machine_check, virt=0
1308 EXC_COMMON_BEGIN(machine_check_common)
1310 * Machine check is different because we use a different
1311 * save area: PACA_EXMC instead of PACA_EXGEN.
1313 GEN_COMMON machine_check
1316 /* Enable MSR_RI when finished with PACA_EXMC */
1319 addi r3,r1,STACK_FRAME_OVERHEAD
1320 bl machine_check_exception
1323 GEN_KVM machine_check
1326 #ifdef CONFIG_PPC_P7_NAP
1328 * This is an idle wakeup. Low level machine check has already been
1329 * done. Queue the event then call the idle code to do the wake up.
1331 EXC_COMMON_BEGIN(machine_check_idle_common)
1332 bl machine_check_queue_event
1335 * GPR-loss wakeups are relatively straightforward, because the
1336 * idle sleep code has saved all non-volatile registers on its
1337 * own stack, and r1 in PACAR1.
1339 * For no-loss wakeups the r1 and lr registers used by the
1340 * early machine check handler have to be restored first. r2 is
1341 * the kernel TOC, so no need to restore it.
1343 * Then decrement MCE nesting after finishing with the stack.
1349 lhz r11,PACA_IN_MCE(r13)
1351 sth r11,PACA_IN_MCE(r13)
1354 rlwinm r10,r3,47-31,30,31
1356 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1357 b idle_return_gpr_loss
1360 EXC_COMMON_BEGIN(unrecoverable_mce)
1362 * We are going down. But there are chances that we might get hit by
1363 * another MCE during panic path and we may run into unstable state
1364 * with no way out. Hence, turn ME bit off while going down, so that
1365 * when another MCE is hit during panic path, system will checkstop
1366 * and hypervisor will get restarted cleanly by SP.
1369 li r10,0 /* clear MSR_RI */
1371 bl disable_machine_check
1372 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1373 ld r10,PACAKMSR(r13)
1378 lhz r12,PACA_IN_MCE(r13)
1380 sth r12,PACA_IN_MCE(r13)
1382 /* Invoke machine_check_exception to print MCE event and panic. */
1383 addi r3,r1,STACK_FRAME_OVERHEAD
1384 bl machine_check_exception
1387 * We will not reach here. Even if we did, there is no way out.
1388 * Call unrecoverable_exception and die.
1390 addi r3,r1,STACK_FRAME_OVERHEAD
1391 bl unrecoverable_exception
1396 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1397 * This is a synchronous interrupt generated due to a data access exception,
1398 * e.g., a load orstore which does not have a valid page table entry with
1399 * permissions. DAWR matches also fault here, as do RC updates, and minor misc
1400 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc.
1404 * Go to do_hash_page first to see if the HPT can be filled from an entry in
1405 * the Linux page table. Hash faults can hit in kernel mode in a fairly
1406 * arbitrary state (e.g., interrupts disabled, locks held) when accessing
1407 * "non-bolted" regions, e.g., vmalloc space. However these should always be
1408 * backed by Linux page tables.
1410 * If none is found, do a Linux page fault. Linux page faults can happen in
1411 * kernel mode due to user copy operations of course.
1414 * The hardware loads from the Linux page table directly, so a fault goes
1415 * immediately to Linux page fault.
1417 * Conditions like DAWR match are handled on the way in to Linux page fault.
1419 INT_DEFINE_BEGIN(data_access)
1423 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1427 INT_DEFINE_END(data_access)
1429 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1430 GEN_INT_ENTRY data_access, virt=0
1431 EXC_REAL_END(data_access, 0x300, 0x80)
1432 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1433 GEN_INT_ENTRY data_access, virt=1
1434 EXC_VIRT_END(data_access, 0x4300, 0x80)
1435 EXC_COMMON_BEGIN(data_access_common)
1436 GEN_COMMON data_access
1439 BEGIN_MMU_FTR_SECTION
1442 b do_hash_page /* Try to handle as hpte fault */
1443 MMU_FTR_SECTION_ELSE
1445 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1451 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1452 * This is a synchronous interrupt in response to an MMU fault missing SLB
1453 * entry for HPT, or an address outside RPT translation range.
1457 * This refills the SLB, or reports an access fault similarly to a bad page
1458 * fault. When coming from user-mode, the SLB handler may access any kernel
1459 * data, though it may itself take a DSLB. When coming from kernel mode,
1460 * recursive faults must be avoided so access is restricted to the kernel
1461 * image text/data, kernel stack, and any data allocated below
1462 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping
1463 * on user-handler data structures.
1465 * A dedicated save area EXSLB is used (XXX: but it actually need not be
1466 * these days, we could use EXGEN).
1468 INT_DEFINE_BEGIN(data_access_slb)
1473 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1477 INT_DEFINE_END(data_access_slb)
1479 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1480 GEN_INT_ENTRY data_access_slb, virt=0
1481 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1482 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1483 GEN_INT_ENTRY data_access_slb, virt=1
1484 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1485 EXC_COMMON_BEGIN(data_access_slb_common)
1486 GEN_COMMON data_access_slb
1488 addi r3,r1,STACK_FRAME_OVERHEAD
1489 BEGIN_MMU_FTR_SECTION
1490 /* HPT case, do SLB fault */
1494 b fast_interrupt_return
1496 MMU_FTR_SECTION_ELSE
1497 /* Radix case, access is outside page table range */
1499 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1501 RECONCILE_IRQ_STATE(r10, r11)
1504 addi r3,r1,STACK_FRAME_OVERHEAD
1508 GEN_KVM data_access_slb
1512 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1513 * This is a synchronous interrupt in response to an MMU fault due to an
1514 * instruction fetch.
1517 * Similar to DSI, though in response to fetch. The faulting address is found
1518 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR).
1520 INT_DEFINE_BEGIN(instruction_access)
1525 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1528 INT_DEFINE_END(instruction_access)
1530 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1531 GEN_INT_ENTRY instruction_access, virt=0
1532 EXC_REAL_END(instruction_access, 0x400, 0x80)
1533 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1534 GEN_INT_ENTRY instruction_access, virt=1
1535 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1536 EXC_COMMON_BEGIN(instruction_access_common)
1537 GEN_COMMON instruction_access
1540 BEGIN_MMU_FTR_SECTION
1543 b do_hash_page /* Try to handle as hpte fault */
1544 MMU_FTR_SECTION_ELSE
1546 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1548 GEN_KVM instruction_access
1552 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1553 * This is a synchronous interrupt in response to an MMU fault due to an
1554 * instruction fetch.
1557 * Similar to DSLB, though in response to fetch. The faulting address is found
1558 * in SRR0 (rather than DAR).
1560 INT_DEFINE_BEGIN(instruction_access_slb)
1566 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1569 INT_DEFINE_END(instruction_access_slb)
1571 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1572 GEN_INT_ENTRY instruction_access_slb, virt=0
1573 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1574 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1575 GEN_INT_ENTRY instruction_access_slb, virt=1
1576 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1577 EXC_COMMON_BEGIN(instruction_access_slb_common)
1578 GEN_COMMON instruction_access_slb
1580 addi r3,r1,STACK_FRAME_OVERHEAD
1581 BEGIN_MMU_FTR_SECTION
1582 /* HPT case, do SLB fault */
1586 b fast_interrupt_return
1588 MMU_FTR_SECTION_ELSE
1589 /* Radix case, access is outside page table range */
1591 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1593 RECONCILE_IRQ_STATE(r10, r11)
1596 addi r3,r1,STACK_FRAME_OVERHEAD
1600 GEN_KVM instruction_access_slb
1604 * Interrupt 0x500 - External Interrupt.
1605 * This is an asynchronous maskable interrupt in response to an "external
1606 * exception" from the interrupt controller or hypervisor (e.g., device
1607 * interrupt). It is maskable in hardware by clearing MSR[EE], and
1608 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()).
1610 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1611 * interrupts are delivered with HSRR registers, guests use SRRs, which
1612 * reqiures IHSRR_IF_HVMODE.
1614 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
1615 * external interrupts are delivered as Hypervisor Virtualization Interrupts
1616 * rather than External Interrupts.
1619 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead,
1620 * because registers at the time of the interrupt are not so important as it is
1623 * If soft masked, the masked handler will note the pending interrupt for
1624 * replay, and clear MSR[EE] in the interrupted context.
1626 INT_DEFINE_BEGIN(hardware_interrupt)
1632 INT_DEFINE_END(hardware_interrupt)
1634 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1635 GEN_INT_ENTRY hardware_interrupt, virt=0
1636 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1637 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1638 GEN_INT_ENTRY hardware_interrupt, virt=1
1639 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1640 EXC_COMMON_BEGIN(hardware_interrupt_common)
1641 GEN_COMMON hardware_interrupt
1644 addi r3,r1,STACK_FRAME_OVERHEAD
1648 GEN_KVM hardware_interrupt
1652 * Interrupt 0x600 - Alignment Interrupt
1653 * This is a synchronous interrupt in response to data alignment fault.
1655 INT_DEFINE_BEGIN(alignment)
1659 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1662 INT_DEFINE_END(alignment)
1664 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1665 GEN_INT_ENTRY alignment, virt=0
1666 EXC_REAL_END(alignment, 0x600, 0x100)
1667 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1668 GEN_INT_ENTRY alignment, virt=1
1669 EXC_VIRT_END(alignment, 0x4600, 0x100)
1670 EXC_COMMON_BEGIN(alignment_common)
1671 GEN_COMMON alignment
1672 addi r3,r1,STACK_FRAME_OVERHEAD
1673 bl alignment_exception
1674 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1681 * Interrupt 0x700 - Program Interrupt (program check).
1682 * This is a synchronous interrupt in response to various instruction faults:
1683 * traps, privilege errors, TM errors, floating point exceptions.
1686 * This interrupt may use the "emergency stack" in some cases when being taken
1687 * from kernel context, which complicates handling.
1689 INT_DEFINE_BEGIN(program_check)
1691 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1694 INT_DEFINE_END(program_check)
1696 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1697 GEN_INT_ENTRY program_check, virt=0
1698 EXC_REAL_END(program_check, 0x700, 0x100)
1699 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1700 GEN_INT_ENTRY program_check, virt=1
1701 EXC_VIRT_END(program_check, 0x4700, 0x100)
1702 EXC_COMMON_BEGIN(program_check_common)
1703 __GEN_COMMON_ENTRY program_check
1706 * It's possible to receive a TM Bad Thing type program check with
1707 * userspace register values (in particular r1), but with SRR1 reporting
1708 * that we came from the kernel. Normally that would confuse the bad
1709 * stack logic, and we would report a bad kernel stack pointer. Instead
1710 * we switch to the emergency stack if we're taking a TM Bad Thing from
1714 andi. r10,r12,MSR_PR
1715 bne 2f /* If userspace, go normal path */
1717 andis. r10,r12,(SRR1_PROGTM)@h
1718 bne 1f /* If TM, emergency */
1720 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */
1721 blt 2f /* normal path if not */
1723 /* Use the emergency stack */
1724 1: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */
1725 /* 3 in EXCEPTION_PROLOG_COMMON */
1726 mr r10,r1 /* Save r1 */
1727 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1728 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1729 __ISTACK(program_check)=0
1730 __GEN_COMMON_BODY program_check
1733 __ISTACK(program_check)=1
1734 __GEN_COMMON_BODY program_check
1736 addi r3,r1,STACK_FRAME_OVERHEAD
1737 bl program_check_exception
1738 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
1741 GEN_KVM program_check
1745 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1746 * This is a synchronous interrupt in response to executing an fp instruction
1750 * This will load FP registers and enable the FP bit if coming from userspace,
1751 * otherwise report a bad kernel use of FP.
1753 INT_DEFINE_BEGIN(fp_unavailable)
1756 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1759 INT_DEFINE_END(fp_unavailable)
1761 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1762 GEN_INT_ENTRY fp_unavailable, virt=0
1763 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1764 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1765 GEN_INT_ENTRY fp_unavailable, virt=1
1766 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1767 EXC_COMMON_BEGIN(fp_unavailable_common)
1768 GEN_COMMON fp_unavailable
1769 bne 1f /* if from user, just load it up */
1770 RECONCILE_IRQ_STATE(r10, r11)
1771 addi r3,r1,STACK_FRAME_OVERHEAD
1772 bl kernel_fp_unavailable_exception
1774 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1776 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1778 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1779 * transaction), go do TM stuff
1781 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1783 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1786 b fast_interrupt_return
1787 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1788 2: /* User process was in a transaction */
1789 RECONCILE_IRQ_STATE(r10, r11)
1790 addi r3,r1,STACK_FRAME_OVERHEAD
1791 bl fp_unavailable_tm
1795 GEN_KVM fp_unavailable
1799 * Interrupt 0x900 - Decrementer Interrupt.
1800 * This is an asynchronous interrupt in response to a decrementer exception
1801 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing
1802 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e.,
1803 * local_irq_disable()).
1806 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1808 * If soft masked, the masked handler will note the pending interrupt for
1809 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled
1810 * in the interrupted context.
1811 * If PPC_WATCHDOG is configured, the soft masked handler will actually set
1812 * things back up to run soft_nmi_interrupt as a regular interrupt handler
1813 * on the emergency stack.
1815 INT_DEFINE_BEGIN(decrementer)
1818 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1821 INT_DEFINE_END(decrementer)
1823 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1824 GEN_INT_ENTRY decrementer, virt=0
1825 EXC_REAL_END(decrementer, 0x900, 0x80)
1826 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1827 GEN_INT_ENTRY decrementer, virt=1
1828 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1829 EXC_COMMON_BEGIN(decrementer_common)
1830 GEN_COMMON decrementer
1833 addi r3,r1,STACK_FRAME_OVERHEAD
1841 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1842 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1846 * Linux does not use this outside KVM where it's used to keep a host timer
1847 * while the guest is given control of DEC. It should normally be caught by
1848 * the KVM test and routed there.
1850 INT_DEFINE_BEGIN(hdecrementer)
1857 INT_DEFINE_END(hdecrementer)
1859 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1860 GEN_INT_ENTRY hdecrementer, virt=0
1861 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1862 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1863 GEN_INT_ENTRY hdecrementer, virt=1
1864 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1865 EXC_COMMON_BEGIN(hdecrementer_common)
1866 __GEN_COMMON_ENTRY hdecrementer
1868 * Hypervisor decrementer interrupts not caught by the KVM test
1869 * shouldn't occur but are sometimes left pending on exit from a KVM
1870 * guest. We don't need to do anything to clear them, as they are
1873 * Be careful to avoid touching the kernel stack.
1875 ld r10,PACA_EXGEN+EX_CTR(r13)
1878 ld r9,PACA_EXGEN+EX_R9(r13)
1879 ld r10,PACA_EXGEN+EX_R10(r13)
1880 ld r11,PACA_EXGEN+EX_R11(r13)
1881 ld r12,PACA_EXGEN+EX_R12(r13)
1882 ld r13,PACA_EXGEN+EX_R13(r13)
1885 GEN_KVM hdecrementer
1889 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1890 * This is an asynchronous interrupt in response to a msgsndp doorbell.
1891 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
1892 * IRQS_DISABLED mask (i.e., local_irq_disable()).
1895 * Guests may use this for IPIs between threads in a core if the
1896 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1898 * If soft masked, the masked handler will note the pending interrupt for
1899 * replay, leaving MSR[EE] enabled in the interrupted context because the
1900 * doorbells are edge triggered.
1902 INT_DEFINE_BEGIN(doorbell_super)
1905 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1908 INT_DEFINE_END(doorbell_super)
1910 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1911 GEN_INT_ENTRY doorbell_super, virt=0
1912 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1913 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1914 GEN_INT_ENTRY doorbell_super, virt=1
1915 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1916 EXC_COMMON_BEGIN(doorbell_super_common)
1917 GEN_COMMON doorbell_super
1920 addi r3,r1,STACK_FRAME_OVERHEAD
1921 #ifdef CONFIG_PPC_DOORBELL
1922 bl doorbell_exception
1924 bl unknown_exception
1928 GEN_KVM doorbell_super
1931 EXC_REAL_NONE(0xb00, 0x100)
1932 EXC_VIRT_NONE(0x4b00, 0x100)
1935 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1936 * This is a synchronous interrupt invoked with the "sc" instruction. The
1937 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1938 * is directed to the currently running OS. The hypercall is invoked with
1939 * "sc 1" and it sets HV=1, so it elevates to hypervisor.
1941 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1942 * 0x4c00 virtual mode.
1945 * If the KVM test fires then it was due to a hypercall and is accordingly
1946 * routed to KVM. Otherwise this executes a normal Linux system call.
1950 * syscall and hypercalls register conventions are documented in
1951 * Documentation/powerpc/syscall64-abi.rst and
1952 * Documentation/powerpc/papr_hcalls.rst respectively.
1954 * The intersection of volatile registers that don't contain possible
1955 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1956 * without saving, though xer is not a good idea to use, as hardware may
1957 * interpret some bits so it may be costly to change them.
1959 INT_DEFINE_BEGIN(system_call)
1963 INT_DEFINE_END(system_call)
1965 .macro SYSTEM_CALL virt
1966 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1968 * There is a little bit of juggling to get syscall and hcall
1969 * working well. Save r13 in ctr to avoid using SPRG scratch
1972 * Userspace syscalls have already saved the PPR, hcalls must save
1973 * it before setting HMT_MEDIUM.
1977 std r10,PACA_EXGEN+EX_R10(r13)
1979 KVMTEST system_call /* uses r10, branch to system_call_kvm */
1987 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1991 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1994 /* We reach here with PACA in r13, r13 in r9. */
2001 __LOAD_HANDLER(r10, system_call_common)
2003 ld r10,PACAKMSR(r13)
2006 b . /* prevent speculative execution */
2009 mtmsrd r10,1 /* Set RI (EE=0) */
2010 #ifdef CONFIG_RELOCATABLE
2011 __LOAD_HANDLER(r10, system_call_common)
2015 b system_call_common
2019 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
2020 /* Fast LE/BE switch system call */
2021 1: mfspr r12,SPRN_SRR1
2025 RFI_TO_USER /* return to userspace */
2026 b . /* prevent speculative execution */
2030 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
2032 EXC_REAL_END(system_call, 0xc00, 0x100)
2033 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2035 EXC_VIRT_END(system_call, 0x4c00, 0x100)
2037 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2038 TRAMP_REAL_BEGIN(system_call_kvm)
2040 * This is a hcall, so register convention is as above, with these
2044 * orig r10 saved in PACA
2047 * Save the PPR (on systems that support it) before changing to
2048 * HMT_MEDIUM. That allows the KVM code to save that value into the
2049 * guest state (it is the guest's PPR value).
2053 std r10,HSTATE_PPR(r13)
2054 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2059 std r12,HSTATE_SCRATCH0(r13)
2062 #ifdef CONFIG_RELOCATABLE
2064 * Requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives
2065 * outside the head section.
2067 __LOAD_FAR_HANDLER(r10, kvmppc_interrupt)
2069 ld r10,PACA_EXGEN+EX_R10(r13)
2072 ld r10,PACA_EXGEN+EX_R10(r13)
2079 * Interrupt 0xd00 - Trace Interrupt.
2080 * This is a synchronous interrupt in response to instruction step or
2081 * breakpoint faults.
2083 INT_DEFINE_BEGIN(single_step)
2085 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2088 INT_DEFINE_END(single_step)
2090 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2091 GEN_INT_ENTRY single_step, virt=0
2092 EXC_REAL_END(single_step, 0xd00, 0x100)
2093 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2094 GEN_INT_ENTRY single_step, virt=1
2095 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2096 EXC_COMMON_BEGIN(single_step_common)
2097 GEN_COMMON single_step
2098 addi r3,r1,STACK_FRAME_OVERHEAD
2099 bl single_step_exception
2106 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2107 * This is a synchronous interrupt in response to an MMU fault caused by a
2108 * guest data access.
2111 * This should always get routed to KVM. In radix MMU mode, this is caused
2112 * by a guest nested radix access that can't be performed due to the
2113 * partition scope page table. In hash mode, this can be caused by guests
2114 * running with translation disabled (virtual real mode) or with VPM enabled.
2115 * KVM will update the page table structures or disallow the access.
2117 INT_DEFINE_BEGIN(h_data_storage)
2125 INT_DEFINE_END(h_data_storage)
2127 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2128 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2129 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2130 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2131 GEN_INT_ENTRY h_data_storage, virt=1, ool=1
2132 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2133 EXC_COMMON_BEGIN(h_data_storage_common)
2134 GEN_COMMON h_data_storage
2135 addi r3,r1,STACK_FRAME_OVERHEAD
2136 BEGIN_MMU_FTR_SECTION
2140 MMU_FTR_SECTION_ELSE
2141 bl unknown_exception
2142 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2145 GEN_KVM h_data_storage
2149 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2150 * This is a synchronous interrupt in response to an MMU fault caused by a
2151 * guest instruction fetch, similar to HDSI.
2153 INT_DEFINE_BEGIN(h_instr_storage)
2158 INT_DEFINE_END(h_instr_storage)
2160 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2161 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2162 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2163 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2164 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1
2165 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2166 EXC_COMMON_BEGIN(h_instr_storage_common)
2167 GEN_COMMON h_instr_storage
2168 addi r3,r1,STACK_FRAME_OVERHEAD
2169 bl unknown_exception
2172 GEN_KVM h_instr_storage
2176 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2178 INT_DEFINE_BEGIN(emulation_assist)
2183 INT_DEFINE_END(emulation_assist)
2185 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2186 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2187 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2188 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2189 GEN_INT_ENTRY emulation_assist, virt=1, ool=1
2190 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2191 EXC_COMMON_BEGIN(emulation_assist_common)
2192 GEN_COMMON emulation_assist
2193 addi r3,r1,STACK_FRAME_OVERHEAD
2194 bl emulation_assist_interrupt
2195 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2198 GEN_KVM emulation_assist
2202 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2203 * This is an asynchronous interrupt caused by a Hypervisor Maintenance
2204 * Exception. It is always taken in real mode but uses HSRR registers
2205 * unlike SRESET and MCE.
2207 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable
2208 * with IRQS_DISABLED mask (i.e., local_irq_disable()).
2211 * This is a special case, this is handled similarly to machine checks, with an
2212 * initial real mode handler that is not soft-masked, which attempts to fix the
2213 * problem. Then a regular handler which is soft-maskable and reports the
2216 * The emergency stack is used for the early real mode handler.
2218 * XXX: unclear why MCE and HMI schemes could not be made common, e.g.,
2219 * either use soft-masking for the MCE, or use irq_work for the HMI.
2222 * Unlike MCE, this calls into KVM without calling the real mode handler
2225 INT_DEFINE_BEGIN(hmi_exception_early)
2231 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2233 INT_DEFINE_END(hmi_exception_early)
2235 INT_DEFINE_BEGIN(hmi_exception)
2240 INT_DEFINE_END(hmi_exception)
2242 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2243 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2244 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2245 EXC_VIRT_NONE(0x4e60, 0x20)
2247 EXC_COMMON_BEGIN(hmi_exception_early_common)
2248 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early
2250 mr r10,r1 /* Save r1 */
2251 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
2252 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
2254 __GEN_COMMON_BODY hmi_exception_early
2256 addi r3,r1,STACK_FRAME_OVERHEAD
2257 bl hmi_exception_realmode
2261 EXCEPTION_RESTORE_REGS hsrr=1
2262 HRFI_TO_USER_OR_KERNEL
2266 * Go to virtual mode and pull the HMI event information from
2269 EXCEPTION_RESTORE_REGS hsrr=1
2270 GEN_INT_ENTRY hmi_exception, virt=0
2272 GEN_KVM hmi_exception_early
2274 EXC_COMMON_BEGIN(hmi_exception_common)
2275 GEN_COMMON hmi_exception
2278 addi r3,r1,STACK_FRAME_OVERHEAD
2279 bl handle_hmi_exception
2282 GEN_KVM hmi_exception
2286 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2287 * This is an asynchronous interrupt in response to a msgsnd doorbell.
2288 * Similar to the 0xa00 doorbell but for host rather than guest.
2290 INT_DEFINE_BEGIN(h_doorbell)
2296 INT_DEFINE_END(h_doorbell)
2298 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2299 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2300 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2301 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2302 GEN_INT_ENTRY h_doorbell, virt=1, ool=1
2303 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2304 EXC_COMMON_BEGIN(h_doorbell_common)
2305 GEN_COMMON h_doorbell
2308 addi r3,r1,STACK_FRAME_OVERHEAD
2309 #ifdef CONFIG_PPC_DOORBELL
2310 bl doorbell_exception
2312 bl unknown_exception
2320 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2321 * This is an asynchronous interrupt in response to an "external exception".
2322 * Similar to 0x500 but for host only.
2324 INT_DEFINE_BEGIN(h_virt_irq)
2330 INT_DEFINE_END(h_virt_irq)
2332 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2333 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2334 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2335 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2336 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1
2337 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2338 EXC_COMMON_BEGIN(h_virt_irq_common)
2339 GEN_COMMON h_virt_irq
2342 addi r3,r1,STACK_FRAME_OVERHEAD
2349 EXC_REAL_NONE(0xec0, 0x20)
2350 EXC_VIRT_NONE(0x4ec0, 0x20)
2351 EXC_REAL_NONE(0xee0, 0x20)
2352 EXC_VIRT_NONE(0x4ee0, 0x20)
2356 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2357 * This is an asynchronous interrupt in response to a PMU exception.
2358 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
2359 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()).
2362 * This calls into the perf subsystem.
2364 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it
2365 * runs under local_irq_disable. However it may be soft-masked in
2366 * powerpc-specific code.
2368 * If soft masked, the masked handler will note the pending interrupt for
2369 * replay, and clear MSR[EE] in the interrupted context.
2371 INT_DEFINE_BEGIN(performance_monitor)
2373 IMASK=IRQS_PMI_DISABLED
2374 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2377 INT_DEFINE_END(performance_monitor)
2379 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2380 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2381 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2382 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2383 GEN_INT_ENTRY performance_monitor, virt=1, ool=1
2384 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2385 EXC_COMMON_BEGIN(performance_monitor_common)
2386 GEN_COMMON performance_monitor
2389 addi r3,r1,STACK_FRAME_OVERHEAD
2390 bl performance_monitor_exception
2393 GEN_KVM performance_monitor
2397 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2398 * This is a synchronous interrupt in response to
2399 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2400 * Similar to FP unavailable.
2402 INT_DEFINE_BEGIN(altivec_unavailable)
2405 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2408 INT_DEFINE_END(altivec_unavailable)
2410 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2411 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2412 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2413 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2414 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1
2415 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2416 EXC_COMMON_BEGIN(altivec_unavailable_common)
2417 GEN_COMMON altivec_unavailable
2418 #ifdef CONFIG_ALTIVEC
2421 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2422 BEGIN_FTR_SECTION_NESTED(69)
2423 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2424 * transaction), go do TM stuff
2426 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2428 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2431 b fast_interrupt_return
2432 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2433 2: /* User process was in a transaction */
2434 RECONCILE_IRQ_STATE(r10, r11)
2435 addi r3,r1,STACK_FRAME_OVERHEAD
2436 bl altivec_unavailable_tm
2440 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2442 RECONCILE_IRQ_STATE(r10, r11)
2443 addi r3,r1,STACK_FRAME_OVERHEAD
2444 bl altivec_unavailable_exception
2447 GEN_KVM altivec_unavailable
2451 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2452 * This is a synchronous interrupt in response to
2453 * executing a VSX instruction with MSR[VSX]=0.
2454 * Similar to FP unavailable.
2456 INT_DEFINE_BEGIN(vsx_unavailable)
2459 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2462 INT_DEFINE_END(vsx_unavailable)
2464 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2465 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2466 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2467 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2468 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1
2469 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2470 EXC_COMMON_BEGIN(vsx_unavailable_common)
2471 GEN_COMMON vsx_unavailable
2475 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2476 BEGIN_FTR_SECTION_NESTED(69)
2477 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2478 * transaction), go do TM stuff
2480 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2482 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2485 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2486 2: /* User process was in a transaction */
2487 RECONCILE_IRQ_STATE(r10, r11)
2488 addi r3,r1,STACK_FRAME_OVERHEAD
2489 bl vsx_unavailable_tm
2493 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2495 RECONCILE_IRQ_STATE(r10, r11)
2496 addi r3,r1,STACK_FRAME_OVERHEAD
2497 bl vsx_unavailable_exception
2500 GEN_KVM vsx_unavailable
2504 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2505 * This is a synchronous interrupt in response to
2506 * executing an instruction without access to the facility that can be
2507 * resolved by the OS (e.g., FSCR, MSR).
2508 * Similar to FP unavailable.
2510 INT_DEFINE_BEGIN(facility_unavailable)
2512 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2515 INT_DEFINE_END(facility_unavailable)
2517 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2518 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2519 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2520 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2521 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1
2522 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2523 EXC_COMMON_BEGIN(facility_unavailable_common)
2524 GEN_COMMON facility_unavailable
2525 addi r3,r1,STACK_FRAME_OVERHEAD
2526 bl facility_unavailable_exception
2527 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2530 GEN_KVM facility_unavailable
2534 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2535 * This is a synchronous interrupt in response to
2536 * executing an instruction without access to the facility that can only
2537 * be resolved in HV mode (e.g., HFSCR).
2538 * Similar to FP unavailable.
2540 INT_DEFINE_BEGIN(h_facility_unavailable)
2545 INT_DEFINE_END(h_facility_unavailable)
2547 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2548 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2549 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2550 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2551 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1
2552 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2553 EXC_COMMON_BEGIN(h_facility_unavailable_common)
2554 GEN_COMMON h_facility_unavailable
2555 addi r3,r1,STACK_FRAME_OVERHEAD
2556 bl facility_unavailable_exception
2557 REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */
2560 GEN_KVM h_facility_unavailable
2563 EXC_REAL_NONE(0xfa0, 0x20)
2564 EXC_VIRT_NONE(0x4fa0, 0x20)
2565 EXC_REAL_NONE(0xfc0, 0x20)
2566 EXC_VIRT_NONE(0x4fc0, 0x20)
2567 EXC_REAL_NONE(0xfe0, 0x20)
2568 EXC_VIRT_NONE(0x4fe0, 0x20)
2570 EXC_REAL_NONE(0x1000, 0x100)
2571 EXC_VIRT_NONE(0x5000, 0x100)
2572 EXC_REAL_NONE(0x1100, 0x100)
2573 EXC_VIRT_NONE(0x5100, 0x100)
2575 #ifdef CONFIG_CBE_RAS
2576 INT_DEFINE_BEGIN(cbe_system_error)
2581 INT_DEFINE_END(cbe_system_error)
2583 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2584 GEN_INT_ENTRY cbe_system_error, virt=0
2585 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2586 EXC_VIRT_NONE(0x5200, 0x100)
2587 EXC_COMMON_BEGIN(cbe_system_error_common)
2588 GEN_COMMON cbe_system_error
2589 addi r3,r1,STACK_FRAME_OVERHEAD
2590 bl cbe_system_error_exception
2593 GEN_KVM cbe_system_error
2595 #else /* CONFIG_CBE_RAS */
2596 EXC_REAL_NONE(0x1200, 0x100)
2597 EXC_VIRT_NONE(0x5200, 0x100)
2601 INT_DEFINE_BEGIN(instruction_breakpoint)
2603 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2607 INT_DEFINE_END(instruction_breakpoint)
2609 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2610 GEN_INT_ENTRY instruction_breakpoint, virt=0
2611 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2612 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2613 GEN_INT_ENTRY instruction_breakpoint, virt=1
2614 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2615 EXC_COMMON_BEGIN(instruction_breakpoint_common)
2616 GEN_COMMON instruction_breakpoint
2617 addi r3,r1,STACK_FRAME_OVERHEAD
2618 bl instruction_breakpoint_exception
2621 GEN_KVM instruction_breakpoint
2624 EXC_REAL_NONE(0x1400, 0x100)
2625 EXC_VIRT_NONE(0x5400, 0x100)
2628 * Interrupt 0x1500 - Soft Patch Interrupt
2631 * This is an implementation specific interrupt which can be used for a
2632 * range of exceptions.
2634 * This interrupt handler is unique in that it runs the denormal assist
2635 * code even for guests (and even in guest context) without going to KVM,
2636 * for speed. POWER9 does not raise denorm exceptions, so this special case
2637 * could be phased out in future to reduce special cases.
2639 INT_DEFINE_BEGIN(denorm_exception)
2644 INT_DEFINE_END(denorm_exception)
2646 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2647 GEN_INT_ENTRY denorm_exception, virt=0
2648 #ifdef CONFIG_PPC_DENORMALISATION
2649 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2652 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2653 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2654 #ifdef CONFIG_PPC_DENORMALISATION
2655 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2656 GEN_INT_ENTRY denorm_exception, virt=1
2657 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2659 GEN_BRANCH_TO_COMMON denorm_exception, virt=1
2660 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2662 EXC_VIRT_NONE(0x5500, 0x100)
2665 #ifdef CONFIG_PPC_DENORMALISATION
2666 TRAMP_REAL_BEGIN(denorm_assist)
2669 * To denormalise we need to move a copy of the register to itself.
2670 * For POWER6 do that here for all FP regs.
2673 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2674 xori r10,r10,(MSR_FE0|MSR_FE1)
2686 * To denormalise we need to move a copy of the register to itself.
2687 * For POWER7 do that here for the first 32 VSX registers only.
2690 oris r10,r10,MSR_VSX@h
2696 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2700 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2704 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2706 * To denormalise we need to move a copy of the register to itself.
2707 * For POWER8 we need to do that for all 64 VSX registers
2711 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2716 mfspr r11,SPRN_HSRR0
2718 mtspr SPRN_HSRR0,r11
2720 ld r9,PACA_EXGEN+EX_R9(r13)
2722 ld r10,PACA_EXGEN+EX_PPR(r13)
2724 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2726 ld r10,PACA_EXGEN+EX_CFAR(r13)
2728 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2729 ld r10,PACA_EXGEN+EX_R10(r13)
2730 ld r11,PACA_EXGEN+EX_R11(r13)
2731 ld r12,PACA_EXGEN+EX_R12(r13)
2732 ld r13,PACA_EXGEN+EX_R13(r13)
2737 EXC_COMMON_BEGIN(denorm_exception_common)
2738 GEN_COMMON denorm_exception
2739 addi r3,r1,STACK_FRAME_OVERHEAD
2740 bl unknown_exception
2743 GEN_KVM denorm_exception
2746 #ifdef CONFIG_CBE_RAS
2747 INT_DEFINE_BEGIN(cbe_maintenance)
2752 INT_DEFINE_END(cbe_maintenance)
2754 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2755 GEN_INT_ENTRY cbe_maintenance, virt=0
2756 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2757 EXC_VIRT_NONE(0x5600, 0x100)
2758 EXC_COMMON_BEGIN(cbe_maintenance_common)
2759 GEN_COMMON cbe_maintenance
2760 addi r3,r1,STACK_FRAME_OVERHEAD
2761 bl cbe_maintenance_exception
2764 GEN_KVM cbe_maintenance
2766 #else /* CONFIG_CBE_RAS */
2767 EXC_REAL_NONE(0x1600, 0x100)
2768 EXC_VIRT_NONE(0x5600, 0x100)
2772 INT_DEFINE_BEGIN(altivec_assist)
2774 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2777 INT_DEFINE_END(altivec_assist)
2779 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2780 GEN_INT_ENTRY altivec_assist, virt=0
2781 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2782 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2783 GEN_INT_ENTRY altivec_assist, virt=1
2784 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2785 EXC_COMMON_BEGIN(altivec_assist_common)
2786 GEN_COMMON altivec_assist
2787 addi r3,r1,STACK_FRAME_OVERHEAD
2788 #ifdef CONFIG_ALTIVEC
2789 bl altivec_assist_exception
2790 REST_NVGPRS(r1) /* instruction emulation may change GPRs */
2792 bl unknown_exception
2796 GEN_KVM altivec_assist
2799 #ifdef CONFIG_CBE_RAS
2800 INT_DEFINE_BEGIN(cbe_thermal)
2805 INT_DEFINE_END(cbe_thermal)
2807 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2808 GEN_INT_ENTRY cbe_thermal, virt=0
2809 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2810 EXC_VIRT_NONE(0x5800, 0x100)
2811 EXC_COMMON_BEGIN(cbe_thermal_common)
2812 GEN_COMMON cbe_thermal
2813 addi r3,r1,STACK_FRAME_OVERHEAD
2814 bl cbe_thermal_exception
2819 #else /* CONFIG_CBE_RAS */
2820 EXC_REAL_NONE(0x1800, 0x100)
2821 EXC_VIRT_NONE(0x5800, 0x100)
2825 #ifdef CONFIG_PPC_WATCHDOG
2827 INT_DEFINE_BEGIN(soft_nmi)
2830 IRECONCILE=0 /* Soft-NMI may fire under local_irq_disable */
2831 INT_DEFINE_END(soft_nmi)
2834 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2835 * stack is one that is usable by maskable interrupts so long as MSR_EE
2836 * remains off. It is used for recovery when something has corrupted the
2837 * normal kernel stack, for example. The "soft NMI" must not use the process
2838 * stack because we want irq disabled sections to avoid touching the stack
2839 * at all (other than PMU interrupts), so use the emergency stack for this,
2840 * and run it entirely with interrupts hard disabled.
2842 EXC_COMMON_BEGIN(soft_nmi_common)
2845 ld r1,PACAEMERGSP(r13)
2846 subi r1,r1,INT_FRAME_SIZE
2847 __GEN_COMMON_BODY soft_nmi
2850 * Set IRQS_ALL_DISABLED and save PACAIRQHAPPENED (see
2851 * system_reset_common)
2853 li r10,IRQS_ALL_DISABLED
2854 stb r10,PACAIRQSOFTMASK(r13)
2855 lbz r10,PACAIRQHAPPENED(r13)
2857 ori r10,r10,PACA_IRQ_HARD_DIS
2858 stb r10,PACAIRQHAPPENED(r13)
2860 addi r3,r1,STACK_FRAME_OVERHEAD
2861 bl soft_nmi_interrupt
2863 /* Clear MSR_RI before setting SRR0 and SRR1. */
2868 * Restore soft mask settings.
2871 stb r10,PACAIRQHAPPENED(r13)
2873 stb r10,PACAIRQSOFTMASK(r13)
2875 kuap_restore_amr r9, r10
2876 EXCEPTION_RESTORE_REGS hsrr=0
2879 #endif /* CONFIG_PPC_WATCHDOG */
2882 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2883 * - If it was a decrementer interrupt, we bump the dec to max and and return.
2884 * - If it was a doorbell we return immediately since doorbells are edge
2885 * triggered and won't automatically refire.
2886 * - If it was a HMI we return immediately since we handled it in realmode
2887 * and it won't refire.
2888 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2889 * This is called with r10 containing the value to OR to the paca field.
2891 .macro MASKED_INTERRUPT hsrr=0
2897 lbz r11,PACAIRQHAPPENED(r13)
2899 stb r11,PACAIRQHAPPENED(r13)
2900 cmpwi r10,PACA_IRQ_DEC
2905 #ifdef CONFIG_PPC_WATCHDOG
2910 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2912 xori r12,r12,MSR_EE /* clear MSR_EE */
2914 mtspr SPRN_HSRR1,r12
2918 ori r11,r11,PACA_IRQ_HARD_DIS
2919 stb r11,PACAIRQHAPPENED(r13)
2921 ld r10,PACA_EXGEN+EX_CTR(r13)
2925 ld r9,PACA_EXGEN+EX_R9(r13)
2926 ld r10,PACA_EXGEN+EX_R10(r13)
2927 ld r11,PACA_EXGEN+EX_R11(r13)
2928 ld r12,PACA_EXGEN+EX_R12(r13)
2929 ld r13,PACA_EXGEN+EX_R13(r13)
2930 /* May return to masked low address where r13 is not set up */
2939 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2940 std r9,PACA_EXRFI+EX_R9(r13)
2941 std r10,PACA_EXRFI+EX_R10(r13)
2943 ld r9,PACA_EXRFI+EX_R9(r13)
2944 ld r10,PACA_EXRFI+EX_R10(r13)
2952 TRAMP_REAL_BEGIN(rfi_flush_fallback)
2955 std r1,PACA_EXRFI+EX_R12(r13)
2956 ld r1,PACAKSAVE(r13)
2957 std r9,PACA_EXRFI+EX_R9(r13)
2958 std r10,PACA_EXRFI+EX_R10(r13)
2959 std r11,PACA_EXRFI+EX_R11(r13)
2961 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2962 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2963 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2965 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2967 /* order ld/st prior to dcbt stop all streams with flushing */
2971 * The load adresses are at staggered offsets within cachelines,
2972 * which suits some pipelines better (on others it should not
2976 ld r11,(0x80 + 8)*0(r10)
2977 ld r11,(0x80 + 8)*1(r10)
2978 ld r11,(0x80 + 8)*2(r10)
2979 ld r11,(0x80 + 8)*3(r10)
2980 ld r11,(0x80 + 8)*4(r10)
2981 ld r11,(0x80 + 8)*5(r10)
2982 ld r11,(0x80 + 8)*6(r10)
2983 ld r11,(0x80 + 8)*7(r10)
2988 ld r9,PACA_EXRFI+EX_R9(r13)
2989 ld r10,PACA_EXRFI+EX_R10(r13)
2990 ld r11,PACA_EXRFI+EX_R11(r13)
2991 ld r1,PACA_EXRFI+EX_R12(r13)
2995 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2998 std r1,PACA_EXRFI+EX_R12(r13)
2999 ld r1,PACAKSAVE(r13)
3000 std r9,PACA_EXRFI+EX_R9(r13)
3001 std r10,PACA_EXRFI+EX_R10(r13)
3002 std r11,PACA_EXRFI+EX_R11(r13)
3004 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
3005 ld r11,PACA_L1D_FLUSH_SIZE(r13)
3006 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
3008 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
3010 /* order ld/st prior to dcbt stop all streams with flushing */
3014 * The load adresses are at staggered offsets within cachelines,
3015 * which suits some pipelines better (on others it should not
3019 ld r11,(0x80 + 8)*0(r10)
3020 ld r11,(0x80 + 8)*1(r10)
3021 ld r11,(0x80 + 8)*2(r10)
3022 ld r11,(0x80 + 8)*3(r10)
3023 ld r11,(0x80 + 8)*4(r10)
3024 ld r11,(0x80 + 8)*5(r10)
3025 ld r11,(0x80 + 8)*6(r10)
3026 ld r11,(0x80 + 8)*7(r10)
3031 ld r9,PACA_EXRFI+EX_R9(r13)
3032 ld r10,PACA_EXRFI+EX_R10(r13)
3033 ld r11,PACA_EXRFI+EX_R11(r13)
3034 ld r1,PACA_EXRFI+EX_R12(r13)
3038 TRAMP_REAL_BEGIN(rfscv_flush_fallback)
3039 /* system call volatile */
3043 ld r1,PACAKSAVE(r13)
3045 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
3046 ld r11,PACA_L1D_FLUSH_SIZE(r13)
3047 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
3049 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
3051 /* order ld/st prior to dcbt stop all streams with flushing */
3055 * The load adresses are at staggered offsets within cachelines,
3056 * which suits some pipelines better (on others it should not
3060 ld r11,(0x80 + 8)*0(r10)
3061 ld r11,(0x80 + 8)*1(r10)
3062 ld r11,(0x80 + 8)*2(r10)
3063 ld r11,(0x80 + 8)*3(r10)
3064 ld r11,(0x80 + 8)*4(r10)
3065 ld r11,(0x80 + 8)*5(r10)
3066 ld r11,(0x80 + 8)*6(r10)
3067 ld r11,(0x80 + 8)*7(r10)
3081 MASKED_INTERRUPT hsrr=1
3083 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
3084 kvmppc_skip_interrupt:
3086 * Here all GPRs are unchanged from when the interrupt happened
3087 * except for r13, which is saved in SPRG_SCRATCH0.
3089 mfspr r13, SPRN_SRR0
3091 mtspr SPRN_SRR0, r13
3096 kvmppc_skip_Hinterrupt:
3098 * Here all GPRs are unchanged from when the interrupt happened
3099 * except for r13, which is saved in SPRG_SCRATCH0.
3101 mfspr r13, SPRN_HSRR0
3103 mtspr SPRN_HSRR0, r13
3110 * Relocation-on interrupts: A subset of the interrupts can be delivered
3111 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
3112 * it. Addresses are the same as the original interrupt addresses, but
3113 * offset by 0xc000000000004000.
3114 * It's impossible to receive interrupts below 0x300 via this mechanism.
3115 * KVM: None of these traps are from the guest ; anything that escalated
3116 * to HV=1 from HV=0 is delivered via real mode handlers.
3120 * This uses the standard macro, since the original 0x300 vector
3121 * only has extra guff for STAB-based processors -- which never
3125 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
3126 b __ppc64_runlatch_on
3128 USE_FIXED_SECTION(virt_trampolines)
3130 * All code below __end_interrupts is treated as soft-masked. If
3131 * any code runs here with MSR[EE]=1, it must then cope with pending
3132 * soft interrupt being raised (i.e., by ensuring it is replayed).
3134 * The __end_interrupts marker must be past the out-of-line (OOL)
3135 * handlers, so that they are copied to real address 0x100 when running
3136 * a relocatable kernel. This ensures they can be reached from the short
3137 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3138 * directly, without using LOAD_HANDLER().
3141 .globl __end_interrupts
3143 DEFINE_FIXED_SYMBOL(__end_interrupts)
3145 #ifdef CONFIG_PPC_970_NAP
3147 * Called by exception entry code if _TLF_NAPPING was set, this clears
3148 * the NAPPING flag, and redirects the exception exit to
3149 * power4_fixup_nap_return.
3151 .globl power4_fixup_nap
3152 EXC_COMMON_BEGIN(power4_fixup_nap)
3154 std r9,TI_LOCAL_FLAGS(r11)
3155 LOAD_REG_ADDR(r10, power4_idle_nap_return)
3159 power4_idle_nap_return:
3163 CLOSE_FIXED_SECTION(real_vectors);
3164 CLOSE_FIXED_SECTION(real_trampolines);
3165 CLOSE_FIXED_SECTION(virt_vectors);
3166 CLOSE_FIXED_SECTION(virt_trampolines);
3170 /* MSR[RI] should be clear because this uses SRR[01] */
3171 enable_machine_check:
3175 addi r3,r3,(1f - 0b)
3184 /* MSR[RI] should be clear because this uses SRR[01] */
3185 disable_machine_check:
3189 addi r3,r3,(1f - 0b)
3202 .balign IFETCH_ALIGN_BYTES
3204 #ifdef CONFIG_PPC_BOOK3S_64
3205 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
3206 ori r0,r0,DSISR_BAD_FAULT_64S@l
3207 and. r0,r5,r0 /* weird error? */
3208 bne- handle_page_fault /* if not, try to insert a HPTE */
3211 * If we are in an "NMI" (e.g., an interrupt when soft-disabled), then
3212 * don't call hash_page, just fail the fault. This is required to
3213 * prevent re-entrancy problems in the hash code, namely perf
3214 * interrupts hitting while something holds H_PAGE_BUSY, and taking a
3215 * hash fault. See the comment in hash_preload().
3217 ld r11, PACA_THREAD_INFO(r13)
3218 lwz r0,TI_PREEMPT(r11)
3219 andis. r0,r0,NMI_MASK@h
3223 * r3 contains the trap number
3224 * r4 contains the faulting address
3228 * at return r3 = 0 for success, 1 for page fault, negative for error
3230 bl __hash_page /* build HPTE if possible */
3231 cmpdi r3,0 /* see if __hash_page succeeded */
3234 beq interrupt_return /* Return from exception on success */
3239 /* Reload DAR/DSISR into r4/r5 for the DABR check below */
3242 #endif /* CONFIG_PPC_BOOK3S_64 */
3244 /* Here we have a page fault that hash_page can't handle. */
3246 11: andis. r0,r5,DSISR_DABRMATCH@h
3247 bne- handle_dabr_fault
3248 addi r3,r1,STACK_FRAME_OVERHEAD
3251 beq+ interrupt_return
3253 addi r3,r1,STACK_FRAME_OVERHEAD
3258 /* We have a data breakpoint exception - handle it */
3262 addi r3,r1,STACK_FRAME_OVERHEAD
3265 * do_break() may have changed the NV GPRS while handling a breakpoint.
3266 * If so, we need to restore them with their updated values.
3272 #ifdef CONFIG_PPC_BOOK3S_64
3273 /* We have a page fault that hash_page could handle but HV refused
3277 addi r3,r1,STACK_FRAME_OVERHEAD
3284 * We come here as a result of a DSI at a point where we don't want
3285 * to call hash_page, such as when we are accessing memory (possibly
3286 * user memory) inside a PMU interrupt that occurred while interrupts
3287 * were soft-disabled. We want to invoke the exception handler for
3288 * the access, or panic if there isn't a handler.
3290 77: addi r3,r1,STACK_FRAME_OVERHEAD