1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Boot code and exception vectors for Book3E processors
5 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
8 #include <linux/threads.h>
11 #include <asm/ppc_asm.h>
12 #include <asm/asm-offsets.h>
13 #include <asm/cputable.h>
14 #include <asm/setup.h>
15 #include <asm/thread_info.h>
16 #include <asm/reg_a2.h>
17 #include <asm/exception-64e.h>
19 #include <asm/irqflags.h>
20 #include <asm/ptrace.h>
21 #include <asm/ppc-opcode.h>
23 #include <asm/hw_irq.h>
24 #include <asm/kvm_asm.h>
25 #include <asm/kvm_booke_hv_asm.h>
26 #include <asm/feature-fixups.h>
27 #include <asm/context_tracking.h>
29 /* 64e interrupt returns always use SRR registers */
30 #define fast_interrupt_return fast_interrupt_return_srr
31 #define interrupt_return interrupt_return_srr
33 /* XXX This will ultimately add space for a special exception save
34 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
35 * when taking special interrupts. For now we don't support that,
36 * special interrupts from within a non-standard level will probably
39 #define SPECIAL_EXC_SRR0 0
40 #define SPECIAL_EXC_SRR1 1
41 #define SPECIAL_EXC_SPRG_GEN 2
42 #define SPECIAL_EXC_SPRG_TLB 3
43 #define SPECIAL_EXC_MAS0 4
44 #define SPECIAL_EXC_MAS1 5
45 #define SPECIAL_EXC_MAS2 6
46 #define SPECIAL_EXC_MAS3 7
47 #define SPECIAL_EXC_MAS6 8
48 #define SPECIAL_EXC_MAS7 9
49 #define SPECIAL_EXC_MAS5 10 /* E.HV only */
50 #define SPECIAL_EXC_MAS8 11 /* E.HV only */
51 #define SPECIAL_EXC_IRQHAPPENED 12
52 #define SPECIAL_EXC_DEAR 13
53 #define SPECIAL_EXC_ESR 14
54 #define SPECIAL_EXC_SOFTE 15
55 #define SPECIAL_EXC_CSRR0 16
56 #define SPECIAL_EXC_CSRR1 17
57 /* must be even to keep 16-byte stack alignment */
58 #define SPECIAL_EXC_END 18
60 #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
61 #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288)
63 #define SPECIAL_EXC_STORE(reg, name) \
64 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
66 #define SPECIAL_EXC_LOAD(reg, name) \
67 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
71 * We only need (or have stack space) to save this stuff if
72 * we interrupted the kernel.
79 * Advance to the next TLB exception frame for handler
80 * types that don't do it automatically.
82 LOAD_REG_ADDR(r11,extlb_level_exc)
84 mfspr r10,SPRN_SPRG_TLB_EXFRAME
86 mtspr SPRN_SPRG_TLB_EXFRAME,r10
89 * Save registers needed to allow nesting of certain exceptions
90 * (such as TLB misses) inside special exception levels
93 SPECIAL_EXC_STORE(r10,SRR0)
95 SPECIAL_EXC_STORE(r10,SRR1)
96 mfspr r10,SPRN_SPRG_GEN_SCRATCH
97 SPECIAL_EXC_STORE(r10,SPRG_GEN)
98 mfspr r10,SPRN_SPRG_TLB_SCRATCH
99 SPECIAL_EXC_STORE(r10,SPRG_TLB)
101 SPECIAL_EXC_STORE(r10,MAS0)
103 SPECIAL_EXC_STORE(r10,MAS1)
105 SPECIAL_EXC_STORE(r10,MAS2)
107 SPECIAL_EXC_STORE(r10,MAS3)
109 SPECIAL_EXC_STORE(r10,MAS6)
111 SPECIAL_EXC_STORE(r10,MAS7)
114 SPECIAL_EXC_STORE(r10,MAS5)
116 SPECIAL_EXC_STORE(r10,MAS8)
118 /* MAS5/8 could have inappropriate values if we interrupted KVM code */
122 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
124 SPECIAL_EXC_STORE(r10,DEAR)
126 SPECIAL_EXC_STORE(r10,ESR)
129 SPECIAL_EXC_STORE(r10,CSRR0)
131 SPECIAL_EXC_STORE(r10,CSRR1)
135 ret_from_level_except:
143 LOAD_REG_ADDR(r11,extlb_level_exc)
145 mfspr r10,SPRN_SPRG_TLB_EXFRAME
147 mtspr SPRN_SPRG_TLB_EXFRAME,r10
150 * It's possible that the special level exception interrupted a
151 * TLB miss handler, and inserted the same entry that the
152 * interrupted handler was about to insert. On CPUs without TLB
153 * write conditional, this can result in a duplicate TLB entry.
154 * Wipe all non-bolted entries to be safe.
156 * Note that this doesn't protect against any TLB misses
157 * we may take accessing the stack from here to the end of
158 * the special level exception. It's not clear how we can
159 * reasonably protect against that, but only CPUs with
160 * neither TLB write conditional nor bolted kernel memory
161 * are affected. Do any such CPUs even exist?
167 SPECIAL_EXC_LOAD(r10,SRR0)
169 SPECIAL_EXC_LOAD(r10,SRR1)
171 SPECIAL_EXC_LOAD(r10,SPRG_GEN)
172 mtspr SPRN_SPRG_GEN_SCRATCH,r10
173 SPECIAL_EXC_LOAD(r10,SPRG_TLB)
174 mtspr SPRN_SPRG_TLB_SCRATCH,r10
175 SPECIAL_EXC_LOAD(r10,MAS0)
177 SPECIAL_EXC_LOAD(r10,MAS1)
179 SPECIAL_EXC_LOAD(r10,MAS2)
181 SPECIAL_EXC_LOAD(r10,MAS3)
183 SPECIAL_EXC_LOAD(r10,MAS6)
185 SPECIAL_EXC_LOAD(r10,MAS7)
188 SPECIAL_EXC_LOAD(r10,MAS5)
190 SPECIAL_EXC_LOAD(r10,MAS8)
192 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
194 SPECIAL_EXC_LOAD(r10,DEAR)
196 SPECIAL_EXC_LOAD(r10,ESR)
199 stdcx. r0,0,r1 /* to clear the reservation */
211 .macro ret_from_level srr0 srr1 paca_ex scratch
212 bl ret_from_level_except
225 std r10,\paca_ex+EX_R10(r13);
226 std r11,\paca_ex+EX_R11(r13);
233 ld r10,\paca_ex+EX_R10(r13)
234 ld r11,\paca_ex+EX_R11(r13)
238 ret_from_crit_except:
239 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
243 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
246 /* Exception prolog code for all exceptions */
247 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
248 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
249 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
250 std r10,PACA_EX##type+EX_R10(r13); \
251 std r11,PACA_EX##type+EX_R11(r13); \
252 mfcr r10; /* save CR */ \
253 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
254 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
255 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
256 addition; /* additional code for that exc. */ \
257 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
258 type##_SET_KSTACK; /* get special stack if necessary */\
259 andi. r10,r11,MSR_PR; /* save stack pointer */ \
260 beq 1f; /* branch around if supervisor */ \
261 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
262 1: type##_BTB_FLUSH \
263 cmpdi cr1,r1,0; /* check if SP makes sense */ \
264 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
265 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
267 /* Exception type-specific macros */
268 #define GEN_SET_KSTACK \
269 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
270 #define SPRN_GEN_SRR0 SPRN_SRR0
271 #define SPRN_GEN_SRR1 SPRN_SRR1
273 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
274 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
275 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
277 #define CRIT_SET_KSTACK \
278 ld r1,PACA_CRIT_STACK(r13); \
279 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
280 #define SPRN_CRIT_SRR0 SPRN_CSRR0
281 #define SPRN_CRIT_SRR1 SPRN_CSRR1
283 #define DBG_SET_KSTACK \
284 ld r1,PACA_DBG_STACK(r13); \
285 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
286 #define SPRN_DBG_SRR0 SPRN_DSRR0
287 #define SPRN_DBG_SRR1 SPRN_DSRR1
289 #define MC_SET_KSTACK \
290 ld r1,PACA_MC_STACK(r13); \
291 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
292 #define SPRN_MC_SRR0 SPRN_MCSRR0
293 #define SPRN_MC_SRR1 SPRN_MCSRR1
295 #ifdef CONFIG_PPC_FSL_BOOK3E
296 #define GEN_BTB_FLUSH \
297 START_BTB_FLUSH_SECTION \
301 END_BTB_FLUSH_SECTION
303 #define CRIT_BTB_FLUSH \
304 START_BTB_FLUSH_SECTION \
306 END_BTB_FLUSH_SECTION
308 #define DBG_BTB_FLUSH CRIT_BTB_FLUSH
309 #define MC_BTB_FLUSH CRIT_BTB_FLUSH
310 #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
312 #define GEN_BTB_FLUSH
313 #define CRIT_BTB_FLUSH
314 #define DBG_BTB_FLUSH
316 #define GDBELL_BTB_FLUSH
319 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
320 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
322 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
323 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
325 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
326 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
328 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
329 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
331 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
332 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
334 /* Variants of the "addition" argument for the prolog
336 #define PROLOG_ADDITION_NONE_GEN(n)
337 #define PROLOG_ADDITION_NONE_GDBELL(n)
338 #define PROLOG_ADDITION_NONE_CRIT(n)
339 #define PROLOG_ADDITION_NONE_DBG(n)
340 #define PROLOG_ADDITION_NONE_MC(n)
342 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
343 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \
344 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
345 bne masked_interrupt_book3e_##n
348 * Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is
349 * called, because that does SAVE_NVGPRS which must see the original register
350 * values, otherwise the scratch values might be restored when exiting the
353 #define PROLOG_ADDITION_2REGS_GEN(n) \
354 std r14,PACA_EXGEN+EX_R14(r13); \
355 std r15,PACA_EXGEN+EX_R15(r13)
357 #define PROLOG_ADDITION_1REG_GEN(n) \
358 std r14,PACA_EXGEN+EX_R14(r13);
360 #define PROLOG_ADDITION_2REGS_CRIT(n) \
361 std r14,PACA_EXCRIT+EX_R14(r13); \
362 std r15,PACA_EXCRIT+EX_R15(r13)
364 #define PROLOG_ADDITION_2REGS_DBG(n) \
365 std r14,PACA_EXDBG+EX_R14(r13); \
366 std r15,PACA_EXDBG+EX_R15(r13)
368 #define PROLOG_ADDITION_2REGS_MC(n) \
369 std r14,PACA_EXMC+EX_R14(r13); \
370 std r15,PACA_EXMC+EX_R15(r13)
373 /* Core exception code for all exceptions except TLB misses. */
374 #define EXCEPTION_COMMON_LVL(n, scratch, excf) \
376 std r0,GPR0(r1); /* save r0 in stackframe */ \
377 std r2,GPR2(r1); /* save r2 in stackframe */ \
378 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
379 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
380 std r9,GPR9(r1); /* save r9 in stackframe */ \
381 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
382 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
383 beq 2f; /* if from kernel mode */ \
384 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
385 ld r4,excf+EX_R11(r13); /* get back r11 */ \
386 mfspr r5,scratch; /* get back r13 */ \
387 std r12,GPR12(r1); /* save r12 in stackframe */ \
388 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
389 mflr r6; /* save LR in stackframe */ \
390 mfctr r7; /* save CTR in stackframe */ \
391 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
392 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
393 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
394 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \
395 ld r12,exception_marker@toc(r2); \
397 std r3,GPR10(r1); /* save r10 to stackframe */ \
398 std r4,GPR11(r1); /* save r11 to stackframe */ \
399 std r5,GPR13(r1); /* save it to stackframe */ \
403 li r3,(n); /* regs.trap vector */ \
404 std r9,0(r1); /* store stack frame back link */ \
405 std r10,_CCR(r1); /* store orig CR in stackframe */ \
406 std r9,GPR1(r1); /* store stack frame back link */ \
407 std r11,SOFTE(r1); /* and save it to stackframe */ \
408 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
409 std r3,_TRAP(r1); /* set trap number */ \
410 std r0,RESULT(r1); /* clear regs->result */ \
413 #define EXCEPTION_COMMON(n) \
414 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
415 #define EXCEPTION_COMMON_CRIT(n) \
416 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
417 #define EXCEPTION_COMMON_MC(n) \
418 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
419 #define EXCEPTION_COMMON_DBG(n) \
420 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
422 /* XXX FIXME: Restore r14/r15 when necessary */
423 #define BAD_STACK_TRAMPOLINE(n) \
424 exc_##n##_bad_stack: \
425 li r1,(n); /* get exception number */ \
426 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
427 b bad_stack_book3e; /* bad stack error */
429 /* WARNING: If you change the layout of this stub, make sure you check
430 * the debug exception handler which handles single stepping
431 * into exceptions from userspace, and the MM code in
432 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
433 * and would need to be updated if that branch is moved
435 #define EXCEPTION_STUB(loc, label) \
436 . = interrupt_base_book3e + loc; \
437 nop; /* To make debug interrupts happy */ \
438 b exc_##label##_book3e;
448 /* Used by asynchronous interrupt that may happen in the idle loop.
450 * This check if the thread was in the idle loop, and if yes, returns
451 * to the caller rather than the PC. This is to avoid a race if
452 * interrupts happen before the wait instruction.
454 #define CHECK_NAPPING() \
455 ld r11, PACA_THREAD_INFO(r13); \
456 ld r10,TI_LOCAL_FLAGS(r11); \
457 andi. r9,r10,_TLF_NAPPING; \
460 rlwinm r7,r10,0,~_TLF_NAPPING; \
462 std r7,TI_LOCAL_FLAGS(r11); \
466 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
467 START_EXCEPTION(label); \
468 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
469 EXCEPTION_COMMON(trapnum) \
472 addi r3,r1,STACK_FRAME_OVERHEAD; \
476 /* This value is used to mark exception frames on the stack. */
479 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
483 * And here we have the exception vectors !
488 .globl interrupt_base_book3e
489 interrupt_base_book3e: /* fake trap */
490 EXCEPTION_STUB(0x000, machine_check)
491 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */
492 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
493 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
494 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
495 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
496 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
497 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
498 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
499 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
500 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
501 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
502 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
503 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
504 EXCEPTION_STUB(0x1c0, data_tlb_miss)
505 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
506 EXCEPTION_STUB(0x200, altivec_unavailable)
507 EXCEPTION_STUB(0x220, altivec_assist)
508 EXCEPTION_STUB(0x260, perfmon)
509 EXCEPTION_STUB(0x280, doorbell)
510 EXCEPTION_STUB(0x2a0, doorbell_crit)
511 EXCEPTION_STUB(0x2c0, guest_doorbell)
512 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
513 EXCEPTION_STUB(0x300, hypercall)
514 EXCEPTION_STUB(0x320, ehpriv)
515 EXCEPTION_STUB(0x340, lrat_error)
517 .globl __end_interrupts
520 /* Critical Input Interrupt */
521 START_EXCEPTION(critical_input);
522 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
523 PROLOG_ADDITION_NONE)
524 EXCEPTION_COMMON_CRIT(0x100)
527 addi r3,r1,STACK_FRAME_OVERHEAD
528 bl unknown_nmi_exception
529 b ret_from_crit_except
531 /* Machine Check Interrupt */
532 START_EXCEPTION(machine_check);
533 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
534 PROLOG_ADDITION_NONE)
535 EXCEPTION_COMMON_MC(0x000)
538 addi r3,r1,STACK_FRAME_OVERHEAD
539 bl machine_check_exception
542 /* Data Storage Interrupt */
543 START_EXCEPTION(data_storage)
544 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
545 PROLOG_ADDITION_2REGS)
550 ld r14,PACA_EXGEN+EX_R14(r13)
551 ld r15,PACA_EXGEN+EX_R15(r13)
552 EXCEPTION_COMMON(0x300)
553 b storage_fault_common
555 /* Instruction Storage Interrupt */
556 START_EXCEPTION(instruction_storage);
557 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
558 PROLOG_ADDITION_2REGS)
563 ld r14,PACA_EXGEN+EX_R14(r13)
564 ld r15,PACA_EXGEN+EX_R15(r13)
565 EXCEPTION_COMMON(0x400)
566 b storage_fault_common
568 /* External Input Interrupt */
569 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
570 external_input, do_IRQ, ACK_NONE)
573 START_EXCEPTION(alignment);
574 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
575 PROLOG_ADDITION_2REGS)
580 ld r14,PACA_EXGEN+EX_R14(r13)
581 ld r15,PACA_EXGEN+EX_R15(r13)
582 EXCEPTION_COMMON(0x600)
583 b alignment_more /* no room, go out of line */
585 /* Program Interrupt */
586 START_EXCEPTION(program);
587 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
588 PROLOG_ADDITION_1REG)
591 ld r14,PACA_EXGEN+EX_R14(r13)
592 EXCEPTION_COMMON(0x700)
593 addi r3,r1,STACK_FRAME_OVERHEAD
594 bl program_check_exception
598 /* Floating Point Unavailable Interrupt */
599 START_EXCEPTION(fp_unavailable);
600 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
601 PROLOG_ADDITION_NONE)
602 /* we can probably do a shorter exception entry for that one... */
603 EXCEPTION_COMMON(0x800)
608 b fast_interrupt_return
609 1: addi r3,r1,STACK_FRAME_OVERHEAD
610 bl kernel_fp_unavailable_exception
613 /* Altivec Unavailable Interrupt */
614 START_EXCEPTION(altivec_unavailable);
615 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
616 PROLOG_ADDITION_NONE)
617 /* we can probably do a shorter exception entry for that one... */
618 EXCEPTION_COMMON(0x200)
619 #ifdef CONFIG_ALTIVEC
625 b fast_interrupt_return
627 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
629 addi r3,r1,STACK_FRAME_OVERHEAD
630 bl altivec_unavailable_exception
634 START_EXCEPTION(altivec_assist);
635 NORMAL_EXCEPTION_PROLOG(0x220,
636 BOOKE_INTERRUPT_ALTIVEC_ASSIST,
637 PROLOG_ADDITION_NONE)
638 EXCEPTION_COMMON(0x220)
639 addi r3,r1,STACK_FRAME_OVERHEAD
640 #ifdef CONFIG_ALTIVEC
642 bl altivec_assist_exception
643 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
651 /* Decrementer Interrupt */
652 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
653 decrementer, timer_interrupt, ACK_DEC)
655 /* Fixed Interval Timer Interrupt */
656 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
657 fixed_interval, unknown_exception, ACK_FIT)
659 /* Watchdog Timer Interrupt */
660 START_EXCEPTION(watchdog);
661 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
662 PROLOG_ADDITION_NONE)
663 EXCEPTION_COMMON_CRIT(0x9f0)
666 addi r3,r1,STACK_FRAME_OVERHEAD
667 #ifdef CONFIG_BOOKE_WDT
670 bl unknown_nmi_exception
672 b ret_from_crit_except
674 /* System Call Interrupt */
675 START_EXCEPTION(system_call)
676 mr r9,r13 /* keep a copy of userland r13 */
677 mfspr r11,SPRN_SRR0 /* get return address */
678 mfspr r12,SPRN_SRR1 /* get previous MSR */
679 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
682 /* Auxiliary Processor Unavailable Interrupt */
683 START_EXCEPTION(ap_unavailable);
684 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
685 PROLOG_ADDITION_NONE)
686 EXCEPTION_COMMON(0xf20)
687 addi r3,r1,STACK_FRAME_OVERHEAD
691 /* Debug exception as a critical interrupt*/
692 START_EXCEPTION(debug_crit);
693 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
694 PROLOG_ADDITION_2REGS)
697 * If there is a single step or branch-taken exception in an
698 * exception entry sequence, it was probably meant to apply to
699 * the code where the exception occurred (since exception entry
700 * doesn't turn off DE automatically). We simulate the effect
701 * of turning off DE on entry to an exception handler by turning
702 * off DE in the CSRR1 value and clearing the debug status.
705 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
706 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
709 #ifdef CONFIG_RELOCATABLE
711 ld r14,interrupt_base_book3e@got(r15)
712 ld r15,__end_interrupts@got(r15)
716 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
718 LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
724 /* here it looks like we got an inappropriate debug exception. */
725 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
726 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
729 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
730 ld r1,PACA_EXCRIT+EX_R1(r13)
731 ld r14,PACA_EXCRIT+EX_R14(r13)
732 ld r15,PACA_EXCRIT+EX_R15(r13)
734 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
735 ld r11,PACA_EXCRIT+EX_R11(r13)
736 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
739 /* Normal debug exception */
740 /* XXX We only handle coming from userspace for now since we can't
741 * quite save properly an interrupted kernel state yet
743 1: andi. r14,r11,MSR_PR; /* check for userspace again */
744 beq kernel_dbg_exc; /* if from kernel mode */
746 /* Now we mash up things to make it look like we are coming on a
751 ld r14,PACA_EXCRIT+EX_R14(r13)
752 ld r15,PACA_EXCRIT+EX_R15(r13)
753 EXCEPTION_COMMON_CRIT(0xd00)
754 addi r3,r1,STACK_FRAME_OVERHEAD
762 /* Debug exception as a debug interrupt*/
763 START_EXCEPTION(debug_debug);
764 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
765 PROLOG_ADDITION_2REGS)
768 * If there is a single step or branch-taken exception in an
769 * exception entry sequence, it was probably meant to apply to
770 * the code where the exception occurred (since exception entry
771 * doesn't turn off DE automatically). We simulate the effect
772 * of turning off DE on entry to an exception handler by turning
773 * off DE in the DSRR1 value and clearing the debug status.
776 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
777 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
780 #ifdef CONFIG_RELOCATABLE
782 ld r14,interrupt_base_book3e@got(r15)
783 ld r15,__end_interrupts@got(r15)
787 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
789 LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
795 /* here it looks like we got an inappropriate debug exception. */
796 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
797 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
800 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
801 ld r1,PACA_EXDBG+EX_R1(r13)
802 ld r14,PACA_EXDBG+EX_R14(r13)
803 ld r15,PACA_EXDBG+EX_R15(r13)
805 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
806 ld r11,PACA_EXDBG+EX_R11(r13)
807 mfspr r13,SPRN_SPRG_DBG_SCRATCH
810 /* Normal debug exception */
811 /* XXX We only handle coming from userspace for now since we can't
812 * quite save properly an interrupted kernel state yet
814 1: andi. r14,r11,MSR_PR; /* check for userspace again */
815 beq kernel_dbg_exc; /* if from kernel mode */
817 /* Now we mash up things to make it look like we are coming on a
822 ld r14,PACA_EXDBG+EX_R14(r13)
823 ld r15,PACA_EXDBG+EX_R15(r13)
824 EXCEPTION_COMMON_DBG(0xd08)
825 addi r3,r1,STACK_FRAME_OVERHEAD
830 START_EXCEPTION(perfmon);
831 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
832 PROLOG_ADDITION_NONE)
833 EXCEPTION_COMMON(0x260)
835 addi r3,r1,STACK_FRAME_OVERHEAD
836 bl performance_monitor_exception
839 /* Doorbell interrupt */
840 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
841 doorbell, doorbell_exception, ACK_NONE)
843 /* Doorbell critical Interrupt */
844 START_EXCEPTION(doorbell_crit);
845 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
846 PROLOG_ADDITION_NONE)
847 EXCEPTION_COMMON_CRIT(0x2a0)
850 addi r3,r1,STACK_FRAME_OVERHEAD
851 bl unknown_nmi_exception
852 b ret_from_crit_except
855 * Guest doorbell interrupt
856 * This general exception use GSRRx save/restore registers
858 START_EXCEPTION(guest_doorbell);
859 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
860 PROLOG_ADDITION_NONE)
861 EXCEPTION_COMMON(0x2c0)
862 addi r3,r1,STACK_FRAME_OVERHEAD
866 /* Guest Doorbell critical Interrupt */
867 START_EXCEPTION(guest_doorbell_crit);
868 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
869 PROLOG_ADDITION_NONE)
870 EXCEPTION_COMMON_CRIT(0x2e0)
873 addi r3,r1,STACK_FRAME_OVERHEAD
874 bl unknown_nmi_exception
875 b ret_from_crit_except
877 /* Hypervisor call */
878 START_EXCEPTION(hypercall);
879 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
880 PROLOG_ADDITION_NONE)
881 EXCEPTION_COMMON(0x310)
882 addi r3,r1,STACK_FRAME_OVERHEAD
886 /* Embedded Hypervisor priviledged */
887 START_EXCEPTION(ehpriv);
888 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
889 PROLOG_ADDITION_NONE)
890 EXCEPTION_COMMON(0x320)
891 addi r3,r1,STACK_FRAME_OVERHEAD
895 /* LRAT Error interrupt */
896 START_EXCEPTION(lrat_error);
897 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
898 PROLOG_ADDITION_NONE)
899 EXCEPTION_COMMON(0x340)
900 addi r3,r1,STACK_FRAME_OVERHEAD
904 .macro SEARCH_RESTART_TABLE
905 #ifdef CONFIG_RELOCATABLE
907 ld r14,__start___restart_table@got(r11)
908 ld r15,__stop___restart_table@got(r11)
910 LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table)
911 LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table)
933 * An interrupt came in while soft-disabled; We mark paca->irq_happened
934 * accordingly and if the interrupt is level sensitive, we hard disable
935 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
936 * keep these in synch.
939 .macro masked_interrupt_book3e paca_irq full_mask
940 std r14,PACA_EXGEN+EX_R14(r13)
941 std r15,PACA_EXGEN+EX_R15(r13)
943 lbz r10,PACAIRQHAPPENED(r13)
945 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
947 ori r10,r10,\paca_irq
949 stb r10,PACAIRQHAPPENED(r13)
952 xori r11,r11,MSR_EE /* clear MSR_EE */
960 mtspr SPRN_SRR0,r11 /* return to restart address */
963 lwz r11,PACA_EXGEN+EX_CR(r13)
965 ld r10,PACA_EXGEN+EX_R10(r13)
966 ld r11,PACA_EXGEN+EX_R11(r13)
967 ld r14,PACA_EXGEN+EX_R14(r13)
968 ld r15,PACA_EXGEN+EX_R15(r13)
969 mfspr r13,SPRN_SPRG_GEN_SCRATCH
974 masked_interrupt_book3e_0x500:
975 masked_interrupt_book3e PACA_IRQ_EE 1
977 masked_interrupt_book3e_0x900:
979 masked_interrupt_book3e PACA_IRQ_DEC 0
981 masked_interrupt_book3e_0x980:
983 masked_interrupt_book3e PACA_IRQ_DEC 0
985 masked_interrupt_book3e_0x280:
986 masked_interrupt_book3e_0x2c0:
987 masked_interrupt_book3e PACA_IRQ_DBELL 0
990 * This is called from 0x300 and 0x400 handlers after the prologs with
991 * r14 and r15 containing the fault address and error code, with the
992 * original values stashed away in the PACA
994 storage_fault_common:
995 addi r3,r1,STACK_FRAME_OVERHEAD
1000 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1004 addi r3,r1,STACK_FRAME_OVERHEAD
1005 bl alignment_exception
1010 * Trampolines used when spotting a bad kernel stack pointer in
1011 * the exception entry code.
1013 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1014 * index around, etc... to handle crit & mcheck
1016 BAD_STACK_TRAMPOLINE(0x000)
1017 BAD_STACK_TRAMPOLINE(0x100)
1018 BAD_STACK_TRAMPOLINE(0x200)
1019 BAD_STACK_TRAMPOLINE(0x220)
1020 BAD_STACK_TRAMPOLINE(0x260)
1021 BAD_STACK_TRAMPOLINE(0x280)
1022 BAD_STACK_TRAMPOLINE(0x2a0)
1023 BAD_STACK_TRAMPOLINE(0x2c0)
1024 BAD_STACK_TRAMPOLINE(0x2e0)
1025 BAD_STACK_TRAMPOLINE(0x300)
1026 BAD_STACK_TRAMPOLINE(0x310)
1027 BAD_STACK_TRAMPOLINE(0x320)
1028 BAD_STACK_TRAMPOLINE(0x340)
1029 BAD_STACK_TRAMPOLINE(0x400)
1030 BAD_STACK_TRAMPOLINE(0x500)
1031 BAD_STACK_TRAMPOLINE(0x600)
1032 BAD_STACK_TRAMPOLINE(0x700)
1033 BAD_STACK_TRAMPOLINE(0x800)
1034 BAD_STACK_TRAMPOLINE(0x900)
1035 BAD_STACK_TRAMPOLINE(0x980)
1036 BAD_STACK_TRAMPOLINE(0x9f0)
1037 BAD_STACK_TRAMPOLINE(0xa00)
1038 BAD_STACK_TRAMPOLINE(0xb00)
1039 BAD_STACK_TRAMPOLINE(0xc00)
1040 BAD_STACK_TRAMPOLINE(0xd00)
1041 BAD_STACK_TRAMPOLINE(0xd08)
1042 BAD_STACK_TRAMPOLINE(0xe00)
1043 BAD_STACK_TRAMPOLINE(0xf00)
1044 BAD_STACK_TRAMPOLINE(0xf20)
1046 .globl bad_stack_book3e
1048 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1049 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
1050 ld r1,PACAEMERGSP(r13)
1051 subi r1,r1,64+INT_FRAME_SIZE
1054 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1055 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1062 std r0,GPR0(r1); /* save r0 in stackframe */ \
1063 std r2,GPR2(r1); /* save r2 in stackframe */ \
1064 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
1065 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
1066 std r9,GPR9(r1); /* save r9 in stackframe */ \
1067 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
1068 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
1069 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1070 std r3,GPR10(r1); /* save r10 to stackframe */ \
1071 std r4,GPR11(r1); /* save r11 to stackframe */ \
1072 std r12,GPR12(r1); /* save r12 in stackframe */ \
1073 std r5,GPR13(r1); /* save it to stackframe */ \
1082 lhz r12,PACA_TRAP_SAVE(r13)
1084 addi r11,r1,INT_FRAME_SIZE
1089 1: addi r3,r1,STACK_FRAME_OVERHEAD
1094 * Setup the initial TLB for a core. This current implementation
1095 * assume that whatever we are running off will not conflict with
1096 * the new mapping at PAGE_OFFSET.
1098 _GLOBAL(initial_tlb_book3e)
1100 /* Look for the first TLB with IPROT set */
1101 mfspr r4,SPRN_TLB0CFG
1102 andi. r3,r4,TLBnCFG_IPROT
1103 lis r3,MAS0_TLBSEL(0)@h
1106 mfspr r4,SPRN_TLB1CFG
1107 andi. r3,r4,TLBnCFG_IPROT
1108 lis r3,MAS0_TLBSEL(1)@h
1111 mfspr r4,SPRN_TLB2CFG
1112 andi. r3,r4,TLBnCFG_IPROT
1113 lis r3,MAS0_TLBSEL(2)@h
1116 lis r3,MAS0_TLBSEL(3)@h
1117 mfspr r4,SPRN_TLB3CFG
1121 andi. r5,r4,TLBnCFG_HES
1124 mflr r8 /* save LR */
1125 /* 1. Find the index of the entry we're executing in
1127 * r3 = MAS0_TLBSEL (for the iprot array)
1130 bl invstr /* Find our address */
1131 invstr: mflr r6 /* Make it accessible */
1133 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
1138 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
1141 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
1143 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
1144 oris r7,r7,MAS1_IPROT@h
1148 /* 2. Invalidate all entries except the entry we're executing in
1150 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1152 * r5 = ESEL of entry we are running in
1154 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
1155 li r6,0 /* Set Entry counter to 0 */
1156 1: mr r7,r3 /* Set MAS0(TLBSEL) */
1157 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1161 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
1163 beq skpinv /* Dont update the current execution TLB */
1167 skpinv: addi r6,r6,1 /* Increment */
1168 cmpw r6,r4 /* Are we done? */
1169 bne 1b /* If not, repeat */
1171 /* Invalidate all TLBs */
1172 PPC_TLBILX_ALL(0,R0)
1176 /* 3. Setup a temp mapping and jump to it
1178 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1179 * r5 = ESEL of entry we are running in
1181 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
1183 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
1187 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
1191 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
1199 bl 1f /* Find our address */
1201 addi r6,r6,(2f - 1b)
1206 /* 4. Clear out PIDs & Search info
1208 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1209 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1216 /* 5. Invalidate mapping we started in
1218 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1219 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1225 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
1231 /* 6. Setup KERNELBASE mapping in TLB[0]
1233 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1234 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1237 rlwinm r3,r3,0,16,3 /* clear ESEL */
1239 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1240 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1243 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED)
1247 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1254 /* 7. Jump to KERNELBASE mapping
1256 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1258 /* Now we branch the new virtual address mapped by this entry */
1259 bl 1f /* Find our address */
1261 addi r6,r6,(2f - 1b)
1264 ori r7,r7,MSR_KERNEL@l
1267 rfi /* start execution out of TLB1[0] entry */
1270 /* 8. Clear out the temp mapping
1272 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1277 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
1283 /* We translate LR and return */
1289 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1290 * kernel linear mapping. We also set MAS8 once for all here though
1291 * that will have to be made dependent on whether we are running under
1292 * a hypervisor I suppose.
1296 * This code is called as an ordinary function on the boot CPU. But to
1297 * avoid duplication, this code is also used in SCOM bringup of
1298 * secondary CPUs. We read the code between the initial_tlb_code_start
1299 * and initial_tlb_code_end labels one instruction at a time and RAM it
1300 * into the new core via SCOM. That doesn't process branches, so there
1301 * must be none between those two labels. It also means if this code
1302 * ever takes any parameters, the SCOM code must also be updated to
1305 .globl a2_tlbinit_code_start
1306 a2_tlbinit_code_start:
1308 ori r11,r3,MAS0_WQ_ALLWAYS
1309 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1311 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1312 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1314 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1316 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1317 mtspr SPRN_MAS7_MAS3,r3
1321 /* Write the TLB entry */
1324 .globl a2_tlbinit_after_linear_map
1325 a2_tlbinit_after_linear_map:
1327 /* Now we branch the new virtual address mapped by this entry */
1328 #ifdef CONFIG_RELOCATABLE
1332 LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
1337 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1338 * else (including IPROTed things left by firmware)
1340 * r3 = current address (more or less)
1347 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1348 rlwinm r10,r4,8,0xff
1349 addi r10,r10,-1 /* Get inner loop mask */
1354 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1357 rldicr r6,r6,0,51 /* Extract EPN */
1360 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1362 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1367 rlwimi r7,r4,16,MAS0_ESEL_MASK
1378 addis r6,r6,(1<<30)@h
1383 .globl a2_tlbinit_after_iprot_flush
1384 a2_tlbinit_after_iprot_flush:
1390 .globl a2_tlbinit_code_end
1391 a2_tlbinit_code_end:
1393 /* We translate LR and return */
1400 * Main entry (boot CPU, thread 0)
1402 * We enter here from head_64.S, possibly after the prom_init trampoline
1403 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1404 * mode. Anything else is as it was left by the bootloader
1406 * Initial requirements of this port:
1408 * - Kernel loaded at 0 physical
1409 * - A good lump of memory mapped 0:0 by UTLB entry 0
1410 * - MSR:IS & MSR:DS set to 0
1412 * Note that some of the above requirements will be relaxed in the future
1413 * as the kernel becomes smarter at dealing with different initial conditions
1414 * but for now you have to be careful
1416 _GLOBAL(start_initialization_book3e)
1419 /* First, we need to setup some initial TLBs to map the kernel
1420 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1421 * and always use AS 0, so we just set it up to match our link
1422 * address and never use 0 based addresses.
1424 bl initial_tlb_book3e
1426 /* Init global core bits */
1429 /* Init per-thread bits */
1430 bl init_thread_book3e
1432 /* Return to common init code */
1439 * Secondary core/processor entry
1441 * This is entered for thread 0 of a secondary core, all other threads
1442 * are expected to be stopped. It's similar to start_initialization_book3e
1443 * except that it's generally entered from the holding loop in head_64.S
1444 * after CPUs have been gathered by Open Firmware.
1446 * We assume we are in 32 bits mode running with whatever TLB entry was
1447 * set for us by the firmware or POR engine.
1449 _GLOBAL(book3e_secondary_core_init_tlb_set)
1451 b generic_secondary_smp_init
1453 _GLOBAL(book3e_secondary_core_init)
1456 /* Do we need to setup initial TLB entry ? */
1460 /* Setup TLB for this core */
1461 bl initial_tlb_book3e
1463 /* We can return from the above running at a different
1464 * address, so recalculate r2 (TOC)
1468 /* Init global core bits */
1469 2: bl init_core_book3e
1471 /* Init per-thread bits */
1472 3: bl init_thread_book3e
1474 /* Return to common init code at proper virtual address.
1476 * Due to various previous assumptions, we know we entered this
1477 * function at either the final PAGE_OFFSET mapping or using a
1478 * 1:1 mapping at 0, so we don't bother doing a complicated check
1479 * here, we just ensure the return address has the right top bits.
1481 * Note that if we ever want to be smarter about where we can be
1482 * started from, we have to be careful that by the time we reach
1483 * the code below we may already be running at a different location
1484 * than the one we were called from since initial_tlb_book3e can
1485 * have moved us already.
1489 lis r3,PAGE_OFFSET@highest
1495 _GLOBAL(book3e_secondary_thread_init)
1499 .globl init_core_book3e
1501 /* Establish the interrupt vector base */
1503 LOAD_REG_ADDR(r3, interrupt_base_book3e)
1509 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1512 /* Make sure interrupts are off */
1515 /* disable all timers and clear out status */
1523 _GLOBAL(__setup_base_ivors)
1524 SET_IVOR(0, 0x020) /* Critical Input */
1525 SET_IVOR(1, 0x000) /* Machine Check */
1526 SET_IVOR(2, 0x060) /* Data Storage */
1527 SET_IVOR(3, 0x080) /* Instruction Storage */
1528 SET_IVOR(4, 0x0a0) /* External Input */
1529 SET_IVOR(5, 0x0c0) /* Alignment */
1530 SET_IVOR(6, 0x0e0) /* Program */
1531 SET_IVOR(7, 0x100) /* FP Unavailable */
1532 SET_IVOR(8, 0x120) /* System Call */
1533 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1534 SET_IVOR(10, 0x160) /* Decrementer */
1535 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1536 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1537 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1538 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1539 SET_IVOR(15, 0x040) /* Debug */
1545 _GLOBAL(setup_altivec_ivors)
1546 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1547 SET_IVOR(33, 0x220) /* AltiVec Assist */
1550 _GLOBAL(setup_perfmon_ivor)
1551 SET_IVOR(35, 0x260) /* Performance Monitor */
1554 _GLOBAL(setup_doorbell_ivors)
1555 SET_IVOR(36, 0x280) /* Processor Doorbell */
1556 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1559 _GLOBAL(setup_ehv_ivors)
1560 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1561 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1562 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1563 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1566 _GLOBAL(setup_lrat_ivor)
1567 SET_IVOR(42, 0x340) /* LRAT Error */