1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Boot code and exception vectors for Book3E processors
5 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
8 #include <linux/threads.h>
11 #include <asm/ppc_asm.h>
12 #include <asm/asm-offsets.h>
13 #include <asm/cputable.h>
14 #include <asm/setup.h>
15 #include <asm/thread_info.h>
16 #include <asm/reg_a2.h>
17 #include <asm/exception-64e.h>
19 #include <asm/irqflags.h>
20 #include <asm/ptrace.h>
21 #include <asm/ppc-opcode.h>
23 #include <asm/hw_irq.h>
24 #include <asm/kvm_asm.h>
25 #include <asm/kvm_booke_hv_asm.h>
26 #include <asm/feature-fixups.h>
27 #include <asm/context_tracking.h>
29 /* XXX This will ultimately add space for a special exception save
30 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
31 * when taking special interrupts. For now we don't support that,
32 * special interrupts from within a non-standard level will probably
35 #define SPECIAL_EXC_SRR0 0
36 #define SPECIAL_EXC_SRR1 1
37 #define SPECIAL_EXC_SPRG_GEN 2
38 #define SPECIAL_EXC_SPRG_TLB 3
39 #define SPECIAL_EXC_MAS0 4
40 #define SPECIAL_EXC_MAS1 5
41 #define SPECIAL_EXC_MAS2 6
42 #define SPECIAL_EXC_MAS3 7
43 #define SPECIAL_EXC_MAS6 8
44 #define SPECIAL_EXC_MAS7 9
45 #define SPECIAL_EXC_MAS5 10 /* E.HV only */
46 #define SPECIAL_EXC_MAS8 11 /* E.HV only */
47 #define SPECIAL_EXC_IRQHAPPENED 12
48 #define SPECIAL_EXC_DEAR 13
49 #define SPECIAL_EXC_ESR 14
50 #define SPECIAL_EXC_SOFTE 15
51 #define SPECIAL_EXC_CSRR0 16
52 #define SPECIAL_EXC_CSRR1 17
53 /* must be even to keep 16-byte stack alignment */
54 #define SPECIAL_EXC_END 18
56 #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
57 #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288)
59 #define SPECIAL_EXC_STORE(reg, name) \
60 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
62 #define SPECIAL_EXC_LOAD(reg, name) \
63 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
66 lbz r9,PACAIRQHAPPENED(r13)
67 RECONCILE_IRQ_STATE(r3,r4)
70 * We only need (or have stack space) to save this stuff if
71 * we interrupted the kernel.
78 * Advance to the next TLB exception frame for handler
79 * types that don't do it automatically.
81 LOAD_REG_ADDR(r11,extlb_level_exc)
83 mfspr r10,SPRN_SPRG_TLB_EXFRAME
85 mtspr SPRN_SPRG_TLB_EXFRAME,r10
88 * Save registers needed to allow nesting of certain exceptions
89 * (such as TLB misses) inside special exception levels
92 SPECIAL_EXC_STORE(r10,SRR0)
94 SPECIAL_EXC_STORE(r10,SRR1)
95 mfspr r10,SPRN_SPRG_GEN_SCRATCH
96 SPECIAL_EXC_STORE(r10,SPRG_GEN)
97 mfspr r10,SPRN_SPRG_TLB_SCRATCH
98 SPECIAL_EXC_STORE(r10,SPRG_TLB)
100 SPECIAL_EXC_STORE(r10,MAS0)
102 SPECIAL_EXC_STORE(r10,MAS1)
104 SPECIAL_EXC_STORE(r10,MAS2)
106 SPECIAL_EXC_STORE(r10,MAS3)
108 SPECIAL_EXC_STORE(r10,MAS6)
110 SPECIAL_EXC_STORE(r10,MAS7)
113 SPECIAL_EXC_STORE(r10,MAS5)
115 SPECIAL_EXC_STORE(r10,MAS8)
117 /* MAS5/8 could have inappropriate values if we interrupted KVM code */
121 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
122 SPECIAL_EXC_STORE(r9,IRQHAPPENED)
125 SPECIAL_EXC_STORE(r10,DEAR)
127 SPECIAL_EXC_STORE(r10,ESR)
129 lbz r10,PACAIRQSOFTMASK(r13)
130 SPECIAL_EXC_STORE(r10,SOFTE)
132 SPECIAL_EXC_STORE(r10,CSRR0)
134 SPECIAL_EXC_STORE(r10,CSRR1)
138 ret_from_level_except:
145 LOAD_REG_ADDR(r11,extlb_level_exc)
147 mfspr r10,SPRN_SPRG_TLB_EXFRAME
149 mtspr SPRN_SPRG_TLB_EXFRAME,r10
152 * It's possible that the special level exception interrupted a
153 * TLB miss handler, and inserted the same entry that the
154 * interrupted handler was about to insert. On CPUs without TLB
155 * write conditional, this can result in a duplicate TLB entry.
156 * Wipe all non-bolted entries to be safe.
158 * Note that this doesn't protect against any TLB misses
159 * we may take accessing the stack from here to the end of
160 * the special level exception. It's not clear how we can
161 * reasonably protect against that, but only CPUs with
162 * neither TLB write conditional nor bolted kernel memory
163 * are affected. Do any such CPUs even exist?
169 SPECIAL_EXC_LOAD(r10,SRR0)
171 SPECIAL_EXC_LOAD(r10,SRR1)
173 SPECIAL_EXC_LOAD(r10,SPRG_GEN)
174 mtspr SPRN_SPRG_GEN_SCRATCH,r10
175 SPECIAL_EXC_LOAD(r10,SPRG_TLB)
176 mtspr SPRN_SPRG_TLB_SCRATCH,r10
177 SPECIAL_EXC_LOAD(r10,MAS0)
179 SPECIAL_EXC_LOAD(r10,MAS1)
181 SPECIAL_EXC_LOAD(r10,MAS2)
183 SPECIAL_EXC_LOAD(r10,MAS3)
185 SPECIAL_EXC_LOAD(r10,MAS6)
187 SPECIAL_EXC_LOAD(r10,MAS7)
190 SPECIAL_EXC_LOAD(r10,MAS5)
192 SPECIAL_EXC_LOAD(r10,MAS8)
194 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
196 lbz r6,PACAIRQSOFTMASK(r13)
199 /* Interrupts had better not already be enabled... */
200 tweqi r6,IRQS_ENABLED
202 andi. r6,r5,IRQS_DISABLED
206 stb r5,PACAIRQSOFTMASK(r13)
209 * Restore PACAIRQHAPPENED rather than setting it based on
210 * the return MSR[EE], since we could have interrupted
211 * __check_irq_replay() or other inconsistent transitory
212 * states that must remain that way.
214 SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
215 stb r10,PACAIRQHAPPENED(r13)
217 SPECIAL_EXC_LOAD(r10,DEAR)
219 SPECIAL_EXC_LOAD(r10,ESR)
222 stdcx. r0,0,r1 /* to clear the reservation */
234 .macro ret_from_level srr0 srr1 paca_ex scratch
235 bl ret_from_level_except
248 std r10,\paca_ex+EX_R10(r13);
249 std r11,\paca_ex+EX_R11(r13);
256 ld r10,\paca_ex+EX_R10(r13)
257 ld r11,\paca_ex+EX_R11(r13)
261 ret_from_crit_except:
262 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
266 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
269 /* Exception prolog code for all exceptions */
270 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
271 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
272 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
273 std r10,PACA_EX##type+EX_R10(r13); \
274 std r11,PACA_EX##type+EX_R11(r13); \
275 mfcr r10; /* save CR */ \
276 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
277 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
278 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
279 addition; /* additional code for that exc. */ \
280 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
281 type##_SET_KSTACK; /* get special stack if necessary */\
282 andi. r10,r11,MSR_PR; /* save stack pointer */ \
283 beq 1f; /* branch around if supervisor */ \
284 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
285 1: type##_BTB_FLUSH \
286 cmpdi cr1,r1,0; /* check if SP makes sense */ \
287 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
288 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
290 /* Exception type-specific macros */
291 #define GEN_SET_KSTACK \
292 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
293 #define SPRN_GEN_SRR0 SPRN_SRR0
294 #define SPRN_GEN_SRR1 SPRN_SRR1
296 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
297 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
298 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
300 #define CRIT_SET_KSTACK \
301 ld r1,PACA_CRIT_STACK(r13); \
302 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
303 #define SPRN_CRIT_SRR0 SPRN_CSRR0
304 #define SPRN_CRIT_SRR1 SPRN_CSRR1
306 #define DBG_SET_KSTACK \
307 ld r1,PACA_DBG_STACK(r13); \
308 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
309 #define SPRN_DBG_SRR0 SPRN_DSRR0
310 #define SPRN_DBG_SRR1 SPRN_DSRR1
312 #define MC_SET_KSTACK \
313 ld r1,PACA_MC_STACK(r13); \
314 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
315 #define SPRN_MC_SRR0 SPRN_MCSRR0
316 #define SPRN_MC_SRR1 SPRN_MCSRR1
318 #ifdef CONFIG_PPC_FSL_BOOK3E
319 #define GEN_BTB_FLUSH \
320 START_BTB_FLUSH_SECTION \
324 END_BTB_FLUSH_SECTION
326 #define CRIT_BTB_FLUSH \
327 START_BTB_FLUSH_SECTION \
329 END_BTB_FLUSH_SECTION
331 #define DBG_BTB_FLUSH CRIT_BTB_FLUSH
332 #define MC_BTB_FLUSH CRIT_BTB_FLUSH
333 #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
335 #define GEN_BTB_FLUSH
336 #define CRIT_BTB_FLUSH
337 #define DBG_BTB_FLUSH
339 #define GDBELL_BTB_FLUSH
342 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
343 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
345 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
346 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
348 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
349 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
351 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
352 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
354 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
355 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
357 /* Variants of the "addition" argument for the prolog
359 #define PROLOG_ADDITION_NONE_GEN(n)
360 #define PROLOG_ADDITION_NONE_GDBELL(n)
361 #define PROLOG_ADDITION_NONE_CRIT(n)
362 #define PROLOG_ADDITION_NONE_DBG(n)
363 #define PROLOG_ADDITION_NONE_MC(n)
365 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
366 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \
367 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
368 bne masked_interrupt_book3e_##n
370 #define PROLOG_ADDITION_2REGS_GEN(n) \
371 std r14,PACA_EXGEN+EX_R14(r13); \
372 std r15,PACA_EXGEN+EX_R15(r13)
374 #define PROLOG_ADDITION_1REG_GEN(n) \
375 std r14,PACA_EXGEN+EX_R14(r13);
377 #define PROLOG_ADDITION_2REGS_CRIT(n) \
378 std r14,PACA_EXCRIT+EX_R14(r13); \
379 std r15,PACA_EXCRIT+EX_R15(r13)
381 #define PROLOG_ADDITION_2REGS_DBG(n) \
382 std r14,PACA_EXDBG+EX_R14(r13); \
383 std r15,PACA_EXDBG+EX_R15(r13)
385 #define PROLOG_ADDITION_2REGS_MC(n) \
386 std r14,PACA_EXMC+EX_R14(r13); \
387 std r15,PACA_EXMC+EX_R15(r13)
390 /* Core exception code for all exceptions except TLB misses. */
391 #define EXCEPTION_COMMON_LVL(n, scratch, excf) \
393 std r0,GPR0(r1); /* save r0 in stackframe */ \
394 std r2,GPR2(r1); /* save r2 in stackframe */ \
395 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
396 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
397 std r9,GPR9(r1); /* save r9 in stackframe */ \
398 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
399 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
400 beq 2f; /* if from kernel mode */ \
401 ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */ \
402 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
403 ld r4,excf+EX_R11(r13); /* get back r11 */ \
404 mfspr r5,scratch; /* get back r13 */ \
405 std r12,GPR12(r1); /* save r12 in stackframe */ \
406 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
407 mflr r6; /* save LR in stackframe */ \
408 mfctr r7; /* save CTR in stackframe */ \
409 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
410 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
411 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
412 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \
413 ld r12,exception_marker@toc(r2); \
415 std r3,GPR10(r1); /* save r10 to stackframe */ \
416 std r4,GPR11(r1); /* save r11 to stackframe */ \
417 std r5,GPR13(r1); /* save it to stackframe */ \
421 li r3,(n)+1; /* indicate partial regs in trap */ \
422 std r9,0(r1); /* store stack frame back link */ \
423 std r10,_CCR(r1); /* store orig CR in stackframe */ \
424 std r9,GPR1(r1); /* store stack frame back link */ \
425 std r11,SOFTE(r1); /* and save it to stackframe */ \
426 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
427 std r3,_TRAP(r1); /* set trap number */ \
428 std r0,RESULT(r1); /* clear regs->result */
430 #define EXCEPTION_COMMON(n) \
431 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
432 #define EXCEPTION_COMMON_CRIT(n) \
433 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
434 #define EXCEPTION_COMMON_MC(n) \
435 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
436 #define EXCEPTION_COMMON_DBG(n) \
437 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
440 * This is meant for exceptions that don't immediately hard-enable. We
441 * set a bit in paca->irq_happened to ensure that a subsequent call to
442 * arch_local_irq_restore() will properly hard-enable and avoid the
443 * fast-path, and then reconcile irq state.
445 #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4)
448 * This is called by exceptions that don't use INTS_DISABLE (that did not
449 * touch irq indicators in the PACA). This will restore MSR:EE to it's
452 * XXX In the long run, we may want to open-code it in order to separate the
453 * load from the wrtee, thus limiting the latency caused by the dependency
454 * but at this point, I'll favor code clarity until we have a near to final
457 #define INTS_RESTORE_HARD \
461 /* XXX FIXME: Restore r14/r15 when necessary */
462 #define BAD_STACK_TRAMPOLINE(n) \
463 exc_##n##_bad_stack: \
464 li r1,(n); /* get exception number */ \
465 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
466 b bad_stack_book3e; /* bad stack error */
468 /* WARNING: If you change the layout of this stub, make sure you check
469 * the debug exception handler which handles single stepping
470 * into exceptions from userspace, and the MM code in
471 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
472 * and would need to be updated if that branch is moved
474 #define EXCEPTION_STUB(loc, label) \
475 . = interrupt_base_book3e + loc; \
476 nop; /* To make debug interrupts happy */ \
477 b exc_##label##_book3e;
487 /* Used by asynchronous interrupt that may happen in the idle loop.
489 * This check if the thread was in the idle loop, and if yes, returns
490 * to the caller rather than the PC. This is to avoid a race if
491 * interrupts happen before the wait instruction.
493 #define CHECK_NAPPING() \
494 ld r11, PACA_THREAD_INFO(r13); \
495 ld r10,TI_LOCAL_FLAGS(r11); \
496 andi. r9,r10,_TLF_NAPPING; \
499 rlwinm r7,r10,0,~_TLF_NAPPING; \
501 std r7,TI_LOCAL_FLAGS(r11); \
505 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
506 START_EXCEPTION(label); \
507 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
508 EXCEPTION_COMMON(trapnum) \
512 addi r3,r1,STACK_FRAME_OVERHEAD; \
514 b ret_from_except_lite;
516 /* This value is used to mark exception frames on the stack. */
519 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
523 * And here we have the exception vectors !
528 .globl interrupt_base_book3e
529 interrupt_base_book3e: /* fake trap */
530 EXCEPTION_STUB(0x000, machine_check)
531 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */
532 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
533 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
534 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
535 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
536 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
537 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
538 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
539 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
540 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
541 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
542 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
543 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
544 EXCEPTION_STUB(0x1c0, data_tlb_miss)
545 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
546 EXCEPTION_STUB(0x200, altivec_unavailable)
547 EXCEPTION_STUB(0x220, altivec_assist)
548 EXCEPTION_STUB(0x260, perfmon)
549 EXCEPTION_STUB(0x280, doorbell)
550 EXCEPTION_STUB(0x2a0, doorbell_crit)
551 EXCEPTION_STUB(0x2c0, guest_doorbell)
552 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
553 EXCEPTION_STUB(0x300, hypercall)
554 EXCEPTION_STUB(0x320, ehpriv)
555 EXCEPTION_STUB(0x340, lrat_error)
557 .globl __end_interrupts
560 /* Critical Input Interrupt */
561 START_EXCEPTION(critical_input);
562 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
563 PROLOG_ADDITION_NONE)
564 EXCEPTION_COMMON_CRIT(0x100)
568 addi r3,r1,STACK_FRAME_OVERHEAD
570 b ret_from_crit_except
572 /* Machine Check Interrupt */
573 START_EXCEPTION(machine_check);
574 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
575 PROLOG_ADDITION_NONE)
576 EXCEPTION_COMMON_MC(0x000)
580 addi r3,r1,STACK_FRAME_OVERHEAD
581 bl machine_check_exception
584 /* Data Storage Interrupt */
585 START_EXCEPTION(data_storage)
586 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
587 PROLOG_ADDITION_2REGS)
590 EXCEPTION_COMMON(0x300)
592 b storage_fault_common
594 /* Instruction Storage Interrupt */
595 START_EXCEPTION(instruction_storage);
596 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
597 PROLOG_ADDITION_2REGS)
600 EXCEPTION_COMMON(0x400)
602 b storage_fault_common
604 /* External Input Interrupt */
605 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
606 external_input, do_IRQ, ACK_NONE)
609 START_EXCEPTION(alignment);
610 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
611 PROLOG_ADDITION_2REGS)
614 EXCEPTION_COMMON(0x600)
615 b alignment_more /* no room, go out of line */
617 /* Program Interrupt */
618 START_EXCEPTION(program);
619 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
620 PROLOG_ADDITION_1REG)
622 EXCEPTION_COMMON(0x700)
625 addi r3,r1,STACK_FRAME_OVERHEAD
626 ld r14,PACA_EXGEN+EX_R14(r13)
628 bl program_check_exception
631 /* Floating Point Unavailable Interrupt */
632 START_EXCEPTION(fp_unavailable);
633 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
634 PROLOG_ADDITION_NONE)
635 /* we can probably do a shorter exception entry for that one... */
636 EXCEPTION_COMMON(0x800)
641 b fast_exception_return
644 addi r3,r1,STACK_FRAME_OVERHEAD
645 bl kernel_fp_unavailable_exception
648 /* Altivec Unavailable Interrupt */
649 START_EXCEPTION(altivec_unavailable);
650 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
651 PROLOG_ADDITION_NONE)
652 /* we can probably do a shorter exception entry for that one... */
653 EXCEPTION_COMMON(0x200)
654 #ifdef CONFIG_ALTIVEC
660 b fast_exception_return
662 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
666 addi r3,r1,STACK_FRAME_OVERHEAD
667 bl altivec_unavailable_exception
671 START_EXCEPTION(altivec_assist);
672 NORMAL_EXCEPTION_PROLOG(0x220,
673 BOOKE_INTERRUPT_ALTIVEC_ASSIST,
674 PROLOG_ADDITION_NONE)
675 EXCEPTION_COMMON(0x220)
678 addi r3,r1,STACK_FRAME_OVERHEAD
679 #ifdef CONFIG_ALTIVEC
681 bl altivec_assist_exception
682 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
689 /* Decrementer Interrupt */
690 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
691 decrementer, timer_interrupt, ACK_DEC)
693 /* Fixed Interval Timer Interrupt */
694 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
695 fixed_interval, unknown_exception, ACK_FIT)
697 /* Watchdog Timer Interrupt */
698 START_EXCEPTION(watchdog);
699 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
700 PROLOG_ADDITION_NONE)
701 EXCEPTION_COMMON_CRIT(0x9f0)
705 addi r3,r1,STACK_FRAME_OVERHEAD
706 #ifdef CONFIG_BOOKE_WDT
711 b ret_from_crit_except
713 /* System Call Interrupt */
714 START_EXCEPTION(system_call)
715 mr r9,r13 /* keep a copy of userland r13 */
716 mfspr r11,SPRN_SRR0 /* get return address */
717 mfspr r12,SPRN_SRR1 /* get previous MSR */
718 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
721 /* Auxiliary Processor Unavailable Interrupt */
722 START_EXCEPTION(ap_unavailable);
723 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
724 PROLOG_ADDITION_NONE)
725 EXCEPTION_COMMON(0xf20)
728 addi r3,r1,STACK_FRAME_OVERHEAD
732 /* Debug exception as a critical interrupt*/
733 START_EXCEPTION(debug_crit);
734 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
735 PROLOG_ADDITION_2REGS)
738 * If there is a single step or branch-taken exception in an
739 * exception entry sequence, it was probably meant to apply to
740 * the code where the exception occurred (since exception entry
741 * doesn't turn off DE automatically). We simulate the effect
742 * of turning off DE on entry to an exception handler by turning
743 * off DE in the CSRR1 value and clearing the debug status.
746 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
747 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
750 #ifdef CONFIG_RELOCATABLE
752 ld r14,interrupt_base_book3e@got(r15)
753 ld r15,__end_interrupts@got(r15)
757 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
759 LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
765 /* here it looks like we got an inappropriate debug exception. */
766 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
767 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
770 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
771 ld r1,PACA_EXCRIT+EX_R1(r13)
772 ld r14,PACA_EXCRIT+EX_R14(r13)
773 ld r15,PACA_EXCRIT+EX_R15(r13)
775 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
776 ld r11,PACA_EXCRIT+EX_R11(r13)
777 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
780 /* Normal debug exception */
781 /* XXX We only handle coming from userspace for now since we can't
782 * quite save properly an interrupted kernel state yet
784 1: andi. r14,r11,MSR_PR; /* check for userspace again */
785 beq kernel_dbg_exc; /* if from kernel mode */
787 /* Now we mash up things to make it look like we are coming on a
791 EXCEPTION_COMMON_CRIT(0xd00)
793 addi r3,r1,STACK_FRAME_OVERHEAD
795 ld r14,PACA_EXCRIT+EX_R14(r13)
796 ld r15,PACA_EXCRIT+EX_R15(r13)
804 /* Debug exception as a debug interrupt*/
805 START_EXCEPTION(debug_debug);
806 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
807 PROLOG_ADDITION_2REGS)
810 * If there is a single step or branch-taken exception in an
811 * exception entry sequence, it was probably meant to apply to
812 * the code where the exception occurred (since exception entry
813 * doesn't turn off DE automatically). We simulate the effect
814 * of turning off DE on entry to an exception handler by turning
815 * off DE in the DSRR1 value and clearing the debug status.
818 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
819 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
822 #ifdef CONFIG_RELOCATABLE
824 ld r14,interrupt_base_book3e@got(r15)
825 ld r15,__end_interrupts@got(r15)
829 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
831 LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
837 /* here it looks like we got an inappropriate debug exception. */
838 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
839 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
842 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
843 ld r1,PACA_EXDBG+EX_R1(r13)
844 ld r14,PACA_EXDBG+EX_R14(r13)
845 ld r15,PACA_EXDBG+EX_R15(r13)
847 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
848 ld r11,PACA_EXDBG+EX_R11(r13)
849 mfspr r13,SPRN_SPRG_DBG_SCRATCH
852 /* Normal debug exception */
853 /* XXX We only handle coming from userspace for now since we can't
854 * quite save properly an interrupted kernel state yet
856 1: andi. r14,r11,MSR_PR; /* check for userspace again */
857 beq kernel_dbg_exc; /* if from kernel mode */
859 /* Now we mash up things to make it look like we are coming on a
863 EXCEPTION_COMMON_DBG(0xd08)
866 addi r3,r1,STACK_FRAME_OVERHEAD
868 ld r14,PACA_EXDBG+EX_R14(r13)
869 ld r15,PACA_EXDBG+EX_R15(r13)
874 START_EXCEPTION(perfmon);
875 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
876 PROLOG_ADDITION_NONE)
877 EXCEPTION_COMMON(0x260)
880 addi r3,r1,STACK_FRAME_OVERHEAD
881 bl performance_monitor_exception
882 b ret_from_except_lite
884 /* Doorbell interrupt */
885 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
886 doorbell, doorbell_exception, ACK_NONE)
888 /* Doorbell critical Interrupt */
889 START_EXCEPTION(doorbell_crit);
890 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
891 PROLOG_ADDITION_NONE)
892 EXCEPTION_COMMON_CRIT(0x2a0)
896 addi r3,r1,STACK_FRAME_OVERHEAD
898 b ret_from_crit_except
901 * Guest doorbell interrupt
902 * This general exception use GSRRx save/restore registers
904 START_EXCEPTION(guest_doorbell);
905 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
906 PROLOG_ADDITION_NONE)
907 EXCEPTION_COMMON(0x2c0)
908 addi r3,r1,STACK_FRAME_OVERHEAD
914 /* Guest Doorbell critical Interrupt */
915 START_EXCEPTION(guest_doorbell_crit);
916 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
917 PROLOG_ADDITION_NONE)
918 EXCEPTION_COMMON_CRIT(0x2e0)
922 addi r3,r1,STACK_FRAME_OVERHEAD
924 b ret_from_crit_except
926 /* Hypervisor call */
927 START_EXCEPTION(hypercall);
928 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
929 PROLOG_ADDITION_NONE)
930 EXCEPTION_COMMON(0x310)
931 addi r3,r1,STACK_FRAME_OVERHEAD
937 /* Embedded Hypervisor priviledged */
938 START_EXCEPTION(ehpriv);
939 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
940 PROLOG_ADDITION_NONE)
941 EXCEPTION_COMMON(0x320)
942 addi r3,r1,STACK_FRAME_OVERHEAD
948 /* LRAT Error interrupt */
949 START_EXCEPTION(lrat_error);
950 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
951 PROLOG_ADDITION_NONE)
952 EXCEPTION_COMMON(0x340)
953 addi r3,r1,STACK_FRAME_OVERHEAD
960 * An interrupt came in while soft-disabled; We mark paca->irq_happened
961 * accordingly and if the interrupt is level sensitive, we hard disable
962 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
963 * keep these in synch.
966 .macro masked_interrupt_book3e paca_irq full_mask
967 lbz r10,PACAIRQHAPPENED(r13)
969 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
971 ori r10,r10,\paca_irq
973 stb r10,PACAIRQHAPPENED(r13)
976 rldicl r10,r11,48,1 /* clear MSR_EE */
981 lwz r11,PACA_EXGEN+EX_CR(r13)
983 ld r10,PACA_EXGEN+EX_R10(r13)
984 ld r11,PACA_EXGEN+EX_R11(r13)
985 mfspr r13,SPRN_SPRG_GEN_SCRATCH
990 masked_interrupt_book3e_0x500:
991 masked_interrupt_book3e PACA_IRQ_EE 1
993 masked_interrupt_book3e_0x900:
995 masked_interrupt_book3e PACA_IRQ_DEC 0
997 masked_interrupt_book3e_0x980:
999 masked_interrupt_book3e PACA_IRQ_DEC 0
1001 masked_interrupt_book3e_0x280:
1002 masked_interrupt_book3e_0x2c0:
1003 masked_interrupt_book3e PACA_IRQ_DBELL 0
1006 * This is called from 0x300 and 0x400 handlers after the prologs with
1007 * r14 and r15 containing the fault address and error code, with the
1008 * original values stashed away in the PACA
1010 storage_fault_common:
1013 addi r3,r1,STACK_FRAME_OVERHEAD
1014 ld r14,PACA_EXGEN+EX_R14(r13)
1015 ld r15,PACA_EXGEN+EX_R15(r13)
1019 b ret_from_except_lite
1022 addi r3,r1,STACK_FRAME_OVERHEAD
1028 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1034 addi r3,r1,STACK_FRAME_OVERHEAD
1035 ld r14,PACA_EXGEN+EX_R14(r13)
1036 ld r15,PACA_EXGEN+EX_R15(r13)
1039 bl alignment_exception
1043 _GLOBAL(ret_from_except)
1046 bne ret_from_except_lite
1049 _GLOBAL(ret_from_except_lite)
1051 * Disable interrupts so that current_thread_info()->flags
1052 * can't change between when we test it and when we return
1053 * from the interrupt.
1057 ld r9, PACA_THREAD_INFO(r13)
1059 ld r10,PACACURRENT(r13)
1063 lwz r3,(THREAD+THREAD_DBCR0)(r10)
1065 /* Check current_thread_info()->flags */
1066 andi. r0,r4,_TIF_USER_WORK_MASK
1069 * Check to see if the dbcr0 register is set up to debug.
1070 * Use the internal debug mode bit to do this.
1072 andis. r0,r3,DBCR0_IDM@h
1075 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
1081 1: andi. r0,r4,_TIF_NEED_RESCHED
1083 bl restore_interrupts
1085 b ret_from_except_lite
1089 * Use a non volatile GPR to save and restore our thread_info flags
1090 * across the call to restore_interrupts.
1093 bl restore_interrupts
1095 addi r3,r1,STACK_FRAME_OVERHEAD
1100 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
1101 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
1104 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
1107 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
1108 mr r4,r1 /* src: current exception frame */
1109 mr r1,r3 /* Reroute the trampoline frame to r1 */
1111 /* Copy from the original to the trampoline. */
1112 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
1113 li r6,0 /* start offset: 0 */
1120 /* Do real store operation to complete stdu */
1124 /* Clear _TIF_EMULATE_STACK_STORE flag */
1125 lis r11,_TIF_EMULATE_STACK_STORE@h
1133 #ifdef CONFIG_PREEMPT
1134 /* Check if we need to preempt */
1135 andi. r0,r4,_TIF_NEED_RESCHED
1137 /* Check that preempt_count() == 0 and interrupts are enabled */
1138 lwz r8,TI_PREEMPT(r9)
1142 andi. r0,r0,IRQS_DISABLED
1146 * Here we are preempting the current task. We want to make
1147 * sure we are soft-disabled first and reconcile irq state.
1149 RECONCILE_IRQ_STATE(r3,r4)
1150 bl preempt_schedule_irq
1153 * arch_local_irq_restore() from preempt_schedule_irq above may
1154 * enable hard interrupt but we really should disable interrupts
1155 * when we return from the interrupt, and so that we don't get
1156 * interrupted after loading SRR0/1.
1159 #endif /* CONFIG_PREEMPT */
1163 * This is the main kernel exit path. First we check if we
1164 * are about to re-enable interrupts
1167 lbz r6,PACAIRQSOFTMASK(r13)
1168 andi. r5,r5,IRQS_DISABLED
1169 bne .Lrestore_irq_off
1171 /* We are enabling, were we already enabled ? Yes, just return */
1172 andi. r6,r6,IRQS_DISABLED
1173 beq cr0,fast_exception_return
1176 * We are about to soft-enable interrupts (we are hard disabled
1177 * at this point). We check if there's anything that needs to
1178 * be replayed first.
1180 lbz r0,PACAIRQHAPPENED(r13)
1182 bne- .Lrestore_check_irq_replay
1185 * Get here when nothing happened while soft-disabled, just
1186 * soft-enable and move-on. We will hard-enable as a side
1189 .Lrestore_no_replay:
1192 stb r0,PACAIRQSOFTMASK(r13);
1194 /* This is the return from load_up_fpu fast path which could do with
1195 * less GPR restores in fact, but for now we have a single return path
1197 fast_exception_return:
1205 ACCOUNT_CPU_USER_EXIT(r13, r10, r11)
1208 1: stdcx. r0,0,r1 /* to clear the reservation */
1222 mtspr SPRN_SPRG_GEN_SCRATCH,r0
1224 std r10,PACA_EXGEN+EX_R10(r13);
1225 std r11,PACA_EXGEN+EX_R11(r13);
1232 ld r10,PACA_EXGEN+EX_R10(r13)
1233 ld r11,PACA_EXGEN+EX_R11(r13)
1234 mfspr r13,SPRN_SPRG_GEN_SCRATCH
1238 * We are returning to a context with interrupts soft disabled.
1240 * However, we may also about to hard enable, so we need to
1241 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
1242 * or that bit can get out of sync and bad things will happen
1246 lbz r7,PACAIRQHAPPENED(r13)
1249 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
1250 stb r7,PACAIRQHAPPENED(r13)
1252 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
1253 /* The interrupt should not have soft enabled. */
1254 lbz r7,PACAIRQSOFTMASK(r13)
1255 1: tdeqi r7,IRQS_ENABLED
1256 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1258 b fast_exception_return
1261 * Something did happen, check if a re-emit is needed
1262 * (this also clears paca->irq_happened)
1264 .Lrestore_check_irq_replay:
1265 /* XXX: We could implement a fast path here where we check
1266 * for irq_happened being just 0x01, in which case we can
1267 * clear it and return. That means that we would potentially
1268 * miss a decrementer having wrapped all the way around.
1270 * Still, this might be useful for things like hash_page
1272 bl __check_irq_replay
1274 beq .Lrestore_no_replay
1277 * We need to re-emit an interrupt. We do so by re-using our
1278 * existing exception frame. We first change the trap value,
1279 * but we need to ensure we preserve the low nibble of it
1287 * PACA_IRQ_HARD_DIS won't always be set here, so set it now
1288 * to reconcile the IRQ state. Tracing is already accounted for.
1290 lbz r4,PACAIRQHAPPENED(r13)
1291 ori r4,r4,PACA_IRQ_HARD_DIS
1292 stb r4,PACAIRQHAPPENED(r13)
1295 * Then find the right handler and call it. Interrupts are
1296 * still soft-disabled and we keep them that way.
1300 addi r3,r1,STACK_FRAME_OVERHEAD;
1303 1: cmpwi cr0,r3,0x900
1305 addi r3,r1,STACK_FRAME_OVERHEAD;
1308 #ifdef CONFIG_PPC_DOORBELL
1312 addi r3,r1,STACK_FRAME_OVERHEAD;
1313 bl doorbell_exception
1314 #endif /* CONFIG_PPC_DOORBELL */
1315 1: b ret_from_except /* What else to do here ? */
1317 _ASM_NOKPROBE_SYMBOL(ret_from_except);
1318 _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1319 _ASM_NOKPROBE_SYMBOL(resume_kernel);
1320 _ASM_NOKPROBE_SYMBOL(restore);
1321 _ASM_NOKPROBE_SYMBOL(fast_exception_return);
1324 * Trampolines used when spotting a bad kernel stack pointer in
1325 * the exception entry code.
1327 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1328 * index around, etc... to handle crit & mcheck
1330 BAD_STACK_TRAMPOLINE(0x000)
1331 BAD_STACK_TRAMPOLINE(0x100)
1332 BAD_STACK_TRAMPOLINE(0x200)
1333 BAD_STACK_TRAMPOLINE(0x220)
1334 BAD_STACK_TRAMPOLINE(0x260)
1335 BAD_STACK_TRAMPOLINE(0x280)
1336 BAD_STACK_TRAMPOLINE(0x2a0)
1337 BAD_STACK_TRAMPOLINE(0x2c0)
1338 BAD_STACK_TRAMPOLINE(0x2e0)
1339 BAD_STACK_TRAMPOLINE(0x300)
1340 BAD_STACK_TRAMPOLINE(0x310)
1341 BAD_STACK_TRAMPOLINE(0x320)
1342 BAD_STACK_TRAMPOLINE(0x340)
1343 BAD_STACK_TRAMPOLINE(0x400)
1344 BAD_STACK_TRAMPOLINE(0x500)
1345 BAD_STACK_TRAMPOLINE(0x600)
1346 BAD_STACK_TRAMPOLINE(0x700)
1347 BAD_STACK_TRAMPOLINE(0x800)
1348 BAD_STACK_TRAMPOLINE(0x900)
1349 BAD_STACK_TRAMPOLINE(0x980)
1350 BAD_STACK_TRAMPOLINE(0x9f0)
1351 BAD_STACK_TRAMPOLINE(0xa00)
1352 BAD_STACK_TRAMPOLINE(0xb00)
1353 BAD_STACK_TRAMPOLINE(0xc00)
1354 BAD_STACK_TRAMPOLINE(0xd00)
1355 BAD_STACK_TRAMPOLINE(0xd08)
1356 BAD_STACK_TRAMPOLINE(0xe00)
1357 BAD_STACK_TRAMPOLINE(0xf00)
1358 BAD_STACK_TRAMPOLINE(0xf20)
1360 .globl bad_stack_book3e
1362 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1363 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
1364 ld r1,PACAEMERGSP(r13)
1365 subi r1,r1,64+INT_FRAME_SIZE
1368 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1369 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1376 std r0,GPR0(r1); /* save r0 in stackframe */ \
1377 std r2,GPR2(r1); /* save r2 in stackframe */ \
1378 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
1379 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
1380 std r9,GPR9(r1); /* save r9 in stackframe */ \
1381 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
1382 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
1383 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1384 std r3,GPR10(r1); /* save r10 to stackframe */ \
1385 std r4,GPR11(r1); /* save r11 to stackframe */ \
1386 std r12,GPR12(r1); /* save r12 in stackframe */ \
1387 std r5,GPR13(r1); /* save it to stackframe */ \
1396 lhz r12,PACA_TRAP_SAVE(r13)
1398 addi r11,r1,INT_FRAME_SIZE
1403 1: addi r3,r1,STACK_FRAME_OVERHEAD
1408 * Setup the initial TLB for a core. This current implementation
1409 * assume that whatever we are running off will not conflict with
1410 * the new mapping at PAGE_OFFSET.
1412 _GLOBAL(initial_tlb_book3e)
1414 /* Look for the first TLB with IPROT set */
1415 mfspr r4,SPRN_TLB0CFG
1416 andi. r3,r4,TLBnCFG_IPROT
1417 lis r3,MAS0_TLBSEL(0)@h
1420 mfspr r4,SPRN_TLB1CFG
1421 andi. r3,r4,TLBnCFG_IPROT
1422 lis r3,MAS0_TLBSEL(1)@h
1425 mfspr r4,SPRN_TLB2CFG
1426 andi. r3,r4,TLBnCFG_IPROT
1427 lis r3,MAS0_TLBSEL(2)@h
1430 lis r3,MAS0_TLBSEL(3)@h
1431 mfspr r4,SPRN_TLB3CFG
1435 andi. r5,r4,TLBnCFG_HES
1438 mflr r8 /* save LR */
1439 /* 1. Find the index of the entry we're executing in
1441 * r3 = MAS0_TLBSEL (for the iprot array)
1444 bl invstr /* Find our address */
1445 invstr: mflr r6 /* Make it accessible */
1447 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
1452 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
1455 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
1457 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
1458 oris r7,r7,MAS1_IPROT@h
1462 /* 2. Invalidate all entries except the entry we're executing in
1464 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1466 * r5 = ESEL of entry we are running in
1468 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
1469 li r6,0 /* Set Entry counter to 0 */
1470 1: mr r7,r3 /* Set MAS0(TLBSEL) */
1471 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1475 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
1477 beq skpinv /* Dont update the current execution TLB */
1481 skpinv: addi r6,r6,1 /* Increment */
1482 cmpw r6,r4 /* Are we done? */
1483 bne 1b /* If not, repeat */
1485 /* Invalidate all TLBs */
1486 PPC_TLBILX_ALL(0,R0)
1490 /* 3. Setup a temp mapping and jump to it
1492 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1493 * r5 = ESEL of entry we are running in
1495 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
1497 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
1501 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
1505 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
1513 bl 1f /* Find our address */
1515 addi r6,r6,(2f - 1b)
1520 /* 4. Clear out PIDs & Search info
1522 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1523 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1530 /* 5. Invalidate mapping we started in
1532 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1533 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1539 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
1545 /* 6. Setup KERNELBASE mapping in TLB[0]
1547 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1548 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1551 rlwinm r3,r3,0,16,3 /* clear ESEL */
1553 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1554 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1557 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED)
1561 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1568 /* 7. Jump to KERNELBASE mapping
1570 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1572 /* Now we branch the new virtual address mapped by this entry */
1573 bl 1f /* Find our address */
1575 addi r6,r6,(2f - 1b)
1578 ori r7,r7,MSR_KERNEL@l
1581 rfi /* start execution out of TLB1[0] entry */
1584 /* 8. Clear out the temp mapping
1586 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1591 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
1597 /* We translate LR and return */
1603 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1604 * kernel linear mapping. We also set MAS8 once for all here though
1605 * that will have to be made dependent on whether we are running under
1606 * a hypervisor I suppose.
1610 * This code is called as an ordinary function on the boot CPU. But to
1611 * avoid duplication, this code is also used in SCOM bringup of
1612 * secondary CPUs. We read the code between the initial_tlb_code_start
1613 * and initial_tlb_code_end labels one instruction at a time and RAM it
1614 * into the new core via SCOM. That doesn't process branches, so there
1615 * must be none between those two labels. It also means if this code
1616 * ever takes any parameters, the SCOM code must also be updated to
1619 .globl a2_tlbinit_code_start
1620 a2_tlbinit_code_start:
1622 ori r11,r3,MAS0_WQ_ALLWAYS
1623 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1625 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1626 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1628 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1630 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1631 mtspr SPRN_MAS7_MAS3,r3
1635 /* Write the TLB entry */
1638 .globl a2_tlbinit_after_linear_map
1639 a2_tlbinit_after_linear_map:
1641 /* Now we branch the new virtual address mapped by this entry */
1642 LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
1646 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1647 * else (including IPROTed things left by firmware)
1649 * r3 = current address (more or less)
1656 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1657 rlwinm r10,r4,8,0xff
1658 addi r10,r10,-1 /* Get inner loop mask */
1663 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1666 rldicr r6,r6,0,51 /* Extract EPN */
1669 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1671 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1676 rlwimi r7,r4,16,MAS0_ESEL_MASK
1687 addis r6,r6,(1<<30)@h
1692 .globl a2_tlbinit_after_iprot_flush
1693 a2_tlbinit_after_iprot_flush:
1699 .globl a2_tlbinit_code_end
1700 a2_tlbinit_code_end:
1702 /* We translate LR and return */
1709 * Main entry (boot CPU, thread 0)
1711 * We enter here from head_64.S, possibly after the prom_init trampoline
1712 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1713 * mode. Anything else is as it was left by the bootloader
1715 * Initial requirements of this port:
1717 * - Kernel loaded at 0 physical
1718 * - A good lump of memory mapped 0:0 by UTLB entry 0
1719 * - MSR:IS & MSR:DS set to 0
1721 * Note that some of the above requirements will be relaxed in the future
1722 * as the kernel becomes smarter at dealing with different initial conditions
1723 * but for now you have to be careful
1725 _GLOBAL(start_initialization_book3e)
1728 /* First, we need to setup some initial TLBs to map the kernel
1729 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1730 * and always use AS 0, so we just set it up to match our link
1731 * address and never use 0 based addresses.
1733 bl initial_tlb_book3e
1735 /* Init global core bits */
1738 /* Init per-thread bits */
1739 bl init_thread_book3e
1741 /* Return to common init code */
1748 * Secondary core/processor entry
1750 * This is entered for thread 0 of a secondary core, all other threads
1751 * are expected to be stopped. It's similar to start_initialization_book3e
1752 * except that it's generally entered from the holding loop in head_64.S
1753 * after CPUs have been gathered by Open Firmware.
1755 * We assume we are in 32 bits mode running with whatever TLB entry was
1756 * set for us by the firmware or POR engine.
1758 _GLOBAL(book3e_secondary_core_init_tlb_set)
1760 b generic_secondary_smp_init
1762 _GLOBAL(book3e_secondary_core_init)
1765 /* Do we need to setup initial TLB entry ? */
1769 /* Setup TLB for this core */
1770 bl initial_tlb_book3e
1772 /* We can return from the above running at a different
1773 * address, so recalculate r2 (TOC)
1777 /* Init global core bits */
1778 2: bl init_core_book3e
1780 /* Init per-thread bits */
1781 3: bl init_thread_book3e
1783 /* Return to common init code at proper virtual address.
1785 * Due to various previous assumptions, we know we entered this
1786 * function at either the final PAGE_OFFSET mapping or using a
1787 * 1:1 mapping at 0, so we don't bother doing a complicated check
1788 * here, we just ensure the return address has the right top bits.
1790 * Note that if we ever want to be smarter about where we can be
1791 * started from, we have to be careful that by the time we reach
1792 * the code below we may already be running at a different location
1793 * than the one we were called from since initial_tlb_book3e can
1794 * have moved us already.
1798 lis r3,PAGE_OFFSET@highest
1804 _GLOBAL(book3e_secondary_thread_init)
1808 .globl init_core_book3e
1810 /* Establish the interrupt vector base */
1812 LOAD_REG_ADDR(r3, interrupt_base_book3e)
1818 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1821 /* Make sure interrupts are off */
1824 /* disable all timers and clear out status */
1832 _GLOBAL(__setup_base_ivors)
1833 SET_IVOR(0, 0x020) /* Critical Input */
1834 SET_IVOR(1, 0x000) /* Machine Check */
1835 SET_IVOR(2, 0x060) /* Data Storage */
1836 SET_IVOR(3, 0x080) /* Instruction Storage */
1837 SET_IVOR(4, 0x0a0) /* External Input */
1838 SET_IVOR(5, 0x0c0) /* Alignment */
1839 SET_IVOR(6, 0x0e0) /* Program */
1840 SET_IVOR(7, 0x100) /* FP Unavailable */
1841 SET_IVOR(8, 0x120) /* System Call */
1842 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1843 SET_IVOR(10, 0x160) /* Decrementer */
1844 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1845 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1846 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1847 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1848 SET_IVOR(15, 0x040) /* Debug */
1854 _GLOBAL(setup_altivec_ivors)
1855 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1856 SET_IVOR(33, 0x220) /* AltiVec Assist */
1859 _GLOBAL(setup_perfmon_ivor)
1860 SET_IVOR(35, 0x260) /* Performance Monitor */
1863 _GLOBAL(setup_doorbell_ivors)
1864 SET_IVOR(36, 0x280) /* Processor Doorbell */
1865 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1868 _GLOBAL(setup_ehv_ivors)
1869 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1870 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1871 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1872 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1875 _GLOBAL(setup_lrat_ivor)
1876 SET_IVOR(42, 0x340) /* LRAT Error */