3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/firmware.h>
33 #include <asm/ptrace.h>
34 #include <asm/irqflags.h>
35 #include <asm/ftrace.h>
36 #include <asm/hw_irq.h>
37 #include <asm/context_tracking.h>
45 .tc sys_call_table[TC],sys_call_table
47 /* This value is used to mark exception frames on the stack. */
49 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
54 .globl system_call_common
56 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
58 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
60 END_FTR_SECTION_IFSET(CPU_FTR_TM)
64 addi r1,r1,-INT_FRAME_SIZE
72 beq 2f /* if from kernel mode */
73 ACCOUNT_CPU_USER_ENTRY(r10, r11)
92 * This clears CR0.SO (bit 28), which is the error indication on
93 * return from this system call.
95 rldimi r2,r11,28,(63-28)
102 addi r9,r1,STACK_FRAME_OVERHEAD
103 ld r11,exception_marker@toc(r2)
104 std r11,-16(r9) /* "regshere" marker */
105 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
108 /* if from user, see if there are any DTL entries to process */
109 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
110 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
111 addi r10,r10,LPPACA_DTLIDX
112 LDX_BE r10,0,r10 /* get log write index */
115 bl accumulate_stolen_time
119 addi r9,r1,STACK_FRAME_OVERHEAD
121 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
122 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
125 * A syscall should always be called with interrupts enabled
126 * so we just unconditionally hard-enable here. When some kind
127 * of irq tracing is used, we additionally check that condition
130 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
131 lbz r10,PACASOFTIRQEN(r13)
134 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
137 #ifdef CONFIG_PPC_BOOK3E
143 #endif /* CONFIG_PPC_BOOK3E */
145 /* We do need to set SOFTE in the stack frame or the return
146 * from interrupt will be painful
151 CURRENT_THREAD_INFO(r11, r1)
153 andi. r11,r10,_TIF_SYSCALL_DOTRACE
154 bne syscall_dotrace /* does not return */
155 cmpldi 0,r0,NR_syscalls
158 system_call: /* label this so stack traces look sane */
160 * Need to vector to 32 Bit or default sys_call_table here,
161 * based on caller's run-mode / personality.
163 ld r11,SYS_CALL_TABLE@toc(2)
164 andi. r10,r10,_TIF_32BIT
166 addi r11,r11,8 /* use 32-bit syscall entries */
175 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
177 bctrl /* Call handler */
181 CURRENT_THREAD_INFO(r12, r1)
184 #ifdef CONFIG_PPC_BOOK3S
185 /* No MSR:RI on BookE */
190 * Disable interrupts so current_thread_info()->flags can't change,
191 * and so that we don't get interrupted after loading SRR0/1.
193 #ifdef CONFIG_PPC_BOOK3E
198 * For performance reasons we clear RI the same time that we
199 * clear EE. We only need to clear RI just before we restore r13
200 * below, but batching it with EE saves us one expensive mtmsrd call.
201 * We have to be careful to restore RI if we branch anywhere from
202 * here (eg syscall_exit_work).
207 #endif /* CONFIG_PPC_BOOK3E */
211 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
212 bne- syscall_exit_work
216 .Lsyscall_error_cont:
219 stdcx. r0,0,r1 /* to clear the reservation */
220 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
225 ACCOUNT_CPU_USER_EXIT(r11, r12)
226 HMT_MEDIUM_LOW_HAS_PPR
227 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
235 b . /* prevent speculative execution */
238 oris r5,r5,0x1000 /* Set SO bit in CR */
241 b .Lsyscall_error_cont
243 /* Traced system call support */
246 addi r3,r1,STACK_FRAME_OVERHEAD
247 bl do_syscall_trace_enter
250 * We use the return value of do_syscall_trace_enter() as the syscall
251 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
252 * returns an invalid syscall number and the test below against
253 * NR_syscalls will fail.
257 /* Restore argument registers just clobbered and/or possibly changed. */
265 /* Repopulate r9 and r10 for the system_call path */
266 addi r9,r1,STACK_FRAME_OVERHEAD
267 CURRENT_THREAD_INFO(r10, r1)
270 cmpldi r0,NR_syscalls
273 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
282 #ifdef CONFIG_PPC_BOOK3S
283 mtmsrd r10,1 /* Restore RI */
285 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
286 If TIF_NOERROR is set, just save r3 as it is. */
288 andi. r0,r9,_TIF_RESTOREALL
292 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
294 andi. r0,r9,_TIF_NOERROR
298 oris r5,r5,0x1000 /* Set SO bit in CR */
301 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
304 /* Clear per-syscall TIF flags if any are set. */
306 li r11,_TIF_PERSYSCALL_MASK
307 addi r12,r12,TI_FLAGS
312 subi r12,r12,TI_FLAGS
314 4: /* Anything else left to do? */
315 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
316 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
317 beq ret_from_except_lite
319 /* Re-enable interrupts */
320 #ifdef CONFIG_PPC_BOOK3E
326 #endif /* CONFIG_PPC_BOOK3E */
329 addi r3,r1,STACK_FRAME_OVERHEAD
330 bl do_syscall_trace_leave
333 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
335 /* Firstly we need to enable TM in the kernel */
338 rldimi r10, r13, MSR_TM_LG, 63-MSR_TM_LG
341 /* tabort, this dooms the transaction, nothing else */
342 li r13, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
346 * Return directly to userspace. We have corrupted user register state,
347 * but userspace will never see that register state. Execution will
348 * resume after the tbegin of the aborted transaction with the
349 * checkpointed register state.
358 b . /* prevent speculative execution */
361 /* Save non-volatile GPRs, if not already saved. */
373 * The sigsuspend and rt_sigsuspend system calls can call do_signal
374 * and thus put the process into the stopped state where we might
375 * want to examine its user state with ptrace. Therefore we need
376 * to save all the nonvolatile registers (r14 - r31) before calling
377 * the C code. Similarly, fork, vfork and clone need the full
378 * register state on the stack so that it can be copied to the child.
396 _GLOBAL(ppc32_swapcontext)
398 bl compat_sys_swapcontext
401 _GLOBAL(ppc64_swapcontext)
406 _GLOBAL(ppc_switch_endian)
411 _GLOBAL(ret_from_fork)
417 _GLOBAL(ret_from_kernel_thread)
422 #if defined(_CALL_ELF) && _CALL_ELF == 2
430 * This routine switches between two different tasks. The process
431 * state of one is saved on its kernel stack. Then the state
432 * of the other is restored from its kernel stack. The memory
433 * management hardware is updated to the second process's state.
434 * Finally, we can return to the second process, via ret_from_except.
435 * On entry, r3 points to the THREAD for the current task, r4
436 * points to the THREAD for the new task.
438 * Note: there are two ways to get to the "going out" portion
439 * of this code; either by coming in via the entry (_switch)
440 * or via "fork" which must set up an environment equivalent
441 * to the "_switch" path. If you change this you'll have to change
442 * the fork code also.
444 * The code which creates the new task context is in 'copy_thread'
445 * in arch/powerpc/kernel/process.c
451 stdu r1,-SWITCH_FRAME_SIZE(r1)
452 /* r3-r13 are caller saved -- Cort */
455 mflr r20 /* Return to switch caller */
460 std r1,KSP(r3) /* Set old stack pointer */
463 /* We need a sync somewhere here to make sure that if the
464 * previous task gets rescheduled on another CPU, it sees all
465 * stores it has performed on this one.
468 #endif /* CONFIG_SMP */
471 * If we optimise away the clear of the reservation in system
472 * calls because we know the CPU tracks the address of the
473 * reservation, then we need to clear it here to cover the
474 * case that the kernel context switch path has no larx
479 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
481 #ifdef CONFIG_PPC_BOOK3S
482 /* Cancel all explict user streams as they will have no use after context
483 * switch and will stop the HW from creating streams itself
485 DCBT_STOP_ALL_STREAM_IDS(r6)
488 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
489 std r6,PACACURRENT(r13) /* Set new 'current' */
491 ld r8,KSP(r4) /* new stack pointer */
492 #ifdef CONFIG_PPC_BOOK3S
494 clrrdi r6,r8,28 /* get its ESID */
495 clrrdi r9,r1,28 /* get current sp ESID */
497 clrrdi r6,r8,40 /* get its 1T ESID */
498 clrrdi r9,r1,40 /* get current sp 1T ESID */
499 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
500 clrldi. r0,r6,2 /* is new ESID c00000000? */
501 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
503 beq 2f /* if yes, don't slbie it */
505 /* Bolt in the new stack SLB entry */
506 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
507 oris r0,r6,(SLB_ESID_V)@h
508 ori r0,r0,(SLB_NUM_BOLTED-1)@l
510 li r9,MMU_SEGSIZE_1T /* insert B field */
511 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
512 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
513 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
515 /* Update the last bolted SLB. No write barriers are needed
516 * here, provided we only update the current CPU's SLB shadow
519 ld r9,PACA_SLBSHADOWPTR(r13)
521 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
522 li r12,SLBSHADOW_STACKVSID
523 STDX_BE r7,r12,r9 /* Save VSID */
524 li r12,SLBSHADOW_STACKESID
525 STDX_BE r0,r12,r9 /* Save ESID */
527 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
528 * we have 1TB segments, the only CPUs known to have the errata
529 * only support less than 1TB of system memory and we'll never
530 * actually hit this code path.
534 slbie r6 /* Workaround POWER5 < DD2.1 issue */
538 #endif /* !CONFIG_PPC_BOOK3S */
540 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
541 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
542 because we don't need to leave the 288-byte ABI gap at the
543 top of the kernel stack. */
544 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
546 mr r1,r8 /* start using new stack pointer */
547 std r7,PACAKSAVE(r13)
552 /* r3-r13 are destroyed -- Cort */
556 /* convert old thread to its task_struct for return value */
558 ld r7,_NIP(r1) /* Return to _switch caller in new task */
560 addi r1,r1,SWITCH_FRAME_SIZE
564 _GLOBAL(ret_from_except)
567 bne ret_from_except_lite
570 _GLOBAL(ret_from_except_lite)
572 * Disable interrupts so that current_thread_info()->flags
573 * can't change between when we test it and when we return
574 * from the interrupt.
576 #ifdef CONFIG_PPC_BOOK3E
579 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
580 mtmsrd r10,1 /* Update machine state */
581 #endif /* CONFIG_PPC_BOOK3E */
583 CURRENT_THREAD_INFO(r9, r1)
585 #ifdef CONFIG_PPC_BOOK3E
586 ld r10,PACACURRENT(r13)
587 #endif /* CONFIG_PPC_BOOK3E */
591 #ifdef CONFIG_PPC_BOOK3E
592 lwz r3,(THREAD+THREAD_DBCR0)(r10)
593 #endif /* CONFIG_PPC_BOOK3E */
595 /* Check current_thread_info()->flags */
596 andi. r0,r4,_TIF_USER_WORK_MASK
597 #ifdef CONFIG_PPC_BOOK3E
600 * Check to see if the dbcr0 register is set up to debug.
601 * Use the internal debug mode bit to do this.
603 andis. r0,r3,DBCR0_IDM@h
606 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
615 1: andi. r0,r4,_TIF_NEED_RESCHED
617 bl restore_interrupts
619 b ret_from_except_lite
621 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
622 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
623 bne 3f /* only restore TM if nothing else to do */
624 addi r3,r1,STACK_FRAME_OVERHEAD
631 * Use a non volatile GPR to save and restore our thread_info flags
632 * across the call to restore_interrupts.
635 bl restore_interrupts
637 addi r3,r1,STACK_FRAME_OVERHEAD
642 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
643 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
646 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
649 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
650 mr r4,r1 /* src: current exception frame */
651 mr r1,r3 /* Reroute the trampoline frame to r1 */
653 /* Copy from the original to the trampoline. */
654 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
655 li r6,0 /* start offset: 0 */
662 /* Do real store operation to complete stwu */
666 /* Clear _TIF_EMULATE_STACK_STORE flag */
667 lis r11,_TIF_EMULATE_STACK_STORE@h
675 #ifdef CONFIG_PREEMPT
676 /* Check if we need to preempt */
677 andi. r0,r4,_TIF_NEED_RESCHED
679 /* Check that preempt_count() == 0 and interrupts are enabled */
680 lwz r8,TI_PREEMPT(r9)
684 crandc eq,cr1*4+eq,eq
688 * Here we are preempting the current task. We want to make
689 * sure we are soft-disabled first and reconcile irq state.
691 RECONCILE_IRQ_STATE(r3,r4)
692 1: bl preempt_schedule_irq
694 /* Re-test flags and eventually loop */
695 CURRENT_THREAD_INFO(r9, r1)
697 andi. r0,r4,_TIF_NEED_RESCHED
701 * arch_local_irq_restore() from preempt_schedule_irq above may
702 * enable hard interrupt but we really should disable interrupts
703 * when we return from the interrupt, and so that we don't get
704 * interrupted after loading SRR0/1.
706 #ifdef CONFIG_PPC_BOOK3E
709 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
710 mtmsrd r10,1 /* Update machine state */
711 #endif /* CONFIG_PPC_BOOK3E */
712 #endif /* CONFIG_PREEMPT */
714 .globl fast_exc_return_irq
718 * This is the main kernel exit path. First we check if we
719 * are about to re-enable interrupts
722 lbz r6,PACASOFTIRQEN(r13)
726 /* We are enabling, were we already enabled ? Yes, just return */
731 * We are about to soft-enable interrupts (we are hard disabled
732 * at this point). We check if there's anything that needs to
735 lbz r0,PACAIRQHAPPENED(r13)
737 bne- restore_check_irq_replay
740 * Get here when nothing happened while soft-disabled, just
741 * soft-enable and move-on. We will hard-enable as a side
747 stb r0,PACASOFTIRQEN(r13);
750 * Final return path. BookE is handled in a different file
753 #ifdef CONFIG_PPC_BOOK3E
754 b exception_return_book3e
757 * Clear the reservation. If we know the CPU tracks the address of
758 * the reservation then we can potentially save some cycles and use
759 * a larx. On POWER6 and POWER7 this is significantly faster.
762 stdcx. r0,0,r1 /* to clear the reservation */
765 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
768 * Some code path such as load_up_fpu or altivec return directly
769 * here. They run entirely hard disabled and do not alter the
770 * interrupt state. They also don't use lwarx/stwcx. and thus
771 * are known not to leave dangling reservations.
773 .globl fast_exception_return
774 fast_exception_return:
788 /* Load PPR from thread struct before we clear MSR:RI */
790 ld r2,PACACURRENT(r13)
791 ld r2,TASKTHREADPPR(r2)
792 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
795 * Clear RI before restoring r13. If we are returning to
796 * userspace and we take an exception after restoring r13,
797 * we end up corrupting the userspace r13 value.
799 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
800 andc r4,r4,r0 /* r0 contains MSR_RI here */
803 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
805 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
808 * r13 is our per cpu area, only restore it if we are returning to
809 * userspace the value stored in the stack frame may belong to
815 mtspr SPRN_PPR,r2 /* Restore PPR */
816 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
817 ACCOUNT_CPU_USER_EXIT(r2, r4)
834 b . /* prevent speculative execution */
836 #endif /* CONFIG_PPC_BOOK3E */
839 * We are returning to a context with interrupts soft disabled.
841 * However, we may also about to hard enable, so we need to
842 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
843 * or that bit can get out of sync and bad things will happen
847 lbz r7,PACAIRQHAPPENED(r13)
850 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
851 stb r7,PACAIRQHAPPENED(r13)
853 stb r0,PACASOFTIRQEN(r13);
858 * Something did happen, check if a re-emit is needed
859 * (this also clears paca->irq_happened)
861 restore_check_irq_replay:
862 /* XXX: We could implement a fast path here where we check
863 * for irq_happened being just 0x01, in which case we can
864 * clear it and return. That means that we would potentially
865 * miss a decrementer having wrapped all the way around.
867 * Still, this might be useful for things like hash_page
869 bl __check_irq_replay
871 beq restore_no_replay
874 * We need to re-emit an interrupt. We do so by re-using our
875 * existing exception frame. We first change the trap value,
876 * but we need to ensure we preserve the low nibble of it
884 * Then find the right handler and call it. Interrupts are
885 * still soft-disabled and we keep them that way.
889 addi r3,r1,STACK_FRAME_OVERHEAD;
892 1: cmpwi cr0,r3,0xe60
894 addi r3,r1,STACK_FRAME_OVERHEAD;
895 bl handle_hmi_exception
897 1: cmpwi cr0,r3,0x900
899 addi r3,r1,STACK_FRAME_OVERHEAD;
902 #ifdef CONFIG_PPC_DOORBELL
904 #ifdef CONFIG_PPC_BOOK3E
911 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
912 #endif /* CONFIG_PPC_BOOK3E */
914 addi r3,r1,STACK_FRAME_OVERHEAD;
915 bl doorbell_exception
917 #endif /* CONFIG_PPC_DOORBELL */
918 1: b ret_from_except /* What else to do here ? */
921 addi r3,r1,STACK_FRAME_OVERHEAD
922 bl unrecoverable_exception
925 #ifdef CONFIG_PPC_RTAS
927 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
928 * called with the MMU off.
930 * In addition, we need to be in 32b mode, at least for now.
932 * Note: r3 is an input parameter to rtas, so don't trash it...
937 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
939 /* Because RTAS is running in 32b mode, it clobbers the high order half
940 * of all registers that it saves. We therefore save those registers
941 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
943 SAVE_GPR(2, r1) /* Save the TOC */
944 SAVE_GPR(13, r1) /* Save paca */
945 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
946 SAVE_10GPRS(22, r1) /* ditto */
959 /* Temporary workaround to clear CR until RTAS can be modified to
966 /* There is no way it is acceptable to get here with interrupts enabled,
967 * check it with the asm equivalent of WARN_ON
969 lbz r0,PACASOFTIRQEN(r13)
971 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
974 /* Hard-disable interrupts */
980 /* Unfortunately, the stack pointer and the MSR are also clobbered,
981 * so they are saved in the PACA which allows us to restore
982 * our original state after RTAS returns.
985 std r6,PACASAVEDMSR(r13)
987 /* Setup our real return addr */
988 LOAD_REG_ADDR(r4,rtas_return_loc)
989 clrldi r4,r4,2 /* convert to realmode address */
993 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
997 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
998 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1000 sync /* disable interrupts so SRR0/1 */
1001 mtmsrd r0 /* don't get trashed */
1003 LOAD_REG_ADDR(r4, rtas)
1004 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1005 ld r4,RTASBASE(r4) /* get the rtas->base value */
1010 b . /* prevent speculative execution */
1015 /* relocation is off at this point */
1017 clrldi r4,r4,2 /* convert to realmode address */
1021 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1029 ld r1,PACAR1(r4) /* Restore our SP */
1030 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1035 b . /* prevent speculative execution */
1038 1: .llong rtas_restore_regs
1041 /* relocation is on at this point */
1042 REST_GPR(2, r1) /* Restore the TOC */
1043 REST_GPR(13, r1) /* Restore paca */
1044 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1045 REST_10GPRS(22, r1) /* ditto */
1060 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1061 ld r0,16(r1) /* get return address */
1064 blr /* return to caller */
1066 #endif /* CONFIG_PPC_RTAS */
1071 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1073 /* Because PROM is running in 32b mode, it clobbers the high order half
1074 * of all registers that it saves. We therefore save those registers
1075 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1086 /* Put PROM address in SRR0 */
1089 /* Setup our trampoline return addr in LR */
1092 addi r4,r4,(1f - 0b)
1095 /* Prepare a 32-bit mode big endian MSR
1097 #ifdef CONFIG_PPC_BOOK3E
1098 rlwinm r11,r11,0,1,31
1101 #else /* CONFIG_PPC_BOOK3E */
1102 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1106 #endif /* CONFIG_PPC_BOOK3E */
1108 1: /* Return from OF */
1111 /* Just make sure that r1 top 32 bits didn't get
1116 /* Restore the MSR (back to 64 bits) */
1121 /* Restore other registers */
1129 addi r1,r1,PROM_FRAME_SIZE
1134 #ifdef CONFIG_FUNCTION_TRACER
1135 #ifdef CONFIG_DYNAMIC_FTRACE
1140 _GLOBAL_TOC(ftrace_caller)
1141 /* Taken from output of objdump from lib64/glibc */
1147 subi r3, r3, MCOUNT_INSN_SIZE
1152 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1153 .globl ftrace_graph_call
1156 _GLOBAL(ftrace_graph_stub)
1161 _GLOBAL(ftrace_stub)
1164 _GLOBAL_TOC(_mcount)
1165 /* Taken from output of objdump from lib64/glibc */
1172 subi r3, r3, MCOUNT_INSN_SIZE
1173 LOAD_REG_ADDR(r5,ftrace_trace_function)
1181 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1182 b ftrace_graph_caller
1187 _GLOBAL(ftrace_stub)
1190 #endif /* CONFIG_DYNAMIC_FTRACE */
1192 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1193 _GLOBAL(ftrace_graph_caller)
1194 /* load r4 with local address */
1196 subi r4, r4, MCOUNT_INSN_SIZE
1198 /* Grab the LR out of the caller stack frame */
1202 bl prepare_ftrace_return
1206 * prepare_ftrace_return gives us the address we divert to.
1207 * Change the LR in the callers stack frame to this.
1217 _GLOBAL(return_to_handler)
1218 /* need to save return values */
1228 * We might be called from a module.
1229 * Switch to our TOC to run inside the core kernel.
1233 bl ftrace_return_to_handler
1236 /* return value has real return address */
1245 /* Jump back to real return address */
1247 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1248 #endif /* CONFIG_FUNCTION_TRACER */