3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/code-patching-asm.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/firmware.h>
34 #include <asm/ptrace.h>
35 #include <asm/irqflags.h>
36 #include <asm/hw_irq.h>
37 #include <asm/context_tracking.h>
39 #include <asm/ppc-opcode.h>
40 #include <asm/barrier.h>
41 #include <asm/export.h>
42 #include <asm/asm-compat.h>
43 #ifdef CONFIG_PPC_BOOK3S
44 #include <asm/exception-64s.h>
46 #include <asm/exception-64e.h>
48 #include <asm/feature-fixups.h>
55 .tc sys_call_table[TC],sys_call_table
57 COMPAT_SYS_CALL_TABLE:
58 .tc compat_sys_call_table[TC],compat_sys_call_table
60 /* This value is used to mark exception frames on the stack. */
62 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
67 .globl system_call_common
69 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
71 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
73 END_FTR_SECTION_IFSET(CPU_FTR_TM)
77 addi r1,r1,-INT_FRAME_SIZE
85 beq 2f /* if from kernel mode */
86 #ifdef CONFIG_PPC_FSL_BOOK3E
87 START_BTB_FLUSH_SECTION
91 ACCOUNT_CPU_USER_ENTRY(r13, r10, r11)
110 * This clears CR0.SO (bit 28), which is the error indication on
111 * return from this system call.
113 rldimi r2,r11,28,(63-28)
120 addi r9,r1,STACK_FRAME_OVERHEAD
121 ld r11,exception_marker@toc(r2)
122 std r11,-16(r9) /* "regshere" marker */
123 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
126 /* if from user, see if there are any DTL entries to process */
127 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
128 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
129 addi r10,r10,LPPACA_DTLIDX
130 LDX_BE r10,0,r10 /* get log write index */
133 bl accumulate_stolen_time
137 addi r9,r1,STACK_FRAME_OVERHEAD
139 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
140 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
143 * A syscall should always be called with interrupts enabled
144 * so we just unconditionally hard-enable here. When some kind
145 * of irq tracing is used, we additionally check that condition
148 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
149 lbz r10,PACAIRQSOFTMASK(r13)
150 1: tdnei r10,IRQS_ENABLED
151 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
154 #ifdef CONFIG_PPC_BOOK3E
160 #endif /* CONFIG_PPC_BOOK3E */
162 system_call: /* label this so stack traces look sane */
163 /* We do need to set SOFTE in the stack frame or the return
164 * from interrupt will be painful
169 ld r11, PACA_THREAD_INFO(r13)
171 andi. r11,r10,_TIF_SYSCALL_DOTRACE
172 bne .Lsyscall_dotrace /* does not return */
173 cmpldi 0,r0,NR_syscalls
174 bge- .Lsyscall_enosys
178 * Need to vector to 32 Bit or default sys_call_table here,
179 * based on caller's run-mode / personality.
181 ld r11,SYS_CALL_TABLE@toc(2)
182 andis. r10,r10,_TIF_32BIT@h
184 ld r11,COMPAT_SYS_CALL_TABLE@toc(2)
196 * Prevent the load of the handler below (based on the user-passed
197 * system call number) being speculatively executed until the test
198 * against NR_syscalls and branch to .Lsyscall_enosys above has
202 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
204 bctrl /* Call handler */
209 #ifdef CONFIG_DEBUG_RSEQ
210 /* Check whether the syscall is issued inside a restartable sequence */
211 addi r3,r1,STACK_FRAME_OVERHEAD
216 ld r12, PACA_THREAD_INFO(r13)
219 #ifdef CONFIG_PPC_BOOK3S
220 /* No MSR:RI on BookE */
222 beq- .Lunrecov_restore
226 * This is a few instructions into the actual syscall exit path (which actually
227 * starts at .Lsyscall_exit) to cater to kprobe blacklisting and to reduce the
228 * number of visible symbols for profiling purposes.
230 * We can probe from system_call until this point as MSR_RI is set. But once it
231 * is cleared below, we won't be able to take a trap.
233 * This is blacklisted from kprobes further below with _ASM_NOKPROBE_SYMBOL().
237 * Disable interrupts so current_thread_info()->flags can't change,
238 * and so that we don't get interrupted after loading SRR0/1.
240 * Leave MSR_RI enabled for now, because with THREAD_INFO_IN_TASK we
241 * could fault on the load of the TI_FLAGS below.
243 #ifdef CONFIG_PPC_BOOK3E
248 #endif /* CONFIG_PPC_BOOK3E */
252 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
253 bne- .Lsyscall_exit_work
257 #ifdef CONFIG_ALTIVEC
258 andis. r0,r8,MSR_VEC@h
261 2: addi r3,r1,STACK_FRAME_OVERHEAD
270 .Lsyscall_error_cont:
273 stdcx. r0,0,r1 /* to clear the reservation */
274 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
278 #ifdef CONFIG_PPC_BOOK3S
280 * Clear MSR_RI, MSR_EE is already and remains disabled. We could do
281 * this later, but testing shows that doing it here causes less slow
282 * down than doing it closer to the rfid.
289 ACCOUNT_CPU_USER_EXIT(r13, r11, r12)
293 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
295 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
296 std r8, PACATMSCRATCH(r13)
299 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
307 b . /* prevent speculative execution */
317 b . /* prevent speculative execution */
320 oris r5,r5,0x1000 /* Set SO bit in CR */
323 b .Lsyscall_error_cont
325 /* Traced system call support */
328 addi r3,r1,STACK_FRAME_OVERHEAD
329 bl do_syscall_trace_enter
332 * We use the return value of do_syscall_trace_enter() as the syscall
333 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
334 * returns an invalid syscall number and the test below against
335 * NR_syscalls will fail.
339 /* Restore argument registers just clobbered and/or possibly changed. */
347 /* Repopulate r9 and r10 for the syscall path */
348 addi r9,r1,STACK_FRAME_OVERHEAD
349 ld r10, PACA_THREAD_INFO(r13)
352 cmpldi r0,NR_syscalls
355 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
364 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
365 If TIF_NOERROR is set, just save r3 as it is. */
367 andi. r0,r9,_TIF_RESTOREALL
371 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
373 andi. r0,r9,_TIF_NOERROR
377 oris r5,r5,0x1000 /* Set SO bit in CR */
380 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
383 /* Clear per-syscall TIF flags if any are set. */
385 li r11,_TIF_PERSYSCALL_MASK
386 addi r12,r12,TI_FLAGS
391 subi r12,r12,TI_FLAGS
393 4: /* Anything else left to do? */
395 lis r3,DEFAULT_PPR@highest /* Set default PPR */
396 sldi r3,r3,32 /* bits 11-13 are used for ppr */
398 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
400 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
401 beq ret_from_except_lite
403 /* Re-enable interrupts */
404 #ifdef CONFIG_PPC_BOOK3E
410 #endif /* CONFIG_PPC_BOOK3E */
413 addi r3,r1,STACK_FRAME_OVERHEAD
414 bl do_syscall_trace_leave
417 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
419 /* Firstly we need to enable TM in the kernel */
422 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
425 /* tabort, this dooms the transaction, nothing else */
426 li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
430 * Return directly to userspace. We have corrupted user register state,
431 * but userspace will never see that register state. Execution will
432 * resume after the tbegin of the aborted transaction with the
433 * checkpointed register state.
441 b . /* prevent speculative execution */
443 _ASM_NOKPROBE_SYMBOL(system_call_common);
444 _ASM_NOKPROBE_SYMBOL(system_call_exit);
446 /* Save non-volatile GPRs, if not already saved. */
455 _ASM_NOKPROBE_SYMBOL(save_nvgprs);
459 * The sigsuspend and rt_sigsuspend system calls can call do_signal
460 * and thus put the process into the stopped state where we might
461 * want to examine its user state with ptrace. Therefore we need
462 * to save all the nonvolatile registers (r14 - r31) before calling
463 * the C code. Similarly, fork, vfork and clone need the full
464 * register state on the stack so that it can be copied to the child.
482 _GLOBAL(ppc32_swapcontext)
484 bl compat_sys_swapcontext
487 _GLOBAL(ppc64_swapcontext)
492 _GLOBAL(ppc_switch_endian)
497 _GLOBAL(ret_from_fork)
503 _GLOBAL(ret_from_kernel_thread)
508 #ifdef PPC64_ELF_ABI_v2
515 #ifdef CONFIG_PPC_BOOK3S_64
517 #define FLUSH_COUNT_CACHE \
519 patch_site 1b, patch__call_flush_count_cache
522 #define BCCTR_FLUSH .long 0x4c400420
531 .global flush_count_cache
533 /* Save LR into r9 */
551 patch_site 2b patch__flush_count_cache_return
563 #define FLUSH_COUNT_CACHE
564 #endif /* CONFIG_PPC_BOOK3S_64 */
567 * This routine switches between two different tasks. The process
568 * state of one is saved on its kernel stack. Then the state
569 * of the other is restored from its kernel stack. The memory
570 * management hardware is updated to the second process's state.
571 * Finally, we can return to the second process, via ret_from_except.
572 * On entry, r3 points to the THREAD for the current task, r4
573 * points to the THREAD for the new task.
575 * Note: there are two ways to get to the "going out" portion
576 * of this code; either by coming in via the entry (_switch)
577 * or via "fork" which must set up an environment equivalent
578 * to the "_switch" path. If you change this you'll have to change
579 * the fork code also.
581 * The code which creates the new task context is in 'copy_thread'
582 * in arch/powerpc/kernel/process.c
588 stdu r1,-SWITCH_FRAME_SIZE(r1)
589 /* r3-r13 are caller saved -- Cort */
592 std r0,_NIP(r1) /* Return to switch caller */
595 std r1,KSP(r3) /* Set old stack pointer */
600 * On SMP kernels, care must be taken because a task may be
601 * scheduled off CPUx and on to CPUy. Memory ordering must be
604 * Cacheable stores on CPUx will be visible when the task is
605 * scheduled on CPUy by virtue of the core scheduler barriers
606 * (see "Notes on Program-Order guarantees on SMP systems." in
607 * kernel/sched/core.c).
609 * Uncacheable stores in the case of involuntary preemption must
610 * be taken care of. The smp_mb__before_spin_lock() in __schedule()
611 * is implemented as hwsync on powerpc, which orders MMIO too. So
612 * long as there is an hwsync in the context switch path, it will
613 * be executed on the source CPU after the task has performed
614 * all MMIO ops on that CPU, and on the destination CPU before the
615 * task performs any MMIO ops there.
619 * The kernel context switch path must contain a spin_lock,
620 * which contains larx/stcx, which will clear any reservation
621 * of the task being switched.
623 #ifdef CONFIG_PPC_BOOK3S
624 /* Cancel all explict user streams as they will have no use after context
625 * switch and will stop the HW from creating streams itself
627 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
630 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
631 std r6,PACACURRENT(r13) /* Set new 'current' */
632 #if defined(CONFIG_STACKPROTECTOR)
633 ld r6, TASK_CANARY(r6)
634 std r6, PACA_CANARY(r13)
637 ld r8,KSP(r4) /* new stack pointer */
638 #ifdef CONFIG_PPC_BOOK3S_64
639 BEGIN_MMU_FTR_SECTION
641 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
643 clrrdi r6,r8,28 /* get its ESID */
644 clrrdi r9,r1,28 /* get current sp ESID */
646 clrrdi r6,r8,40 /* get its 1T ESID */
647 clrrdi r9,r1,40 /* get current sp 1T ESID */
648 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
649 clrldi. r0,r6,2 /* is new ESID c00000000? */
650 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
652 beq 2f /* if yes, don't slbie it */
654 /* Bolt in the new stack SLB entry */
655 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
656 oris r0,r6,(SLB_ESID_V)@h
657 ori r0,r0,(SLB_NUM_BOLTED-1)@l
659 li r9,MMU_SEGSIZE_1T /* insert B field */
660 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
661 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
662 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
664 /* Update the last bolted SLB. No write barriers are needed
665 * here, provided we only update the current CPU's SLB shadow
668 ld r9,PACA_SLBSHADOWPTR(r13)
670 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
671 li r12,SLBSHADOW_STACKVSID
672 STDX_BE r7,r12,r9 /* Save VSID */
673 li r12,SLBSHADOW_STACKESID
674 STDX_BE r0,r12,r9 /* Save ESID */
676 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
677 * we have 1TB segments, the only CPUs known to have the errata
678 * only support less than 1TB of system memory and we'll never
679 * actually hit this code path.
685 slbie r6 /* Workaround POWER5 < DD2.1 issue */
686 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
690 #endif /* CONFIG_PPC_BOOK3S_64 */
692 clrrdi r7, r8, THREAD_SHIFT /* base of new stack */
693 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
694 because we don't need to leave the 288-byte ABI gap at the
695 top of the kernel stack. */
696 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
699 * PMU interrupts in radix may come in here. They will use r1, not
700 * PACAKSAVE, so this stack switch will not cause a problem. They
701 * will store to the process stack, which may then be migrated to
702 * another CPU. However the rq lock release on this CPU paired with
703 * the rq lock acquire on the new CPU before the stack becomes
704 * active on the new CPU, will order those stores.
706 mr r1,r8 /* start using new stack pointer */
707 std r7,PACAKSAVE(r13)
712 /* r3-r13 are destroyed -- Cort */
716 /* convert old thread to its task_struct for return value */
718 ld r7,_NIP(r1) /* Return to _switch caller in new task */
720 addi r1,r1,SWITCH_FRAME_SIZE
724 _GLOBAL(ret_from_except)
727 bne ret_from_except_lite
730 _GLOBAL(ret_from_except_lite)
732 * Disable interrupts so that current_thread_info()->flags
733 * can't change between when we test it and when we return
734 * from the interrupt.
736 #ifdef CONFIG_PPC_BOOK3E
740 mtmsrd r10,1 /* Update machine state */
741 #endif /* CONFIG_PPC_BOOK3E */
743 ld r9, PACA_THREAD_INFO(r13)
745 #ifdef CONFIG_PPC_BOOK3E
746 ld r10,PACACURRENT(r13)
747 #endif /* CONFIG_PPC_BOOK3E */
751 #ifdef CONFIG_PPC_BOOK3E
752 lwz r3,(THREAD+THREAD_DBCR0)(r10)
753 #endif /* CONFIG_PPC_BOOK3E */
755 /* Check current_thread_info()->flags */
756 andi. r0,r4,_TIF_USER_WORK_MASK
758 #ifdef CONFIG_PPC_BOOK3E
760 * Check to see if the dbcr0 register is set up to debug.
761 * Use the internal debug mode bit to do this.
763 andis. r0,r3,DBCR0_IDM@h
766 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
773 addi r3,r1,STACK_FRAME_OVERHEAD
777 1: andi. r0,r4,_TIF_NEED_RESCHED
779 bl restore_interrupts
781 b ret_from_except_lite
783 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
784 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
785 bne 3f /* only restore TM if nothing else to do */
786 addi r3,r1,STACK_FRAME_OVERHEAD
793 * Use a non volatile GPR to save and restore our thread_info flags
794 * across the call to restore_interrupts.
797 bl restore_interrupts
799 addi r3,r1,STACK_FRAME_OVERHEAD
804 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
805 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
808 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
811 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
812 mr r4,r1 /* src: current exception frame */
813 mr r1,r3 /* Reroute the trampoline frame to r1 */
815 /* Copy from the original to the trampoline. */
816 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
817 li r6,0 /* start offset: 0 */
824 /* Do real store operation to complete stdu */
828 /* Clear _TIF_EMULATE_STACK_STORE flag */
829 lis r11,_TIF_EMULATE_STACK_STORE@h
837 #ifdef CONFIG_PREEMPT
838 /* Check if we need to preempt */
839 andi. r0,r4,_TIF_NEED_RESCHED
841 /* Check that preempt_count() == 0 and interrupts are enabled */
842 lwz r8,TI_PREEMPT(r9)
846 andi. r0,r0,IRQS_DISABLED
850 * Here we are preempting the current task. We want to make
851 * sure we are soft-disabled first and reconcile irq state.
853 RECONCILE_IRQ_STATE(r3,r4)
854 1: bl preempt_schedule_irq
856 /* Re-test flags and eventually loop */
857 ld r9, PACA_THREAD_INFO(r13)
859 andi. r0,r4,_TIF_NEED_RESCHED
863 * arch_local_irq_restore() from preempt_schedule_irq above may
864 * enable hard interrupt but we really should disable interrupts
865 * when we return from the interrupt, and so that we don't get
866 * interrupted after loading SRR0/1.
868 #ifdef CONFIG_PPC_BOOK3E
872 mtmsrd r10,1 /* Update machine state */
873 #endif /* CONFIG_PPC_BOOK3E */
874 #endif /* CONFIG_PREEMPT */
876 .globl fast_exc_return_irq
880 * This is the main kernel exit path. First we check if we
881 * are about to re-enable interrupts
884 lbz r6,PACAIRQSOFTMASK(r13)
885 andi. r5,r5,IRQS_DISABLED
886 bne .Lrestore_irq_off
888 /* We are enabling, were we already enabled ? Yes, just return */
889 andi. r6,r6,IRQS_DISABLED
893 * We are about to soft-enable interrupts (we are hard disabled
894 * at this point). We check if there's anything that needs to
897 lbz r0,PACAIRQHAPPENED(r13)
899 bne- .Lrestore_check_irq_replay
902 * Get here when nothing happened while soft-disabled, just
903 * soft-enable and move-on. We will hard-enable as a side
909 stb r0,PACAIRQSOFTMASK(r13);
912 * Final return path. BookE is handled in a different file
915 #ifdef CONFIG_PPC_BOOK3E
916 b exception_return_book3e
919 * Clear the reservation. If we know the CPU tracks the address of
920 * the reservation then we can potentially save some cycles and use
921 * a larx. On POWER6 and POWER7 this is significantly faster.
924 stdcx. r0,0,r1 /* to clear the reservation */
927 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
930 * Some code path such as load_up_fpu or altivec return directly
931 * here. They run entirely hard disabled and do not alter the
932 * interrupt state. They also don't use lwarx/stwcx. and thus
933 * are known not to leave dangling reservations.
935 .globl fast_exception_return
936 fast_exception_return:
948 beq- .Lunrecov_restore
951 * Clear RI before restoring r13. If we are returning to
952 * userspace and we take an exception after restoring r13,
953 * we end up corrupting the userspace r13 value.
958 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
960 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
963 * r13 is our per cpu area, only restore it if we are returning to
964 * userspace the value stored in the stack frame may belong to
973 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
974 ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
990 b . /* prevent speculative execution */
992 1: mtspr SPRN_SRR1,r3
1000 * Leaving a stale exception_marker on the stack can confuse
1001 * the reliable stack unwinder later on. Clear it.
1004 std r2,STACK_FRAME_OVERHEAD-16(r1)
1012 b . /* prevent speculative execution */
1014 #endif /* CONFIG_PPC_BOOK3E */
1017 * We are returning to a context with interrupts soft disabled.
1019 * However, we may also about to hard enable, so we need to
1020 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
1021 * or that bit can get out of sync and bad things will happen
1025 lbz r7,PACAIRQHAPPENED(r13)
1028 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
1029 stb r7,PACAIRQHAPPENED(r13)
1031 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
1032 /* The interrupt should not have soft enabled. */
1033 lbz r7,PACAIRQSOFTMASK(r13)
1034 1: tdeqi r7,IRQS_ENABLED
1035 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1040 * Something did happen, check if a re-emit is needed
1041 * (this also clears paca->irq_happened)
1043 .Lrestore_check_irq_replay:
1044 /* XXX: We could implement a fast path here where we check
1045 * for irq_happened being just 0x01, in which case we can
1046 * clear it and return. That means that we would potentially
1047 * miss a decrementer having wrapped all the way around.
1049 * Still, this might be useful for things like hash_page
1051 bl __check_irq_replay
1053 beq .Lrestore_no_replay
1056 * We need to re-emit an interrupt. We do so by re-using our
1057 * existing exception frame. We first change the trap value,
1058 * but we need to ensure we preserve the low nibble of it
1066 * PACA_IRQ_HARD_DIS won't always be set here, so set it now
1067 * to reconcile the IRQ state. Tracing is already accounted for.
1069 lbz r4,PACAIRQHAPPENED(r13)
1070 ori r4,r4,PACA_IRQ_HARD_DIS
1071 stb r4,PACAIRQHAPPENED(r13)
1074 * Then find the right handler and call it. Interrupts are
1075 * still soft-disabled and we keep them that way.
1079 addi r3,r1,STACK_FRAME_OVERHEAD;
1082 1: cmpwi cr0,r3,0xf00
1084 addi r3,r1,STACK_FRAME_OVERHEAD;
1085 bl performance_monitor_exception
1087 1: cmpwi cr0,r3,0xe60
1089 addi r3,r1,STACK_FRAME_OVERHEAD;
1090 bl handle_hmi_exception
1092 1: cmpwi cr0,r3,0x900
1094 addi r3,r1,STACK_FRAME_OVERHEAD;
1097 #ifdef CONFIG_PPC_DOORBELL
1099 #ifdef CONFIG_PPC_BOOK3E
1103 #endif /* CONFIG_PPC_BOOK3E */
1105 addi r3,r1,STACK_FRAME_OVERHEAD;
1106 bl doorbell_exception
1107 #endif /* CONFIG_PPC_DOORBELL */
1108 1: b ret_from_except /* What else to do here ? */
1111 addi r3,r1,STACK_FRAME_OVERHEAD
1112 bl unrecoverable_exception
1115 _ASM_NOKPROBE_SYMBOL(ret_from_except);
1116 _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1117 _ASM_NOKPROBE_SYMBOL(resume_kernel);
1118 _ASM_NOKPROBE_SYMBOL(fast_exc_return_irq);
1119 _ASM_NOKPROBE_SYMBOL(restore);
1120 _ASM_NOKPROBE_SYMBOL(fast_exception_return);
1123 #ifdef CONFIG_PPC_RTAS
1125 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1126 * called with the MMU off.
1128 * In addition, we need to be in 32b mode, at least for now.
1130 * Note: r3 is an input parameter to rtas, so don't trash it...
1135 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
1137 /* Because RTAS is running in 32b mode, it clobbers the high order half
1138 * of all registers that it saves. We therefore save those registers
1139 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
1141 SAVE_GPR(2, r1) /* Save the TOC */
1142 SAVE_GPR(13, r1) /* Save paca */
1143 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
1144 SAVE_10GPRS(22, r1) /* ditto */
1157 /* Temporary workaround to clear CR until RTAS can be modified to
1164 /* There is no way it is acceptable to get here with interrupts enabled,
1165 * check it with the asm equivalent of WARN_ON
1167 lbz r0,PACAIRQSOFTMASK(r13)
1168 1: tdeqi r0,IRQS_ENABLED
1169 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1172 /* Hard-disable interrupts */
1178 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1179 * so they are saved in the PACA which allows us to restore
1180 * our original state after RTAS returns.
1183 std r6,PACASAVEDMSR(r13)
1185 /* Setup our real return addr */
1186 LOAD_REG_ADDR(r4,rtas_return_loc)
1187 clrldi r4,r4,2 /* convert to realmode address */
1191 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1195 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1196 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1200 sync /* disable interrupts so SRR0/1 */
1201 mtmsrd r0 /* don't get trashed */
1203 LOAD_REG_ADDR(r4, rtas)
1204 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1205 ld r4,RTASBASE(r4) /* get the rtas->base value */
1210 b . /* prevent speculative execution */
1216 * Clear RI and set SF before anything.
1221 sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
1226 /* relocation is off at this point */
1228 clrldi r4,r4,2 /* convert to realmode address */
1232 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1234 ld r1,PACAR1(r4) /* Restore our SP */
1235 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1240 b . /* prevent speculative execution */
1241 _ASM_NOKPROBE_SYMBOL(__enter_rtas)
1242 _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
1245 1: .8byte rtas_restore_regs
1248 /* relocation is on at this point */
1249 REST_GPR(2, r1) /* Restore the TOC */
1250 REST_GPR(13, r1) /* Restore paca */
1251 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1252 REST_10GPRS(22, r1) /* ditto */
1267 addi r1,r1,SWITCH_FRAME_SIZE /* Unstack our frame */
1268 ld r0,16(r1) /* get return address */
1271 blr /* return to caller */
1273 #endif /* CONFIG_PPC_RTAS */
1278 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
1280 /* Because PROM is running in 32b mode, it clobbers the high order half
1281 * of all registers that it saves. We therefore save those registers
1282 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1293 /* Put PROM address in SRR0 */
1296 /* Setup our trampoline return addr in LR */
1299 addi r4,r4,(1f - 0b)
1302 /* Prepare a 32-bit mode big endian MSR
1304 #ifdef CONFIG_PPC_BOOK3E
1305 rlwinm r11,r11,0,1,31
1308 #else /* CONFIG_PPC_BOOK3E */
1309 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1313 #endif /* CONFIG_PPC_BOOK3E */
1315 1: /* Return from OF */
1318 /* Just make sure that r1 top 32 bits didn't get
1323 /* Restore the MSR (back to 64 bits) */
1328 /* Restore other registers */
1336 addi r1,r1,SWITCH_FRAME_SIZE