3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ptrace.h>
35 #include <asm/export.h>
36 #include <asm/asm-405.h>
37 #include <asm/feature-fixups.h>
38 #include <asm/barrier.h>
41 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
43 #if MSR_KERNEL >= 0x10000
44 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
46 #define LOAD_MSR_KERNEL(r, x) li r,(x)
50 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
51 * fit into one page in order to not encounter a TLB miss between the
52 * modification of srr0/srr1 and the associated rfi.
57 .globl mcheck_transfer_to_handler
58 mcheck_transfer_to_handler:
65 .globl debug_transfer_to_handler
66 debug_transfer_to_handler:
73 .globl crit_transfer_to_handler
74 crit_transfer_to_handler:
75 #ifdef CONFIG_PPC_BOOK3E_MMU
86 #ifdef CONFIG_PHYS_64BIT
89 #endif /* CONFIG_PHYS_64BIT */
90 #endif /* CONFIG_PPC_BOOK3E_MMU */
100 /* set the stack limit to the current stack */
101 mfspr r8,SPRN_SPRG_THREAD
103 stw r0,SAVED_KSP_LIMIT(r11)
104 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
110 .globl crit_transfer_to_handler
111 crit_transfer_to_handler:
117 stw r0,crit_srr0@l(0)
119 stw r0,crit_srr1@l(0)
121 /* set the stack limit to the current stack */
122 mfspr r8,SPRN_SPRG_THREAD
124 stw r0,saved_ksp_limit@l(0)
125 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
131 * This code finishes saving the registers to the exception frame
132 * and jumps to the appropriate handler for the exception, turning
133 * on address translation.
134 * Note that we rely on the caller having set cr0.eq iff the exception
135 * occurred in kernel mode (i.e. MSR:PR = 0).
137 .globl transfer_to_handler_full
138 transfer_to_handler_full:
142 .globl transfer_to_handler
152 mfspr r12,SPRN_SPRG_THREAD
154 beq 2f /* if from user, fix up THREAD.regs */
155 addi r11,r1,STACK_FRAME_OVERHEAD
157 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
158 /* Check to see if the dbcr0 register is set up to debug. Use the
159 internal debug mode bit to do this. */
160 lwz r12,THREAD_DBCR0(r12)
161 andis. r12,r12,DBCR0_IDM@h
163 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
164 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
166 /* From user and task is ptraced - load up global dbcr0 */
167 li r12,-1 /* clear all pending debug events */
169 lis r11,global_dbcr0@ha
171 addi r11,r11,global_dbcr0@l
186 2: /* if from kernel, check interrupted DOZE/NAP mode and
187 * check for stack overflow
189 lwz r9,KSP_LIMIT(r12)
190 cmplw r1,r9 /* if r1 <= ksp_limit */
191 ble- stack_ovf /* then the kernel stack overflowed */
193 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
194 lwz r12,TI_LOCAL_FLAGS(r2)
196 bt- 31-TLF_NAPPING,4f
197 bt- 31-TLF_SLEEPING,7f
198 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
199 .globl transfer_to_handler_cont
200 transfer_to_handler_cont:
203 tovirt(r2, r2) /* set r2 to current */
204 lwz r11,0(r9) /* virtual address of handler */
205 lwz r9,4(r9) /* where to go when done */
206 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
209 #ifdef CONFIG_TRACE_IRQFLAGS
210 lis r12,reenable_mmu@h
211 ori r12,r12,reenable_mmu@l
216 reenable_mmu: /* re-enable mmu so we can */
220 andi. r10,r10,MSR_EE /* Did EE change? */
224 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
225 * If from user mode there is only one stack frame on the stack, and
226 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
227 * stack frame to make trace_hardirqs_off happy.
229 * This is handy because we also need to save a bunch of GPRs,
230 * r3 can be different from GPR3(r1) at this point, r9 and r11
231 * contains the old MSR and handler address respectively,
232 * r4 & r5 can contain page fault arguments that need to be passed
233 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
234 * they aren't useful past this point (aren't syscall arguments),
235 * the rest is restored from the exception frame.
243 bl trace_hardirqs_off
256 bctr /* jump to handler */
257 #else /* CONFIG_TRACE_IRQFLAGS */
262 RFI /* jump to handler, enable MMU */
263 #endif /* CONFIG_TRACE_IRQFLAGS */
265 #if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
266 4: rlwinm r12,r12,0,~_TLF_NAPPING
267 stw r12,TI_LOCAL_FLAGS(r2)
268 b power_save_ppc32_restore
270 7: rlwinm r12,r12,0,~_TLF_SLEEPING
271 stw r12,TI_LOCAL_FLAGS(r2)
272 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
273 rlwinm r9,r9,0,~MSR_EE
274 lwz r12,_LINK(r11) /* and return to address in LR */
275 b fast_exception_return
279 * On kernel stack overflow, load up an initial stack pointer
280 * and call StackOverflow(regs), which should not return.
283 /* sometimes we use a statically-allocated stack, which is OK. */
287 ble 5b /* r1 <= &_end is OK */
289 addi r3,r1,STACK_FRAME_OVERHEAD
290 lis r1,init_thread_union@ha
291 addi r1,r1,init_thread_union@l
292 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
293 lis r9,StackOverflow@ha
294 addi r9,r9,StackOverflow@l
295 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
296 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
305 * Handle a system call.
307 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
308 .stabs "entry_32.S",N_SO,0,0,0f
315 lwz r11,_CCR(r1) /* Clear SO bit in CR */
318 #ifdef CONFIG_TRACE_IRQFLAGS
319 /* Return from syscalls can (and generally will) hard enable
320 * interrupts. You aren't supposed to call a syscall with
321 * interrupts disabled in the first place. However, to ensure
322 * that we get it right vs. lockdep if it happens, we force
323 * that hard enable here with appropriate tracing if we see
324 * that we have been called with interrupts off
329 /* We came in with interrupts disabled, we enable them now */
342 #endif /* CONFIG_TRACE_IRQFLAGS */
344 andi. r11,r11,_TIF_SYSCALL_DOTRACE
346 syscall_dotrace_cont:
347 cmplwi 0,r0,NR_syscalls
348 lis r10,sys_call_table@h
349 ori r10,r10,sys_call_table@l
355 * Prevent the load of the handler below (based on the user-passed
356 * system call number) being speculatively executed until the test
357 * against NR_syscalls and branch to .66f above has
361 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
363 addi r9,r1,STACK_FRAME_OVERHEAD
365 blrl /* Call handler */
366 .globl ret_from_syscall
368 #ifdef CONFIG_DEBUG_RSEQ
369 /* Check whether the syscall is issued inside a restartable sequence */
371 addi r3,r1,STACK_FRAME_OVERHEAD
376 /* disable interrupts so current_thread_info()->flags can't change */
377 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
378 /* Note: We don't bother telling lockdep about it */
383 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
384 bne- syscall_exit_work
386 blt+ syscall_exit_cont
387 lwz r11,_CCR(r1) /* Load CR */
389 oris r11,r11,0x1000 /* Set SO bit in CR */
393 #ifdef CONFIG_TRACE_IRQFLAGS
394 /* If we are going to return from the syscall with interrupts
395 * off, we trace that here. It shouldn't happen though but we
396 * want to catch the bugger if it does right ?
401 bl trace_hardirqs_off
404 #endif /* CONFIG_TRACE_IRQFLAGS */
405 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
406 /* If the process has its own DBCR0 value, load it up. The internal
407 debug mode bit tells us that dbcr0 should be loaded. */
408 lwz r0,THREAD+THREAD_DBCR0(r2)
409 andis. r10,r0,DBCR0_IDM@h
413 BEGIN_MMU_FTR_SECTION
414 lis r4,icache_44x_need_flush@ha
415 lwz r5,icache_44x_need_flush@l(r4)
419 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
420 #endif /* CONFIG_44x */
423 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
424 stwcx. r0,0,r1 /* to clear the reservation */
425 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
428 ACCOUNT_CPU_USER_EXIT(r2, r5, r7)
438 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
448 stw r7,icache_44x_need_flush@l(r4)
450 #endif /* CONFIG_44x */
462 .globl ret_from_kernel_thread
463 ret_from_kernel_thread:
473 /* Traced system call support */
478 addi r3,r1,STACK_FRAME_OVERHEAD
479 bl do_syscall_trace_enter
481 * Restore argument registers possibly just changed.
482 * We use the return value of do_syscall_trace_enter
483 * for call number to look up in the table (r0).
494 cmplwi r0,NR_syscalls
495 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
496 bge- ret_from_syscall
497 b syscall_dotrace_cont
500 andi. r0,r9,_TIF_RESTOREALL
506 andi. r0,r9,_TIF_NOERROR
508 lwz r11,_CCR(r1) /* Load CR */
510 oris r11,r11,0x1000 /* Set SO bit in CR */
513 1: stw r6,RESULT(r1) /* Save result */
514 stw r3,GPR3(r1) /* Update return value */
515 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
518 /* Clear per-syscall TIF flags if any are set. */
520 li r11,_TIF_PERSYSCALL_MASK
524 #ifdef CONFIG_IBM405_ERR77
530 4: /* Anything which requires enabling interrupts? */
531 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
534 /* Re-enable interrupts. There is no need to trace that with
535 * lockdep as we are supposed to have IRQs on at this point
541 /* Save NVGPRS if they're not saved already */
549 addi r3,r1,STACK_FRAME_OVERHEAD
550 bl do_syscall_trace_leave
551 b ret_from_except_full
554 * The fork/clone functions need to copy the full register set into
555 * the child process. Therefore we need to save all the nonvolatile
556 * registers (r13 - r31) before calling the C code.
562 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
563 stw r0,_TRAP(r1) /* register set saved */
570 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
571 stw r0,_TRAP(r1) /* register set saved */
578 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
579 stw r0,_TRAP(r1) /* register set saved */
582 .globl ppc_swapcontext
586 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
587 stw r0,_TRAP(r1) /* register set saved */
591 * Top-level page fault handling.
592 * This is in assembler because if do_page_fault tells us that
593 * it is a bad kernel page fault, we want to save the non-volatile
594 * registers before calling bad_page_fault.
596 .globl handle_page_fault
599 addi r3,r1,STACK_FRAME_OVERHEAD
600 #ifdef CONFIG_PPC_BOOK3S_32
601 andis. r0,r5,DSISR_DABRMATCH@h
602 bne- handle_dabr_fault
612 addi r3,r1,STACK_FRAME_OVERHEAD
615 b ret_from_except_full
617 #ifdef CONFIG_PPC_BOOK3S_32
618 /* We have a data breakpoint exception - handle it */
625 b ret_from_except_full
629 * This routine switches between two different tasks. The process
630 * state of one is saved on its kernel stack. Then the state
631 * of the other is restored from its kernel stack. The memory
632 * management hardware is updated to the second process's state.
633 * Finally, we can return to the second process.
634 * On entry, r3 points to the THREAD for the current task, r4
635 * points to the THREAD for the new task.
637 * This routine is always called with interrupts disabled.
639 * Note: there are two ways to get to the "going out" portion
640 * of this code; either by coming in via the entry (_switch)
641 * or via "fork" which must set up an environment equivalent
642 * to the "_switch" path. If you change this , you'll have to
643 * change the fork code also.
645 * The code which creates the new task context is in 'copy_thread'
646 * in arch/ppc/kernel/process.c
649 stwu r1,-INT_FRAME_SIZE(r1)
651 stw r0,INT_FRAME_SIZE+4(r1)
652 /* r3-r12 are caller saved -- Cort */
654 stw r0,_NIP(r1) /* Return to switch caller */
656 li r0,MSR_FP /* Disable floating-point */
657 #ifdef CONFIG_ALTIVEC
659 oris r0,r0,MSR_VEC@h /* Disable altivec */
660 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
661 stw r12,THREAD+THREAD_VRSAVE(r2)
662 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
663 #endif /* CONFIG_ALTIVEC */
666 oris r0,r0,MSR_SPE@h /* Disable SPE */
667 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
668 stw r12,THREAD+THREAD_SPEFSCR(r2)
669 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
670 #endif /* CONFIG_SPE */
671 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
679 stw r1,KSP(r3) /* Set old stack pointer */
682 /* We need a sync somewhere here to make sure that if the
683 * previous task gets rescheduled on another CPU, it sees all
684 * stores it has performed on this one.
687 #endif /* CONFIG_SMP */
690 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
691 lwz r1,KSP(r4) /* Load new stack pointer */
693 /* save the old current 'last' for return value */
695 addi r2,r4,-THREAD /* Update current */
697 #ifdef CONFIG_ALTIVEC
699 lwz r0,THREAD+THREAD_VRSAVE(r2)
700 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
701 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
702 #endif /* CONFIG_ALTIVEC */
705 lwz r0,THREAD+THREAD_SPEFSCR(r2)
706 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
707 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
708 #endif /* CONFIG_SPE */
712 /* r3-r12 are destroyed -- Cort */
715 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
717 addi r1,r1,INT_FRAME_SIZE
720 .globl fast_exception_return
721 fast_exception_return:
722 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
723 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
724 beq 1f /* if not, we've got problems */
727 2: REST_4GPRS(3, r11)
733 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
737 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
748 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
749 /* check if the exception happened in a restartable section */
750 1: lis r3,exc_exit_restart_end@ha
751 addi r3,r3,exc_exit_restart_end@l
754 lis r4,exc_exit_restart@ha
755 addi r4,r4,exc_exit_restart@l
758 lis r3,fee_restarts@ha
760 lwz r5,fee_restarts@l(r3)
762 stw r5,fee_restarts@l(r3)
763 mr r12,r4 /* restart at exc_exit_restart */
772 /* aargh, a nonrecoverable interrupt, panic */
773 /* aargh, we don't know which trap this is */
774 /* but the 601 doesn't implement the RI bit, so assume it's OK */
778 END_FTR_SECTION_IFSET(CPU_FTR_601)
781 addi r3,r1,STACK_FRAME_OVERHEAD
783 ori r10,r10,MSR_KERNEL@l
784 bl transfer_to_handler_full
785 .long unrecoverable_exception
786 .long ret_from_except
789 .globl ret_from_except_full
790 ret_from_except_full:
794 .globl ret_from_except
796 /* Hard-disable interrupts so that current_thread_info()->flags
797 * can't change between when we test it and when we return
798 * from the interrupt. */
799 /* Note: We don't bother telling lockdep about it */
800 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
801 SYNC /* Some chip revs have problems here... */
802 MTMSRD(r10) /* disable interrupts */
804 lwz r3,_MSR(r1) /* Returning to user mode? */
808 user_exc_return: /* r10 contains MSR_KERNEL here */
809 /* Check current_thread_info()->flags */
811 andi. r0,r9,_TIF_USER_WORK_MASK
815 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
816 /* Check whether this process has its own DBCR0 value. The internal
817 debug mode bit tells us that dbcr0 should be loaded. */
818 lwz r0,THREAD+THREAD_DBCR0(r2)
819 andis. r10,r0,DBCR0_IDM@h
822 ACCOUNT_CPU_USER_EXIT(r2, r10, r11)
826 /* N.B. the only way to get here is from the beq following ret_from_except. */
828 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
830 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
833 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
836 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
837 mr r4,r1 /* src: current exception frame */
838 mr r1,r3 /* Reroute the trampoline frame to r1 */
840 /* Copy from the original to the trampoline. */
841 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
842 li r6,0 /* start offset: 0 */
849 /* Do real store operation to complete stwu */
853 /* Clear _TIF_EMULATE_STACK_STORE flag */
854 lis r11,_TIF_EMULATE_STACK_STORE@h
858 #ifdef CONFIG_IBM405_ERR77
865 #ifdef CONFIG_PREEMPT
866 /* check current_thread_info->preempt_count */
867 lwz r0,TI_PREEMPT(r2)
868 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
870 andi. r8,r8,_TIF_NEED_RESCHED
873 andi. r0,r3,MSR_EE /* interrupts off? */
874 beq restore /* don't schedule if so */
875 #ifdef CONFIG_TRACE_IRQFLAGS
876 /* Lockdep thinks irqs are enabled, we need to call
877 * preempt_schedule_irq with IRQs off, so we inform lockdep
878 * now that we -did- turn them off already
880 bl trace_hardirqs_off
882 1: bl preempt_schedule_irq
884 andi. r0,r3,_TIF_NEED_RESCHED
886 #ifdef CONFIG_TRACE_IRQFLAGS
887 /* And now, to properly rebalance the above, we tell lockdep they
888 * are being turned back on, which will happen when we return
892 #endif /* CONFIG_PREEMPT */
894 /* interrupts are hard-disabled at this point */
897 BEGIN_MMU_FTR_SECTION
899 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
900 lis r4,icache_44x_need_flush@ha
901 lwz r5,icache_44x_need_flush@l(r4)
906 stw r6,icache_44x_need_flush@l(r4)
908 #endif /* CONFIG_44x */
911 #ifdef CONFIG_TRACE_IRQFLAGS
912 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
913 * off in this assembly code while peeking at TI_FLAGS() and such. However
914 * we need to inform it if the exception turned interrupts off, and we
915 * are about to trun them back on.
917 * The problem here sadly is that we don't know whether the exceptions was
918 * one that turned interrupts off or not. So we always tell lockdep about
919 * turning them on here when we go back to wherever we came from with EE
920 * on, even if that may meen some redudant calls being tracked. Maybe later
921 * we could encode what the exception did somewhere or test the exception
922 * type in the pt_regs but that sounds overkill
927 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
928 * which is the stack frame here, we need to force a stack frame
929 * in case we came from user space.
940 #endif /* CONFIG_TRACE_IRQFLAGS */
955 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
956 stwcx. r0,0,r1 /* to clear the reservation */
958 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
959 andi. r10,r9,MSR_RI /* check if this exception occurred */
960 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
967 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
971 * Once we put values in SRR0 and SRR1, we are in a state
972 * where exceptions are not recoverable, since taking an
973 * exception will trash SRR0 and SRR1. Therefore we clear the
974 * MSR:RI bit to indicate this. If we do take an exception,
975 * we can't return to the point of the exception but we
976 * can restart the exception exit path at the label
977 * exc_exit_restart below. -- paulus
979 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
981 MTMSRD(r10) /* clear the RI bit */
982 .globl exc_exit_restart
989 .globl exc_exit_restart_end
990 exc_exit_restart_end:
994 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
996 * This is a bit different on 4xx/Book-E because it doesn't have
997 * the RI bit in the MSR.
998 * The TLB miss handler checks if we have interrupted
999 * the exception exit path and restarts it if so
1000 * (well maybe one day it will... :).
1006 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1010 .globl exc_exit_restart
1019 .globl exc_exit_restart_end
1020 exc_exit_restart_end:
1023 b . /* prevent prefetch past rfi */
1026 * Returning from a critical interrupt in user mode doesn't need
1027 * to be any different from a normal exception. For a critical
1028 * interrupt in the kernel, we just return (without checking for
1029 * preemption) since the interrupt may have happened at some crucial
1030 * place (e.g. inside the TLB miss handler), and because we will be
1031 * running with r1 pointing into critical_stack, not the current
1032 * process's kernel stack (and therefore current_thread_info() will
1033 * give the wrong answer).
1034 * We have to restore various SPRs that may have been in use at the
1035 * time of the critical interrupt.
1039 #define PPC_40x_TURN_OFF_MSR_DR \
1040 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1041 * assume the instructions here are mapped by a pinned TLB entry */ \
1047 #define PPC_40x_TURN_OFF_MSR_DR
1050 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1053 andi. r3,r3,MSR_PR; \
1054 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1055 bne user_exc_return; \
1058 REST_4GPRS(3, r1); \
1059 REST_2GPRS(7, r1); \
1062 mtspr SPRN_XER,r10; \
1064 PPC405_ERR77(0,r1); \
1065 stwcx. r0,0,r1; /* to clear the reservation */ \
1066 lwz r11,_LINK(r1); \
1070 PPC_40x_TURN_OFF_MSR_DR; \
1073 mtspr SPRN_DEAR,r9; \
1074 mtspr SPRN_ESR,r10; \
1077 mtspr exc_lvl_srr0,r11; \
1078 mtspr exc_lvl_srr1,r12; \
1080 lwz r12,GPR12(r1); \
1081 lwz r10,GPR10(r1); \
1082 lwz r11,GPR11(r1); \
1084 PPC405_ERR77_SYNC; \
1086 b .; /* prevent prefetch past exc_lvl_rfi */
1088 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1089 lwz r9,_##exc_lvl_srr0(r1); \
1090 lwz r10,_##exc_lvl_srr1(r1); \
1091 mtspr SPRN_##exc_lvl_srr0,r9; \
1092 mtspr SPRN_##exc_lvl_srr1,r10;
1094 #if defined(CONFIG_PPC_BOOK3E_MMU)
1095 #ifdef CONFIG_PHYS_64BIT
1096 #define RESTORE_MAS7 \
1098 mtspr SPRN_MAS7,r11;
1100 #define RESTORE_MAS7
1101 #endif /* CONFIG_PHYS_64BIT */
1102 #define RESTORE_MMU_REGS \
1106 mtspr SPRN_MAS0,r9; \
1108 mtspr SPRN_MAS1,r10; \
1110 mtspr SPRN_MAS2,r11; \
1111 mtspr SPRN_MAS3,r9; \
1112 mtspr SPRN_MAS6,r10; \
1114 #elif defined(CONFIG_44x)
1115 #define RESTORE_MMU_REGS \
1117 mtspr SPRN_MMUCR,r9;
1119 #define RESTORE_MMU_REGS
1123 .globl ret_from_crit_exc
1125 mfspr r9,SPRN_SPRG_THREAD
1126 lis r10,saved_ksp_limit@ha;
1127 lwz r10,saved_ksp_limit@l(r10);
1129 stw r10,KSP_LIMIT(r9)
1130 lis r9,crit_srr0@ha;
1131 lwz r9,crit_srr0@l(r9);
1132 lis r10,crit_srr1@ha;
1133 lwz r10,crit_srr1@l(r10);
1135 mtspr SPRN_SRR1,r10;
1136 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1137 #endif /* CONFIG_40x */
1140 .globl ret_from_crit_exc
1142 mfspr r9,SPRN_SPRG_THREAD
1143 lwz r10,SAVED_KSP_LIMIT(r1)
1144 stw r10,KSP_LIMIT(r9)
1145 RESTORE_xSRR(SRR0,SRR1);
1147 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1149 .globl ret_from_debug_exc
1151 mfspr r9,SPRN_SPRG_THREAD
1152 lwz r10,SAVED_KSP_LIMIT(r1)
1153 stw r10,KSP_LIMIT(r9)
1154 RESTORE_xSRR(SRR0,SRR1);
1155 RESTORE_xSRR(CSRR0,CSRR1);
1157 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1159 .globl ret_from_mcheck_exc
1160 ret_from_mcheck_exc:
1161 mfspr r9,SPRN_SPRG_THREAD
1162 lwz r10,SAVED_KSP_LIMIT(r1)
1163 stw r10,KSP_LIMIT(r9)
1164 RESTORE_xSRR(SRR0,SRR1);
1165 RESTORE_xSRR(CSRR0,CSRR1);
1166 RESTORE_xSRR(DSRR0,DSRR1);
1168 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1169 #endif /* CONFIG_BOOKE */
1172 * Load the DBCR0 value for a task that is being ptraced,
1173 * having first saved away the global DBCR0. Note that r0
1174 * has the dbcr0 value to set upon entry to this.
1177 mfmsr r10 /* first disable debug exceptions */
1178 rlwinm r10,r10,0,~MSR_DE
1181 mfspr r10,SPRN_DBCR0
1182 lis r11,global_dbcr0@ha
1183 addi r11,r11,global_dbcr0@l
1195 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1203 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1205 do_work: /* r10 contains MSR_KERNEL here */
1206 andi. r0,r9,_TIF_NEED_RESCHED
1209 do_resched: /* r10 contains MSR_KERNEL here */
1210 /* Note: We don't need to inform lockdep that we are enabling
1211 * interrupts here. As far as it knows, they are already enabled
1215 MTMSRD(r10) /* hard-enable interrupts */
1218 /* Note: And we don't tell it we are disabling them again
1219 * neither. Those disable/enable cycles used to peek at
1220 * TI_FLAGS aren't advertised.
1222 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1224 MTMSRD(r10) /* disable interrupts */
1226 andi. r0,r9,_TIF_NEED_RESCHED
1228 andi. r0,r9,_TIF_USER_WORK_MASK
1230 do_user_signal: /* r10 contains MSR_KERNEL here */
1233 MTMSRD(r10) /* hard-enable interrupts */
1234 /* save r13-r31 in the exception frame, if not already done */
1241 2: addi r3,r1,STACK_FRAME_OVERHEAD
1248 * We come here when we are at the end of handling an exception
1249 * that occurred at a place where taking an exception will lose
1250 * state information, such as the contents of SRR0 and SRR1.
1253 lis r10,exc_exit_restart_end@ha
1254 addi r10,r10,exc_exit_restart_end@l
1257 lis r11,exc_exit_restart@ha
1258 addi r11,r11,exc_exit_restart@l
1261 lis r10,ee_restarts@ha
1262 lwz r12,ee_restarts@l(r10)
1264 stw r12,ee_restarts@l(r10)
1265 mr r12,r11 /* restart at exc_exit_restart */
1267 3: /* OK, we can't recover, kill this process */
1268 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1271 END_FTR_SECTION_IFSET(CPU_FTR_601)
1278 5: mfspr r2,SPRN_SPRG_THREAD
1280 tovirt(r2,r2) /* set back r2 to current */
1281 4: addi r3,r1,STACK_FRAME_OVERHEAD
1282 bl unrecoverable_exception
1283 /* shouldn't return */
1293 * PROM code for specific machines follows. Put it
1294 * here so it's easy to add arch-specific sections later.
1297 #ifdef CONFIG_PPC_RTAS
1299 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1300 * called with the MMU off.
1303 stwu r1,-INT_FRAME_SIZE(r1)
1305 stw r0,INT_FRAME_SIZE+4(r1)
1306 LOAD_REG_ADDR(r4, rtas)
1307 lis r6,1f@ha /* physical return address for rtas */
1311 lwz r8,RTASENTRY(r4)
1315 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1316 SYNC /* disable interrupts so SRR0/1 */
1317 MTMSRD(r0) /* don't get trashed */
1318 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1320 stw r7, THREAD + RTAS_SP(r2)
1325 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1326 lwz r9,8(r9) /* original msr value */
1327 addi r1,r1,INT_FRAME_SIZE
1330 stw r0, THREAD + RTAS_SP(r7)
1333 RFI /* return to caller */
1335 .globl machine_check_in_rtas
1336 machine_check_in_rtas:
1338 /* XXX load up BATs and panic */
1340 #endif /* CONFIG_PPC_RTAS */