1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/barrier.h>
35 #include <asm/interrupt.h>
40 * powerpc relies on return from interrupt/syscall being context synchronising
41 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
42 * synchronisation instructions.
46 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
47 * fit into one page in order to not encounter a TLB miss between the
48 * modification of srr0/srr1 and the associated rfi.
52 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
53 .globl prepare_transfer_to_handler
54 prepare_transfer_to_handler:
55 /* if from kernel, check interrupted DOZE/NAP mode */
56 lwz r12,TI_LOCAL_FLAGS(r2)
59 bt- 31-TLF_SLEEPING,7f
62 4: rlwinm r12,r12,0,~_TLF_NAPPING
63 stw r12,TI_LOCAL_FLAGS(r2)
64 b power_save_ppc32_restore
66 7: rlwinm r12,r12,0,~_TLF_SLEEPING
67 stw r12,TI_LOCAL_FLAGS(r2)
68 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
69 rlwinm r9,r9,0,~MSR_EE
70 lwz r12,_LINK(r11) /* and return to address in LR */
72 b fast_exception_return
73 _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
74 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
76 .globl transfer_to_syscall
82 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
83 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
85 lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
87 addi r12,r12,STACK_FRAME_REGS_MARKER@l
89 li r2, INTERRUPT_SYSCALL
98 /* Calling convention has r9 = orig r0, r10 = regs */
99 addi r10,r1,STACK_FRAME_OVERHEAD
101 bl system_call_exception
104 addi r4,r1,STACK_FRAME_OVERHEAD
106 bl syscall_exit_prepare
107 #ifdef CONFIG_PPC_47x
108 lis r4,icache_44x_need_flush@ha
109 lwz r5,icache_44x_need_flush@l(r4)
112 #endif /* CONFIG_PPC_47x */
131 b . /* Prevent prefetch past rfi */
149 stw r7,icache_44x_need_flush@l(r4)
151 #endif /* CONFIG_44x */
160 .globl ret_from_kernel_thread
161 ret_from_kernel_thread:
172 * This routine switches between two different tasks. The process
173 * state of one is saved on its kernel stack. Then the state
174 * of the other is restored from its kernel stack. The memory
175 * management hardware is updated to the second process's state.
176 * Finally, we can return to the second process.
177 * On entry, r3 points to the THREAD for the current task, r4
178 * points to the THREAD for the new task.
180 * This routine is always called with interrupts disabled.
182 * Note: there are two ways to get to the "going out" portion
183 * of this code; either by coming in via the entry (_switch)
184 * or via "fork" which must set up an environment equivalent
185 * to the "_switch" path. If you change this , you'll have to
186 * change the fork code also.
188 * The code which creates the new task context is in 'copy_thread'
189 * in arch/ppc/kernel/process.c
192 stwu r1,-INT_FRAME_SIZE(r1)
194 stw r0,INT_FRAME_SIZE+4(r1)
195 /* r3-r12 are caller saved -- Cort */
197 stw r0,_NIP(r1) /* Return to switch caller */
200 stw r1,KSP(r3) /* Set old stack pointer */
203 /* We need a sync somewhere here to make sure that if the
204 * previous task gets rescheduled on another CPU, it sees all
205 * stores it has performed on this one.
208 #endif /* CONFIG_SMP */
211 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
212 lwz r1,KSP(r4) /* Load new stack pointer */
214 /* save the old current 'last' for return value */
216 addi r2,r4,-THREAD /* Update current */
220 /* r3-r12 are destroyed -- Cort */
223 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
225 addi r1,r1,INT_FRAME_SIZE
228 .globl fast_exception_return
229 fast_exception_return:
230 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
231 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
232 beq 3f /* if not, we've got problems */
235 2: REST_4GPRS(3, r11)
241 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
245 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
255 b . /* Prevent prefetch past rfi */
257 _ASM_NOKPROBE_SYMBOL(fast_exception_return)
259 /* aargh, a nonrecoverable interrupt, panic */
260 /* aargh, we don't know which trap this is */
264 prepare_transfer_to_handler
265 bl unrecoverable_exception
266 trap /* should not get here */
268 .globl interrupt_return
271 addi r3,r1,STACK_FRAME_OVERHEAD
273 beq .Lkernel_interrupt_return
274 bl interrupt_exit_user_prepare
276 bne- .Lrestore_nvgprs
278 .Lfast_user_interrupt_return:
285 stwcx. r0,0,r1 /* to clear the reservation */
288 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
297 * Leaving a stale exception_marker on the stack can confuse
298 * the reliable stack unwinder later on. Clear it.
315 b . /* Prevent prefetch past rfi */
320 b .Lfast_user_interrupt_return
322 .Lkernel_interrupt_return:
323 bl interrupt_exit_kernel_prepare
325 .Lfast_kernel_interrupt_return:
333 stwcx. r0,0,r1 /* to clear the reservation */
336 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
352 * Leaving a stale exception_marker on the stack can confuse
353 * the reliable stack unwinder later on. Clear it.
359 bne- cr1,1f /* emulate stack store */
366 b . /* Prevent prefetch past rfi */
370 * Emulate stack store with update. New r1 value was already calculated
371 * and updated in our interrupt regs by emulate_loadstore, but we can't
372 * store the previous value of r1 to the stack before re-loading our
373 * registers from it, otherwise they could be clobbered. Use
374 * SPRG Scratch0 as temporary storage to hold the store
375 * data, as interrupts are disabled here so it won't be clobbered.
379 mtspr SPRN_SPRG_WSCRATCH0, r9
381 mtspr SPRN_SPRG_SCRATCH0, r9
383 addi r9,r1,INT_FRAME_SIZE /* get original r1 */
387 stw r9,0(r1) /* perform store component of stwu */
389 mfspr r9, SPRN_SPRG_RSCRATCH0
391 mfspr r9, SPRN_SPRG_SCRATCH0
395 b . /* Prevent prefetch past rfi */
397 _ASM_NOKPROBE_SYMBOL(interrupt_return)
399 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
402 * Returning from a critical interrupt in user mode doesn't need
403 * to be any different from a normal exception. For a critical
404 * interrupt in the kernel, we just return (without checking for
405 * preemption) since the interrupt may have happened at some crucial
406 * place (e.g. inside the TLB miss handler), and because we will be
407 * running with r1 pointing into critical_stack, not the current
408 * process's kernel stack (and therefore current_thread_info() will
409 * give the wrong answer).
410 * We have to restore various SPRs that may have been in use at the
411 * time of the critical interrupt.
415 #define PPC_40x_TURN_OFF_MSR_DR \
416 /* avoid any possible TLB misses here by turning off MSR.DR, we \
417 * assume the instructions here are mapped by a pinned TLB entry */ \
423 #define PPC_40x_TURN_OFF_MSR_DR
426 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
429 andi. r3,r3,MSR_PR; \
430 bne interrupt_return; \
437 mtspr SPRN_XER,r10; \
439 stwcx. r0,0,r1; /* to clear the reservation */ \
444 PPC_40x_TURN_OFF_MSR_DR; \
447 mtspr SPRN_DEAR,r9; \
448 mtspr SPRN_ESR,r10; \
451 mtspr exc_lvl_srr0,r11; \
452 mtspr exc_lvl_srr1,r12; \
459 b .; /* prevent prefetch past exc_lvl_rfi */
461 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
462 lwz r9,_##exc_lvl_srr0(r1); \
463 lwz r10,_##exc_lvl_srr1(r1); \
464 mtspr SPRN_##exc_lvl_srr0,r9; \
465 mtspr SPRN_##exc_lvl_srr1,r10;
467 #if defined(CONFIG_PPC_BOOK3E_MMU)
468 #ifdef CONFIG_PHYS_64BIT
469 #define RESTORE_MAS7 \
474 #endif /* CONFIG_PHYS_64BIT */
475 #define RESTORE_MMU_REGS \
479 mtspr SPRN_MAS0,r9; \
481 mtspr SPRN_MAS1,r10; \
483 mtspr SPRN_MAS2,r11; \
484 mtspr SPRN_MAS3,r9; \
485 mtspr SPRN_MAS6,r10; \
487 #elif defined(CONFIG_44x)
488 #define RESTORE_MMU_REGS \
492 #define RESTORE_MMU_REGS
496 .globl ret_from_crit_exc
499 lwz r9,crit_srr0@l(r9);
500 lis r10,crit_srr1@ha;
501 lwz r10,crit_srr1@l(r10);
504 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
505 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
506 #endif /* CONFIG_40x */
509 .globl ret_from_crit_exc
511 RESTORE_xSRR(SRR0,SRR1);
513 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
514 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
516 .globl ret_from_debug_exc
518 RESTORE_xSRR(SRR0,SRR1);
519 RESTORE_xSRR(CSRR0,CSRR1);
521 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
522 _ASM_NOKPROBE_SYMBOL(ret_from_debug_exc)
524 .globl ret_from_mcheck_exc
526 RESTORE_xSRR(SRR0,SRR1);
527 RESTORE_xSRR(CSRR0,CSRR1);
528 RESTORE_xSRR(DSRR0,DSRR1);
530 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
531 _ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
532 #endif /* CONFIG_BOOKE */
533 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
536 * PROM code for specific machines follows. Put it
537 * here so it's easy to add arch-specific sections later.
540 #ifdef CONFIG_PPC_RTAS
542 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
543 * called with the MMU off.
546 stwu r1,-INT_FRAME_SIZE(r1)
548 stw r0,INT_FRAME_SIZE+4(r1)
549 LOAD_REG_ADDR(r4, rtas)
550 lis r6,1f@ha /* physical return address for rtas */
557 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
558 mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */
559 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
561 stw r1, THREAD + RTAS_SP(r2)
568 LOAD_REG_IMMEDIATE(r9,MSR_KERNEL)
571 rfi /* Reactivate MMU translation */
573 lwz r8,INT_FRAME_SIZE+4(r1) /* get return address */
574 lwz r9,8(r1) /* original msr value */
575 addi r1,r1,INT_FRAME_SIZE
577 stw r0, THREAD + RTAS_SP(r2)
580 blr /* return to caller */
581 _ASM_NOKPROBE_SYMBOL(enter_rtas)
582 #endif /* CONFIG_PPC_RTAS */