1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/barrier.h>
39 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
40 * fit into one page in order to not encounter a TLB miss between the
41 * modification of srr0/srr1 and the associated rfi.
46 .globl mcheck_transfer_to_handler
47 mcheck_transfer_to_handler:
54 .globl debug_transfer_to_handler
55 debug_transfer_to_handler:
62 .globl crit_transfer_to_handler
63 crit_transfer_to_handler:
64 #ifdef CONFIG_PPC_BOOK3E_MMU
75 #ifdef CONFIG_PHYS_64BIT
78 #endif /* CONFIG_PHYS_64BIT */
79 #endif /* CONFIG_PPC_BOOK3E_MMU */
89 /* set the stack limit to the current stack */
90 mfspr r8,SPRN_SPRG_THREAD
92 stw r0,SAVED_KSP_LIMIT(r11)
93 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
99 .globl crit_transfer_to_handler
100 crit_transfer_to_handler:
106 stw r0,crit_srr0@l(0)
108 stw r0,crit_srr1@l(0)
110 /* set the stack limit to the current stack */
111 mfspr r8,SPRN_SPRG_THREAD
113 stw r0,saved_ksp_limit@l(0)
114 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
120 * This code finishes saving the registers to the exception frame
121 * and jumps to the appropriate handler for the exception, turning
122 * on address translation.
123 * Note that we rely on the caller having set cr0.eq iff the exception
124 * occurred in kernel mode (i.e. MSR:PR = 0).
126 .globl transfer_to_handler_full
127 transfer_to_handler_full:
131 .globl transfer_to_handler
141 mfspr r12,SPRN_SPRG_THREAD
142 tovirt_vmstack r12, r12
143 beq 2f /* if from user, fix up THREAD.regs */
144 addi r2, r12, -THREAD
145 addi r11,r1,STACK_FRAME_OVERHEAD
147 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
148 /* Check to see if the dbcr0 register is set up to debug. Use the
149 internal debug mode bit to do this. */
150 lwz r12,THREAD_DBCR0(r12)
151 andis. r12,r12,DBCR0_IDM@h
153 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
154 #ifdef CONFIG_PPC_BOOK3S_32
157 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
159 /* From user and task is ptraced - load up global dbcr0 */
160 li r12,-1 /* clear all pending debug events */
162 lis r11,global_dbcr0@ha
164 addi r11,r11,global_dbcr0@l
179 2: /* if from kernel, check interrupted DOZE/NAP mode and
180 * check for stack overflow
182 kuap_save_and_lock r11, r12, r9, r2, r6
183 addi r2, r12, -THREAD
184 #ifndef CONFIG_VMAP_STACK
185 lwz r9,KSP_LIMIT(r12)
186 cmplw r1,r9 /* if r1 <= ksp_limit */
187 ble- stack_ovf /* then the kernel stack overflowed */
190 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
191 lwz r12,TI_LOCAL_FLAGS(r2)
193 bt- 31-TLF_NAPPING,4f
194 bt- 31-TLF_SLEEPING,7f
195 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
196 .globl transfer_to_handler_cont
197 transfer_to_handler_cont:
200 tovirt_novmstack r2, r2 /* set r2 to current */
201 tovirt_vmstack r9, r9
202 lwz r11,0(r9) /* virtual address of handler */
203 lwz r9,4(r9) /* where to go when done */
204 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
207 #ifdef CONFIG_TRACE_IRQFLAGS
209 * When tracing IRQ state (lockdep) we enable the MMU before we call
210 * the IRQ tracing functions as they might access vmalloc space or
211 * perform IOs for console output.
213 * To speed up the syscall path where interrupts stay on, let's check
214 * first if we are changing the MSR value at all.
216 tophys_novmstack r12, r1
221 /* MSR isn't changing, just transition directly */
227 RFI /* jump to handler, enable MMU */
229 #ifdef CONFIG_TRACE_IRQFLAGS
230 1: /* MSR is changing, re-enable MMU so we can notify lockdep. We need to
231 * keep interrupts disabled at this point otherwise we might risk
232 * taking an interrupt before we tell lockdep they are enabled.
234 lis r12,reenable_mmu@h
235 ori r12,r12,reenable_mmu@l
236 LOAD_REG_IMMEDIATE(r0, MSR_KERNEL)
244 * We save a bunch of GPRs,
245 * r3 can be different from GPR3(r1) at this point, r9 and r11
246 * contains the old MSR and handler address respectively,
247 * r4 & r5 can contain page fault arguments that need to be passed
248 * along as well. r0, r6-r8, r12, CCR, CTR, XER etc... are left
249 * clobbered as they aren't useful past this point.
259 /* If we are disabling interrupts (normal case), simply log it with
262 1: bl trace_hardirqs_off
271 bctr /* jump to handler */
272 #endif /* CONFIG_TRACE_IRQFLAGS */
274 #if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
275 4: rlwinm r12,r12,0,~_TLF_NAPPING
276 stw r12,TI_LOCAL_FLAGS(r2)
277 b power_save_ppc32_restore
279 7: rlwinm r12,r12,0,~_TLF_SLEEPING
280 stw r12,TI_LOCAL_FLAGS(r2)
281 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
282 rlwinm r9,r9,0,~MSR_EE
283 lwz r12,_LINK(r11) /* and return to address in LR */
284 kuap_restore r11, r2, r3, r4, r5
286 b fast_exception_return
289 #ifndef CONFIG_VMAP_STACK
291 * On kernel stack overflow, load up an initial stack pointer
292 * and call StackOverflow(regs), which should not return.
295 /* sometimes we use a statically-allocated stack, which is OK. */
299 ble 5b /* r1 <= &_end is OK */
301 addi r3,r1,STACK_FRAME_OVERHEAD
302 lis r1,init_thread_union@ha
303 addi r1,r1,init_thread_union@l
304 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
305 lis r9,StackOverflow@ha
306 addi r9,r9,StackOverflow@l
307 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
308 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
317 #ifdef CONFIG_TRACE_IRQFLAGS
318 trace_syscall_entry_irq_off:
320 * Syscall shouldn't happen while interrupts are disabled,
321 * so let's do a warning here.
324 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
327 /* Now enable for real */
328 LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
335 #endif /* CONFIG_TRACE_IRQFLAGS */
337 .globl transfer_to_syscall
339 #ifdef CONFIG_TRACE_IRQFLAGS
341 beq- trace_syscall_entry_irq_off
342 #endif /* CONFIG_TRACE_IRQFLAGS */
345 * Handle a system call.
347 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
348 .stabs "entry_32.S",N_SO,0,0,0f
355 #ifdef CONFIG_TRACE_IRQFLAGS
356 /* Make sure interrupts are enabled */
359 /* We came in with interrupts disabled, we WARN and mark them enabled
362 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
363 #endif /* CONFIG_TRACE_IRQFLAGS */
365 andi. r11,r11,_TIF_SYSCALL_DOTRACE
367 syscall_dotrace_cont:
368 cmplwi 0,r0,NR_syscalls
369 lis r10,sys_call_table@h
370 ori r10,r10,sys_call_table@l
376 * Prevent the load of the handler below (based on the user-passed
377 * system call number) being speculatively executed until the test
378 * against NR_syscalls and branch to .66f above has
382 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
384 addi r9,r1,STACK_FRAME_OVERHEAD
386 blrl /* Call handler */
387 .globl ret_from_syscall
389 #ifdef CONFIG_DEBUG_RSEQ
390 /* Check whether the syscall is issued inside a restartable sequence */
392 addi r3,r1,STACK_FRAME_OVERHEAD
397 /* disable interrupts so current_thread_info()->flags can't change */
398 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */
399 /* Note: We don't bother telling lockdep about it */
404 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
405 bne- syscall_exit_work
407 blt+ syscall_exit_cont
408 lwz r11,_CCR(r1) /* Load CR */
410 oris r11,r11,0x1000 /* Set SO bit in CR */
414 #ifdef CONFIG_TRACE_IRQFLAGS
415 /* If we are going to return from the syscall with interrupts
416 * off, we trace that here. It shouldn't normally happen.
421 bl trace_hardirqs_off
424 #endif /* CONFIG_TRACE_IRQFLAGS */
425 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
426 /* If the process has its own DBCR0 value, load it up. The internal
427 debug mode bit tells us that dbcr0 should be loaded. */
428 lwz r0,THREAD+THREAD_DBCR0(r2)
429 andis. r10,r0,DBCR0_IDM@h
433 BEGIN_MMU_FTR_SECTION
434 lis r4,icache_44x_need_flush@ha
435 lwz r5,icache_44x_need_flush@l(r4)
439 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
440 #endif /* CONFIG_44x */
443 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
444 stwcx. r0,0,r1 /* to clear the reservation */
445 ACCOUNT_CPU_USER_EXIT(r2, r5, r7)
446 #ifdef CONFIG_PPC_BOOK3S_32
457 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
467 stw r7,icache_44x_need_flush@l(r4)
469 #endif /* CONFIG_44x */
481 .globl ret_from_kernel_thread
482 ret_from_kernel_thread:
492 /* Traced system call support */
497 addi r3,r1,STACK_FRAME_OVERHEAD
498 bl do_syscall_trace_enter
500 * Restore argument registers possibly just changed.
501 * We use the return value of do_syscall_trace_enter
502 * for call number to look up in the table (r0).
513 cmplwi r0,NR_syscalls
514 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
515 bge- ret_from_syscall
516 b syscall_dotrace_cont
519 andi. r0,r9,_TIF_RESTOREALL
525 andi. r0,r9,_TIF_NOERROR
527 lwz r11,_CCR(r1) /* Load CR */
529 oris r11,r11,0x1000 /* Set SO bit in CR */
532 1: stw r6,RESULT(r1) /* Save result */
533 stw r3,GPR3(r1) /* Update return value */
534 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
537 /* Clear per-syscall TIF flags if any are set. */
539 li r11,_TIF_PERSYSCALL_MASK
546 4: /* Anything which requires enabling interrupts? */
547 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
550 /* Re-enable interrupts. There is no need to trace that with
551 * lockdep as we are supposed to have IRQs on at this point
557 /* Save NVGPRS if they're not saved already */
565 addi r3,r1,STACK_FRAME_OVERHEAD
566 bl do_syscall_trace_leave
567 b ret_from_except_full
570 * System call was called from kernel. We get here with SRR1 in r9.
571 * Mark the exception as recoverable once we have retrieved SRR0,
572 * trap a warning and return ENOSYS with CR[SO] set.
574 .globl ret_from_kernel_syscall
575 ret_from_kernel_syscall:
578 #if !defined(CONFIG_4xx) && !defined(CONFIG_BOOKE)
579 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_IR|MSR_DR))
584 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
588 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
597 * The fork/clone functions need to copy the full register set into
598 * the child process. Therefore we need to save all the nonvolatile
599 * registers (r13 - r31) before calling the C code.
605 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
606 stw r0,_TRAP(r1) /* register set saved */
613 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
614 stw r0,_TRAP(r1) /* register set saved */
621 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
622 stw r0,_TRAP(r1) /* register set saved */
629 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
630 stw r0,_TRAP(r1) /* register set saved */
633 .globl ppc_swapcontext
637 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
638 stw r0,_TRAP(r1) /* register set saved */
642 * Top-level page fault handling.
643 * This is in assembler because if do_page_fault tells us that
644 * it is a bad kernel page fault, we want to save the non-volatile
645 * registers before calling bad_page_fault.
647 .globl handle_page_fault
649 addi r3,r1,STACK_FRAME_OVERHEAD
650 #ifdef CONFIG_PPC_BOOK3S_32
651 andis. r0,r5,DSISR_DABRMATCH@h
652 bne- handle_dabr_fault
662 addi r3,r1,STACK_FRAME_OVERHEAD
665 b ret_from_except_full
667 #ifdef CONFIG_PPC_BOOK3S_32
668 /* We have a data breakpoint exception - handle it */
675 b ret_from_except_full
679 * This routine switches between two different tasks. The process
680 * state of one is saved on its kernel stack. Then the state
681 * of the other is restored from its kernel stack. The memory
682 * management hardware is updated to the second process's state.
683 * Finally, we can return to the second process.
684 * On entry, r3 points to the THREAD for the current task, r4
685 * points to the THREAD for the new task.
687 * This routine is always called with interrupts disabled.
689 * Note: there are two ways to get to the "going out" portion
690 * of this code; either by coming in via the entry (_switch)
691 * or via "fork" which must set up an environment equivalent
692 * to the "_switch" path. If you change this , you'll have to
693 * change the fork code also.
695 * The code which creates the new task context is in 'copy_thread'
696 * in arch/ppc/kernel/process.c
699 stwu r1,-INT_FRAME_SIZE(r1)
701 stw r0,INT_FRAME_SIZE+4(r1)
702 /* r3-r12 are caller saved -- Cort */
704 stw r0,_NIP(r1) /* Return to switch caller */
706 li r0,MSR_FP /* Disable floating-point */
707 #ifdef CONFIG_ALTIVEC
709 oris r0,r0,MSR_VEC@h /* Disable altivec */
710 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
711 stw r12,THREAD+THREAD_VRSAVE(r2)
712 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
713 #endif /* CONFIG_ALTIVEC */
716 oris r0,r0,MSR_SPE@h /* Disable SPE */
717 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
718 stw r12,THREAD+THREAD_SPEFSCR(r2)
719 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
720 #endif /* CONFIG_SPE */
721 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
729 stw r1,KSP(r3) /* Set old stack pointer */
733 /* We need a sync somewhere here to make sure that if the
734 * previous task gets rescheduled on another CPU, it sees all
735 * stores it has performed on this one.
738 #endif /* CONFIG_SMP */
741 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
742 lwz r1,KSP(r4) /* Load new stack pointer */
744 /* save the old current 'last' for return value */
746 addi r2,r4,-THREAD /* Update current */
748 #ifdef CONFIG_ALTIVEC
750 lwz r0,THREAD+THREAD_VRSAVE(r2)
751 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
752 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
753 #endif /* CONFIG_ALTIVEC */
756 lwz r0,THREAD+THREAD_SPEFSCR(r2)
757 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
758 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
759 #endif /* CONFIG_SPE */
763 /* r3-r12 are destroyed -- Cort */
766 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
768 addi r1,r1,INT_FRAME_SIZE
771 .globl fast_exception_return
772 fast_exception_return:
773 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
774 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
775 beq 1f /* if not, we've got problems */
778 2: REST_4GPRS(3, r11)
784 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
788 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
799 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
800 /* check if the exception happened in a restartable section */
801 1: lis r3,exc_exit_restart_end@ha
802 addi r3,r3,exc_exit_restart_end@l
804 #ifdef CONFIG_PPC_BOOK3S_601
809 lis r4,exc_exit_restart@ha
810 addi r4,r4,exc_exit_restart@l
812 #ifdef CONFIG_PPC_BOOK3S_601
817 lis r3,fee_restarts@ha
819 lwz r5,fee_restarts@l(r3)
821 stw r5,fee_restarts@l(r3)
822 mr r12,r4 /* restart at exc_exit_restart */
831 /* aargh, a nonrecoverable interrupt, panic */
832 /* aargh, we don't know which trap this is */
833 /* but the 601 doesn't implement the RI bit, so assume it's OK */
837 addi r3,r1,STACK_FRAME_OVERHEAD
839 ori r10,r10,MSR_KERNEL@l
840 bl transfer_to_handler_full
841 .long unrecoverable_exception
842 .long ret_from_except
845 .globl ret_from_except_full
846 ret_from_except_full:
850 .globl ret_from_except
852 /* Hard-disable interrupts so that current_thread_info()->flags
853 * can't change between when we test it and when we return
854 * from the interrupt. */
855 /* Note: We don't bother telling lockdep about it */
856 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
857 SYNC /* Some chip revs have problems here... */
858 mtmsr r10 /* disable interrupts */
860 lwz r3,_MSR(r1) /* Returning to user mode? */
864 user_exc_return: /* r10 contains MSR_KERNEL here */
865 /* Check current_thread_info()->flags */
867 andi. r0,r9,_TIF_USER_WORK_MASK
871 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
872 /* Check whether this process has its own DBCR0 value. The internal
873 debug mode bit tells us that dbcr0 should be loaded. */
874 lwz r0,THREAD+THREAD_DBCR0(r2)
875 andis. r10,r0,DBCR0_IDM@h
878 ACCOUNT_CPU_USER_EXIT(r2, r10, r11)
879 #ifdef CONFIG_PPC_BOOK3S_32
885 /* N.B. the only way to get here is from the beq following ret_from_except. */
887 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
889 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
892 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
895 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
896 mr r4,r1 /* src: current exception frame */
897 mr r1,r3 /* Reroute the trampoline frame to r1 */
899 /* Copy from the original to the trampoline. */
900 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
901 li r6,0 /* start offset: 0 */
908 /* Do real store operation to complete stwu */
912 /* Clear _TIF_EMULATE_STACK_STORE flag */
913 lis r11,_TIF_EMULATE_STACK_STORE@h
921 #ifdef CONFIG_PREEMPTION
922 /* check current_thread_info->preempt_count */
923 lwz r0,TI_PREEMPT(r2)
924 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
926 andi. r8,r8,_TIF_NEED_RESCHED
929 andi. r0,r3,MSR_EE /* interrupts off? */
930 beq restore_kuap /* don't schedule if so */
931 #ifdef CONFIG_TRACE_IRQFLAGS
932 /* Lockdep thinks irqs are enabled, we need to call
933 * preempt_schedule_irq with IRQs off, so we inform lockdep
934 * now that we -did- turn them off already
936 bl trace_hardirqs_off
938 bl preempt_schedule_irq
939 #ifdef CONFIG_TRACE_IRQFLAGS
940 /* And now, to properly rebalance the above, we tell lockdep they
941 * are being turned back on, which will happen when we return
945 #endif /* CONFIG_PREEMPTION */
947 kuap_restore r1, r2, r9, r10, r0
949 /* interrupts are hard-disabled at this point */
952 BEGIN_MMU_FTR_SECTION
954 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
955 lis r4,icache_44x_need_flush@ha
956 lwz r5,icache_44x_need_flush@l(r4)
961 stw r6,icache_44x_need_flush@l(r4)
963 #endif /* CONFIG_44x */
966 #ifdef CONFIG_TRACE_IRQFLAGS
967 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
968 * off in this assembly code while peeking at TI_FLAGS() and such. However
969 * we need to inform it if the exception turned interrupts off, and we
970 * are about to trun them back on.
981 #endif /* CONFIG_TRACE_IRQFLAGS */
995 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
996 stwcx. r0,0,r1 /* to clear the reservation */
998 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
999 andi. r10,r9,MSR_RI /* check if this exception occurred */
1000 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
1007 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1011 * Once we put values in SRR0 and SRR1, we are in a state
1012 * where exceptions are not recoverable, since taking an
1013 * exception will trash SRR0 and SRR1. Therefore we clear the
1014 * MSR:RI bit to indicate this. If we do take an exception,
1015 * we can't return to the point of the exception but we
1016 * can restart the exception exit path at the label
1017 * exc_exit_restart below. -- paulus
1019 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
1021 mtmsr r10 /* clear the RI bit */
1022 .globl exc_exit_restart
1029 .globl exc_exit_restart_end
1030 exc_exit_restart_end:
1034 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1036 * This is a bit different on 4xx/Book-E because it doesn't have
1037 * the RI bit in the MSR.
1038 * The TLB miss handler checks if we have interrupted
1039 * the exception exit path and restarts it if so
1040 * (well maybe one day it will... :).
1046 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1050 .globl exc_exit_restart
1059 .globl exc_exit_restart_end
1060 exc_exit_restart_end:
1062 b . /* prevent prefetch past rfi */
1065 * Returning from a critical interrupt in user mode doesn't need
1066 * to be any different from a normal exception. For a critical
1067 * interrupt in the kernel, we just return (without checking for
1068 * preemption) since the interrupt may have happened at some crucial
1069 * place (e.g. inside the TLB miss handler), and because we will be
1070 * running with r1 pointing into critical_stack, not the current
1071 * process's kernel stack (and therefore current_thread_info() will
1072 * give the wrong answer).
1073 * We have to restore various SPRs that may have been in use at the
1074 * time of the critical interrupt.
1078 #define PPC_40x_TURN_OFF_MSR_DR \
1079 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1080 * assume the instructions here are mapped by a pinned TLB entry */ \
1086 #define PPC_40x_TURN_OFF_MSR_DR
1089 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1092 andi. r3,r3,MSR_PR; \
1093 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \
1094 bne user_exc_return; \
1097 REST_4GPRS(3, r1); \
1098 REST_2GPRS(7, r1); \
1101 mtspr SPRN_XER,r10; \
1103 stwcx. r0,0,r1; /* to clear the reservation */ \
1104 lwz r11,_LINK(r1); \
1108 PPC_40x_TURN_OFF_MSR_DR; \
1111 mtspr SPRN_DEAR,r9; \
1112 mtspr SPRN_ESR,r10; \
1115 mtspr exc_lvl_srr0,r11; \
1116 mtspr exc_lvl_srr1,r12; \
1118 lwz r12,GPR12(r1); \
1119 lwz r10,GPR10(r1); \
1120 lwz r11,GPR11(r1); \
1123 b .; /* prevent prefetch past exc_lvl_rfi */
1125 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1126 lwz r9,_##exc_lvl_srr0(r1); \
1127 lwz r10,_##exc_lvl_srr1(r1); \
1128 mtspr SPRN_##exc_lvl_srr0,r9; \
1129 mtspr SPRN_##exc_lvl_srr1,r10;
1131 #if defined(CONFIG_PPC_BOOK3E_MMU)
1132 #ifdef CONFIG_PHYS_64BIT
1133 #define RESTORE_MAS7 \
1135 mtspr SPRN_MAS7,r11;
1137 #define RESTORE_MAS7
1138 #endif /* CONFIG_PHYS_64BIT */
1139 #define RESTORE_MMU_REGS \
1143 mtspr SPRN_MAS0,r9; \
1145 mtspr SPRN_MAS1,r10; \
1147 mtspr SPRN_MAS2,r11; \
1148 mtspr SPRN_MAS3,r9; \
1149 mtspr SPRN_MAS6,r10; \
1151 #elif defined(CONFIG_44x)
1152 #define RESTORE_MMU_REGS \
1154 mtspr SPRN_MMUCR,r9;
1156 #define RESTORE_MMU_REGS
1160 .globl ret_from_crit_exc
1162 mfspr r9,SPRN_SPRG_THREAD
1163 lis r10,saved_ksp_limit@ha;
1164 lwz r10,saved_ksp_limit@l(r10);
1166 stw r10,KSP_LIMIT(r9)
1167 lis r9,crit_srr0@ha;
1168 lwz r9,crit_srr0@l(r9);
1169 lis r10,crit_srr1@ha;
1170 lwz r10,crit_srr1@l(r10);
1172 mtspr SPRN_SRR1,r10;
1173 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1174 #endif /* CONFIG_40x */
1177 .globl ret_from_crit_exc
1179 mfspr r9,SPRN_SPRG_THREAD
1180 lwz r10,SAVED_KSP_LIMIT(r1)
1181 stw r10,KSP_LIMIT(r9)
1182 RESTORE_xSRR(SRR0,SRR1);
1184 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1186 .globl ret_from_debug_exc
1188 mfspr r9,SPRN_SPRG_THREAD
1189 lwz r10,SAVED_KSP_LIMIT(r1)
1190 stw r10,KSP_LIMIT(r9)
1191 RESTORE_xSRR(SRR0,SRR1);
1192 RESTORE_xSRR(CSRR0,CSRR1);
1194 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1196 .globl ret_from_mcheck_exc
1197 ret_from_mcheck_exc:
1198 mfspr r9,SPRN_SPRG_THREAD
1199 lwz r10,SAVED_KSP_LIMIT(r1)
1200 stw r10,KSP_LIMIT(r9)
1201 RESTORE_xSRR(SRR0,SRR1);
1202 RESTORE_xSRR(CSRR0,CSRR1);
1203 RESTORE_xSRR(DSRR0,DSRR1);
1205 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1206 #endif /* CONFIG_BOOKE */
1209 * Load the DBCR0 value for a task that is being ptraced,
1210 * having first saved away the global DBCR0. Note that r0
1211 * has the dbcr0 value to set upon entry to this.
1214 mfmsr r10 /* first disable debug exceptions */
1215 rlwinm r10,r10,0,~MSR_DE
1218 mfspr r10,SPRN_DBCR0
1219 lis r11,global_dbcr0@ha
1220 addi r11,r11,global_dbcr0@l
1232 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1237 .global global_dbcr0
1241 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1243 do_work: /* r10 contains MSR_KERNEL here */
1244 andi. r0,r9,_TIF_NEED_RESCHED
1247 do_resched: /* r10 contains MSR_KERNEL here */
1248 #ifdef CONFIG_TRACE_IRQFLAGS
1249 bl trace_hardirqs_on
1254 mtmsr r10 /* hard-enable interrupts */
1257 /* Note: And we don't tell it we are disabling them again
1258 * neither. Those disable/enable cycles used to peek at
1259 * TI_FLAGS aren't advertised.
1261 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
1263 mtmsr r10 /* disable interrupts */
1265 andi. r0,r9,_TIF_NEED_RESCHED
1267 andi. r0,r9,_TIF_USER_WORK_MASK
1269 do_user_signal: /* r10 contains MSR_KERNEL here */
1272 mtmsr r10 /* hard-enable interrupts */
1273 /* save r13-r31 in the exception frame, if not already done */
1280 2: addi r3,r1,STACK_FRAME_OVERHEAD
1287 * We come here when we are at the end of handling an exception
1288 * that occurred at a place where taking an exception will lose
1289 * state information, such as the contents of SRR0 and SRR1.
1292 lis r10,exc_exit_restart_end@ha
1293 addi r10,r10,exc_exit_restart_end@l
1295 #ifdef CONFIG_PPC_BOOK3S_601
1300 lis r11,exc_exit_restart@ha
1301 addi r11,r11,exc_exit_restart@l
1303 #ifdef CONFIG_PPC_BOOK3S_601
1308 lis r10,ee_restarts@ha
1309 lwz r12,ee_restarts@l(r10)
1311 stw r12,ee_restarts@l(r10)
1312 mr r12,r11 /* restart at exc_exit_restart */
1314 3: /* OK, we can't recover, kill this process */
1315 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1322 5: mfspr r2,SPRN_SPRG_THREAD
1324 tovirt(r2,r2) /* set back r2 to current */
1325 4: addi r3,r1,STACK_FRAME_OVERHEAD
1326 bl unrecoverable_exception
1327 /* shouldn't return */
1337 * PROM code for specific machines follows. Put it
1338 * here so it's easy to add arch-specific sections later.
1341 #ifdef CONFIG_PPC_RTAS
1343 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1344 * called with the MMU off.
1347 stwu r1,-INT_FRAME_SIZE(r1)
1349 stw r0,INT_FRAME_SIZE+4(r1)
1350 LOAD_REG_ADDR(r4, rtas)
1351 lis r6,1f@ha /* physical return address for rtas */
1354 tophys_novmstack r7, r1
1355 lwz r8,RTASENTRY(r4)
1359 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
1360 SYNC /* disable interrupts so SRR0/1 */
1361 mtmsr r0 /* don't get trashed */
1362 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1364 stw r7, THREAD + RTAS_SP(r2)
1368 1: tophys_novmstack r9, r1
1369 #ifdef CONFIG_VMAP_STACK
1370 li r0, MSR_KERNEL & ~MSR_IR /* can take DTLB miss */
1374 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1375 lwz r9,8(r9) /* original msr value */
1376 addi r1,r1,INT_FRAME_SIZE
1378 tophys_novmstack r7, r2
1379 stw r0, THREAD + RTAS_SP(r7)
1382 RFI /* return to caller */
1383 #endif /* CONFIG_PPC_RTAS */